Memory device and memory system

Abstract

To improve the reliability of a memory device.SOLUTION: A memory device according to an embodiment includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to the plurality of first memory cell transistors included in the plurality of memory cell transistors. The controller executes loop processing repeatedly including a program loop including program operation and first verification operation. The storage circuit stores status information. In write operation targeted on the plurality of first memory cell transistors, the controller executes second verification operation after executing the loop processing and stores, into the storage circuit, first status data corresponding to results of the loop processing and second status data corresponding to results of the second verification operation.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The embodiments relate to memory devices and memory systems. [Background technology]

[0002] 2. Description of the Related Art NAND flash memories capable of storing data in a non-volatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-147535 A Summary of the Invention [Problem to be solved by the invention]

[0004] Improve data reliability. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of bits of data. The first word line is connected to a plurality of first memory cell transistors among the plurality of memory cell transistors. The controller executes a loop process including a repetition of a program loop including a program operation and a first verify operation. The storage circuit stores status information. In a write operation targeting the plurality of first memory cell transistors, the controller executes the loop process and then executes a second verify operation, and causes the storage circuit to store first status data corresponding to a result of the loop process and second status data corresponding to a result of the second status verify operation. [Brief description of the drawings]

[0006] [Figure 1]1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a memory device according to the first embodiment. [Diagram 3] 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to a first embodiment. [Figure 4] 3 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the memory device according to the first embodiment. [Diagram 5] 3 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in the memory device according to the first embodiment. [Figure 6] 1 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of a memory cell array included in the memory device according to the first embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a memory cell pillar included in the memory device according to the first embodiment. [Figure 9] 3 is a schematic diagram showing an example of threshold voltage distributions and data allocation of memory cell transistors in the memory system according to the first embodiment; [Figure 10] 6 is a flowchart showing an example of a write operation of the memory system according to the first embodiment. [Figure 11] 5 is a schematic diagram showing an example of a command sequence in a write operation of the memory system according to the first embodiment. [Figure 12] 6 is a table showing an example of status information output from a memory device in a write operation of the memory system according to the first embodiment. [Figure 13] 6 is a flowchart showing an example of a write operation of the memory device according to the first embodiment. [Figure 14] 6 is a timing chart showing an example of a voltage applied to a selected word line in a write operation of the memory device according to the first embodiment. [Figure 15] 1 is a table showing an example of a combination of statuses corresponding to results of a write operation in a memory device according to the first embodiment. [Figure 16] 13 is a table showing an example of a combination of a target page of a second verify operation and a target state of the second verify operation in a write operation of a first modified example of the first embodiment. [Figure 17] FIG. 11 is a threshold voltage distribution diagram showing an example of settings of verify voltages used in a first verify operation and a second verify operation in a write operation according to a second modified example of the first embodiment. [Figure 18] FIG. 13 is a threshold voltage distribution diagram showing an example of setting the number of ignored bits in a write operation according to a third modified example of the first embodiment. [Figure 19] 10 is a flowchart showing an example of a write operation of the memory system according to the second embodiment. [Figure 20] 10 is a flowchart showing an example of a write operation in a modified example of the second embodiment. [Figure 21] 13 is a flowchart showing an example of a write operation of a memory device according to a third embodiment. [Figure 22] 13 is a flowchart showing an example of a write operation of the memory system according to the fourth embodiment. [Figure 23] FIG. 13 is a schematic diagram showing an example of a command sequence in a write operation of the memory system according to the fourth embodiment. [Figure 24] 13 is a table showing an example of status information output from a memory device in a write operation of the memory system according to the fourth embodiment. [Diagram 25] 13 is a flowchart showing an example of a write operation of the memory system according to the fifth embodiment. [Figure 26] 13 is a table showing an example of status information output from a memory device in a write operation of a memory system according to a fifth embodiment. [Figure 27] 13 is a timing chart showing an example of a voltage applied to a selected word line in a write operation of a memory device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. The technical idea of ​​the present invention is not specified by the shape, structure, arrangement, etc. of the components.

[0008] In the following description, components having substantially the same functions and configurations are given the same reference numerals. The numerals following the letters of the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and that have similar configurations. Similarly, the numerals following the letters of the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same numbers and that have similar configurations.

[0009] [1] First embodiment The memory system 1 according to the first embodiment will be described below.

[0010] [1-1] Configuration [1-1-1] Overall configuration of memory system 1 Fig. 1 is a block diagram showing an example of a configuration of a memory system 1 according to the first embodiment. As shown in Fig. 1, the memory system 1 includes, for example, a memory set 10 and a memory controller 20. The memory system 1 is connected to an external host device 30, and can execute operations according to commands from the host device 30.

[0011] The memory set 10 includes a plurality of memory devices MD0 to MD15. Each memory device MD is a NAND type flash memory that stores data in a non-volatile manner, and is formed on a different semiconductor chip. The number of memory devices MD included in the memory set 10 can be designed to be any number. A detailed configuration of the memory devices MD will be described later.

[0012] The memory controller 20 is, for example, a SoC (System on Chip), and issues read, write, erase, and other commands to each of the memory devices MD0 to MD15 in response to a command from the host device 30. The memory controller 20 includes, for example, a CPU (Central Processing Unit) 21, a ROM (Read Only Memory) 22, a RAM (Random Access Memory) 23, an ECC (Error Correction Code) circuit 24, a host interface circuit 25, and a NAND interface circuit 26.

[0013] The CPU 21 controls the overall operation of the memory controller 20. The CPU 21 issues a command in response to an instruction received from, for example, the host device 30, and transmits the issued command to the memory device MD. The CPU 21 can also execute various processes for managing the storage space of the memory device MD, such as garbage collection and wear leveling.

[0014] The ROM 22 is a read-only storage device that holds data in a non-volatile manner. The ROM 22 stores, for example, a control program and control data for the memory controller 20.

[0015] The RAM 23 is a storage device used as a working area of ​​the CPU 21. The RAM 23 stores, for example, a lookup table LUT for managing the storage area of ​​the memory device MD. As the RAM 23, for example, a volatile memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is used. The RAM 23 is also used as a temporary storage area of ​​the memory controller 20. The RAM 23 temporarily stores, for example, write data received from the host device 30 and read data received from the memory device MD. Note that a storage device such as the RAM 23 may be externally connected to the memory controller 20.

[0016] The ECC circuit 24 executes error correction processing of data. For example, during a write operation, the ECC circuit 24 generates parity based on write data received from the host device 30, and adds the generated parity to the write data. During a read operation, the ECC circuit 24 generates a syndrome based on read data received from the memory device MD, and detects and corrects errors in the read data based on the generated syndrome.

[0017] The host interface circuit 25 is connected to the host device 30 and controls the transfer of data, commands, and addresses between the memory controller 20 and the host device 30. The host interface circuit 25 supports a variety of standards, including SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe (PCI Express), TM It may support communication interface standards such as:

[0018] The NAND interface circuit 26 is connected to the memory device MD and controls the transfer of data, commands, and addresses between the memory device MD and the memory controller 20. The connection between the NAND interface circuit 26 and the memory device MD supports the NAND interface standard. For example, the NAND interface circuit 26 includes channels CH0 to CH3 that can be controlled in parallel. The channel CH0 is connected to memory devices MD0, MD4, MD8, and MD12. The channel CH1 is connected to memory devices MD1, MD5, MD9, and MD13. The channel CH2 is connected to memory devices MD2, MD6, MD10, and MD14. The channel CH3 is connected to memory devices MD3, MD7, MD11, and MD15.

[0019] A set of multiple memory devices MD controlled in parallel is called, for example, a "bank." In this example, the memory set 10 includes four banks B0 to B3. Bank B0 includes memory devices MD0 to MD3, bank B1 includes memory devices MD4 to MD7, bank B2 includes memory devices MD8 to MD11, and bank B3 includes memory devices MD12 to MD15. Multiple memory devices MD connected to a common channel CH can operate in parallel, except for operations involving communication between the memory devices MD and the NAND interface circuit 26. The number of memory devices MD included in the memory set 10 and the configuration of the banks and channels can be designed arbitrarily.

[0020] [1-1-2] Configuration of memory device MD Fig. 2 is a block diagram showing an example of the configuration of a memory device MD according to the first embodiment. As shown in Fig. 2, the memory device MD includes, for example, an input / output circuit 101, a register set 102, a logic control circuit 103, a sequencer 104, a ready-busy control circuit 105, a driver circuit 106, a memory cell array 107, a row decoder module 108, a sense amplifier module 109, and a counter 110.

[0021] The input / output circuit 101 transmits and receives, for example, 8-bit input / output signals I / O0 to I / O7 to and from the memory controller 20. The input / output signals I / O may include data, status information, address information, commands, etc. The input / output circuit 101 also transmits and receives data DAT to and from the sense amplifier module 109.

[0022] The register set 102 includes a status register (STS Reg) 102A, an address register (ADD Reg) 102B, and a command register (CMD Reg) 102C. The status register 102A, the address register 102B, and the command register 102C hold status information STS, address information ADD, and a command CMD, respectively. The status information STS is transferred from the status register 102A to the input / output circuit 101 based on an instruction from the memory controller 20, and is output to the memory controller 20. The address information ADD is transferred from the input / output circuit 101 to the address register 102B, and may include a block address, a page address, a column address, and the like. The command CMD is transferred from the input / output circuit 101 to the command register 102C, and includes instructions regarding various operations of the memory device MD.

[0023] The logic control circuit 103 controls each of the input / output circuit 101 and the sequencer 104 based on a control signal received from the memory controller 20. Examples of such control signals include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The chip enable signal CEn is a signal that enables the memory device MD. The command latch enable signal CLE is a signal that notifies the input / output circuit 101 that the received input / output signal I / O is a command CMD. The address latch enable signal ALE is a signal that notifies the input / output circuit 101 that the received input / output signal I / O is address information ADD. The write enable signal WEn is a signal that instructs the input / output circuit 101 to input the input / output signal I / O. The read enable signal REn is a signal that instructs the input / output circuit 101 to output the input / output signal I / O. The write protect signal WPn is a signal that puts the memory device MD into a protected state when the power is turned on or off.

[0024] The sequencer 104 controls the overall operation of the memory device MD. For example, the sequencer 104 executes a read operation, a write operation, an erase operation, etc. based on a command CMD held in a command register 102C and address information ADD held in an address register 102B. The sequencer 104 also updates the status information STS in the status register 102A based on the operation and state of the memory device MD.

[0025] The ready-busy control circuit 105 generates a ready-busy signal RBn based on the operation state of the sequencer 104. The ready-busy signal RBn is a signal that notifies the memory controller 20 whether the memory device MD is in a ready state or a busy state. In this specification, the "ready state" indicates that the memory device MD is in a state in which it can accept commands from the memory controller 20, and the "busy state" indicates that the memory device MD is in a state in which it cannot accept commands from the memory controller 20.

[0026] The driver circuit 106 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 106 then supplies the generated voltages to the memory cell array 107, the row decoder module 108, and the sense amplifier module 109.

[0027] The memory cell array 107 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The block BLK is a set of a plurality of memory cell transistors capable of storing data in a non-volatile manner. The block BLK is used, for example, as a data erase unit. The memory cell array 107 is also provided with a plurality of bit lines BL0 to BLm (m is an integer equal to or greater than 1), a plurality of word lines, and a source line. Each memory cell transistor is associated with one bit line BL and one word line.

[0028] The row decoder module 108 selects a block BLK to be operated on based on a block address. Then, the row decoder module 108 transfers the voltage supplied from the driver circuit 106 to various wirings in the selected block BLK. The row decoder module 108 also includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively.

[0029] During a read operation, the sense amplifier module 109 reads data from the memory cell array 107 and transfers the read data to the input / output circuit 101. During a write operation, the sense amplifier module 109 applies a desired voltage to the bit line BL based on data received from the input / output circuit 101. For example, the sense amplifier module 109 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with the bit lines BL0 to BLm, respectively.

[0030] The counter 110 counts, for example, the number of "1" data or the number of "0" data transferred from the sense amplifier module 109. Then, the counter 110 transfers the count result to the sequencer 104. The counter 110 is used, for example, to determine whether or not a verify pass occurs during a write operation.

[0031] [1-1-3] Circuit configuration of memory device MD (Circuit configuration of memory cell array 107) 3 is a circuit diagram showing an example of a circuit configuration of a memory cell array 107 included in the memory device MD according to the first embodiment. FIG. 3 shows one block BLK. As shown in FIG. 3, the block BLK includes string units SU0 to SU4, word lines WL0 to WL11, select gate lines SGD0 to SGD4, and a select gate line SGS. Each string unit SU includes a plurality of NAND strings NS respectively connected to bit lines BL0 to BLm. Each NAND string NS includes memory cell transistors MT0 to MT11 and select transistors ST1 and ST2.

[0032] Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select a string unit SU during various operations. Each of the bit lines BL0 to BLm is assigned a different column address. Each bit line BL is connected to a plurality of NAND strings NS in each of the plurality of blocks BLK. The source line SL is shared, for example, between the plurality of blocks BLK.

[0033] The memory cell transistors MT0 to MT11 of each NAND string NS are connected in series. One end and the other end of the serially connected memory cell transistors MT0 to MT11 are connected to the source of the selection transistor ST1 and the drain of the selection transistor ST2, respectively. The drain of the selection transistor ST1 of each NAND string NS is connected to the associated bit line BL. The source of the selection transistor ST1 of each NAND string NS is connected to a source line SL. The word lines WL0 to WL11 are connected to the memory cell transistors MT0 to MT11 of each NAND string NS, respectively. The selection gate lines SGD0 to SGD4 are connected to the gates of the selection transistors ST1 included in the string units SU0 to SU4, respectively. The selection gate line SGS is connected to the gate of the selection transistor ST2 of each NAND string NS.

[0034] The circuit configuration of the memory cell array 107 may be other circuit configurations. The number of string units SU included in each block BLK and the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be freely designed. In this specification, a set of multiple memory cell transistors MT connected to a common word line WL in one string unit SU is called a "cell unit CU." When each memory cell transistor MT stores one bit of data, the cell unit CU stores "one page data." The cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits stored in each memory cell transistor MT.

[0035] (Circuit configuration of row decoder module 108) FIG. 4 is a circuit diagram showing an example of a circuit configuration of the row decoder module 108 included in the memory device MD according to the first embodiment. FIG. 4 shows a connection between the driver circuit 106 and the memory cell array 107 via the row decoder module 108, and shows a detailed circuit configuration of one row decoder RD0. As shown in FIG. 4, each row decoder RD of the row decoder module 108 is connected to the driver circuit 106 via signal lines CG0 to CG11, SGDD0 to SGDD4, SGSD, USGD, and USGS. Each row decoder RD of the row decoder module 108 is connected to the associated block BLK via word lines WL0 to WL11 and select gate lines SGD0 to SGD4. Each row decoder RD includes transistors TR0 to TR23, transfer gate lines TG and bTG, and a block decoder BD.

[0036] Each of the transistors TR0 to TR23 is a high-voltage N-type MOS transistor. The drain and source of the transistor TR0 are connected to the signal line SGSD and the select gate line SGS, respectively. The drains of the transistors TR1 to TR12 are connected to the signal lines CG0 to CG11, respectively. The sources of the transistors TR1 to TR12 are connected to the word lines WL0 to WL11, respectively. The drains of the transistors TR13 to TR17 are connected to the signal lines SGDD0 to SGDD4, respectively. The sources of the transistors TR13 to TR17 are connected to the select gate lines SGD0 to SGD4, respectively. The drain and source of the transistor TR18 are connected to the signal line USGS and the select gate line SGS, respectively. The drains of the transistors TR19 to TR23 are connected to the signal line USGD. The sources of the transistors TR19 to TR23 are connected to the select gate lines SGD0 to SGD3, respectively. The gates of the transistors TR0 to TR17 are connected to the transfer gate line TG. The gates of the transistors TR18 to TR23 are connected to a transfer gate line bTG.

[0037] The block decoder BD decodes the block address BA, and applies a predetermined voltage to each of the transfer gate lines TG and bTG based on the decoded result. In other words, the row decoder module 108 selects a block BLK based on the block address BA input to the block decoder BD of each row decoder RD. Specifically, for example, the block decoder BD corresponding to the selected block BLK applies voltages of "H" level and "L" level to the transfer gate lines TG and bTG, respectively, and the block decoder BD corresponding to the unselected block BLK applies voltages of "L" level and "H" level to the transfer gate lines TG and bTG, respectively. As a result, the voltages of the signal lines CG0 to CG11 are transferred to the word lines WL0 to WL11 of the selected block BLK, respectively, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are transferred to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively, and the signal lines USGD and USGS are transferred to the select gate lines SGD and SGS of the unselected block BLK, respectively.

[0038] The row decoder module 108 may have other circuit configurations. For example, the number of transistors TR included in the row decoder module 108 may be changed according to the number of wirings provided in each block BLK. The signal line CG may be called a "global word line" because it is shared between multiple blocks BLK. The word line WL may be called a "local word line" because it is provided for each block. Each of the signal lines SGDD and SGSD may be called a "global transfer gate line" because it is shared between multiple blocks BLK. Each of the selection gate lines SGD and SGS may be called a "local transfer gate line" because it is provided for each block.

[0039] (Circuit configuration of sense amplifier module 109) Fig. 5 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module 109 included in a memory device MD according to the first embodiment. Fig. 5 shows one sense amplifier unit SAU. As shown in Fig. 5, the sense amplifier unit SAU includes a sense amplifier section SA, a bit line connection section BLHU, latch circuits SDL, ADL, BDL, CDL, DDL, and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, DDL, and XDL are configured to be able to transmit and receive data via the bus LBUS.

[0040] When a control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. Each of the latch circuits SDL, ADL, BDL, and XDL temporarily holds read data, write data, etc. The latch circuit XDL is used for inputting and outputting data between the sense amplifier unit SAU and the input / output circuit 101. The latch circuit XDL can also be used as a cache memory. The memory device MD can be in a ready state if at least the latch circuit XDL is free. The latch circuit XDL can also transfer data to the counter 110.

[0041] The sense amplifier section SA includes transistors T0 to T7, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU includes a transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. The circuit configurations of the latch circuits ADL, BDL, CDL, DDL, and XDL are similar to that of the latch circuit SDL. The transistor T0 is a P-type MOS transistor. Each of the transistors T1 to T8, T10, and T11 is an N-type MOS transistor. The transistor T8 is an N-type MOS transistor with a higher withstand voltage than the N-type transistor in the sense amplifier section SA.

[0042] The node ND1 is connected to the drain of the transistor T0 and to the drains of the transistors T1 and T2. The node ND2 is connected to the sources of the transistors T1 and T3 and to the drains of the transistors T4 and T5. The node SEN is connected to the source of the transistor T2, the drain of the transistor T3, the gate of the transistor T6, and one electrode of the capacitor CP. The source of the transistor T0 is connected to the power supply line. The source of the transistor T5 is connected to the node SRC. The source of the transistor T6 is grounded. The drain and source of the transistor T7 are connected to the bus LBUS and to the drain of the transistor T6, respectively. The drain and source of the transistor T8 are connected to the source of the transistor T4 and to the associated bit line BL, respectively. One end of each of the transistors T10 and T11 is connected to the bus LBUS. The node SINV is connected to the other end of the transistor T10, the output node of the inverter IV0, the input node of the inverter IV1, and the gates of the transistors T0 and T5. The node SLAT is connected to the other end of the transistor T11, an input node of the inverter IV0, and an output node of the inverter IV1.

[0043] A power supply voltage VDD, for example, is applied to the source of the transistor T0. A ground voltage VSS, for example, is applied to the node SRC. Control signals BLX, HLL, XXL, BLC, and STB are input to the gates of the transistors T1, T2, T3, T4, and T7, respectively. A control signal BLS is input to the gate of the transistor T8. Control signals STI and STL are input to the gates of the transistors T10 and T11, respectively. A clock signal CLK is input to the other electrode of the capacitor CP. The control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, and the clock signal CLK are each generated by, for example, the sequencer 104. The node SLAT of the latch circuit SDL is used to hold data. The node SINV of the latch circuit SDL is used to hold the inverted data of the node SLAT. The sequencer 104 can control the connection to the bus LBUS for each latch circuit by independently controlling the transistors T10 and T11 of each latch circuit.

[0044] The sense amplifier module 109 may have other circuit configurations. For example, the number of latch circuits included in each sense amplifier unit SAU may be five or less or seven or more. The sense amplifier unit SAU may have an arithmetic circuit capable of performing simple logical operations. In this example, asserting the control signal corresponds to temporarily changing the voltage at the "L" level to a voltage at the "H" level. When the transistor T6 is a P-type transistor, asserting the control signal STB corresponds to temporarily changing the voltage at the "H" level to a voltage at the "L" level.

[0045] [1-1-4] Structure of memory device MD An example of the structure of the memory device MD is described below. In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate used to form the memory device MD. Hatching is appropriately added to the plan view to make the view easier to see. Hatching added to the plan view does not necessarily relate to the material or characteristics of the associated components. In the cross-sectional views, illustrations of the configuration are appropriately omitted to make the view easier to see.

[0046] (Plane layout of memory cell array 107) 6 is a plan view showing an example of a planar layout of a memory cell array 107 included in a memory device MD according to the first embodiment. As shown in FIG. 6, the memory cell array 107 includes a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV.

[0047] Each slit SLT has a portion extending along the X direction. A plurality of slits SLT are arranged in the Y direction. In the memory cell array 107, each of the regions partitioned by the slits SLT corresponds to one block BLK. Each slit SLT separates adjacent wiring (for example, the word lines WL0 to WL11 and the select gate lines SGD and SGS) through the slit SLT. Each slit SLT includes a contact LC and a spacer SP. The contact LI is a conductor having a portion extending along the X direction. The contact LI is used as a part of the source line SL. The spacer SP is an insulator provided on the side of the contact LI. The contact LI is sandwiched in the Y direction by a pair of spacers SP. The contact LI and the conductor adjacent to the contact LI in the Y direction are separated and insulated by the spacer SP.

[0048] Each slit SHE has a portion extending along the X direction. A plurality of slits SHE are arranged in the Y direction. In the memory cell array 107, each of the regions partitioned by the slits SLT and SHE corresponds to one string unit SU. In this example, four slits SHE are disposed between adjacent slits SLT, and five string units SU are provided in each block BLK. Each slit SHE has a structure in which an insulator is embedded, for example. Each slit SHE divides adjacent wiring (at least the selection gate line SGD) via the slit SHE.

[0049] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 24 rows in the region between two adjacent slits SLT. In this example, counting from the top of the page, one slit SHE overlaps the fifth row of memory pillar MP, the tenth row of memory pillar MP, the fifteenth row of memory pillar MP, and the twentieth row of memory pillar MP.

[0050] Each bit line BL has a portion extending along the Y direction. The multiple bit lines are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged so as to overlap each memory pillar MP. A contact CV is provided between one of the multiple bit lines BL overlapping the memory pillar MP and the memory pillar MP. Each memory pillar MP is electrically connected to the corresponding bit line BL via the associated contact CV. In this example, the contact CV between the memory pillar MP in contact with the slit SHE and the bit line BL is omitted.

[0051] In the memory cell array 107, the layout described above is repeatedly arranged in the Y direction. The planar layout of the memory cell array 107 may be other layouts. For example, the number and arrangement of memory pillars MP, slits SHE, etc. provided between adjacent slits SLT may be changed as appropriate. The number of string units SU formed between adjacent slits SLT may be changed based on the number of slits SHE arranged between adjacent slits SLT. The number of bit lines BL overlapping each memory pillar MP may be one or three or more.

[0052] (Cross-sectional structure of memory cell array 107) Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of a cross-sectional structure of the memory cell array 107 included in the memory device MD according to the first embodiment. As shown in Fig. 7, the memory cell array 107 includes, for example, a P-type well region 40, an N-type semiconductor region 41, conductor layers 42-46, insulator layers 50-58, memory pillars MP, contacts CV, and slits SLT and SHE.

[0053] The P-type well region 40 is provided near the surface of the semiconductor substrate. The P-type well region 40 is a diffusion region of P-type impurities. The N-type semiconductor region 41 is provided near the surface of the P-type well region 40. The N-type semiconductor region 41 is a diffusion region of N-type impurities. The N-type semiconductor region 41 is formed by doping the P-type well region 40 with phosphorus, for example.

[0054] An insulator layer 50 is provided on the P-type well region 40. A conductor layer 42 and an insulator layer 51 are alternately stacked on the insulator layer 50. An insulator layer 52 is provided on the uppermost conductor layer 42. A conductor layer 43 and an insulator layer 53 are alternately stacked on the insulator layer 52. An insulator layer 54 is provided on the uppermost conductor layer 43. A conductor layer 44 and an insulator layer 55 are alternately stacked on the insulator layer 54. An insulator layer 56 is provided on the uppermost conductor layer 44. A conductor layer 45 and an insulator layer 57 are alternately stacked on the insulator layer 56. An insulator layer 58 is provided on the uppermost conductor layer 45. A conductor layer 46 is provided on the insulator layer 58.

[0055] Each of the conductive layers 42, 43, 44, and 45 is formed in a plate shape extending along the XY plane, for example. The conductive layer 46 is formed in a line shape extending in the Y direction, for example. The stacked conductive layers 42 are used as a select gate line SGS. The stacked conductive layers 43 are used as word lines WL0 to WL5, respectively, from the lower layer side. The stacked conductive layers 44 are used as word lines WL6 to WL11, respectively, from the lower layer side. The stacked conductive layers 45 are used as a select gate line SGD. The conductive layer 46 is used as a bit line BL. That is, in a region not shown, the multiple conductive layers 46 are arranged along the X direction. Each of the conductive layers 42, 43, 44, and 45 contains, for example, tungsten. The conductive layer 46 contains, for example, copper.

[0056] The memory pillar MP extends along the Z direction and is provided penetrating the conductive layers 42 to 45. Each memory pillar MP has a first portion formed in the lower hole LMH and a second portion formed in the upper hole UMH. The first portion penetrates the conductive layers 42 and 43, and the bottom portion is in contact with the P-type well region 40. The second portion is provided above the first portion and penetrates the conductive layers 44 and 45. The memory pillar MP has a step between the first portion and the second portion (boundary portion). In this specification, the layer including the boundary portion between the first portion and the second portion of the memory pillar MP, that is, the layer on which the insulator layer 54 is provided, is also referred to as the "junction layer JT". The memory pillar MP may have a structure in which the outer diameter is thickened at the junction layer JT. The thickness of the insulator layer 54 is thicker than the thicknesses of the insulator layers 53 and 55. In other words, the distance between the uppermost conductive layer 43 and the lowermost conductive layer 44 is greater than the distance between adjacent conductive layers 43 and the distance between adjacent conductive layers 44 .

[0057] Each memory pillar MP includes a semiconductor layer 60 and a laminated film 61. The semiconductor layer 60 and the laminated film 61 are each provided continuously between the first portion and the second portion of the memory pillar MP. The semiconductor layer 60 is provided extending along the Z direction. The upper end of the semiconductor layer 60 is included in a layer above the uppermost conductive layer 45. The lower end of the semiconductor layer 60 is in contact with the P-type well region 40. The laminated film 61 covers the side surface of the semiconductor layer 60. A portion where the memory pillar MP intersects with the multiple conductive layers 42 functions as a selection transistor ST2. A portion where the memory pillar MP intersects with one conductive layer 43 and a portion where the memory pillar MP intersects with one conductive layer 44 each function as a memory cell transistor MT. A portion where the memory pillar MP intersects with the multiple conductive layers 45 functions as a selection transistor ST1. A detailed cross-sectional structure of the memory pillar MP will be described later.

[0058] A columnar contact CV is provided on the semiconductor layer 60 in each memory pillar MP. One conductive layer 46, i.e., one bit line BL, is in contact with the contact CV. As described above, one conductive layer 46 is connected to one contact CV for each space partitioned by the slits SLT and SHE.

[0059] The slits SLT divide the conductive layers 42 to 45 and the insulating layers 50 to 57. The position of the upper end of the slits SLT is included in the level at which the insulating layer 58 is provided. The lower end of the slits SLT contacts the N-type semiconductor region 41. The bottom of the contact LI is electrically connected to the N-type semiconductor region 41. The contact LI and the conductive layers 42 to 45 are separated and insulated by the spacers SP.

[0060] The slit SHE divides a plurality of conductive layers 45. The position of the upper end of the slit SHE is included in the level at which the insulating layer 58 is provided. The position of the lower end of the slit SHE is included in the level at which the insulating layer 56 is provided, for example. The slit SHE may divide one or more conductive layers 44.

[0061] The cross-sectional structure of the memory cell array 107 may be other structures. For example, the memory pillar MP may be formed on a conductive layer functioning as the source line SL. The memory cell array 107 may be provided above a semiconductor substrate, and peripheral circuits such as the sense amplifier module 109 may be provided below the memory cell array 107. The memory pillar MP may have a structure formed using three or more connected holes, or may have a structure formed using one hole. The number of layers of each of the conductive layers 42 to 45 may be appropriately changed depending on the number of wirings provided in the memory cell array 107.

[0062] (Memory pillar MP cross-sectional structure) 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a memory pillar MP included in the memory device MD according to the first embodiment. As shown in FIG. 8, the stacked film 61 includes, for example, a tunnel insulating film 62, an insulating film 63, and a block insulating film 64. In the cross section including the conductor layer 44, the semiconductor layer 60 is provided in the central portion of the memory pillar MP. The side surface of the semiconductor layer 60 is surrounded by the tunnel insulating film 62. The side surface of the tunnel insulating film 62 is surrounded by the insulating film 63. The side surface of the insulating film 63 is surrounded by the block insulating film 64. The side surface of the block insulating film 64 is surrounded by the conductor layer 44.

[0063] Each of the tunnel insulating film 62 and the block insulating film 64 includes, for example, silicon oxide. The insulating film 63 includes, for example, silicon nitride. The semiconductor layer 60 functions as a channel (current path) of the memory cell transistors MT0 to MT11 and the select transistors ST1 and ST2. The insulating film 63 is used as a charge storage layer of the memory cell transistors MT. The memory device MD can pass a current between the bit line BL and the contact LI (source line SL) via the memory pillar MP by turning on the memory cell transistors MT0 to MT11 and the select transistors ST1 and ST2. The cross-sectional structure of the memory pillar MP may be other structures. For example, an insulator or a void whose sides are surrounded by the semiconductor layer 60 may be provided in the central part of the memory pillar MP.

[0064] [1-1-5] Data storage method 9 is a schematic diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistors MT in the memory system 1 according to the first embodiment. "NMTs" on the vertical axis indicates the number of memory cell transistors MT. "Vth" on the horizontal axis indicates the threshold voltage of the memory cell transistor MT. Hereinafter, an example of the threshold voltage distribution and data allocation of the memory cell transistors MT will be described with reference to FIG. 9.

[0065] When each memory cell transistor MT stores 3-bit data, eight states are formed by the threshold voltages of the memory cell transistors MT. In this specification, the eight states are called "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state, in order from the lowest threshold voltage. Different 3-bit data is assigned to each of the "S0" to "S7" states. In other words, different 3-bit data is assigned to each of the multiple states set according to the level of the threshold voltage of the memory cell transistor MT. An example of data allocation to the eight states is listed below. “S0” state: “111 (high-order bit / middle-order bit / low-order bit)” data “S1” state: “110” data “S2” state: “100” data “S3” state: “000” data “S4” state: “010” data “S5” state: “011” data “S6” state: “001” data “S7” state: “101” data.

[0066] A read voltage and a verify voltage are set between adjacent states. Specifically, the read voltage R1 is set between the "S0" and "S1" states. The read voltage R2 is set between the "S1" and "S2" states. The read voltage R3 is set between the "S2" and "S3" states. The read voltage R4 is set between the "S3" and "S4" states. The read voltage R5 is set between the "S4" and "S5" states. The read voltage R6 is set between the "S5" and "S6" states. The read voltage R7 is set between the "S6" and "S7" states. The verify voltages V1 to V7 are used for verify reads of the "S1" to "S7" states in a verify operation. The verify voltages V1 to V7 may be the same as or different from the read voltages R1 to R7. Furthermore, the read pass voltage VREAD is set to a voltage higher than the state "S7" with the highest threshold voltage. The memory cell transistor MT with the read pass voltage VREAD applied to its gate is turned on regardless of the data stored therein.

[0067] When such data allocation is applied, one page of data (lower page data) composed of lower bits is determined by a read operation using read voltages R1 and R5. One page of data (middle page data) composed of middle bits is determined by a read operation using read voltages R2, R4, and R6. One page of data (upper page data) composed of upper bits is determined by a read operation using read voltages R3 and R7. In a page read operation using multiple read voltages, arithmetic processing is appropriately performed in the sense amplifier unit SAU. Note that other data allocations may be used as a storage method for 3-bit data. Each memory cell transistor MT may store 1 bit, 2 bits, or 4 or more bits of data.

[0068] [1-2] Operation Next, the operation of the memory system 1 according to the first embodiment will be described. In the following, the selected word line WL is called "WLsel". The application of a voltage to the word line WL corresponds to the driver circuit 106 applying a voltage to the word line WL via the row decoder module 108. The address information ADD and the command CMD received by the memory device MD are transferred to the address register 102B and the command register 102C, respectively. The write data received by the memory device MD is transferred to the latch circuit XDL in each sense amplifier unit SAU included in the sense amplifier module 109.

[0069] [1-2-1] Overview of write operation (Write operation flow) 10 is a flowchart showing an example of a write operation of the memory system 1 according to the first embodiment. The flow of the write operation of the memory system 1 will be described below with reference to FIG.

[0070] When the host device 30 transmits write data to the memory system 1, the memory controller 20 starts a series of processes in FIG. 10 (START).

[0071] First, the memory controller 20 receives write data from the host device 30 (step S100). The write data received by the memory controller 20 is stored in the RAM 23, for example.

[0072] Next, the memory controller 20 determines a destination to which the write data is to be written (step S101). In determining the destination, for example, a management table of the storage area developed in the RAM 23 is referenced.

[0073] Next, the memory controller 20 causes the memory device MD to execute a write operation (step S102). Specifically, the memory controller 20 transmits a command instructing the write operation and write data to the memory device MD, and the memory device MD that receives the command and write data executes the write operation.

[0074] When the write operation of the memory device MD is completed, the memory controller 20 reads the status information STS from the memory device MD and checks whether the status of the write operation is pass or not (step S103). That is, the memory controller 20 judges whether the data writing is successful or not based on the status information STS. Hereinafter, the operation of the memory controller 20 to read the status information STS from the memory device MD is also called "status read".

[0075] If the status pass is not confirmed in the process of step S103 (step S103, NO), that is, if the status fail is confirmed, the memory controller 20 registers the block BLK to which the data writing has failed as a bad block (step S104). Then, the memory controller 20 proceeds to the process of step S101. That is, the memory controller 20 changes the write destination and retries the write operation.

[0076] When the status pass is confirmed in the process of step S103 (ES in step S103), the memory controller 20 updates the lookup table LUT based on the address to which the data has been successfully written (step S105).

[0077] After the process of step S105, the memory controller 20 discards the write data held in the RAM 23, and ends the series of processes in FIG. 10 (END).

[0078] (Command sequence for write operation) Fig. 11 is a schematic diagram showing an example of a command sequence in a write operation of the memory system 1 according to the first embodiment. Fig. 11 shows the exchange of input / output signals I / O between the memory controller 20 and the memory device MD, and the change in the ready-busy state. The command sequence of the write operation will be described below with reference to Fig. 11.

[0079] First, as shown in FIG. 11(1), the memory controller 20 transfers to the memory device MD a command set including the first page data (lower page data in TLC mode) of the three pages of data assigned to the cell unit CU of the write destination. Specifically, the memory controller 20 transmits to the memory device MD, in this order, a command “01h”, a command “80h”, address information “ADD”, write data “Din” of the lower page, and a command “1Ah”. The command “01h” is a command instructing an operation corresponding to the first page data. The command “80h” is a command instructing a write operation. The address information “ADD” includes an address assigned to the cell unit CU of the write destination. The command “1Ah” is a command instructing the transfer of the data held in the latch circuit XDL to another latch circuit. When the memory device MD receives the command “1Ah”, it temporarily transitions to a busy state and transfers the lower page data from the latch circuit XDL to, for example, the latch circuit ADL.

[0080] Next, as shown in FIG. 11(2), the memory controller 20 transfers to the memory device MD a command set including the second page data (middle page data in TLC mode) of the three page data assigned to the write destination cell unit CU. Specifically, the memory controller 20 transmits to the memory device MD, in this order, a command “02h”, a command “80h”, address information “ADD”, write data “Din” of the middle page, and a command “1Ah”. The command “02h” is a command instructing an operation corresponding to the second page data. Upon receiving the command “1Ah”, the memory device MD temporarily transitions to a busy state and transfers the middle page data from the latch circuit XDL to, for example, the latch circuit BDL.

[0081] Next, as shown in FIG. 11(3), the memory controller 20 transfers to the memory device MD a command set including the third page data (upper page data in TLC mode) of the three page data assigned to the cell unit CU to be written. Specifically, the memory controller 20 transmits to the memory device MD, in this order, a command “03h”, a command “80h”, address information “ADD”, upper page write data “Din”, and a command “10h”. The command “03h” is a command instructing an operation corresponding to the third page data. The command “10h” is a command instructing to start a write operation after transferring the upper page data stored in the latch circuit XDL to the latch circuit CDL, for example.

[0082] When the memory device MD receives the command “10h”, it transitions from a ready state (RBn=“H” level) to a busy state (RBn=“L” level) as shown in FIG. 11(4). Then, the memory device MD executes a write operation, for example, using 3-bit data stored in the latch circuits ADL, BDL and CDL. When the write operation is completed, the memory device MD transitions from a busy state to a ready state and notifies the memory controller 20 of the completion of the write operation. The illustrated “tProg” corresponds to the time during which the memory device MD is executing the write operation.

[0083] When the write operation is completed and the memory device MD transitions from a busy state to a ready state, the memory controller 20 executes a first status read, as shown in FIG. 11(5). Specifically, the memory controller 20 transmits a command “70h” to the memory device MD. The memory device MD that receives the command “70h” transmits the status information “Sout” stored in the status register 102A to the memory controller 20. This status information “Sout” includes the status information STS of the write operation executed immediately before. Then, the memory controller 20 checks the status of the write operation by referring to the status information “Sout” (step S103 in FIG. 10).

[0084] FIG. 12 is a table showing an example of status information STS (Sout) output from the memory device MD in a write operation of the memory system 1 according to the first embodiment. As shown in FIG. 12, the status information STS output by the first status read includes data indicating the write result. The data indicating the write result is transmitted, for example, via I / O0. For example, data "0" stored in I / O0 of the status information STS indicates that the write operation has been completed successfully. Data "1" stored in I / O0 of the status information STS indicates that the write operation has not been completed successfully, for example, that the write has not been completed in a predetermined number of program loops. Each piece of data included in the status information may be called "status data."

[0085] The status information STS may include, for example, data (True busyn) indicating whether the memory device MD is performing an operation, data (Cache busyn) indicating whether the cache is free, and a write protect signal WPn. For example, True busyn, Cache busyn, and WPn are transmitted via I / O5, I / O6, and I / O7, respectively. The status information STS read after a write operation may include at least data indicating the write result. Note that the assignment of the status information STS to the input / output signal I / O in the first status read may be other assignments.

[0086] [1-2-2] Operation of memory device MD (Flow of write operation by memory device MD) 13 is a flowchart showing an example of a write operation of the memory device MD according to the first embodiment. The flow of the write operation of the memory device MD will be described below with reference to FIG.

[0087] When the memory device MD receives a command instructing a write operation and write data from the memory controller 20, the sequencer 104 of the memory device MD starts a series of processes in FIG. 10 (START).

[0088] First, the sequencer 104 executes a program operation (step S110). The program operation is an operation of applying a program voltage to the memory cell transistor MT to be written. In the program operation, the memory cell transistor MT in the selected cell unit CU is set to be programmed or to be program-prohibited based on the write data held in the sense amplifier unit SAU. In the memory cell transistor MT to be programmed, the threshold voltage increases due to the program operation. On the other hand, in the memory cell transistor MT that is program-prohibited, the increase in the threshold voltage due to the program operation is suppressed.

[0089] Next, the sequencer 104 executes a first verify operation (step S111). The first verify operation is a read operation that determines whether the threshold voltage of the memory cell transistor MT to be written has reached a desired state. In the write operation, a set of a program operation and a first verify operation is executed multiple times. Hereinafter, a set of one program operation and one first verify operation is called a "program loop." When the first verify operation is completed, the result of the first verify operation is transferred to the counter 110. The counter 110 counts, for example, the number of memory cell transistors MT that have not passed the first verify operation for each state.

[0090] Next, the sequencer 104 determines whether or not the writing of the state to be verified has been completed, that is, whether or not the program has passed, based on the count result of the counter 110 (step S112).

[0091] If the "program pass" is not confirmed in the process of step S112 (step S112, NO), the sequencer 104 checks whether or not "Nloop>NloopMAX" is satisfied (step S113). That is, the sequencer 104 determines whether or not the number of times Nloop, the current program loop, exceeds a predetermined number of loops NloopMAX.

[0092] If "Nloop>NloopMAX" is not satisfied in the process of step S113 (NO in step S113), the sequencer 104 steps up the program voltage VPGM (step S114). Details will be described later with reference to FIG. 14. After that, the sequencer 104 proceeds to the process of step S110. That is, the sequencer 104 executes the next program loop.

[0093] If "Nloop>NloopMAX" is satisfied in the process of step S113 (YES in step S113), the sequencer 104 proceeds to the process of step S115. Also, if a "program pass" is confirmed in the process of step S112 (YES in step S112), that is, if the program pass of all states is detected, the sequencer 104 proceeds to the process of step S115.

[0094] In the process of step S115, the sequencer 104 executes a second verify operation (step S115). The second verify operation is executed after multiple program loop processes (hereinafter, referred to as loop processes) are completed. In the second verify operation of the first embodiment, the same verify voltage as that in the first verify operation is used.

[0095] After the process of step S115, the sequencer 104 updates the status information STS (step S116). In the process of step S116, if the process of "step S112, YES" is executed in this write operation, the sequencer 104 stores information of program status pass in the status register 102A, and if the process of "step S113, YES" is executed, the sequencer 104 stores information of program status fail in the status register 102A. In addition, the sequencer 104 stores the result of the second verify operation in the status register 102A.

[0096] After the process of step S116, the sequencer 104 ends the series of processes in FIG. 13 (END).

[0097] (Detailed operation of memory device MD in write operation) FIG. 14 is a timing chart showing an example of a voltage applied to the selected word line WLsel in a write operation of the memory device MD according to the first embodiment. FIG. 14 shows the respective states of the ready-busy signal RBn and the voltage applied to the selected word line WLsel in a write operation. Note that the voltage of the selected word line WLsel before the start of the write operation is, for example, VSS. Time t0 corresponds to the start time of the write operation of the memory device MD, time t1 corresponds to the start time of the second verify operation, and time t2 corresponds to the end time of the write operation of the memory device MD. As shown in FIG. 11, when the write operation starts, the sequencer 104 transitions the memory device MD from the ready state to the busy state and executes a loop process.

[0098] In a program operation, a program voltage VPGM is applied to a selected word line WLsel. The program voltage VPGM is a high voltage capable of raising the threshold voltage of a memory cell transistor MT. When the program voltage VPGM is applied to the selected word line WLsel, the threshold voltage of the memory cell transistor MT to be programmed increases. The program voltage VPGM is stepped up each time a program loop is repeated, and becomes higher according to the number of program loops that have been executed.

[0099] In the first verify operation, a read operation using a verify voltage is executed. That is, while the verify voltage is being applied, a control signal STB is asserted. Each sense amplifier unit SAU judges whether or not the verify voltage corresponding to the write data held therein has been exceeded. In the verify operation, the type and number of verify voltages applied to the selected word line WLsel are appropriately changed according to the progress of the program loop. For example, in the first program loop, a read operation using a verify voltage V1 is executed.

[0100] When the sequencer 104 detects program passes for all states (S112, YES) or detects that the number of program loops has exceeded a predetermined number (S113, YES), it starts the second verify operation. At the start of the second verify operation, each sense amplifier unit SAU holds the write data referred to in the program loop as is. In the second verify operation, for example, verify voltages V1 to V7 are applied to the selected word line WLsel in order. Then, while each of the verify voltages V1 to V7 is being applied, a control signal STB is asserted, and each sense amplifier unit SAU stores the read result when a verify voltage corresponding to the held write data is applied in one of its internal latch circuits.

[0101] Then, the sequencer 104 executes the process of step S116. After that, the sequencer 104 transitions the memory device MD from the busy state to the ready state. That is, the sequencer 104 updates the status information STS based on the result of the loop process and the result of the second verify operation, and transitions the memory device MD to the ready state.

[0102] (Status read result output by memory device MD) 15 is a table showing an example of a combination of statuses corresponding to the results of a write operation in the memory device MD according to the first embodiment. Below, the status read result output by the memory device MD will be described with reference to FIG.

[0103] The "parameters" in this table include a "program status", a "second verify status", and an "output information (write result)". The "program status" is set to "pass (e.g., data "0")" when the process of "step S112, YES" in FIG. 13 is executed in the write operation, and is set to "fail (e.g., data "1")" when the process of "step S113, YES" in FIG. 13 is executed. The "second verify status" is set to "pass" when all verify operations of the states in which verify reads are executed are passed in the second verify operation, and is set to "fail" when at least one verify operation of the states in which verify reads are executed is failed. In this example, the "output information" corresponds to the result of a logical OR operation of the "program status" and the "second verify status".

[0104] The "status" in this table corresponds to a combination of "parameters", and in this example, there are four types of combinations (1) to (4). (1) in FIG. 15 is a combination in which the "program status" and the "second verify status" are "pass". (2) in FIG. 15 is a combination in which the "program status" is "pass" and the "second verify status" is "fail". (3) in FIG. 15 is a combination in which the "program status" and the "second verify status" are "fail". (4) in FIG. 15 is a combination in which the "program status" is "fail" and the "second verify status" is "pass". Therefore, when a logical OR operation is performed on the "program status" and the "second verify status", the output information of (1), (2), (3), and (4) is "pass", "fail", and "fail", respectively.

[0105] When the memory controller 20 detects by the first status read that the status data corresponding to the output information (write result) stores status fail information, the memory controller 20 registers the block BLK in which the immediately preceding write operation was executed as a bad block in, for example, a management table stored in the RAM 23. Then, the memory controller 20 does not use the block BLK registered as a bad block in subsequent operations.

[0106] [1-3] Effects of the first embodiment The reliability of data can be improved by the memory device MD according to the first embodiment described above. The effects of the memory device MD according to the first embodiment will be described in detail below.

[0107] For example, during a write operation, a memory device executes a program loop including a program operation and a verify operation to raise the threshold voltage of a memory cell to a level corresponding to the write data. However, in rare cases, even if the verify operation of the write operation is passed, a read failure may occur in the subsequent read operation. This may be caused by misjudgment during the verify read operation, over-writing, or the presence of a bit whose on / off state is unstable during the read operation.

[0108] When a read error occurs, a method of preventing data loss may be to use rescue by RAID (Redundant Arrays of Inexpensive Disks). The ability of RAID to rescue data depends on the performance of the memory controller. If RAID cannot rescue data, data loss occurs and the block is registered as a bad block. On the other hand, since the latency decreases when the RAID rescue mode is used, it is preferable to avoid using the RAID rescue mode as much as possible.

[0109] In order to prevent the occurrence of read failures themselves, it is preferable that the memory controller detects bits that may become read failures before the occurrence of a read failure, that is, during a write operation, and registers the blocks that may become failures as bad blocks and does not use them. If a bit that may become failures is detected during a write operation, the memory controller can retry the write operation targeting another block because the write data is held in the RAM of the memory controller or the memory device itself holds a parity bit, and the occurrence of the immediate read failure can be avoided.

[0110] Therefore, the memory device MD according to the first embodiment has a function of detecting in advance bits that may become read failures during a write operation. Briefly, when the memory device MD according to the first embodiment starts a write operation based on an instruction from the memory controller 20, it executes a program loop process multiple times and a second verify operation corresponding to the detection of a read failure. In other words, the memory device MD according to the first embodiment executes a read operation (second verify operation) after the loop process as part of the write operation, and checks whether a read failure occurs. Then, the memory device MD updates the status information STS based on the result of the logical OR operation between the result of the loop process and the result of the second verify operation. After that, the memory controller 20 judges whether the data has been successfully written based on the result of the first status read. In this case, the result of the first status read checked by the memory controller 20 reflects information on whether a read failure may occur immediately after the write operation by the second verify operation.

[0111] As a result, the memory device MD according to the first embodiment can improve the reliability of stored data and suppress the occurrence of read failures. That is, the memory system 1 according to the first embodiment can reduce the frequency of use of the RAID rescue mode and suppress a decrease in the latency of the memory system 1. Furthermore, in the memory system 1 according to the first embodiment, detection of read failures is executed by the memory device MD. That is, the memory system 1 according to the first embodiment can detect read failures during a write operation without increasing the load on the memory controller 20, and therefore the cost of the memory controller 20 can be suppressed.

[0112] [1-4] Modification of the first embodiment Various modifications are possible to the memory system 1 according to the first embodiment. A first modification, a second modification, and a third modification of the first embodiment will be described below in this order.

[0113] (First Modification of the First Embodiment) In the first modification of the first embodiment, the target states for performing the verify read in the second verify operation are limited to some states. For example, the memory device MD according to the first modification of the first embodiment is configured to be able to select the target states for the second verify operation for each page when the data allocation shown in FIG.

[0114] 16 is a table showing an example of a combination of a target page of the second verify operation and a target state of the second verify operation in a write operation of the first modified example of the first embodiment. As shown in FIG. 16, in the first modified example of the first embodiment, for example, an "upper page", a "middle page", and a "lower page" can be selected as the target page of the second verify operation. In this case, as the target states of the second verify operation, when the upper page is selected, the "S3" and "S7" states are selected, when the middle page is selected, the "S2", "S4", and "S6" states are selected, and when the lower page is selected, the "S1" and "S5" states are selected.

[0115] The "second verify status" in the first modified example of the first embodiment is set to "pass" if all verify operations of the states in which verify reads are executed pass in the second verify operation, and is set to "fail" if at least one verify operation of the states in which verify reads are executed fails. The setting of the target page of the second verify operation may be changed or preset based on an instruction from the memory controller 20. This allows the memory device MD according to the first modified example of the first embodiment to selectively execute the second verify operation on pages in which defects are likely to occur, and to omit the second verify operation on pages in which defects occur at a low rate. As a result, the memory device MD according to the first modified example of the first embodiment can reduce the time of the write operation while suppressing a decrease in the accuracy of defect detection due to the second verify operation.

[0116] In the above description, the target state of the second verify operation is set based on a page, but this is not limited to this. The memory device MD may execute the second verify operation on a specific state, regardless of the page. In this case, it is possible to select, for example, the lowest state (e.g., the "S0" state) or the highest state (e.g., the "S7" state) in which defects are likely to occur as the target state of the second verify operation. This allows the memory device MD to detect defects across multiple pages with a minimum number of verify reads.

[0117] (Second Modification of the First Embodiment) In the second modified example of the first embodiment, the verify voltage of the first verify operation and the verify voltage of the second verify operation are set to different voltages. Hereinafter, the verify voltage used in the verify read of the “S(x) (where “x” is an integer equal to or greater than 1)” state in the first verify operation is referred to as “V(x)a”, and the verify voltage used in the verify read of the “S(x)” state in the second verify operation is referred to as “V(x)b”.

[0118] FIG. 17 is a threshold voltage distribution diagram showing an example of the setting of the verify voltage used in the first verify operation and the second verify operation in the write operation of the second modified example of the first embodiment. The vertical axis and the horizontal axis correspond to "NMTs" and "Vth", respectively. FIG. 17 shows the "S(x-1)" and "S(x)" states. As shown in FIG. 17, the verify voltage V(x)a of the "S(x)" state is set between the "S(x-1)" state and the "S(x)" state. In the second modified example of the first embodiment, the verify voltage V(x)b of the "S(x)" state is set to a voltage between the "S(x-1)" state and the "S(x)" state and equal to or higher than the verify voltage V(x)a.

[0119] The setting of the verify voltage V(x)b is given by, for example, a parameter indicating the amount of change with respect to the verify voltage V(x)a. The amount of change of the verify voltage V(x)b with respect to the verify voltage V(x)a may be the same for each state, or may be different. The memory controller 20 can change the setting of the verify voltage V(x)b by a setting change command described later. The setting of the verify voltage V(x)b may be preset in the memory device MD.

[0120] When the verify voltage V(x)b is set high, the conditions for passing the second verify operation become stricter, and the reliability of the data written to the cell unit CU improves. On the other hand, the number of failures in the second verify operation increases due to the deterioration of the memory device MD, and the number of blocks BLK registered as bad blocks tends to increase. In other words, when the verify voltage V(x)b is set high, the reliability of the data improves, and the rate at which the memory capacity decreases due to the deterioration of the memory device MD increases.

[0121] When the verify voltage V(x)b is set low, the conditions for passing the second verify operation are relaxed, and the reliability of the data written to the cell unit CU is lower than when the verify voltage V(x)b is set high. On the other hand, the number of fails in the second verify operation due to deterioration of the memory device MD is reduced, and the number of blocks BLK registered as bad blocks increases more slowly than when the verify voltage V(x)b is set high. In other words, when the verify voltage V(x)b is set low, the reliability of the data is slightly reduced, and the pace of decrease in storage capacity due to deterioration of the memory device MD is slowed.

[0122] In light of the above, it is conceivable that a user may change the verify voltage V(x)b according to the desired specifications of the memory system 1. In other words, in the second modified example of the first embodiment, the user can appropriately change the verify voltage V(x)b, and a memory system 1 with performance that meets the user's desire can be realized.

[0123] (Third Modification of the First Embodiment) In the third modified example of the first embodiment, the number of bits to be ignored in the first verify operation and the number of bits to be ignored in the second verify operation are set to different values. The "number of bits to be ignored" corresponds to the number of memory cell transistors MT that have not passed the verify operation in determining whether the verify operation is passed for each state. Hereinafter, the number of bits to be ignored in the first verify operation is referred to as "Nbd1", and the number of bits to be ignored in the second verify operation is referred to as "Nbd2".

[0124] FIG. 18 is a threshold voltage distribution diagram showing an example of setting the number of ignored bits in a write operation of the third modified example of the first embodiment. The vertical and horizontal axes correspond to "NMTs" and "Vth", respectively. FIG. 18 shows the "S(x-1)" and "S(x)" states. As shown in FIG. 18, when the verify voltage V(x) overlaps with the "S(x)" state, a memory cell transistor MT having a threshold voltage equal to or lower than the verify voltage V(x) in the "S(x)" state is detected as a fail bit FB. The fail bit FB corresponds to a verify fail memory cell transistor MT. Then, in the third modified example of the first embodiment, the number of ignored bits Nbd2 in the second verify operation is set to a value equal to or lower than the number of ignored bits Nbd1 in the first verify operation.

[0125] The setting of the number of ignored bits Nbd2 is given by, for example, a parameter indicating the amount of change relative to the number of ignored bits Nbd1. The amount of change of the number of ignored bits Nbd2 relative to the number of ignored bits Nbd1 may be the same for each state, or may be different. The memory controller 20 can change the setting of the number of ignored bits Nbd2 by a setting change command. The setting of the number of ignored bits Nbd2 may be preset in the memory device MD.

[0126] When the number of ignored bits Nbd2 is set small, the conditions for passing the second verify operation become stricter, and the reliability of the data written to the cell unit CU improves. On the other hand, the number of failures in the second verify operation increases due to the deterioration of the memory device MD, and the number of blocks BLK registered as bad blocks tends to increase. In other words, when the number of ignored bits Nbd2 is set small, the reliability of the data improves, and the rate at which the memory capacity decreases due to the deterioration of the memory device MD increases.

[0127] When the number of ignored bits Nbd2 is set large, the conditions for passing the second verify operation are relaxed, and the reliability of the data written to the cell unit CU is lower than when the number of ignored bits Nbd2 is set small and high. On the other hand, the number of fails in the second verify operation due to deterioration of the memory device MD is reduced, and the number of blocks BLK registered as bad blocks increases more slowly than when the number of ignored bits Nbd2 is set small. In other words, when the number of ignored bits Nbd2 is set large and low, the reliability of the data is slightly reduced, and the pace of decrease in storage capacity due to deterioration of the memory device MD is slowed.

[0128] In light of the above, it is conceivable that the user may change the number of ignored bits Nbd2 according to the desired specifications of the memory system 1. That is, in the third modified example of the first embodiment, the user can appropriately change the number of ignored bits Nbd2, and it is possible to realize a memory system 1 with performance that meets the user's desire.

[0129] [2] Second embodiment The memory system 1 according to the second embodiment has a similar configuration to that of the first embodiment. The memory system 1 according to the second embodiment determines whether or not to execute the second verify operation depending on the address of the string unit SU to be written. The following describes the memory system 1 according to the second embodiment and the differences from the first embodiment.

[0130] [2-1] Write operation flow Fig. 19 is a flowchart showing an example of a write operation of the memory system 1 according to the second embodiment. As shown in Fig. 19, the write operation of the second embodiment has a configuration in which the process of step S102 in the write operation described with reference to Fig. 10 in the first embodiment is replaced with the processes of steps S200 to S202.

[0131] Specifically, similarly to the first embodiment, the memory controller 20 receives write data from the host device 30 (step S100) and determines the write destination (step S101). Then, the memory controller 20 checks whether the write destination is a string unit SU that is the target of the second verify operation (step S200). The string unit SU that is the target of the second verify operation is set in advance by the user. As the string unit SU that is the target of the second verify operation, a string unit SU that is likely to cause defects is selected in the manufacturing process of the memory device MD. Examples of string units SU that are likely to cause defects include string units SU adjacent to slits SLT.

[0132] If the write destination is the target of the second verify operation (step S200, YES), the memory controller 20 executes a write operation including the second verify operation (step S201). After executing the process of step S201, the memory controller 20 proceeds to the process of step S103.

[0133] If the write destination is not the target of the second verify operation (step S200, NO), the memory controller 20 executes a write operation that does not include the second verify operation (step S202). After executing the process of step S202, the memory controller 20 proceeds to the process of step S103.

[0134] The memory device MD distinguishes, for example, between a command for a write operation including the second verify operation for the memory device MD and a command for a write operation not including the second verify operation for the memory device MD by using a prefix command. For example, when the memory controller 20 commands the memory device MD to perform a write operation including the second verify operation, it first transmits a prefix command to the memory device MD, and then transmits a command set for the write operation such as (1) to (3) in FIG. 11 to the memory device MD. Note that the method of distinguishing whether the memory device MD executes the second verify operation may be other methods. The memory device MD may determine whether to execute the second verify operation by referring to the address information ADD.

[0135] In the process of step S103, the memory controller 20 checks whether the status of the write operation is pass (step S103) in the same manner as in the first embodiment. Other operations of the write operation in the second embodiment are the same as those in the first embodiment.

[0136] [2-2] Effects of the second embodiment As described above, the memory device MD according to the second embodiment omits the second verify operation targeted at the string units SU that are assumed to be unlikely to cause read errors in the write operation, and executes the second verify operation targeted at the string units SU that are assumed to be likely to cause read errors. As a result, the memory device MD according to the second embodiment can reduce the time for the second verify operation while suppressing a decrease in data reliability.

[0137] [2-3] Modification of the second embodiment Fig. 20 is a flowchart showing an example of a write operation in the modification of the second embodiment. As shown in Fig. 20, the write operation in the modification of the second embodiment has a configuration in which the process of step S200 in the write operation described with reference to Fig. 19 in the second embodiment is replaced with the process of step S210.

[0138] Specifically, the memory controller 20 receives write data from the host device 30 (step S100) and determines the write destination (step S101) in the same manner as in the first embodiment. Then, the memory controller 20 checks whether the write destination is a layer (word line WL) that is the target of the second verify operation (step S210). The word line WL that is the target of the second verify operation is set in advance by the user. As the word line WL that is the target of the second verify operation, a word line WL that is likely to cause defects in the manufacturing process of the memory device MD is selected. Examples of the word line WL that is likely to cause defects include a word line WL (e.g., word line WL0) close to the bottom of the memory pillar MP and a word line WL (e.g., word lines WL6 and WL7) close to the junction layer JT of the memory pillar MP.

[0139] If the write destination is a target for the second verify operation (step S210, YES), the memory controller 20 executes a write operation including the second verify operation (step S201) as in the second embodiment. If the write destination is not a target for the second verify operation (step S210, NO), the memory controller 20 executes a write operation not including the second verify operation (step S202) as in the second embodiment. Other operations of the write operation of the modified example of the second embodiment are the same as those of the second embodiment.

[0140] As described above, the condition for determining whether to execute the second verify operation in the write operation in the process of step S200 described in the second embodiment may be other conditions. Even in such a case, the memory system 1 according to the modification of the second embodiment can obtain the same effect as the second embodiment.

[0141] [3] Third embodiment The memory system 1 according to the third embodiment has a similar configuration to that of the first embodiment. The memory system 1 according to the third embodiment executes the second verify operation multiple times in the write operation. The following describes the memory system 1 according to the third embodiment and the differences from the first embodiment.

[0142] [3-1] Write operation flow Fig. 21 is a flowchart showing an example of a write operation of the memory device MD according to the third embodiment. As shown in Fig. 21, the write operation of the third embodiment has a configuration in which the process from step S115 onwards in the write operation described with reference to Fig. 13 in the first embodiment is replaced with the process of steps S300 to S302.

[0143] Specifically, the sequencer 104 executes the loop process (steps S110 to S114) in the same manner as in the first embodiment. Then, if the "program pass" is confirmed in the process of step S112 (step S112, YES), or if "Nloop>NloopMAX" is satisfied in the process of step S113 (step S112, YES), the sequencer 104 proceeds to the process of step S300.

[0144] In the process of step S300, the sequencer 104 executes the first second verify operation. The first second verify operation is similar to the second verify operation described in the first embodiment. When the process of step S300 is completed, the sequencer 104 proceeds to the process of step S301.

[0145] In the process of step S301, the sequencer 104 executes the second verify operation for the second time. The second verify operation uses the same verify voltage as the first verify operation. When the process of step S301 is completed, the sequencer 104 proceeds to the process of step S302.

[0146] In the process of step S302, the sequencer 104 updates the status information STS. In the process of step S302, the sequencer 104 stores the result of the first second verify operation and the result of the second second verify operation in the status register 102A. Other information stored in the status register 102A in the process of step S302 is similar to that in step S116 described in the first embodiment.

[0147] In the third embodiment, the result of a logical OR operation between the result of the first second verify operation and the result of the second second verify operation is used as the "second verify status" used in the calculation of the write result. That is, when a verify pass result is obtained at least once by performing the second verify operation multiple times, the sequencer 104 sets the second verify status to "pass".

[0148] After the process of step S302, the sequencer 104 ends the series of processes in FIG. 21 (END). Other operations of the write operation of the third embodiment are similar to those of the first embodiment. Note that the number of times that the memory device MD according to the third embodiment executes the second verify in the write operation is not limited to two times, but may be at least multiple times. In the third embodiment, the sequencer 104 may determine the second verify status based on the results of multiple second verify operations.

[0149] [3-2] Effects of the third embodiment As described above, the memory device MD according to the third embodiment executes the second verify operation multiple times in a write operation, and notifies the memory controller 20 of the status information STS based on the results of the multiple second verify operations. This makes it possible for the memory device MD according to the third embodiment to increase the possibility of detecting that the threshold voltage of the memory cell transistor MT corresponding to an unstable bit exceeds a desired threshold voltage when the verify target is an unstable bit. As a result, the memory device MD according to the third embodiment can suppress the excessive registration of bad blocks, and can suppress the rate of decrease in the storage capacity of the memory device MD.

[0150] [4] Fourth embodiment The memory system 1 according to the fourth embodiment has a similar configuration to that of the first embodiment. In addition, the memory system 1 according to the fourth embodiment retries the second verify operation in the write operation according to the result of the second status read. The following describes the memory system 1 according to the fourth embodiment and the differences from the first embodiment.

[0151] [4-1] Operation (Write operation flow) Fig. 22 is a flowchart showing an example of a write operation of the memory system 1 according to the fourth embodiment. As shown in Fig. 22, the write operation of the fourth embodiment has a configuration in which the process of step S103 is removed and processes of steps S400 to S403 are added to the write operation described with reference to Fig. 10 in the first embodiment.

[0152] Specifically, the memory controller 20 receives write data from the host device 30 (step S100), determines a write destination (step S101), and executes a write operation (step S102) in the same manner as in the first embodiment. Then, the memory controller 20 executes a second status read and checks the status information STS (step S400). In the process of step S400, the memory controller 20 checks which of the multiple status combinations described in the first embodiment with reference to FIG. 15 corresponds to the status information STS obtained by the second status read.

[0153] As shown in FIG. 15(1), when the "program status" and the "second verify status" are both "pass" (step S400, (1)), the memory controller 20 proceeds to the process of step S105.

[0154] If the “program status” and the “second verify status” are each “fail” as in (3) of FIG. 15 (step S400, (3)), or if the “program status” and the “second verify status” are each “fail” and “pass” as in (4) of FIG. 15 (step S400, (4)), the memory controller 20 proceeds to processing of step S104.

[0155] As shown in FIG. 15(2), when the “program status” and the “second verify status” are “pass” and “fail”, respectively (step S400, (2)), the memory controller 20 proceeds to the process of step S401.

[0156] In the process of step S401, the memory controller 20 changes the verify voltage and executes the second verify operation. To change the verify voltage used in the second verify operation, for example, a setting change command described later is used. In the fourth embodiment, when the memory controller 20 commands the memory device MD to execute the second verify operation in step S401, the memory device MD holds the write data received in step S102 as it is. The memory device MD generates a second verify status based on the write data held by each sense amplifier unit SAU and the read result of the second verify operation executed based on the instruction of the memory controller 20, similar to the first embodiment.

[0157] When the process of step S401 is completed, the memory controller 20 reads the status information STS from the memory device MD by the second status read, and checks whether the second verify status is "pass", that is, whether the status is pass (step S402).

[0158] If the status pass is not confirmed in the processing of step S402 (step S402, NO), that is, if the status fail is confirmed, the memory controller 20 registers the block BLK to which the data writing failed as a bad block (step S104), and proceeds to the processing of step S101.

[0159] If the status pass is confirmed in the process of step S402 (step S402, YES), the memory controller 20 sets a correction value of the read voltage for the word line WL on which the write operation was executed based on the changed verify voltage of the second verify operation (step S403). In the fourth embodiment, the verify voltage V(x)b of the second verify operation corresponds to the read voltage of the "S(x)" state. Therefore, the memory controller 20 can change the read voltage of the "S(x)" state according to the voltage value of the verify voltage V(x)b that passed the verify read.

[0160] When the process of step S403 is completed, the memory controller 20 proceeds to the process of step S105. Other operations of the write operation of the fourth embodiment are similar to those of the first embodiment. In the above description, the case where the process of step S401 is executed once has been exemplified, but the memory controller 20 may retry the process of step S401 if the process of step S402 is a status fail. The number of retries of the process of step S401 can be freely determined. The memory device MD executes the second verify operation using a different verify voltage every time the process of step S401 is retried.

[0161] (Command sequence for write operation) 23 is a schematic diagram showing an example of a command sequence in a write operation of the memory system 1 according to the fourth embodiment. Hereinafter, with reference to FIG. 23, an example of a command sequence in a write operation of the radio signal processing unit 1 according to the fourth embodiment will be described.

[0162] The sequence shown in (1) to (4) of Fig. 23 is similar to the sequence in (1) to (4) of Fig. 11. In brief, the memory controller 20 transfers lower page data ((1) of Fig. 23), middle page data ((2) of Fig. 23), and upper page data ((3) of Fig. 23) to the memory device MD, and causes the memory device MD to perform a write operation ((4) of Fig. 23).

[0163] Then, the memory controller 20 executes a second status read, as shown in (5) of FIG. 23. Specifically, the memory controller 20 transmits a command "xxh" to the memory device MD. The command "xxh" is a command associated with the second status read. The memory device MD that receives the command "xxh" transmits the status information "Sout" stored in the status register 102A to the memory controller 20. Then, the memory controller 20 checks the status of the write operation by referring to the status information "Sout" (step S400 of FIG. 22).

[0164] In this example, it is confirmed that the "program status" and the "second verify status" are "pass" and "fail", respectively, in step S400. In this case, the memory controller 20 executes a setting change operation as shown in (6) of FIG. 23. Specifically, the memory controller 20 transmits a command "EFh", address information "ADD2", and setting data "D0h", "D1h", "D2h", and "D3h" to the memory device MD in this order. The command "EFh" is a command associated with the first status read. The address information "ADD2" indicates an address in which parameters corresponding to the verify voltage used in the second verify operation, for example, are stored. The setting data "D0h" to "D3h" in the fourth embodiment include parameters to be applied to the verify voltage used in the second verify operation.

[0165] When the memory device MD receives the address information "ADD2" and the setting data "D0h" to "D3h" after receiving the command "EFh", the memory device MD transitions from the ready state to the busy state. Then, the memory device MD changes the parameters corresponding to the verify voltage used in the second verify operation to the parameters included in the setting data "D0h" to "D3h". When the setting change is completed, the memory device MD transitions from the busy state to the ready state and ends the setting change operation. Note that it is sufficient that the setting data is transmitted in at least one cycle or more, and it is sufficient that the number of cycles is the same as that associated with the command "EFh". The setting change operation can also change other parameters by changing the address and setting data.

[0166] Next, the memory controller 20 executes the second verify operation as shown in (7) of FIG. 23. Specifically, the memory controller 20 transmits a command "yyh", a command "00h", address information "ADD", and a command "30h" to the memory device MD in this order. The command "yyh" is a command instructing the execution of the second verify operation. The command "00h" is a command instructing a read operation. The command "30h" is a command instructing the start of a read operation. The memory device MD that has received these commands etc. transitions to a busy state and executes the second verify operation, and transitions to a ready state when the second verify operation is completed.

[0167] Next, the memory controller 20 executes a second status read, as shown in (8) of Fig. 23. The command sequence of this second status read is the same as that in (5) of Fig. 23.

[0168] (Status information STS obtained by the second status read) FIG. 24 is a table showing an example of status information STS output from the memory device MD in the write operation of the memory system 1 according to the fourth embodiment. As shown in FIG. 24, the status information STS obtained by the second status read of the fourth embodiment includes data indicating the write result, data indicating a program fail (Loop Max), and data indicating the result of the second verify operation. The data indicating the write result is transmitted, for example, via I / O0. The data indicating the program fail is transmitted, for example, via I / O1. For example, data "0" of I / O1 indicates that the program loop has ended within a predetermined number of times, and data "1" of I / O1 indicates that the program loop has not ended within a predetermined number of times. The data indicating the result of the second verify operation is transmitted, for example, via I / O2. For example, data "0" of I / O2 indicates that the second verify operation has failed, and data "1" of I / O2 indicates that the second verify operation has passed. Note that the data indicating the write result may be omitted in the status information STS obtained by the second status read. The allocation of the status information STS to the input / output signals I / O in the second status read may be other allocations.

[0169] [4-2] Effects of the fourth embodiment As described above, in the memory system 1 according to the fourth embodiment, the second status read allows the memory controller 20 to know whether the loop process has failed or the second verify operation has failed. Then, when the memory controller 20 passes the loop process and fails the second verify operation, the memory controller 20 changes the verify voltage used in the second verify operation and retries the second verify operation. Then, depending on the result of the retried second verify operation, the memory controller 20 registers the block BLK as a bad block if the verify fails, and determines a correction value of the read voltage for the word line WL on which the write operation has been performed if the verify passes. This allows the memory system 1 according to the fourth embodiment to use a more appropriate read voltage in the read operation after the write operation, and to suppress the occurrence of read failures. Also, the memory system 1 according to the fourth embodiment can rescue the block BLK that is still usable, and suppress the excessive registration of bad blocks, thereby suppressing the rate of decrease in the storage capacity of the memory device MD.

[0170] [5] Fifth embodiment The memory system 1 according to the fifth embodiment has a similar configuration to that of the first embodiment. In addition, the memory system 1 according to the fifth embodiment performs a second verify operation multiple times by varying the second verify voltage in a write operation. The following describes the memory system 1 according to the fifth embodiment and the differences from the first embodiment.

[0171] [5-1] Operation (Write operation flow) Fig. 25 is a flowchart showing an example of a write operation of the memory system 1 according to the fifth embodiment. As shown in Fig. 25, the write operation of the fifth embodiment has a configuration in which the processes of steps S102 and S103 are excluded and processes of steps S500 to S503 are added to the write operation described with reference to Fig. 10 in the first embodiment.

[0172] Specifically, similarly to the first embodiment, the memory controller 20 receives write data from the host device 30 (step S100) and determines a write destination (step S101). Then, the memory controller 20 executes a write operation including a plurality of second verify operations to which different settings are applied (step S500).

[0173] Next, the memory controller 20 executes a second status read and checks the status information STS (step S501). In the process of step S501, the memory controller 20 checks the results of each of the second verify operations executed multiple times based on the status information STS obtained by the second status read.

[0174] When the "program status" is "pass" and the statuses of the multiple second verify operations are all pass (step S501, all pass), the memory controller 20 proceeds to the process of step S105.

[0175] If the "program status" is "fail", or if the "program status" is "pass" and all the statuses of the multiple second verify operations are fail (step S501, all fail), the memory controller 20 proceeds to the process of step S104.

[0176] If the "program status" is "pass" and at least one of the statuses of the multiple second verify operations is pass (step S501, at least one of the second verify operations is pass), the memory controller 20 proceeds to the process of step S502.

[0177] In the process of step S502, the memory controller 20 checks the setting that has passed the second verify operation. In other words, the memory controller 20 checks how many times the second verify operation has passed from the result of the second status read. When the process of step S502 is completed, the memory controller 20 proceeds to the process of step S503.

[0178] In the process of step S503, the memory controller 20 sets a correction value of the read voltage for the word line WL on which the write operation was executed, according to the confirmation result in step S502. For example, if there is only one second verify operation that has passed the verify, the memory controller 20 sets a correction value of the read voltage based on the verify voltage used in the second verify operation. On the other hand, if there are two or more second verify operations that have passed the verify, the memory controller 20 selects one of the second verify operations that have passed the verify based on a preset priority order. Then, the memory controller 20 sets a correction value of the read voltage based on the verify voltage used in the selected second verify operation.

[0179] When the process of step S503 is completed, the memory controller 20 proceeds to the process of step S105. The other operations of the write operation in the fifth embodiment are similar to those in the first embodiment.

[0180] (Status information STS obtained by the second status read) FIG. 26 is a table showing an example of status information output from the memory device MD in a write operation of the memory system 1 according to the fifth embodiment. As shown in FIG. 26, the status information STS obtained by the second status read of the fifth embodiment includes data indicating a write result, data indicating a program fail (Loop Max), data indicating a result of the first second verify operation, and data indicating a result of the second second verify operation. The data indicating the write result is transmitted, for example, via I / O0. The data indicating a program fail is transmitted, for example, via I / O1. The data indicating the result of the first second verify operation is transmitted, for example, via I / O2. The data indicating the result of the second second verify operation is transmitted, for example, via I / O3. For example, data "0" of each of I / O1 and I / O2 indicates that the second verify operation has failed, and data "1" of each of I / O1 and I / O2 indicates that the second verify operation has passed. Note that the data indicating the write result may be omitted in the status information STS obtained by the second status read.

[0181] (Detailed operation of memory device MD in write operation) Fig. 27 is a timing chart showing an example of a voltage applied to a selected word line WLsel in a write operation of the memory device MD according to the fifth embodiment. As shown in Fig. 27, the write operation of the fifth embodiment is different from the write operation described in the first embodiment with reference to Fig. 14 in that a second verify operation is executed multiple times.

[0182] Specifically, the memory device MD transitions from a ready state to a busy state, executes a loop process, and then executes a first second verify operation and a second second verify operation. In the first second verify operation, for example, verify voltages V1 to V7 are applied in sequence, and the verify results are stored in the corresponding sense amplifier units SAU. In the second second verify operation, for example, verify voltages V1a to V7a higher than the verify voltages V1 to V7 are applied in sequence, and the verify results are stored in the corresponding sense amplifier units SAU. Thereafter, the memory device MD updates the status register 102A, and then transitions from the busy state to the ready state.

[0183] In the fifth embodiment, the first second verify operation and the second second verify operation do not have to be performed in order. For example, after the verify voltage V1 corresponding to the first second verify voltage is applied, the verify voltage V1a corresponding to the second second verify voltage is applied, ..., after the verify voltage V7 corresponding to the first second verify voltage is applied, the verify voltage V7a corresponding to the seventh second verify voltage may be applied. That is, in the memory device MD according to the fifth embodiment, it is only necessary that the read results corresponding to each of the multiple second verify voltages can be stored in the sense amplifier unit SAU, and the order in which the verify voltages are applied is not particularly limited.

[0184] [5-2] Effects of the fifth embodiment As described above, the memory device MD according to the fifth embodiment executes a plurality of second verify operations with different verify voltage settings in a write operation, and notifies the memory controller 20 of the results of each of the plurality of second verify operations by the second status read. Then, the memory controller 20 determines a correction value of the read voltage for the word line WL on which the write operation was performed according to the result of the second status read. In this manner, the memory system 1 according to the fifth embodiment allows the memory controller 20 to grasp each of the results of the plurality of second verify operations. As a result, the memory controller 20 can apply a more appropriate correction value as the read voltage used in the read operation on the word line WL after the write operation. As a result, the memory system 1 according to the fifth embodiment can suppress the occurrence of read failures.

[0185] [6] Other In the second verify operation in the above embodiment, the memory device MD may change the read voltage applied to the selected word line WLsel from a low level to a high level, or from a high level to a low level. If the result of the second verify operation does not change, the order in which the read voltage is applied may be changed as appropriate. In each of the flowcharts referred to in the above embodiment, the order of processing may be changed to the extent possible, or other processing may be added, as long as the same result as that of the corresponding embodiment is obtained. In the above embodiment, the operation in the case where one memory cell transistor MT stores 3-bit data is exemplified, but the operation of each embodiment may also be applied to the case where one memory cell transistor MT stores 2-bit data or 4-bit data or more.

[0186] The command sequence illustrated in the above embodiment is merely an example. For example, each of the commands "01h" to "03h", "xxh", and "yyh" used in the description may be replaced with other commands. The command specifying the read page may be omitted by including page information in the address information ADD. In this specification, a case is illustrated in which the address information ADD transmitted from the memory controller 20 to the memory device MD is one cycle, but the address information ADD may be transmitted in multiple cycles (for example, five cycles).

[0187] In the read operation in the above embodiment, the voltage applied to the selected word line WL is the same as the voltage of the signal line through which the driver circuit 106 supplies voltage to the row decoder module 108. In other words, the voltages applied to various wirings and the period during which the voltages are applied can be roughly known by checking the voltage of the corresponding signal line. When estimating the voltages of the select gate line, word line, etc. from the voltages of each signal line connected to the driver circuit 106, the voltage drop due to the transistors included in the row decoder RD may be taken into consideration. In this case, the voltages of the select gate line and word line are lower than the voltage applied to the corresponding signal line by the voltage drop of the transistor.

[0188] In this specification, elements including the input / output circuit 101, the logic control circuit 103, the sequencer 104, the ready / busy control circuit 105, and the driver circuit 106 may be called a "controller" or a "control circuit." For example, the sequencer 104 may be called a "controller." Each register in the register set 102 may be called a "storage circuit." In this specification, "connected" indicates that the elements are electrically connected, and does not exclude the presence of another element between the two connected elements. In this specification, "off state" indicates that a voltage lower than the threshold voltage of the corresponding transistor is applied to the gate of the transistor, and does not exclude the flow of a minute current, such as a leakage current of the transistor.

[0189] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0190] 1...memory system, 10...memory set, 20...memory controller, 21...CPU, 22...ROM, 23...RAM, 24...ECC circuit, 25...host interface circuit, 26...NAND interface circuit, 30...host device, 40...P-type well region, 41...N-type semiconductor region, 42-46...conductor layer, 50-58...insulating layer, 60...semiconductor layer, 61...laminated film, 62...tunnel insulating film, 63...insulating film, 64...block insulating film, 101...input / output circuit, 102...register set, 102A...status register, 102B...address register, 102C...command register, 103...logic control circuit, 104...sequencer, 105...read busy control circuit, 106... driver circuit, 107... memory cell array, 108... row decoder module, 109... sense amplifier module, 110... counter, MD... memory device, BLK... block, SU... string unit, NS... NAND string, MT... memory cell transistor, ST1, ST2... selection transistor, BL... bit line, WL... word line, SGD, SGS... selection gate line, CG, SGDD, SGSD, USGD, USGS... signal line, IV... inverter, ND1, ND2, SRC... node, RD... row decoder, SAU... sense amplifier unit, T0 to T8, T10, T11, TR0 to TR23... transistor

Claims

1. a plurality of memory cell transistors each storing a plurality of bits of data; a first word line connected to a first plurality of memory cell transistors among the plurality of memory cell transistors; a controller that executes a loop process including a repetition of a program loop including a program operation and a first verify operation; A storage circuit for storing the status information, the controller, in a write operation targeting the plurality of first memory cell transistors, executes a second verify operation after executing the loop process, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verify operation in the memory circuit; Memory device.

2. A plurality of mutually different bits of data are assigned to each of a plurality of states set according to the magnitude of a threshold voltage of a memory cell transistor, and a verify voltage used in a verify read included in a verify operation is set to each of the plurality of states; The controller: In the first verify operation included in the loop process, a verify read is performed for each of the plurality of states; In the second verify operation, a verify read is performed on at least one state among the plurality of states. The memory device of claim 1 .

3. when the controller receives a first status read command from an external memory controller after the write operation, the controller transmits a result of a logical OR operation between the first status data and the second status data to the memory controller as a part of the status information; The memory device of claim 1 .

4. the number of states to be verified read in the second verify operation is equal to the number of states to be verified read in the first verify operation; The memory device of claim 1 .

5. the number of states to be verified in the second verify operation is smaller than the number of states to be verified and read in the first verify operation; The memory device of claim 1 .

6. the first memory cell transistors store a plurality of pages of data respectively corresponding to the plurality of bits of data; a state to be verified in the second verify operation corresponds to a state associated with a read voltage used when reading at least one page data of the plurality of page data; The memory device of claim 5 .

7. the controller is capable of changing a verify voltage used in each state of the second verify operation to a setting different from that of the first verify operation; The memory device of claim 1 .

8. The controller includes: In the first verify operation, a state in which a number of verify fail bits is detected to be equal to or less than a first value in a verify read of each of the plurality of states is determined to be a verify pass; In the second verify operation, a state in which a number of verify fail bits is detected to be equal to or less than a second value in the verify read of each of the plurality of states is determined to be a verify pass; The second value is changeable to a setting different from the first value. The memory device of claim 1 .

9. a plurality of second memory cell transistors included in the plurality of memory cell transistors and connected to the first word line; a plurality of first selection transistors respectively connected to the plurality of first memory cell transistors; a plurality of second selection transistors respectively connected to the plurality of second memory cell transistors; a first selection line connected to the plurality of first selection transistors; a second selection line connected to the plurality of second selection transistors and different from the first selection line; Further equipped with the controller omits the second verify operation after executing the loop process in a write operation targeting the plurality of second memory cell transistors; The memory device of claim 1 .

10. a plurality of third memory cell transistors included in the plurality of memory cell transistors and connected to the plurality of first memory cell transistors, respectively; a second word line connected to the plurality of third memory cell transistors; the controller omits the second verify operation after executing the loop process in a write operation targeting the plurality of third memory cell transistors; The memory device of claim 1 .

11. A memory device according to claim 9 or 10; a memory controller for controlling the memory device; a combination of commands for the memory controller to instruct the memory device to perform a write operation including the second verify operation is different from a combination of commands for the memory controller to instruct the memory device to perform a write operation not including the second verify operation. Memory system.

12. the controller, in the write operation, executes the second verify operation a plurality of times after the loop processing, and when at least one of the results of the plurality of second verify operations is determined to be verify pass, stores information of a status pass as the second status data, and when all of the results are determined to be verify fail, stores information of a status fail as the second status data. The memory device of claim 1 .

13. when the controller receives a second status read command from an external memory controller after the write operation, the controller transmits each of the first status data and the second status data to the memory controller as a part of the status information; The memory device of claim 1 .

14. A memory device according to claim 13; a memory controller for controlling the memory device; the memory controller receives the status information from the memory device after transmitting the second status read command to the memory device, and when it detects that status fail information is stored in the first status data and status pass information is stored in the second status data, it instructs the memory device to execute a second verify operation in which a verify voltage setting is changed. Memory system.

15. When the memory controller detects that information of a status pass is stored in the second status data, the memory controller sets a correction value of a read voltage in a read operation in which the first word line is selected, based on a setting of a verify voltage used in a second verify operation corresponding to the status pass.

15. The memory system of claim 14.

16. the controller, in the write operation, executes a second verify operation a plurality of times using different verify voltages after the loop process, and stores a plurality of second status data indicating respective results of the plurality of second verify operations in the memory circuit; The memory device of claim 1 .

17. when the controller receives a second status read command from an external memory controller after the write operation, the controller transmits the first status data and each of the plurality of second status data to the memory controller as a part of the status information; 17. The memory device of claim 16.

18. A memory device according to claim 17; a memory controller for controlling the memory device; the memory controller receives the status information from the memory device after transmitting the second status read command to the memory device, and when it detects that status fail information is stored in the first status data and status pass information is stored in at least one of the plurality of second status data, sets a correction value of a read voltage in a read operation in which the first word line is selected for the memory device based on a setting of a verify voltage used in the at least one second verify operation. Memory system.

Images