Signal generating device and signal generating method

Abstract

To provide a signal generator and a signal generating method that can achieve 0.1 UI or less of an absolute value of a phase difference among pieces of serial data output from a plurality of transceivers.SOLUTION: A signal generator comprises m transceivers, an usage determination unit 17 that executes first and second usage determination processes for determining usage of each of FIFOs 15 of the transceivers, and a phase adjustment unit 18 for adjusting phases of read-out clock signals of the FIFOs 15. When the number of continuous determination that the usage of the FIFO of each of the transceivers in the first usage determination process is less than an usage threshold reaches a first determination number, the second usage determination process is executed, and further when the number of continuous determination that the usage of the FIFO of each of the transceivers is the usage threshold or more in the second usage determination process reaches a second determination number, the adjustment of the phases of the read-out clock signals is ended.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a signal generating device and a signal generating method, and more particularly to a signal generating device and a signal generating method for converting parallel data into high-speed serial data and outputting the data. [Background technology]

[0002] The speed of Ethernet has increased remarkably in recent years, and the standardization of 800GbE (Gigabit Ethernet) and 1.6TbE (Terabit Ethernet) is in sight. With the development of these high-speed Ethernets, there is a demand for a measurement environment that can measure the bit error rate (BER) to evaluate the quality of communication equipment. It is desirable for such a measurement environment to be able to handle high-speed signals, and also to be able to flexibly respond to changes that accompany changes in the standard policy and changes in development targets. To achieve this, for example, a signal generator that generates test signals can be configured using an FPGA (Field Programmable Gate Array), and a signal generator that can output signals of 128G Symbol / s (1024Gbps) using an FPGA is desirable.

[0003] However, normally, one transceiver channel of an FPGA cannot output a signal at that speed. For this reason, it is necessary to ensure the target signal output rate by serializing the parallel outputs from multiple transceivers using a multiplexer (MUX) or a digital-to-analog converter (DAC) (see, for example, Patent Document 1). At this time, the output data from all transceiver channels must be input to the MUX in a phase-aligned state (see, for example, Patent Document 2). Specifically, it is desirable that the maximum phase difference between all channels is 0.1 UI (Unit Interval) or less. For example, if the output per transceiver channel is 32 Gbps, it is desirable that the time be approximately 3.1 ps or less.

[0004] One way to adjust the phase between channels is to individually control the phase of the external clock input to each channel. However, if the maximum speed of one channel of a transceiver is 32 Gbps, for example, 32 channel outputs are required to achieve a signal output of 1024 Gbps. Since a clock input is required for each of these outputs, there is a risk that the transceiver's IO resources will be insufficient. In addition, since these I / O channels basically need to be close to each other, it may be physically impossible to wire them even for FPGAs with a total of 64 or more channels.

[0005] 8 is a block diagram showing the configuration of a conventional data signal generating device, which uses a MUX to convert parallel data into high-speed serial data and outputs it, as described in Patent Document 1. Data signal generating device 100 includes a synchronizer 120 for properly synchronizing the output timing of parallel data input from data output unit 111 to MUX 113 with the serial conversion operation of MUX 113.

[0006] The synchronization device 120 is composed of a frequency divider 126 that divides a reference clock signal CK1 and outputs a divided clock signal CK2, a phase comparator 121 that compares the phase of a signal A that determines the timing of the serial conversion operation of the MUX 113 with the phase of a data synchronization clock signal CKp from the data output unit 111, a comparison timing instruction unit 122 that instructs the comparison timing of the phase comparator 121 randomly in time, a memory 123 that sequentially stores the voltage Vd of the detection signal detected by the phase comparator 121, an averaging unit 124 that acquires the voltage Vd of the detection signal a predetermined number of times based on the instruction of the comparison timing instruction unit 122 and calculates an average voltage Va of the detection signal, a control unit 125 that generates a control signal corresponding to the average voltage Va, and a variable delay unit 130 that gives a delay of an amount corresponding to the control signal to the reference clock signal CK1 or the divided clock signal CK2.

[0007] That is, the technology disclosed in Patent Document 1 measures the phase difference between signal A, which determines the timing of the serial conversion operation of MUX 113, and data synchronization clock signal CKp from data output unit 111, and adjusts the output timing of parallel data from data output unit 111. Furthermore, in order to reduce the maximum phase difference between channels, it is desirable that the parallel data output from data output unit 111 is input to MUX 113 with its phase adjusted by the automatic phase adjustment method disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6082419 [Patent Document 2] Patent No. 6346212 Summary of the Invention [Problem to be solved by the invention]

[0009] However, the technique disclosed in Patent Document 2 has a problem in that, depending on the magnitude of the maximum phase difference between the channels of the data output unit 111, the phases of the serial data constituting the parallel data output from the data output unit 111 are adjusted to positions shifted by one clock or more from each other. In this case, unintended data is generated when the parallel data is multiplexed using the MUX 113. For example, if this unintended data is used as a test signal for BER measurement, the test signal itself will have an error, making it impossible to perform a correct BER measurement.

[0010] The present invention has been made to solve the above-mentioned problems in the conventional technology, and has an object to provide a signal generating device and a signal generating method that can reduce the absolute value of the phase difference between serial data output from multiple transceivers to 0.1 UI or less. [Means for solving the problem]

[0011] In order to solve the above problems, a signal generating device according to the present invention is a signal generating device comprising: a parallel data output unit that outputs m×N-bit wide parallel data; a transceiver unit that converts the m×N-bit wide parallel data output from the parallel data output unit into m-bit wide parallel data and outputs the converted data; and a phase synchronization control unit that controls a phase of the m-bit wide parallel data output from the transceiver unit, wherein the transceiver unit has m transceivers that convert the N-bit wide parallel data, of the m×N-bit wide parallel data, into 1-bit wide serial data, and each of the transceivers comprises a FIFO that stores the N-bit wide parallel data and from which the N-bit wide parallel data is read out in response to a read clock signal; a PISO that converts the N-bit wide parallel data read out from the FIFO into the 1-bit wide serial data; Usage determination processand a phase adjustment unit that performs a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount, wherein the phase synchronization control unit causes the usage determination unit to execute the first usage amount determination process on condition that output of the serial data from each of the transceivers has started, and the phase synchronization control unit causes the phase adjustment unit to execute the first phase adjustment process on condition that the first usage amount determination process has determined that the usage amount of the FIFO of each of the transceivers is equal to or greater than the usage amount threshold, and the phase synchronization control unit causes the phase adjustment unit to execute the first phase adjustment process on condition that the first usage amount determination process has determined that the usage amount of each of the previous transceivers is equal to or greater than the usage amount threshold. The phase synchronization control unit is configured to cause the phase adjustment unit to execute the second phase adjustment process on condition that the number of times that the usage of the FIFO of the transceiver is consecutively determined to be less than the usage threshold reaches a first determination number, and the phase synchronization control unit is configured to cause the phase adjustment unit to execute the second phase adjustment process on condition that the second usage determination process determines that the usage of the FIFO of each of the transceivers is less than the usage threshold, and the phase synchronization control unit is configured to cause the phase adjustment unit to terminate adjustment of the phase of the read clock signal on condition that the number of times that the usage of the FIFO of each of the transceivers is consecutively determined to be greater than or equal to the usage threshold reaches a second determination number.

[0012] With this configuration, the signal generating device of the present invention executes the second usage determination process on condition that the number of consecutive times that the FIFO usage of each transceiver is determined to be less than the usage threshold by the first usage determination process reaches a first determination number. Furthermore, the signal generating device of the present invention terminates the adjustment of the phase of the read clock signal on condition that the number of consecutive times that the FIFO usage of each transceiver is determined to be equal to or greater than the usage threshold by the second usage determination process reaches a second determination number. With this configuration, the signal generating device of the present invention can reduce the absolute value of the phase difference between the serial data output from each of the multiple transceivers to 0.1 UI or less.

[0013] In the signal generating device according to the present invention, the parallel data output section, the transceiver section, and the phase synchronization control section may be configured on an FPGA.

[0014] With this configuration, the signal generating device of the present invention can easily change the bit width of the parallel data output from the parallel data output section and the number of transceiver channels, thereby enabling it to flexibly respond to future changes and expansions in standards.

[0015] Moreover, the signal generating device according to the present invention may further include a judgment count setting unit that sets the first and second judgment counts in the phase synchronization control unit, and the judgment count setting unit may include: a judgment count provisional setting unit that provisionally sets arbitrary values ​​as the first and second judgment counts in the phase synchronization control unit; a maximum phase difference acquisition unit that acquires a maximum phase difference among the phase differences between the serial data output from the m transceivers when adjustment of the phase of the read clock signal by the phase adjustment unit based on the first and second judgment counts provisionally set by the judgment count provisional setting unit is completed; a memory unit that stores data indicating a relationship between the first and second judgment counts provisionally set by the judgment count provisional setting unit and the maximum phase difference acquired by the maximum phase difference acquisition unit; an approximation curve calculation unit that calculates an approximation curve of the data stored in the memory unit; a judgment count estimation unit that estimates the first and second judgment counts that realize a target maximum phase difference based on the approximation curve; and a judgment count final setting unit that finally sets the first and second judgment counts estimated by the judgment count estimation unit in the phase synchronization control unit.

[0016] With this configuration, the signal generator according to the present invention can estimate the optimal number of judgments by approximating the first and second number of judgments and the measurement result of the maximum phase difference. In this way, the signal generator according to the present invention can estimate the optimal number of judgments, thereby eliminating the need to unnecessarily increase the number of judgments and shortening the time required to complete phase synchronization processing between transceiver channels.

[0017] Furthermore, the signal generating device according to the present invention may further include a multiplexer that receives the m-bit wide parallel data output from the transceiver unit based on a divided clock signal obtained by dividing a reference clock signal by m, and outputs n-bit wide data corresponding to a rate of the reference clock signal; a synchronization device that synchronizes the m-bit wide parallel data output from the transceiver unit with the divided clock signal based on a phase difference between the phase of a data synchronization clock signal synchronized with the m-bit wide parallel data output from the transceiver unit and the phase of the divided clock signal; and a DAC that outputs an analog signal corresponding to the n-bit wide data output from the multiplexer.

[0018] With this configuration, the signal generating device of the present invention reduces the absolute value of the maximum phase difference between the serial data output from each of the multiple transceivers to 0.1 UI or less, making it possible to generate intended serial data when multiplexing the parallel data output from the transceiver units using a MUX.

[0019] Furthermore, a signal generating method according to the present invention is a signal generating method using a signal generating device including a parallel data output unit that outputs parallel data of m×N bits width, a transceiver unit that converts the m×N-bit wide parallel data output from the parallel data output unit into m-bit wide parallel data and outputs the parallel data, and a phase synchronization control unit that controls a phase of the m-bit wide parallel data output from the transceiver unit, wherein the transceiver unit has m transceivers that convert the N-bit wide parallel data, of the m×N-bit wide parallel data, into 1-bit wide serial data, and each of the transceivers includes a FIFO that stores the N-bit wide parallel data and from which the N-bit wide parallel data is read out in response to a read clock signal, a PISO that converts the N-bit wide parallel data read out from the FIFO into the 1-bit wide serial data, and a first phase synchronization control unit that determines whether the usage amount of the FIFO is equal to or greater than a usage amount threshold. Usage determination processand a phase adjustment unit that performs a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount, and the phase synchronization control unit performs a step of causing the usage amount determination unit to execute the first usage amount determination process on condition that output of the serial data from each of the transceivers has started, a step of causing the phase adjustment unit to execute the first phase adjustment process on condition that the first usage amount determination process has determined that the usage amount of the FIFO of each of the transceivers is equal to or greater than the usage amount threshold, and the number of times that it is consecutively determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold reaches a first determination number; the number of times that it is consecutively determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold, the number of times that it is consecutively determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold, the number of times that it is consecutively determined by the second usage determination process that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold reaches a second determination number. Effect of the Invention

[0020] The present invention provides a signal generating device and a signal generating method capable of reducing the absolute value of the phase difference between serial data output from a plurality of transceivers to 0.1 UI or less. [Brief description of the drawings]

[0021] [Figure 1] 1 is a block diagram showing a configuration of a signal generating device according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram showing a configuration of one channel of a transceiver section included in a signal generating device according to an embodiment of the present invention. [Diagram 3]FIG. 4 is a state transition diagram for explaining a phase synchronization process performed by a signal generating device according to an embodiment of the present invention. [Figure 4] 11 is a table showing the relationship between the number of consecutive determinations in phase synchronization processing and the maximum phase difference among m transceivers. [Diagram 5] 11 is a graph showing the relationship between the number of successive determinations in phase synchronization processing and the maximum phase difference among m transceivers. [Figure 6] 4 is a block diagram showing a configuration of a determination count setting unit included in the signal generating device according to the embodiment of the present invention. FIG. [Figure 7] 6 is a graph showing an approximation curve calculated by an approximation curve calculation unit included in the signal generating device according to the embodiment of the present invention, superimposed on the data of FIG. 5. [Figure 8] FIG. 1 is a block diagram showing a configuration of a conventional data signal generating device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a signal generating device and a signal generating method according to the present invention will be described with reference to the drawings.

[0023] 1 includes a data output section 10, a judgment count setting section 32, an inter-channel phase adjustment section 40, a MUX 41, a DAC 42, an operation section 43, a synchronizer 50, and a control section 60. The data output section 10 is configured on, for example, an FPGA or an ASIC, but the following description will be given assuming that these are configured on an FPGA.

[0024] The data output section 10 includes a parallel data output section 11, a transceiver section 12, and a phase synchronization control section 31.

[0025] The parallel data output unit 11 has an internal memory (not shown) that stores a series of data strings of a predetermined pattern in advance, or an arithmetic circuit (not shown) that generates the data strings, and outputs parallel data with a width of m×N bits, where m and N are each an integer of 2 or more.

[0026] The parallel data output unit 11 outputs a PAM signal pattern consisting of, for example, two or more multi-values ​​K (K is an integer of 2 or more) as m×N-bit-wide parallel data based on pattern information input from the operation unit 43. The parallel data output unit 11 generates a PAM signal pattern consisting of any multi-value K, such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), or a PAM8 signal (K=8). Here, the pattern information is information on the pattern of the PAM signal, such as the value of K and the type of pattern (for example, a Pseudo Random Binary Sequence (PRBS) pattern, a Short Stress Pattern Random Quaternary (SSPRQ) pattern, or any pattern).

[0027] The transceiver unit 12 has a clock generating unit 13 that generates a clock signal based on a data request signal A' from the synchronizer 50, and m transceivers 14-1 to 14-m.

[0028] Each of the transceivers 14-1 to 14-m is an output unit of an FPGA, and outputs a digital signal of 0 or 1. Each of the transceivers 14-1 to 14-m is adapted to convert the m×N-bit-wide parallel data output from the parallel data output unit 11 into 1-bit-wide serial data at the timing of the clock signal generated by the clock generation unit 13. That is, the transceiver unit 12 converts the m×N-bit-wide parallel data output from the parallel data output unit 11 into m-bit-wide parallel data Dp and outputs it.

[0029] The transceiver unit 12 is also adapted to output a data synchronous clock signal CKp synchronized with the output timing of the m-bit-wide parallel data Dp. As a configuration for outputting the data synchronous clock signal CKp, for example, a clock recovery circuit (not shown) that generates a recovered clock signal from the parallel data Dp may be provided in the data output unit 10. Alternatively, in addition to the m transceivers 14-1 to 14-m, the transceiver unit 12 may be provided with a clock output transceiver (not shown) that outputs a data synchronous clock signal CKp synchronized with the output timing of the parallel data Dp.

[0030] 2 is a diagram showing the configuration of one channel of the transceiver unit 12. Here, the configuration of the transceiver 14-1 is shown as an example, but the other transceivers 14-2 to 14-m have the same configuration.

[0031] As shown in FIG. 2, each of transceivers 14-1 to 14-m includes a FIFO (First-In First-Out) 15 that stores N-bit parallel data out of the m×N-bit parallel data output from parallel data output unit 11, a Parallel-In Serial-Out (PISO) 16 that converts the N-bit parallel data read from FIFO 15 in response to a read clock signal into 1-bit serial data, a usage determination unit 17 that executes first and second usage determination processes to determine whether the usage of FIFO 15 is equal to or greater than a usage threshold, a phase adjustment unit 18 that adjusts the phase of the read clock signal of FIFO 15 to decrease or increase it, frequency dividers 19 and 20, and a subtractor 21.

[0032] That is, each of the transceivers 14-1 to 14-m reads out the stored parallel data of N-bit width from the FIFO 15, performs parallel / serial conversion on the read parallel data in the PISO 16, and outputs the serial data.

[0033] In the signal generating device 1 of this embodiment, the transceiver unit 12 can be configured with a transceiver equipped with a function for adjusting the phase of a read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TXPI") provided by Xilinx, Inc. Also, for example, an FPGA that configures the data output unit 10 can be suitably used, such as UltraScale+ equipped with a GTY transceiver manufactured by Xilinx, Inc.

[0034] In general, the timing at which multiple transceivers configured on an FPGA actually output data after they are started or reset does not necessarily match one another. Therefore, when the data output starts, the usage amount of the FIFO 15 of each of the transceivers 14-1 to 14-m is usually different. Even when focusing on one transceiver, the usage amount may differ when the data output starts for each start or reset.

[0035] The basic operation of TXPI will be described below with reference to FIG.

[0036] The FIFO 15 functions as a buffer for the parallel data output from the parallel data output unit 11, and is capable of storing up to M words of parallel data with an N-bit width. The FIFO 15 writes or reads parallel data with an N-bit width at the rising edge of an input write clock signal or read clock signal. The write clock signal and read clock signal are, for example, signals based on a clock signal generated by the clock generation unit 13. The clock signal generated by the clock generation unit 13 is distributed to each of the transceivers 14-1 to 14-m. This allows the number of clock inputs to the transceiver unit 12 to be less than the number m of the transceivers 14-1 to 14-m, thereby reducing consumption of IO resources in the transceiver unit 12.

[0037] A frequency divider 19 divides the read clock signal by the maximum word number M of the FIFO 15 to obtain a read address of the FIFO 15. On the other hand, a frequency divider 20 divides the write clock signal by the maximum word number M of the FIFO 15 to obtain a write address of the FIFO 15.

[0038] The subtractor 21 outputs the difference between the read address and the write address output from the frequency dividers 19 and 20. The difference output from the subtractor 21 reflects the amount of usage of the FIFO 15.

[0039] The usage determination unit 17 executes first and second usage determination processes for determining whether or not the difference output from the subtractor 21 is equal to or greater than the usage threshold for each clock of the operation clock of the FPGA that constitutes the data output unit 10. The usage determination unit 17 constantly monitors the difference between the read address and write address of the FIFO 15 as the usage of the FIFO 15, and outputs 0 if the usage is less than the usage threshold and outputs 1 if the usage is equal to or greater than the usage threshold. For example, the usage threshold is M / 2, that is, half the maximum number of words M of the FIFO 15. The usage of the FIFO 15 changes as the phase of the read clock signal changes.

[0040] The phase adjustment unit 18 executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount, and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount. The first phase adjustment process is a process for decreasing the usage of the FIFO 15, and the second phase adjustment process is a process for increasing the usage of the FIFO 15.

[0041] Phase adjustment unit 18 can shift the read address value of FIFO 15 by adjusting the phase of the read clock signal of FIFO 15. This shifts the phase of the parallel data output from FIFO 15. However, phase adjustment unit 18 cannot adjust the phase of the parallel data output from FIFO 15 to an arbitrary value, and the phase adjustment width that can be adjusted at one time is also limited. For example, when the output data rate of each of transceivers 14-1 to 14-m is 32 Gbps, the phase adjustment width that phase adjustment unit 18 can adjust is 1 / 64 UI step width.

[0042] 3, a description will be given of the phase synchronization process of the phase synchronization control unit 31 that controls the phase of the m-bit parallel data Dp output from the transceiver unit 12. The phase synchronization process of the phase synchronization control unit 31 is executed independently for each channel, i.e., for each transceiver 14-1 to 14-m.

[0043] 3, the phase synchronization control unit 31 includes eight states S1 to S7, namely, an initial state, a PRESET state, a BUFCHK1 state, a TXPI_DEC state, a TXPI_INC state, a BUFCHK2 state, and a PHASEADJ state. The arrows between the states indicate the transitions and their directions.

[0044] First, the phase synchronization control unit 31 transitions from the initial state S1 to a PRESET state S2. The PRESET state S2 is a standby state until each of the transceivers 14-1 to 14-m starts outputting serial data. Here, each of the transceivers 14-1 to 14-m starts generating a clock in a clock generation circuit (not shown) when it becomes possible to start outputting serial data after startup or resetting. The phase synchronization control unit 31 can detect the rising edge of this clock to detect the timing at which each of the transceivers 14-1 to 14-m starts outputting serial data.

[0045] When the phase synchronization control unit 31 detects that each of the transceivers 14-1 to 14-m has started outputting serial data, the phase synchronization control unit 31 transitions from the PRESET state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the phase synchronization control unit 31 causes the usage determination unit 17 to execute a first usage determination process.

[0046] The phase synchronization control unit 31 transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 on the condition that the first usage determination process determines that the usage of the FIFO 15 of each of the transceivers 14-1 to 14-m is equal to or greater than the usage threshold. The TXPI_DEC state S4 is a state in which the phase synchronization control unit 31 causes the phase adjustment unit 18 to execute the first phase adjustment process.

[0047] The phase synchronization control unit 31 transitions from the TXPI_DEC state S4 back to the BUFCHK1 state S3 on the condition that the phase of the read clock signal of the FIFO 15 of each of the transceivers 14-1 to 14-m is decreased by a predetermined amount by the first phase adjustment process.

[0048] The phase synchronization control unit 31 transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 on the condition that the number of consecutive times that the usage of the FIFO 15 of each of the transceivers 14-1 to 14-m is determined to be less than the usage threshold by the first usage determination process reaches the first determination number. The TXPI_INC state S5 is a state in which the phase synchronization control unit 31 causes the phase adjustment unit 18 to execute the second phase adjustment process.

[0049] The phase synchronization control unit 31 transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the FIFO 15 of each of the transceivers 14-1 to 14-m is increased by a predetermined amount by the second phase adjustment process. The BUFCHK2 state S6 is a state in which the phase synchronization control unit 31 causes the usage determination unit 17 to execute the second usage determination process.

[0050] The phase synchronization control unit 31 transitions from the BUFCHK2 state S6 back to the TXPI_INC state S5 on the condition that it is determined by the second usage determination process that the usage of the FIFO 15 of each of the transceivers 14-1 to 14-m is less than the usage threshold.

[0051] The phase synchronization control unit 31 transitions from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of consecutive times that the usage of the FIFO 15 of each of the transceivers 14-1 to 14-m is determined to be equal to or greater than the usage threshold value by the second usage determination process reaches the second determination number. The PHASEADJ state S7 is a state in which the phase synchronization control unit 31 causes the phase adjustment unit 18 to finish adjusting the phase of the read clock signal, and waits until a reset signal is input to the transceivers 14-1 to 14-m.

[0052] 3 for all transceivers 14-1 to 14-m, the phase synchronization control unit 31 can halve the usage of the FIFO 15 of all channels, thereby aligning the data latency of all channels. Since the phase of the m×N-bit parallel data output from the parallel data output unit 11 is the same for all channels, the phase of the serial data output from each transceiver 14-1 to 14-m is also aligned to approximately the same phase.

[0053] 3, when the phase adjustment width by phase adjustment unit 18 is 1 / 64 UI, the phase of the serial data output from each of transceivers 14-1 to 14-m can be adjusted with a calculated accuracy of ±0.008 UI (theoretical limit value). Note that the first and second determination times may be the same or different from each other.

[0054] 3, if the transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4, the transition from the BUFCHK2 state S6 to the TXPI_INC state S5, the transition from the BUFCHK1 state S3 to the TXPI_INC state S5, and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7 are executed if the respective judgment conditions are satisfied once, the maximum phase difference between the serial data output from the m transceivers 14-1 to 14-m after the completion of the phase adjustment becomes a value larger than the theoretical limit value. This is considered to be because the usage of the FIFO 15 is constantly fluctuating due to the jitter components of the write clock signal and the read clock signal, and therefore the judgment results of the first and second usage judgment processes by the usage judgment unit 17 also fluctuate.

[0055] Therefore, in the signal generating device 1 of this embodiment, in the processing of the phase synchronization control unit 31 shown in Figure 3, for the transition from the BUFCHK1 state S3 to the TXPI_INC state S5 and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7, the first and second judgment numbers that must be consecutively satisfied for the transition condition are specified, and the transition is executed only when the transition condition is satisfied for those consecutive numbers of times.

[0056] The interval at which the usage determination unit 17 executes the first and second usage determination processes depends on the operating clock frequency of the FPGA in which the data output unit 10 is configured. For example, when the operating clock frequency of the FPGA is 125 MHz, and the first and second usage determination processes are executed at 8 ns intervals, FIG. 4 shows a table showing the relationship between the number of consecutive determinations and the maximum phase difference between the m transceivers 14-1 to 14-m, and FIG. 5 shows a graph of the relationship. Here, it is assumed that the first and second determination numbers are equal, and for example, the number of consecutive determinations is 1000 means that the first determination number is 1000 and the second determination number is also 1000. In addition, the output data rate of each of the transceivers 14-1 to 14-m at this time is 32 Gbps per channel. From the results shown in FIG. 4 and FIG. 5, it can be seen that there is a correlation between the number of consecutive determinations and the maximum phase difference, and that the absolute value of the maximum phase difference is less than 0.1 UI under the condition that the number of consecutive determinations is 8000 or more.

[0057] In addition, when the transition condition is no longer satisfied in the first or second usage determination process while the number of consecutive determinations has not been reached, the phase synchronization control unit 31 resets the count of the number of consecutive determinations. For example, when the first usage determination process in the BUFCHK1 state S3 determines that the usage of the FIFO 15 of the transceivers 14-1 to 14-m is equal to or greater than the usage threshold before the first determination count is reached, the phase synchronization control unit 31 resets the count of the first determination count and transitions to the TXPI_DEC state S4. Similarly, when the second usage determination process in the BUFCHK2 state S6 determines that the usage of the FIFO 15 of the transceivers 14-1 to 14-m is less than the usage threshold before the second determination count is reached, the phase synchronization control unit 31 resets the count of the second determination count and transitions to the TXPI_INC state S5.

[0058] For this reason, even when the number of consecutive determinations is 65535, the time required for the first and second phase adjustment processes by the phase adjustment unit 18 to be completed is a maximum of about 50 ms, and there is little time disadvantage in increasing the number of consecutive determinations. Therefore, in this example, by providing a margin and setting the number of consecutive determinations to 10000 or more, it is possible to more reliably achieve phase adjustment between channels such that the absolute value of the required maximum phase difference is 0.1 UI or less.

[0059] Furthermore, if it is necessary to further shorten the time of about 50 ms required to complete the first and second phase adjustment processes, in this example, by setting the number of consecutive judgments to between 5,000 and 10,000, the maximum phase difference can be effectively reduced compared to the time required for the first and second phase adjustment processes.

[0060] 1 and the like is configured to set a first and a second judgment count in the phase synchronization control unit 31. For example, as shown in FIG. 6, the judgment count setting unit 32 may include a judgment count tentative setting unit 33, a maximum phase difference acquisition unit 34, a storage unit 35, an approximation curve calculation unit 36, a judgment count estimation unit 37, and a judgment count final setting unit 38.

[0061] The provisional determination count setting unit 33 provisionally sets arbitrary values ​​as the first and second determination counts in the phase synchronization control unit 31. For example, in the example shown in Fig. 4 and Fig. 5, any of 10, 100, 1000, 5000, 8000, 10000, and 65535 is set as the first and second determination counts. As a result, the phase synchronization control unit 31 executes the process shown in Fig. 3 based on the provisionally set first and second determination counts.

[0062] The maximum phase difference acquisition unit 34 is configured to acquire the maximum phase difference among the phase differences between the serial data output from the m transceivers 14-1 to 14-m when the adjustment of the phase of the read clock signal by the phase adjustment unit 18 based on the first and second judgment counts set by the judgment count temporary setting unit 33 is completed (PHASEADJ state S7).

[0063] For example, the maximum phase difference acquisition unit 34 may acquire the maximum phase difference from among the phase differences obtained from a measuring device (not shown) such as an oscilloscope that measures the phase difference between the serial data output from each of the m transceivers 14-1 to 14-m.

[0064] The storage section 35 is configured to store data indicating the relationship between the first and second judgment counts provisionally set by the judgment count provisional setting section 33 and the maximum phase difference acquired by the maximum phase difference acquisition section 34.

[0065] The approximation curve calculation section 36 calculates an approximation curve of the data stored in the storage section 35 .

[0066] Hereinafter, a method for calculating an approximate curve by the approximate curve calculation unit 36 ​​will be described using the data in FIG. 4 and FIG. 5 as an example.

[0067] As shown in the graph in Figure 5, the reason why the maximum phase difference decreases as the number of consecutive judgments increases is thought to be that the fluctuation in the usage amount of FIFO15 caused by the jitter components of the write clock signal and the read clock signal is canceled out as the number of consecutive judgments increases.

[0068] Clock jitter components are roughly divided into the time axis direction and the voltage axis direction. Generally, the jitter component in the time axis direction is larger in terms of the amount of jitter and has a larger impact, so we will first focus on the jitter component in the time axis direction. The jitter component in the time axis direction is given by Tj / Tbit, the ratio of the amount of jitter in the time axis direction per 1 bit of the clock, Tj, to the interval of 1 bit, Tbit.

[0069] Here, we assume that the jitter component in the time axis direction follows an ideal distribution (normal distribution). If the clock jitter component has a distribution close to the normal distribution, we can infer that the relationship between the number of consecutive decisions and the maximum phase difference will also be close to the normal distribution.

[0070] Fig. 7 is a graph in which an approximation curve 39 calculated by the approximation curve calculation unit 36 ​​based on data showing the relationship between the number of consecutive judgments and the maximum phase difference stored in the storage unit 35 is superimposed on the data in Fig. 5. The horizontal line at the bottom of the figure indicates the theoretical limit value of ±0.008 UI. Here, the approximation curve 39 shown in Fig. 7 is a graph of the standard normal distribution to which coefficients α and β have been added, as shown in the following formula (1).

[0071]

number

[0072] First, the approximation curve calculation unit 36 ​​calculates the coefficient α in the formula (1). The coefficient α is 0.55 (=0.22 / 0.4), which is the ratio between 0.22 UI, which is the absolute value of the maximum phase difference when the number of continuous judgments is 10, and 0.4, which is the y-axis value of the apex of the standard normal distribution graph.

[0073] Moreover, the approximation curve calculation unit 36 ​​calculates the coefficient β in the formula (1) as follows: In the graph of Fig. 5, the data point closest to ±0.11 UI, which is half the maximum phase difference of ±0.22 UI when the number of continuous judgments is 10, is the point when the number of continuous judgments is 5000 and the maximum phase difference is ±0.13 UI.

[0074] The approximation curve calculation unit 36 ​​extracts data points of maximum phase difference in the range of 1 / 10 to 10 / 1 of 5000 consecutive judgments, i.e., 500 to 50000, and obtains an approximation line of these data points. The approximation line obtained at this time is y=-0.00001326x+0.18206522. The coefficient β in formula (1) is a value for adjusting the approximation curve of formula (1) so that it is tangent to the approximation line y=-0.00001326x+0.18206522 at y=0.11.

[0075] As shown in Figure 7, the data in Figure 5 is close to the shape of a standard normal distribution curve, so it can be confirmed that the relationship between the number of consecutive judgments and the maximum phase difference shown in Figure 5 reflects the jitter components of the write clock signal and the read clock signal.

[0076] Next, we will discuss the jitter component in the voltage direction. In Figure 7, the data points after 65,535 consecutive judgments, where the jitter component in the time direction is no longer dominant, are affected by the theoretical limit value and are not thought to asymptotically approach 0 as in the graph of approximation curve 39. In other words, the difference between approximation curve 39 based on this standard normal distribution and the data points of the maximum phase difference after 65,535 consecutive judgments is due to the jitter component in the voltage direction and the theoretical limit.

[0077] 6, the judgment count estimation unit 37 estimates the number of consecutive judgments or the first and second judgment counts for realizing a target maximum phase difference, based on the approximation curve 39 calculated by the approximation curve calculation unit 36. For example, the target maximum phase difference may be set by a user's operation input to the operation unit 43 within a range that satisfies the maximum phase difference of ±0.1 UI.

[0078] For example, the judgment count estimation unit 37 can estimate the optimal number of consecutive judgments by determining an intersection point between the theoretical limit value and the approximation curve 39, or an intersection point between another target maximum phase difference value and the approximation curve 39. In this way, by determining the optimal number of consecutive judgments by the judgment count estimation unit 37, it becomes unnecessary to increase the number of consecutive judgments unnecessarily, and it becomes possible to shorten the time required for the phase synchronization control unit 31 to complete the phase synchronization process as shown in the state transition diagram of FIG.

[0079] 4 and 5, the time required for the phase synchronization control unit 31 to complete the phase synchronization process was approximately 50 ms at most, but this was a value under the condition that the FPGA operating clock frequency was 125 MHz. Even under conditions where operation at a lower operating clock frequency is forced due to device or power constraints, the signal generating device 1 of this embodiment can realize phase synchronization between channels in the minimum time by estimating the number of consecutive judgments using the approximation curve 39 as described above.

[0080] Alternatively, the judgment count setting unit 32 may set the first and second judgment counts or the consecutive judgment count input by the user via the operation unit 43 to the phase synchronization control unit 31 within a range that can realize a maximum phase difference of ±0.1 UI. For example, in the examples of Figs. 4 and 5, the user may be able to freely set the consecutive judgment count in the judgment count setting unit 32 within a range from 8000 times to 65535 times.

[0081] The judgment count setting unit 38 is configured to finally set, in the phase synchronization control unit 31, the first and second judgment counts or consecutive judgment counts input by the user via the operation unit 43, or the first and second judgment counts or consecutive judgment counts estimated by the judgment count estimation unit 37.

[0082] Returning to FIG. 1, the configuration and function of the inter-channel phase adjustment unit 40 are the same as those of the error rate measurement device described in Japanese Patent No. 6346212. That is, the inter-channel phase adjustment unit 40 in this embodiment changes the phase of the clock signal CK3 input from the outside by m phase changers (not shown) corresponding to the number of channels of the transceivers 14-1 to 14-m, and punches out the serial data output from each of the transceivers 14-1 to 14-m for each channel at the timing of the changed clock signal. The phase amount of each phase changer is adjusted based on the center position of the opening of the eye pattern for each channel of the serial data output from each of the transceivers 14-1 to 14-m. Since the absolute value of the maximum phase difference between the serial data output from each of the transceivers 14-1 to 14-m is reduced to 0.1 UI or less, the inter-channel phase adjustment unit 40 can align the phase of the serial data constituting the parallel data Dp output from the transceiver unit 12 in all channels. As the clock signal CK3, the clock signal CK1 or the data request signal A' may be used.

[0083] The configuration and functions of the MUX 41 are the same as those of the multiplexer described in, for example, Japanese Patent No. 6082419. That is, the MUX 41 in this embodiment latches the m-bit parallel data Dp output from the transceiver unit 12 via the inter-channel phase adjustment unit 40, selects n bits at a time in a predetermined order in synchronization with a high-speed reference clock signal CK1, and outputs it as n-bit data Ds according to the rate of the reference clock signal CK1. Here, n is an integer equal to or greater than 1. That is, the MUX 41 can multiplex the m-channel output from the transceiver unit 12 into n channels.

[0084] Moreover, MUX41 divides the reference clock signal CK1 by m to generate a divided clock signal A, and outputs the generated divided clock signal A to the synchronizer 50. The divided clock signal A is a data request signal for requesting the next parallel data Dp from the transceiver unit 12 every time MUX41 outputs m pieces of data. The divided clock signal A also determines the operation timing of the serial conversion process of MUX41.

[0085] The configuration and functions of the synchronizer 50 are similar to those of the synchronizer described in Japanese Patent No. 6082419. That is, the synchronizer 50 in this embodiment measures the phase difference between the phase of the frequency-divided clock signal A output from the MUX 41 and the phase of the data synchronous clock signal CKp output from the transceiver unit 12 in synchronization with the output timing of the m-bit-wide parallel data Dp, and adjusts the output timing of the parallel data Dp from the transceiver unit 12 based on the measured phase difference.

[0086] For example, the synchronizer 50 adjusts the timing of the divided clock signal CK2 (see FIG. 8) of the reference clock signal CK1 in accordance with the phase difference between the divided clock signal A and the data synchronization clock signal CKp to generate a data request signal A', and outputs the data request signal A' to the transceiver unit 12. In this way, the synchronizer 50 can synchronize the m-bit parallel data Dp output from the transceiver unit 12 with the divided clock signal A.

[0087] The data output unit 10 in this embodiment can output parallel data Dp in which the absolute value of the maximum phase difference between channels is 0.1 UI or less. Therefore, when the MUX 41 multiplexes the parallel data Dp output from the transceiver unit 12 via the inter-channel phase adjustment unit 40, unintended data is not generated.

[0088] The DAC42 is an n-bit DAC, and outputs an analog signal corresponding to the n-bit width data Ds output from the MUX41, that is, a multi-value K PAM signal. The MUX41 and the DAC42 may be separate entities, or may be integrated. For example, when the signal generating device 1 of the present embodiment serializes 32 lines of 32 Gbps serial data output from each channel of the transceiver unit 12 via the inter-channel phase adjustment unit 40 using the MUX41 and the DAC42, it can generate an analog signal of 128 G Symbol / s (1024 Gbps), and can generate a signal desirable as a test signal for BER measurement.

[0089] The operation unit 43 is for accepting operation input by the user, and is configured, for example, as a touch panel equipped with a touch sensor for detecting a contact position by a touch operation on an input surface corresponding to a display screen of the display device. Alternatively, the operation unit 43 may be configured to include an input device such as a keyboard or a mouse. The operation input to the operation unit 43 is detected by the control unit 60. For example, the operation unit 43 allows the user to arbitrarily set the pattern information to be input to the parallel data output unit 11, the target maximum phase difference, the first and second judgment counts or the consecutive judgment counts, and the like.

[0090] The control unit 60 is composed of, for example, a microcomputer or a personal computer including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and a HDD (Hard Disk Drive), and controls the operation of each of the above-mentioned components constituting the signal generating device 1 in accordance with a program pre-stored in the ROM.

[0091] As described above, the signal generating device 1 according to the present embodiment executes the second usage amount judgment process on the condition that the number of consecutive times that the usage amount of the FIFO 15 of each of the transceivers 14-1 to 14-m is judged to be less than the usage amount threshold by the first usage amount judgment process reaches the first judgment number. Furthermore, the signal generating device 1 according to the present embodiment ends the adjustment of the phase of the read clock signal on the condition that the number of consecutive times that the usage amount of the FIFO 15 of each of the transceivers 14-1 to 14-m is judged to be equal to or greater than the usage amount threshold by the second usage amount judgment process reaches the second judgment number. With this configuration, the signal generating device 1 according to the present embodiment can reduce the absolute value of the maximum phase difference between the serial data output from each of the transceivers 14-1 to 14-m to 0.1 UI or less.

[0092] For example, when the output of one channel of the transceivers 14-1 to 14-m of the FPGA constituting the data output unit 10 is 32 Gbps, if no phase adjustment of the read clock signal is performed, the maximum phase difference between the channels will be about ±500 ps, ​​or ±8 UI. In contrast, if the phase synchronization process of the phase synchronization control unit 31 shown in the state transition diagram of Figure 3 is used, the maximum phase difference between the channels can be reduced to about ±0.02 UI.

[0093] Furthermore, in the signal generating device 1 according to this embodiment, since the data output unit 10 is configured on an FPGA, the bit width of the parallel data output from the parallel data output unit 11 and the number of channels m of the transceivers 14-1 to 14-m can be easily changed, so that the signal generating device 1 can flexibly respond to future changes and extensions to standards.

[0094] Moreover, the signal generating device 1 according to the present embodiment can estimate the optimal number of judgments by approximating the first and second number of judgments and the measurement result of the maximum phase difference. In this way, the signal generating device 1 according to the present embodiment can estimate the optimal number of judgments, thereby eliminating the need to unnecessarily increase the number of judgments and shortening the time required to complete phase synchronization processing between transceiver channels.

[0095] Furthermore, in the signal generating device 1 according to this embodiment, the absolute value of the maximum phase difference between the serial data output from each of the transceivers 14-1 to 14-m is reduced to 0.1 UI or less, so that it is possible to prevent the phase between these serial data from being adjusted to a position shifted by one clock or more in the inter-channel phase adjusting unit 40. As a result, the signal generating device 1 according to this embodiment can generate intended serial data when multiplexing the parallel data output from the inter-channel phase adjusting unit 40 using the MUX 41. [Explanation of symbols]

[0096] 1. Signal Generator 10 Data output section 11 Parallel data output section 12 Transceiver section 13 Clock Generation Unit 14-1~14-m transceiver 15 FIFO 16 PISO 17 Usage amount determination section 18 Phase adjustment section 19,20 frequency divider 21 Subtractor 31 Phase synchronization control section 32 Judgment count setting section 33. Temporary setting unit for number of judgments 34 Maximum phase difference acquisition section 35 Storage section 36 Approximate curve calculation section 37 Judgment Number Estimation Unit 38 Number of judgments setting section 39 Approximate curve 40 Inter-channel phase adjustment section 41 MUX 42 DAC 43 Operation section 50 Synchronization Device 60 Control section

Claims

1. A parallel data output unit (11) that outputs parallel data having a width of m×N bits; a transceiver unit (12) that converts the m×N-bit parallel data output from the parallel data output unit into m-bit parallel data and outputs the converted data; a phase synchronization control unit (31) for controlling a phase of the m-bit parallel data output from the transceiver unit, the transceiver unit has m transceivers (14-1 to 14-m) that convert the parallel data of N bits of the m×N-bit width into serial data of 1 bit width, Each of the transceivers is a FIFO (15) for storing the N-bit parallel data and for reading the N-bit parallel data in response to a read clock signal; a PISO (16) that converts the N-bit parallel data read from the FIFO into the 1-bit serial data; a usage amount determination unit (17) that executes a first usage amount determination process and a second usage amount determination process to determine whether or not the usage amount of the FIFO is equal to or greater than a usage amount threshold; a phase adjustment unit (18) that executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount, and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, the phase synchronization control unit causes the usage determination unit to execute the first usage determination process on condition that output of the serial data from each of the transceivers has started; the phase synchronization control unit causes the phase adjustment unit to execute the first phase adjustment process on condition that it is determined by the first usage determination process that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold; the phase synchronization control unit causes the usage determination unit to execute the second usage determination process on condition that a number of consecutive times that the usage of the FIFO of each of the transceivers is determined to be less than the usage threshold value by the first usage determination process has reached a first determination number; the phase synchronization control unit causes the phase adjustment unit to execute the second phase adjustment process on condition that it is determined by the second usage amount determination process that the usage amount of the FIFO of each of the transceivers is less than the usage amount threshold; a phase synchronization control unit that causes the phase adjustment unit to terminate adjustment of the phase of the read clock signal on the condition that the number of consecutive times that the usage of the FIFO of each of the transceivers is determined to be equal to or greater than the usage threshold value by the second usage determination process reaches a second determination number.

2. 2. The signal generating device according to claim 1, wherein the parallel data output section, the transceiver section, and the phase synchronization control section are configured on an FPGA (Field Programmable Gate Array).

3. A determination count setting unit (32) that sets the first and second determination counts in the phase synchronization control unit, The determination count setting unit is a provisional determination count setting unit (33) for provisionally setting arbitrary values ​​as the first and second determination counts in the phase synchronization control unit; a maximum phase difference acquisition unit (34) that acquires a maximum phase difference among phase differences between the serial data output from the m transceivers when adjustment of the phase of the read clock signal by the phase adjustment unit based on the first and second judgment counts provisionally set by the judgment count provisional setting unit is completed; a storage unit (35) that stores data indicating a relationship between the first and second judgment counts provisionally set by the judgment count provisional setting unit and the maximum phase difference acquired by the maximum phase difference acquisition unit; an approximation curve calculation unit (36) for calculating an approximation curve of the data stored in the storage unit; a judgment number estimation unit (37) that estimates the first and second judgment numbers that realize the target maximum phase difference based on the approximation curve; 3. The signal generating device according to claim 1, further comprising: a decision count final setting unit (38) that finally sets the first and second decision counts estimated by the decision count estimation unit in the phase synchronization control unit.

4. a multiplexer (41) that receives the m-bit parallel data output from the transceiver unit based on a frequency-divided clock signal obtained by dividing a reference clock signal by m, and outputs n-bit data according to a rate of the reference clock signal; a synchronization device (50) that synchronizes the m-bit-wide parallel data output from the transceiver unit with the divided clock signal based on a phase difference between a phase of a data synchronous clock signal synchronized with the m-bit-wide parallel data output from the transceiver unit and a phase of the divided clock signal; 3. The signal generating device according to claim 1, further comprising: a DAC (42) that outputs an analog signal corresponding to the n-bit width data output from the multiplexer.

5. A parallel data output unit (11) that outputs parallel data having a width of m×N bits; a transceiver unit (12) that converts the m×N-bit parallel data output from the parallel data output unit into m-bit parallel data and outputs the converted data; a phase synchronization control unit (31) for controlling a phase of the m-bit parallel data output from the transceiver unit, the transceiver unit has m transceivers (14-1 to 14-m) that convert the parallel data of N bits of the m×N-bit width into serial data of 1 bit width, Each of the transceivers is a FIFO (15) for storing the N-bit parallel data and for reading the N-bit parallel data in response to a read clock signal; a PISO (16) that converts the N-bit parallel data read from the FIFO into the 1-bit serial data; a usage amount determination unit (17) that executes a first usage amount determination process and a second usage amount determination process to determine whether or not the usage amount of the FIFO is equal to or greater than a usage amount threshold; a phase adjustment unit (18) that executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount, and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, The phase synchronization control unit includes: a step (S3) of causing the usage amount determining unit to execute the first usage amount determining process on the condition that output of the serial data from each of the transceivers has started; a step (S4) of causing the phase adjustment unit to execute the first phase adjustment process on condition that it is determined by the first usage determination process that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold; a step (S6) of causing the usage determination unit to execute the second usage determination process on condition that the number of consecutive times that the usage of the FIFO of each of the transceivers is determined to be less than the usage threshold value by the first usage determination process has reached a first determination number; a step (S5) of causing the phase adjustment unit to execute the second phase adjustment process on condition that it is determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold; and a step (S7) of causing the phase adjustment unit to terminate adjustment of the phase of the read clock signal on condition that the number of consecutive times that the usage of the FIFO of each of the transceivers is determined to be equal to or greater than the usage threshold value by the second usage determination process reaches a second determination number.

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