Pulse receiving circuit, signal transmission device

Abstract

A pulse receiving circuit 221 configuring a signal transmission device 200 comprises: a first pulse detector 221E which receives a differential input between a first received pulse signal S3 (= internal signal s21) appearing in a secondary winding 231s of a first transformer 231 and a second received pulse signal S4 (= internal signal s22) appearing in a secondary winding 232s of a second transformer 232; a second pulse detector 221F which receives a differential input between a first received pulse signal S3 and a second received pulse signal S4 with an input polarity opposite to that of the first pulse detector 221E; and a logic unit 221H which generates a received pulse signal S5 on the basis of the respective output signals s23 and s24 of the first pulse detector 221E and the second pulse detector 221F.

Description

[Technical field]

[0001] The invention disclosed herein relates to a pulse receiving circuit and a signal transmission device. [Background technology]

[0002] 2. Description of the Related Art Signal transmission devices that transmit pulse signals while electrically insulating input and output have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] As an example of the related art, Patent Document 1 by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-011108 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional signal transmission devices, there was room for further improvement in the process of reducing instantaneous transient in-phase noise (so-called common mode noise) that is superimposed on each of the received pulse signals input in parallel to the secondary side pulse receiving circuit.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a signal transmission device that is less susceptible to the effects of common mode noise, and a pulse receiving circuit used therein. [Means for solving the problem]

[0007] The signal transmission device disclosed in this specification is configured to include a first pulse detector that receives a differential input of a first received pulse signal appearing on a secondary winding of a first transformer and a second received pulse signal appearing on a secondary winding of a second transformer, a second pulse detector that receives a differential input of the first received pulse signal and the second received pulse signal with an input polarity opposite to that of the first pulse detector, and a logic unit that generates a received pulse signal based on the output signals of the first pulse detector and the second pulse detector. Effect of the Invention

[0008] According to the invention disclosed in this specification, it is possible to provide a signal transmission device that is less susceptible to the effects of common mode noise. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an application example of a signal transmission device. [Diagram 2] FIG. 2 is a diagram showing a first embodiment of a signal transmission device. [Diagram 3] FIG. 3 is a diagram illustrating an example of a noise removal operation in the first embodiment. [Figure 4] FIG. 4 is a diagram showing a second embodiment of a signal transmission device. [Diagram 5] FIG. 5 is a diagram illustrating an example of a noise removal operation in the second embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of a comparison operation of the comparator. [Figure 7] FIG. 7 is a diagram showing a structural example of a transformer chip according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing a two-channel signal transmission device. [Figure 9] FIG. 9 is a perspective view of a semiconductor device used as the transformer chip shown in FIG. [Figure 10] FIG. 10 is a plan view of the semiconductor device shown in FIG. [Figure 11]FIG. 11 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 15] FIG. 15 is an enlarged view of the region X shown in FIG. [Figure 16] FIG. 16 is an enlarged view of region XI shown in FIG. [Figure 17] FIG. 17 is an enlarged view of region XII shown in FIG. [Figure 18] FIG. 18 is an enlarged view of region XIII shown in FIG. 13, showing an isolation structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Signal transmission device (application)> 1 is a diagram showing an example of an application using a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from a primary circuit system (VCC1-GND1 system) to a secondary circuit system (VCC2-GND2 system) while electrically insulating the primary circuit system from the secondary circuit system, and drives the gate of a transistor provided in the secondary circuit system.

[0011] The signal transmission device 200 has a plurality of external terminals (in this figure, input terminals INA and INB, an output terminal OUT, power supply terminals VCC1 and VCC2, and ground terminals GND1 and GND2) as means for establishing electrical connection with the outside of the device, and various discrete components (in this figure, an N-channel MOS [metal oxide semiconductor] field effect transistor N1, capacitors C1 and C2, and a resistor R1) are externally attached to these external terminals.

[0012] A ground terminal GND1, a power supply terminal VCC1, an input terminal INA, an input terminal INB, and a ground terminal GND1 are arranged in order from the top on a first side (= the left side in this figure) of the package forming the signal transmission device 200. Meanwhile, a ground terminal GND2, a power supply terminal VCC2, an output terminal OUT, and a ground terminal GND2 are arranged in order from the top on a second side (= the side opposite to the first side, and the right side in this figure) of the same package.

[0013] In this way, the external terminals of the primary circuit system (GND1, VCC1, INA, and INB) are concentrated on the first side of the package, and the external terminals of the secondary circuit system (GND2, VCC2, OUT) are concentrated on the second side of the package.

[0014] In addition, it is preferable to provide ground terminals GND1 and GND2 at both ends of the first and second sides of the package, respectively. That is, it is preferable to provide two ground terminals each of GND1 and GND2.

[0015] Outside the signal transmission device 200 (primary circuit system), the power supply terminal VCC1 is connected to the power supply line of the primary circuit system. The two ground terminals GND1 are both connected to the ground lines of the primary circuit system. A capacitor C1 is connected between the power supply line and the ground line of the primary circuit system. Two input signals (for example, one is a gate control signal and the other is an enable signal) are input to the input terminals INA and INB, respectively.

[0016] Moreover, outside the signal transmission device 200 (secondary circuit system), the power supply terminal VCC2 is connected to the power supply line of the secondary circuit system. The two ground terminals GND2 are both connected to the ground lines of the secondary circuit system. A capacitor C2 is connected between the power supply line and the ground line of the secondary circuit system. A first end of a resistor R1 is connected to the output terminal OUT. 1 The second end of the transistor N1 is connected to the gate of the transistor N2.

[0017] <Signal transmission device (outline)> Continuing with reference to Fig. 1, a schematic configuration of the signal transmission device 200 will be described. The signal transmission device 200 of this configuration example is configured by sealing a controller chip 210 (corresponding to a first chip), a driver chip 220 (corresponding to a second chip), and a transformer chip 230 (corresponding to a third chip) in a single package.

[0018] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, up to 7 V based on GND1). In addition, the controller chip 210 includes, for example, Schmitt buffers 211A and 211B, an AND gate 211C, a pulse transmission circuit 212, and a low-voltage protection circuit 213 integrated therein.

[0019] The Schmitt buffer 211A is an example of a waveform shaping means, and is connected between the input terminal INA and the first input terminal (non-inverting input terminal) of the AND gate 211C.

[0020] The Schmitt buffer 211B is an example of a waveform shaping means, and is connected between the input terminal INB and a second input terminal (inverting input terminal) of the AND gate 211C.

[0021] The AND gate 211C generates an input pulse signal S0 by performing a logical AND operation on the input pulse signal INA and the inverted input pulse signal XINB (=the logical inversion signal of the input pulse signal INB), and outputs this to the pulse transmission circuit 212. Therefore, if INB=H (logical level when disabled), then S0=L (fixed value), and if INB=L (logical level when enabled), then S0=INA.

[0022] The pulse transmitting circuit 212 generates the transmission pulse signals S1 and S2 in response to the input pulse signal S0. More specifically, when the pulse transmitting circuit 212 notifies that the input pulse signal S0 is at a high level, it pulse-drives the transmission pulse signal S1 (outputs a single or multiple transmission pulses), and when it notifies that the input pulse signal S0 is at a low level, it pulse-drives the transmission pulse signal S2. That is, the pulse transmitting circuit 212 pulse-drives either the transmission pulse signal S1 or S2 in response to the logical level of the input pulse signal S0.

[0023] The low voltage protection circuit 213 prevents malfunctions during low voltage input by putting the controller chip 210 into a standby state until the power supply voltage VCC1 reaches a UVLO [under voltage lock out] release voltage.

[0024] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V based on GND2). Note that the driver chip 220 includes, for example, a pulse receiving circuit 221, a driver 222, and a low-voltage protection circuit 223 integrated therein.

[0025] The pulse receiving circuit 221 generates a receiving pulse signal S5 in response to the receiving pulse signals S3 and S4 input from the transformer chip 230. More specifically, the pulse receiving circuit 221 receives the pulse drive of the receiving pulse signal S3 to drop the receiving pulse signal S5 to a low level, and receives the pulse drive of the receiving pulse signal S4 to raise the receiving pulse signal S5 to a high level. That is, the pulse receiving circuit 221 switches the logical level of the receiving pulse signal S5 in response to the logical level of the input pulse signal S0.

[0026] The driver 222 generates an output pulse signal OUT (corresponding to the gate signal of the transistor N1) in response to the received pulse signal S5 input from the pulse receiving circuit 221. More specifically, the driver 222 sets the output pulse signal OUT to a high level when the received pulse signal S5 is at a low level, and sets the output pulse signal OUT to a low level when the received pulse signal S5 is at a high level.

[0027] As shown in the figure, the driver 222 may be a half-bridge output stage (CMOS [complementary MOS] inverter stage) made up of a P-channel MOS field effect transistor 222H and an N-channel MOS field effect transistor 222L.

[0028] Regarding connections, the source of the transistor 222H is connected to a power supply terminal VCC2, the source of the transistor 222L is connected to a ground terminal GND2, and the drains of the transistors 222H and 222L are both connected to the output terminal OUT.

[0029] The received pulse signal S5 is input to the gates of the transistors 222H and 222L. Therefore, when S5=L, the transistor 222H is turned on and the transistor 222L is turned off, so that OUT=H (=VCC2). On the other hand, when S5=H, the transistor 222H is turned off and the transistor 222L is turned on, so that OUT=L (=GND2).

[0030] The low-voltage protection circuit 223 prevents malfunctions during low-voltage input by putting the driver chip 220 into a standby state until the power supply voltage VCC2 reaches the UVLO release voltage.

[0031] The transformer chip 230 uses transformers 231 and 232 to provide DC insulation between the controller chip 210 and the driver chip 220, and outputs the transmission pulse signals S1 and S2 input from the pulse transmission circuit 212 to the pulse receiving circuit 221 as reception pulse signals S3 and S4, respectively.

[0032] More specifically, the transformer 231 outputs a receiving pulse signal S3 from a secondary winding 231s in response to a transmitting pulse signal S1 input to a primary winding 231p, while the transformer 232 outputs a receiving pulse signal S4 from a secondary winding 232s in response to a transmitting pulse signal S2 input to a primary winding 232p.

[0033] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal S0 is separated into two transmission pulse signals S1 and S2 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system to the secondary circuit system via the transformers 231 and 232.

[0034] Incidentally, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0035] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0036] In addition, both the controller chip 210 and the driver chip 220 can be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0037] Furthermore, even if a DC isolation element other than a transformer (e.g., a photocoupler) is used, it can be easily accommodated by simply replacing the transformer chip 230, eliminating the need to redevelop the controller chip 210 and the driver chip 220, thereby contributing to shortening the development period and reducing development costs.

[0038] The following will focus on the internal configuration of the signal transmission device 200 and provide a more detailed description.

[0039] <Signal Transmission Device (First Embodiment)> FIG. 2 is a diagram showing a first embodiment of a signal transmission device 200. In this diagram, based on the above-mentioned FIG. 1, the circuit configurations of the pulse transmission circuit 212 and the pulse reception circuit 221 are specifically depicted. The above-mentioned input terminals INA and INB are replaced with a single input terminal IN. The above-mentioned Schmitt buffers 211A and 211B and the AND gate 211C are replaced with a single Schmitt buffer 211. The above-mentioned transistors 222H and 222L are omitted from the diagram.

[0040] Further, external terminals T11 to T18 are clearly indicated on the transformer chip 230. A primary winding 231p of the transformer 231 is connected between the external terminal T11 and the external terminal T12. A primary winding 232p of the transformer 232 is connected between the external terminal T13 and the external terminal T14. A secondary winding 231s of the transformer 231 is connected between the external terminal T15 and the external terminal T16. A secondary winding 232s of the transformer 232 is connected between the external terminal T17 and the external terminal T18.

[0041] Due to their structures, the transformers 231 and 232 each have a parasitic capacitance between the primary winding 231p and the secondary winding 231s, and between the primary winding 232p and the secondary winding 232s.

[0042] The pulse transmitting circuit 212 includes a logic section 212a, buffers 212b and 212c, and diodes 212d and 212e.

[0043] The logic unit 212a drives the buffers 212b and 212c in response to the input pulse signal S0 (which corresponds to the input pulse signal IN). More specifically, the logic unit 212a drives the buffer 212b when notifying that the input pulse signal S0 is at a high level, and drives the buffer 212c when notifying that the input pulse signal S0 is at a low level.

[0044] The buffer 212b is driven by the logic unit 212a to generate a transmission pulse signal S1 and outputs it to the external terminal T11 of the transformer chip 230.

[0045] The buffer 212c is driven by the logic unit 212a to generate a transmission pulse signal S2 and outputs it to the external terminal T13 of the transformer chip 230.

[0046] The diode 212d is an example of an electrostatic protection element having a cathode connected to the external terminal T11 of the transformer chip 230 and an anode connected to the external terminals T12 and T14 of the transformer chip 230.

[0047] The diode 212e is an example of an electrostatic protection element having a cathode connected to the external terminal T13 of the transformer chip 230 and an anode connected to the external terminals T12 and T14 of the transformer chip 230.

[0048] The pulse receiving circuit 221 includes diodes 221a and 221b, buffers 221c to 221f, delay units 221g and 221h, AND gates 221i and 221j, and a logic unit 221k.

[0049] The cathode of the diode 221a is connected to the external terminal T15 of the transformer chip 230. The anode of the diode 221a is connected to the external terminals T16 and T18 of the transformer chip 230. The diode 221a thus connected functions as an electrostatic protection element connected across the secondary winding 231s that forms the transformer 231.

[0050] The cathode of the diode 221b is connected to the external terminal T17 of the transformer chip 230. The anode of the diode 221b is connected to the external terminals T16 and T18 of the transformer chip 230. The diode 221b thus connected functions as an electrostatic protection element connected across the secondary winding 232s that forms the transformer 232.

[0051] The buffers 221c and 221d are means for shaping the waveform of the received pulse signal S3 (=internal signal s11). More specifically, the buffers 221c and 221d raise the output signal to a high level when the internal signal s11 becomes higher than the threshold voltage Vth, and lower the output signal to a low level when the internal signal s11 becomes lower than the threshold voltage Vth. The output signal of the buffer 221c is output to the AND gate 221i as the internal signal s13 (=main signal).

[0052] The buffers 221e and 221f are means for shaping the waveform of the received pulse signal S4 (=internal signal s12). More specifically, the buffers 221e and 221f raise the output signal to a high level when the internal signal s12 becomes higher than the threshold voltage Vth, and lower the output signal to a low level when the internal signal s12 becomes lower than the threshold voltage Vth. The output signal of the buffer 221f is output to the AND gate 221j as the internal signal s16 (=main signal).

[0053] For example, the delay unit 221g raises the internal signal s17 (=mask signal) to a high level without delay when the output signal of the buffer 221d is raised to a high level, and then lowers the internal signal s17 to a low level after a predetermined mask time tm1 has elapsed.

[0054] For example, the delay unit 221h raises the internal signal s14 (=mask signal) to a high level without delay when the output signal of the buffer 221e is raised to a high level, and then lowers the internal signal s14 to a low level after a predetermined mask time tm1 has elapsed.

[0055] The AND gate 221i generates an internal signal s15 by logical ANDing the internal signal s13 input non-inverted and the internal signal s14 input inverted. Therefore, if s14=H (logical level when masked), then s15=L (fixed value), and if s14=L (logical level when masked), then s15=s13. The internal signal s15 corresponds to, for example, a set signal of the logic unit 221k.

[0056] The AND gate 221j generates an internal signal s18 by logical AND operation of the internal signal s16 inputted non-inverted and the internal signal s17 inputted inverted. Therefore, if s17=H (logical level when masked), then s18=L (fixed value), and if s17=L (logical level when masked), then s18=s16. The internal signal s15 corresponds to, for example, a reset signal of the logic unit 221k.

[0057] The logic unit 221k generates a receiving pulse signal S5 (and thus an output pulse signal OUT) based on the internal signals s15 and s18. Specifically, the logic unit 221k sets the receiving pulse signal S5 to a high level when the internal signal s15 rises to a high level, and resets the receiving pulse signal S5 to a low level when the internal signal s18 rises to a high level, for example.

[0058] Among the above components of the pulse receiving circuit 221, the buffers 221c to 221f, the delay units 221g and 221h, and the AND gates 221i and 221j function as noise cancellers for removing common mode noise superimposed on the received pulse signals S3 and S4, respectively, via the propagation paths indicated by the thin arrows in the figure.

[0059] FIG. 3 is a diagram showing an example of a noise removal operation in the first embodiment, depicting, from the top, an input pulse signal IN, internal signals s11 to s18, and an output pulse signal OUT.

[0060] First, consider the rising edge of the input pulse signal IN. For example, at time t11, when the input pulse signal IN rises to a high level, the transmission pulse signal S1 (not shown) is pulse-driven. Therefore, at the following time t12, a normal pulse rises in the reception pulse signal S3 (=internal signal s11) via the transformer 231, and exceeds the threshold voltage Vth of the buffers 221c and 221d. As a result, pulses are generated in the internal signals s13 and s17. On the other hand, at time t12, since no pulse rises in the reception pulse signal S4 (=internal signal s12), both the internal signals s14 and s16 remain at a low level.

[0061] When the internal signal s14 (=mask signal) is at a low level, the internal signal s13 (=main signal) is not masked and is directly output as the internal signal s15 (=set signal). As a result, at time t12, the output pulse signal OUT is set to a high level.

[0062] Furthermore, when the internal signal s17 (=mask signal) is at a high level, the internal signal s18 (=reset signal) is fixed at a low level, regardless of the logic level of the internal signal s16 (=main signal). However, at time t12, the internal signal s18 should originally be maintained at a low level, so no inconsistency occurs.

[0063] Next, consider the falling edge of the input pulse signal IN. For example, at time t15, when the input pulse signal IN falls to a low level, the transmission pulse signal S2 (not shown) is pulse-driven. Therefore, at the following time t16, a normal pulse rises in the reception pulse signal S4 (=internal signal s12) via the transformer 232, and exceeds the threshold voltage Vth of the buffers 221e and 221f. As a result, pulses are generated in the internal signals s14 and s16. On the other hand, at time t16, since no pulse rises in the reception pulse signal S3 (=internal signal s11), both the internal signals s13 and s17 remain at a low level.

[0064] When the internal signal s17 (=mask signal) is at a low level, the internal signal s16 (=main signal) is not masked and is directly output as the internal signal s18 (=reset signal). As a result, at time t16, the output pulse signal OUT is reset to a low level.

[0065] Furthermore, when the internal signal s14 (=mask signal) is at a high level, the internal signal s15 (=set signal) is fixed at a low level, regardless of the logic level of the internal signal s13 (=main signal). However, at time t16, the internal signal s15 should originally be maintained at a low level, so no inconsistency occurs.

[0066] Next, consider a case where common mode noise is superimposed on both of the received pulse signals S3 and S4 (=internal signals s11 and s12). For example, at time t14, when a noise pulse rises in both of the internal signals s11 and s12 and exceeds the threshold voltage Vth of each of the buffers 221c to 221f, a pulse is generated in each of the internal signals s13 and s16 (=main signals) and the internal signals s14 and s17 (=mask signals).

[0067] Here, when the internal signal s14 (=mask signal) is at a high level, the internal signal s15 (=set signal) is fixed at a low level, regardless of the logic level of the internal signal s13 (=main signal). Similarly, when the internal signal s17 (=mask signal) is at a high level, the internal signal s18 (=reset signal) is fixed at a low level, regardless of the logic level of the internal signal s16 (=main signal). Therefore, common mode noise superimposed on both the received pulse signals S3 and S4 (=internal signals s11 and s12) can be appropriately removed, and erroneous switching of the logic level of the output pulse signal OUT can be suppressed.

[0068] In order to reliably remove common-mode noise, it is desirable that the mask time tm1 of the internal signals s14 and s17 (=mask signals) be wider than the pulse width W1 of the internal signals s13 and s16 (=main signals) caused by noise superposition, and that the mask time tm1 completely overlaps with the pulse width W1.

[0069] In other words, it is desirable to appropriately design the buffers 221c to 221f and the delay units 221g and 221h so that the internal signals s13 and s16 (=main signals) rise to a high level after the internal signals s14 and s17 (=mask signals) rise to a high level, and the internal signals s14 and s17 (=mask signals) fall to a low level after the internal signals s13 and s16 (=main signals) fall to a low level.

[0070] Furthermore, during pulse driving of the internal signals s11 and s12 (=during reception of normal pulses), there is a period during which the internal signals s11 and s12 swing to a negative potential (=a potential lower than the steady low level) due to the regenerative current flowing through the transformers 231 and 232. If common mode noise is superimposed during this negative potential period, a state may occur in which only one of the internal signals s11 and s12 exceeds the threshold voltage Vth of the buffers 221c to 221f.

[0071] For example, at time t13, common mode noise is superimposed during the negative potential period of the internal signal s11, so that of the internal signals s11 and 12, only the internal signal s12 exceeds the threshold voltage Vth, and pulses are generated in the internal signals s14 and s16. On the other hand, since the internal signal s11 does not exceed the threshold voltage Vth, no trigger is applied to raise the internal signal s17 (=mask signal) to a high level again.

[0072] Therefore, in order to remove the noise-induced pulse generated in the internal signal s16, it is necessary to maintain the internal signal s17 (=mask signal), which has already been brought to a high level by the normal pulse of the internal signal s11, at a high level.

[0073] In particular, if the high-level period (=mask time tm1) of the internal signal s17 is set longer than the negative potential period of the internal signal s11, it is possible to appropriately remove noise-induced pulses occurring in the internal signal s16 even in the worst case where common-mode noise is superimposed immediately before the expiration of the negative potential period.

[0074] Although not described again, it goes without saying that the same applies to the case where common mode noise is superimposed on the internal signal s12 during the negative potential period.

[0075] <Problems with the First Embodiment> However, in the pulse receiving circuit 221 of the first embodiment, the threshold voltage Vth of the buffers 221c to 221f formed by a CMOS circuit is high, and a large amount of energy is required for signal transmission, resulting in large emission noise and power consumption. In addition, simply lowering the threshold voltage Vth of the buffers 221c to 221f makes them more susceptible to malfunction due to noise. Therefore, a new second embodiment capable of solving such problems is proposed below.

[0076] <Signal Transmission Device (Second Embodiment)> Fig. 4 is a diagram showing a second embodiment of the signal transmission device 200. In this diagram, the circuit configuration of the pulse receiving circuit 221 is changed based on the above-mentioned Figs. 1 and 2. Also, the number of external terminals of the transformer chip 230 is reduced from eight to six (=external terminals T21 to T26). Each of the changes will be described in detail below.

[0077] First, a description will be given of changes to the pulse receiving circuit 221. The pulse receiving circuit 221 of this embodiment includes diodes 221A and 221B, N-channel MOS field effect transistors 221C and 221D, comparators 221E and 221F, a timer 221G, and a logic unit 221H.

[0078] The cathode of the diode 221A is connected to the external terminal T24 of the transformer chip 230. The anode of the diode 221A is connected to the external terminal T25 of the transformer chip 230. The diode 221A thus connected functions as a first electrostatic protection element connected across the secondary winding 231s that forms the transformer 231.

[0079] The cathode of the diode 221B is connected to the external terminal T26 of the transformer chip 230. The anode of the diode 221B is connected to the external terminal T25 of the transformer chip 230. The diode 221B thus connected functions as a second electrostatic protection element connected across the secondary winding 232s that forms the transformer 232.

[0080] The drain of the transistor 221C is connected to the external terminal T24 of the transformer chip 230. The source of the transistor 221C is connected to the external terminal T25 of the transformer chip 230. The gate of the transistor 221C is connected to the application terminal of the internal signal s25 (= the output terminal of the timer 221G). Therefore, the transistor 221C is turned on when s25=H, and turned off when s25=L. The transistor 221C connected in this manner functions as a first switch connected between both ends of the secondary winding 231s that forms the transformer 231.

[0081] The drain of the transistor 221D is connected to the external terminal T26 of the transformer chip 230. The source of the transistor 221D is connected to the external terminal T25 of the transformer chip 230. The gate of the transistor 221D is connected to the application terminal of the internal signal s25 (= the output terminal of the timer 221G). Therefore, the transistor 221D is turned on when s25=H, and turned off when s25=L. The transistor 221D connected in this manner functions as a second switch connected between both ends of the secondary winding 232s that forms the transformer 232.

[0082] The non-inverting input terminal (+) of the comparator 221E is connected to the external terminal T24 of the transformer chip 230. The inverting input terminal (-) of the comparator 221E is connected to the external terminal T26 of the transformer chip 230. The comparator 221E connected in this manner corresponds to a first pulse detector that receives a differential input (=s21-s22) of the received pulse signal S3 (=internal signal s21) appearing on the secondary winding 231s of the transformer 231 and the received pulse signal S4 (=internal signal s22) appearing on the secondary winding 232s of the transformer 232, and generates an internal signal s23 by comparing the two signals. Note that the internal signal s23 corresponds to, for example, a set signal of the logic unit 221H, and goes to a high level when s21>s22, and goes to a low level when s21>s22. <s22であるときにローレベルとなる。

[0083] The non-inverting input terminal (+) of the comparator 221F is connected to the external terminal T26 of the transformer chip 230. The inverting input terminal (-) of the comparator 221F is connected to the external terminal T24 of the transformer chip 230. The comparator 221F connected in this manner is EThe second pulse detector receives the differential input of the received pulse signals S3 and S4 (=internal signals s21 and s22) with the input polarity opposite to that of the first pulse detector, and generates the internal signal s24 by comparing the two signals. Note that the internal signal s24 corresponds to, for example, a reset signal of the logic unit 221H, and goes to a low level when s21>s22, and goes to a low level when s21>s22. <s22であるときにハイレベルとなる。

[0084] The timer 221G receives the internal signals s23 and s24, and turns on the transistors 221C and 221D by setting the internal signal s25 to a high level for a predetermined mask time tm2 from the timing at which each signal rises to a high level (=corresponding to the pulse detection timing of each of the first pulse detector and the second pulse detector).

[0085] The logic unit 221H generates a receiving pulse signal S5 (and thus an output pulse signal OUT) based on the internal signals s23 and s24. Specifically, the logic unit 221H sets the receiving pulse signal S5 to a high level when the internal signal s23 rises to a high level, and resets the receiving pulse signal S5 to a low level when the internal signal s24 rises to a high level, for example.

[0086] FIG. 5 is a diagram showing an example of a noise removal operation in the second embodiment, depicting, from the top, an input pulse signal IN, internal signals s21 to s25, and an output pulse signal OUT.

[0087] First, consider the rising edge of the input pulse signal IN. For example, at time t21, when the input pulse signal IN is raised to a high level, the transmission pulse signal S1 (not shown) is pulse-driven. Therefore, at the following time t22, a normal pulse rises in the reception pulse signal S3 (=internal signal s21) via the transformer 231. On the other hand, at time t22, no pulse rises in the reception pulse signal S4 (=internal signal s12). Therefore, a pulse is generated in the internal signal s23, while the internal signal s24 remains at a low level. As a result, at time t22, the output pulse signal OUT is set to a high level.

[0088] Next, consider the falling edge of the input pulse signal IN. For example, at time t25, when the input pulse signal IN falls to a low level, the transmission pulse signal S2 (not shown) is pulse-driven. Therefore, at the following time t26, a normal pulse rises in the reception pulse signal S4 (=internal signal s22) via the transformer 232. On the other hand, at time t26, no pulse rises in the reception pulse signal S3 (=internal signal s21). Therefore, a pulse is generated in the internal signal s24, while the internal signal s23 remains at a low level. As a result, at time t26, the output pulse signal OUT is reset to a low level.

[0089] Next, consider a case where common mode noise is superimposed on both the received pulse signals S3 and S4 (=internal signals s21 and s22). For example, at time t24, noise pulses rise in both the internal signals s21 and s22. However, these noise pulses are differentially input in phase to the comparators 221E and 221F, respectively. Therefore, unintended pulse generation of the internal signals s23 and s24 is unlikely to occur, and erroneous switching of the logic level of the output pulse signal OUT can be suppressed.

[0090] Furthermore, in a configuration in which the internal signals s21 and s22 are differentially detected, the threshold voltage Vth of the pulse receiving circuit 221 (in this figure, the input offset voltages Vofs1 and Vofs2 of the comparators 221E and 221F, respectively) can be set smaller than in the first embodiment (FIG. 2) described above, making it possible to eliminate common mode noise while suppressing emission noise and power consumption.

[0091] Furthermore, during pulse driving of the internal signals s21 and s22 (=during reception of normal pulses), there is a period during which the internal signals s21 and s22 swing to a negative potential due to the regenerative current flowing through the transformers 231 and 232 (see the dashed lines of the internal signals s21 and s22). When such a negative potential period occurs, unnecessary pulses may be generated in the internal signals s23 and s24 generated by the comparators 221E and 221F, leading to erroneous detection of the received pulse signal S5 (and ultimately the output pulse signal OUT).

[0092] Therefore, when the pulses of the internal signals s23 and s24 are detected at times t22 and t26, the internal signal s25 is set to a high level for a predetermined mask time tm2. This turns on the transistors 221C and 221D, and both ends of the secondary windings 231s and 232s are shorted, so that the differential inputs of the comparators 221E and 221F become zero. As a result, unnecessary pulse generation of the internal signals s23 and s24 is suppressed.

[0093] The high level period (=mask time tm2) of the internal signal s25 may be set to be longer than the negative potential period of the internal signals s21 and s22.

[0094] FIG. 6 is a diagram showing an example of the comparison operation of comparators 221E and 221F. From top to bottom in order, internal signals s21 and s22 (= received pulse signals S3 and S4), differential input signal COMP1 (= s21 - s22) to comparator 221E, differential input signal COMP2 (= s22 - s21) to comparator 221F, and internal signals s23 and s24 (= comparison output signals of comparators 221E and 221F respectively) are depicted.

[0095] As shown in this figure, comparators 221E and 221F are circuit - designed to have input offset voltages Vofs1 and Vofs2 respectively. That is, internal signal s23 becomes high - level when COMP1 > Vofs1 and low - level when COMP1 < Vofs1. Also, internal signal s24 becomes high - level when COMP2 > Vofs2 and low - level when COMP2 < Vofs2.

[0096] Therefore, even if internal signals s21 and s22 vary slightly, as long as differential input signals COMP1 and COMP2 do not exceed input offset voltages Vofs1 and Vofs2 respectively, unnecessary pulses do not occur in internal signals s23 and s24. Therefore, it is possible to suppress the misdetection (unintended logic - level switching) of the output pulse signal OUT.

[0097] <Transchip> Next, returning to FIG. 4, the modification points of the transchip 230 in the second embodiment will be described. The transchip 230 of this embodiment has the number of external terminals reduced from 8 to 6 (= external terminals T21 to T26) compared to the first embodiment (FIG. 2).

[0098] The primary winding 231p of the transformer 231 is connected between the external terminal T21 and the external terminal T22. The primary winding 232p of the transformer 232 is connected between the external terminal T23 and the external terminal T22. The secondary winding 231s of the transformer 231 is connected between the external terminal T24 and the external terminal T25. The secondary winding 232s of the transformer 232 is connected between the external terminal T26 and the external terminal T25.

[0099] Thus, the transformer chip 230 has an external terminal T21 to which the first end of the primary winding 231p is connected, an external terminal T22 to which the second end of the primary winding 231p and the first end of the primary winding 232p are connected, an external terminal T23 to which the second end of the primary winding 232p is connected, an external terminal T24 to which the first end of the secondary winding 231s is connected, an external terminal T25 to which the second end of the secondary winding 231s and the first end of the secondary winding 232s are connected, and an external terminal T26 to which the second end of the secondary winding 232s is connected.

[0100] 7 is a diagram showing a structural example of a transformer chip 230 according to the second embodiment. In the transformer chip 230 of this structural example, the transformer 231 includes a primary winding 231p and a secondary winding 231s that face each other in the vertical direction. The transformer 232 includes a primary winding 232p and a secondary winding 232s that face each other in the vertical direction.

[0101] Both the primary windings 231p and 232p are formed on a first layer (lower layer) 230a of the transformer chip 230, and both the secondary windings 231s and 232s are formed on a second layer (upper layer) 230b of the transformer chip 230. The secondary winding 231s is disposed directly above the primary winding 231p and faces the primary winding 231p. The secondary winding 232s is disposed directly above the primary winding 232p and faces the primary winding 232p.

[0102] The primary winding 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21 so as to surround the periphery of the internal terminal X21 in a clockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. Meanwhile, the primary winding 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23 so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0103] The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0104] The secondary winding 231s is laid in a spiral shape starting from a first end connected to the external terminal T24 so as to surround the external terminal T24 in a counterclockwise direction, and a second end corresponding to the end point is connected to the external terminal T25. On the other hand, the secondary winding 232s is laid in a spiral shape starting from a first end connected to the external terminal T26 so as to surround the external terminal T26 in a clockwise direction, and a second end corresponding to the end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the illustrated order, and are used for wire bonding with the driver chip 220.

[0105] The secondary windings 231s and 232s are AC-connected to the primary windings 231p and 232p by magnetic coupling, and are DC-isolated from the primary windings 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0106] <Signal transmission device (2 channels)> 8 is a diagram showing a two-channel configuration of the signal transmission device 200. As shown in this diagram, the signal transmission device 200 has two input terminals IN1 and IN2 and two output terminals OUT1 and OUT2, and is capable of transmitting pulses for two channels.

[0107] The signal transmission path from the input terminal IN1 through the Schmitt buffer 211(1), the pulse transmitting circuit 212, the transformers 231 and 232, the pulse receiving circuit 221, and the driver 222(1) to the output terminal OUT1 is for the first channel. On the other hand, the signal transmission path from the input terminal IN2 through the Schmitt buffer 211(2), the pulse transmitting circuit 212, the transformers 233 and 234, the pulse receiving circuit 221, and the driver 222(2) to the output terminal OUT2 is for the second channel.

[0108] Moreover, the transformer chip 230 is provided with transformers 231 and 232 and external terminals T21 to T26 for the first channel, as well as transformers 233 and 234 and external terminals T31 to T36 for the second channel.

[0109] The primary winding 233p of the transformer 233 is connected between the external terminal T31 and the external terminal T32. The primary winding 234p of the transformer 234 is connected between the external terminal T33 and the external terminal T32. The secondary winding 233s of the transformer 233 is connected between the external terminal T34 and the external terminal T35. The secondary winding 234s of the transformer 234 is connected between the external terminal T36 and the external terminal T35.

[0110] Thus, in addition to the external terminals T21 to T26 mentioned above, the transformer chip 230 has an external terminal T31 to which a first end of the primary winding 233p is connected, an external terminal T32 to which a second end of the primary winding 233p and a first end of the primary winding 234p are connected, an external terminal T33 to which a second end of the primary winding 234p is connected, an external terminal T34 to which a first end of the secondary winding 233s is connected, an external terminal T35 to which a second end of the secondary winding 233s and a first end of the secondary winding 234s are connected, and an external terminal T36 to which a second end of the secondary winding 234s is connected.

[0111] <2ch transformer chip (semiconductor device)> FIG. 9 is a perspective view showing a semiconductor device 5 used as the transformer chip 230 shown in FIG. 8. FIG. 10 is a plan view of the semiconductor device 5 shown in FIG. 9. FIG. 11 is a plan view showing a layer in which the low potential coil 22 (corresponding to the primary windings 231p-234p of the transformers 231-234 shown in FIG. 8) is formed in the semiconductor device 5 shown in FIG. 9. FIG. 12 is a plan view showing a layer in which the high potential coil 23 (corresponding to the secondary windings 231s-234s of the transformers 231-234 shown in FIG. 8) is formed in the semiconductor device 5 shown in FIG. 9. FIG. 13 is a cross-sectional view taken along line VIII-VIII shown in FIG. 12. FIG. 14 is a cross-sectional view taken along line IX-IX shown in FIG. 12. FIG. 15 is an enlarged view of a region X shown in FIG. 12. FIG. 16 is an enlarged view of a region XI shown in FIG. 12. FIG. 17 is an enlarged view of a region XII shown in FIG. 12. FIG. 18 is an enlarged view of a region XIII shown in FIG. 13, showing a separation structure 130.

[0112] 9 to 13, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0113] The wide band gap semiconductor is made of a semiconductor whose band gap exceeds that of silicon (about 1.12 eV). The band gap of the wide band gap semiconductor is preferably 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

[0114] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0115] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0116] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0117] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface in a plan view. The insulating main surface 52 extends parallel to the first main surface .

[0118] The insulating side walls 53A-53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A-44D. Specifically, the insulating side walls 53A-53D are formed flush with the chip side walls 44A-44D. The insulating side walls 53A-53D form ground surfaces flush with the chip side walls 44A-44D.

[0119] The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 layers in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0120] Each of the interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the lowermost insulating layer 55 side and a second insulating layer 59 on the uppermost insulating layer 56 side. The first insulating layer 58 may include silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0121] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0122] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be realized. In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0123] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21. In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating sidewalls 53A-53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0124] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D (corresponding to the transformers 231 to 234 shown in FIG. 8, respectively) formed in this order from the insulating side wall 53C side to the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. In the following, the structure of the first transformer 21A will be described as an example. The structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

[0125] 11 to 14, the first transformer 21A includes a low potential coil 22 and a high potential coil 23 (corresponding to the primary winding 231p and secondary winding 231s of the transformer 231 shown in FIG. 8, respectively). The low potential coil 22 is formed in an insulating layer 51. The high potential coil 23 is formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0126] The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side of the low potential coil 22 within the insulating layer 51. In other words, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 and the high potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high potential coil 23 faces the low potential coil 22 with one or more interlayer insulating layers 57 in between.

[0127] The distance between the low potential coil 22 and the high potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is appropriately adjusted according to the dielectric strength and electric field strength between the low potential coil 22 and the high potential coil 23. In this embodiment, the low potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0128] The low potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. A portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 66 having an elliptical shape in a plan view.

[0129] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0130] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 11 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0131] The low potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0132] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0133] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical portion 29 exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26, or may be equal to the number of turns of the first helical portion 26.

[0134] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0135] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0136] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 12 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0137] The high potential coil 23 is preferably formed of the same conductive material as the low potential coil 22. That is, like the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a body layer.

[0138] 10, the semiconductor device 5 includes a plurality (12 in this embodiment) of low potential terminals 11 (corresponding to the external terminals T21 to T23 and the external terminals T31 to T33 shown in FIG. 8, respectively) and a plurality (12 in this embodiment) of high potential terminals 12 (corresponding to the external terminals T24 to T26 and the external terminals T34 to T36 shown in FIG. 8, respectively). The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0139] The low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the low potential terminals 11 are formed in a region on the insulating sidewall 53B side at intervals in the second direction Y from the transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0140] The low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. In this embodiment, two of each of the low potential terminals 11A to 11F are formed. The number of the low potential terminals 11A to 11F is arbitrary.

[0141] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0142] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0143] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0144] The multiple high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the multiple low potential terminals 11. Specifically, the multiple high potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the multiple low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0145] The multiple high potential terminals 12 are formed in areas close to the corresponding transformers 21A to 21D in a plan view. The closeness of the high potential terminals 12 to the transformers 21A to 21D means that the distance between the high potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low potential terminals 11 and the high potential terminals 12.

[0146] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A-21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A-21D in the first direction X in a plan view.

[0147] The multiple high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the multiple high potential terminals 12A to 12F are formed. The number of the multiple high potential terminals 12A to 12F is arbitrary.

[0148] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0149] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0150] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0151] 11 to 14, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0152] The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 also fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

[0153] The first high potential wiring 33 and the second high potential wiring 34 fix the high potential coil 23 of the first transformer 21A and the high potential coil 23 of the second transformer 21B to the same potential. The first high potential wiring 33 and the second high potential wiring 34 also fix the high potential coil 23 of the third transformer 21C and the high potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high potential wiring 33 and the second high potential wiring 34 fix all the high potential coils 23 of the transformers 21A to 21D to the same potential.

[0154] The multiple first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The structure of the other first low potential wirings 31 will be omitted, as the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

[0155] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a pull-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0156] The through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low potential coil 22, etc. In other words, the through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0157] The through wiring 71 penetrates the interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low potential coil 22.

[0158] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 are each formed of the same conductive material as the low potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0159] The first electrode layer 78 forms an upper end of the through wiring 71. The second electrode layer 79 forms a lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0160] The multiple wiring plug electrodes 80 are embedded in the multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 each have a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0161] The number of layers of the multiple wiring plug electrodes 80 matches the number of layers of the multiple interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the multiple interlayer insulating layers 57 may be formed.

[0162] The low potential connecting wire 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) in the same interlayer insulating layer 57 as the low potential coil 22. The low potential connecting wire 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. It is preferable that the low potential connecting wire 72 has a planar area larger than the planar area of ​​the wiring plug electrode 80. The low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0163] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the lowermost insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0164] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0165] The multiple pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The multiple substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0166] 14, the second low potential wirings 32 are electrically connected to the corresponding low potential terminals 11E, 11F and the first outer ends 25 of the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The second low potential wirings 32 each have a similar structure. In the following, the structure of the second low potential wiring 32 connected to the fifth low potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second low potential wirings 32 will be omitted, since the description of the structure of the second low potential wiring 32 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0167] Like the first low potential wiring 31, the second low potential wiring 32 includes a through wiring 71, a low potential connecting wiring 72, a lead-out wiring 73, a first connecting plug electrode 74, a second connecting plug electrode 75, a pad plug electrode 76, and a substrate plug electrode 77. The second low potential wiring 32 has a similar structure to the first low potential wiring 31, except that the low potential connecting wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22).

[0168] The low potential connection wiring 72 of the second low potential wiring 32 is formed around the low potential coil 22 in the same interlayer insulating layer 57 as the low potential coil 22. Specifically, the low potential connection wiring 72 is formed in a region between two adjacent low potential coils 22 in a plan view. The pad plug electrode 76 is formed in a region between the low potential terminal 11 (fifth low potential terminal 11E) and the low potential connection wiring 72 in the uppermost insulating layer 56, and is electrically connected to the low potential terminal 11 and the low potential connection wiring 72.

[0169] 13, the multiple first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high potential coils 23). The multiple first high potential wirings 33 each have a similar structure. In the following, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. The structure of the other first high potential wirings 33 will be omitted, since the description of the structure of the first high potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

[0170] The first high potential wiring 33 includes a high potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrode 82 are preferably formed of the same conductive material as the low potential coil 22, etc. In other words, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0171] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 in the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81, and increases the dielectric strength voltage of the insulating layer 51.

[0172] The multiple pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81 in the uppermost insulating layer 56, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the multiple pad plug electrodes 82 has a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0173] 14, the second high potential wirings 34 are electrically connected to the corresponding high potential terminals 12E, 12F and the second outer ends 28 of the corresponding transformers 21A to 21D (high potential coils 23), respectively. The second high potential wirings 34 each have a similar structure. In the following, the structure of the second high potential wiring 34 connected to the fifth high potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. The structure of the other second high potential wirings 34 will be omitted, since the description of the structure of the second high potential wiring 34 connected to the first transformer 21A (second transformer 21B) applies mutatis mutandis.

[0174] The second high potential wiring 34, like the first high potential wiring 33, includes a high potential connecting wiring 81 and a pad plug electrode 82. The second high potential wiring 34 has a similar structure to the first high potential wiring 33, except that the high potential connecting wiring 81 is electrically connected to the second outer terminal 28 of the first transformer 21A (high potential coil 23) and the second outer terminal 28 of the second transformer 21B (high potential coil 23).

[0175] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in a region between two adjacent high-potential coils 23 in a plan view, and faces the high-potential terminal 12 (the fifth high-potential terminal 12E) in the normal direction Z. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z.

[0176] The plurality of pad plug electrodes 82 are formed in a region between the high-potential terminal 12 (the fifth high-potential terminal 12E) and the high-potential connection wiring 81 within the topmost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively.

[0177] Referring to FIGS. 13 and 14, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. It is preferable that the distance D2 is 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0178] Referring to FIGS. 12 to 17, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. In FIGS. 15 to 17, the dummy pattern 85 is shown by hatching. The dummy pattern 85 includes a conductor. It is preferable that the dummy pattern 85 is formed of the same conductive material as the low-potential coil 22 or the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0179] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high potential coil 23.

[0180] In this embodiment, the dummy pattern 85 is routed in dense lines so as to partially cover and partially expose the area surrounding one or more high potential coils 23 in a plan view. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to the line density of the high potential coil 23. The line density of the dummy pattern 85 being equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high potential coil 23.

[0181] The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential terminal 11 in a plan view. The dummy pattern 85 being closer to the high potential coil 23 in a plan view means that the distance between the dummy pattern 85 and the high potential coil 23 is less than the distance between the dummy pattern 85 and the low potential terminal 11.

[0182] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. The dummy pattern 85 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low potential coil 22.

[0183] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0184] The dummy patterns 85 are preferably formed around the high potential coils 23 so as to be located in the regions between the adjacent high potential coils 23 in a plan view. In this case, undesired electric field concentration on the high potential coils 23 can be suppressed by utilizing the regions between the adjacent high potential coils 23.

[0185] The dummy pattern 85 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 caused by electric field concentration in the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably interposed in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 caused by electric field concentration in the high potential coil 23 can be suppressed.

[0186] In this embodiment, the dummy pattern 85 is formed along the multiple high potential coils 23 in a plan view, and is interposed in a region between adjacent multiple high potential coils 23. Moreover, the dummy pattern 85 collectively surrounds a region including the multiple high potential coils 23 and the multiple high potential terminals 12 in a plan view. Moreover, the dummy pattern 85 is interposed in a region between the multiple low potential terminals 11A to 11F and the multiple high potential coils 23 in a plan view. Moreover, the dummy pattern 85 is interposed in a region between the multiple low potential terminals 11A to 11F and the multiple high potential terminals 12A to 12F in a plan view.

[0187] 12 to 17, dummy pattern 85 includes a plurality of dummy patterns having different electrical states. Dummy pattern 85 includes high-potential dummy pattern 86. High-potential dummy pattern 86 is formed in insulating layer 51 so as to be located around transformers 21A to 21D in plan view. High-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from high-potential coil 23 and low-potential coil 22, and is independent of transformers 21A to 21D. In other words, high-potential dummy pattern 86 does not function as transformers 21A to 21D.

[0188] In this embodiment, the high-potential dummy pattern 86 is routed in dense lines so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. In this embodiment, the high-potential dummy pattern 86 is routed at a line density per unit area equal to the line density of the high-potential coil 23. The line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within a range of ±20% of the line density of the high-potential coil 23.

[0189] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D, and suppresses electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby moving the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0190] A voltage exceeding the voltage applied to the low potential coil 22 is applied to the high potential dummy pattern 86. This makes it possible to suppress the voltage drop between the high potential coil 23 and the high potential dummy pattern 86, thereby suppressing electric field concentration on the high potential coil 23. It is preferable that the voltage applied to the high potential coil 23 is applied to the high potential dummy pattern 86. In other words, it is preferable that the high potential dummy pattern 86 is fixed to the same potential as the high potential coil 23. This makes it possible to reliably suppress the voltage drop between the high potential coil 23 and the high potential dummy pattern 86, thereby making it possible to appropriately suppress electric field concentration on the high potential coil 23.

[0191] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0192] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the high potential dummy pattern 86 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. It is preferable that the high potential dummy pattern 86 is formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0193] The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 11 in a plan view. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in a plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0194] The high-potential dummy pattern 86 is preferably formed around the multiple high-potential coils 23 so as to be located in the region between the multiple adjacent high-potential coils 23 in a plan view. In this case, undesired electric field concentration on the multiple high-potential coils 23 can be suppressed by utilizing the region between the multiple adjacent high-potential coils 23.

[0195] The high-potential dummy pattern 86 is preferably interposed in a region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably interposed in a region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0196] In this embodiment, the high potential dummy pattern 86 is formed along the multiple high potential coils 23 in a plan view, and is interposed in the region between the multiple adjacent high potential coils 23. Moreover, the high potential dummy pattern 86 collectively surrounds the region including the multiple high potential coils 23 and the multiple high potential terminals 12 in a plan view. Moreover, the high potential dummy pattern 86 is interposed in the region between the multiple low potential terminals 11A to 11F and the multiple high potential coils 23 in a plan view. Moreover, the high potential dummy pattern 86 is interposed in the region between the multiple low potential terminals 11A to 11F and the multiple high potential terminals 12A to 12F in a plan view.

[0197] The high potential dummy pattern 86 is routed around the high potential terminals 12E, 12F in a region between adjacent high potential coils 23 in a plan view so as to expose the region directly below the high potential terminals 12E, 12F. A part of the high potential dummy pattern 86 may face the high potential terminals 12A to 12F in the normal direction Z. In this case, the high potential terminals 12E, 12F, like the high potential dummy pattern 86, shield the electric field to suppress the electric field leaking to the upper side of the high potential coil 23. In other words, the high potential terminals 12E, 12F are formed as a shield conductor layer that suppresses the electric field concentration on the high potential coil 23 together with the high potential dummy pattern 86.

[0198] It is preferable that the high potential dummy pattern 86 is formed in a terminated shape. In this case, it is possible to prevent a current loop circuit (closed circuit) from being formed in the high potential dummy pattern 86. This suppresses noise caused by the current flowing through the high potential dummy pattern 86. As a result, it is possible to suppress undesirable electric field concentration caused by noise, and at the same time, it is possible to suppress fluctuations in the electrical characteristics of the transformers 21A to 21D.

[0199] The high potential dummy pattern 86 specifically includes a first high potential dummy pattern 87 and a second high potential dummy pattern 88. The first high potential dummy pattern 87 is formed in a region between the plurality of transformers 21A to 21D (the plurality of high potential coils 23) adjacent to each other in a planar view. The second high potential dummy pattern 88 is formed in a region outside the region between the plurality of transformers 21A to 21D (the plurality of high potential coils 23) adjacent to each other in a planar view.

[0200] Hereinafter, the region between the adjacent first transformer 21A (high potential coil 23) and second transformer 21B (high potential coil 23) is referred to as a first region 89. Moreover, the region between the second transformer 21B (high potential coil 23) and third transformer 21C (high potential coil 23) is referred to as a second region 90. Moreover, the region between the third transformer 21C (high potential coil 23) and fourth transformer 21D (high potential coil 23) is referred to as a third region 91.

[0201] In this embodiment, the first high potential dummy pattern 87 is electrically connected to the high potential terminal 12 (fifth high potential terminal 12E) via the first high potential wiring 33. Specifically, the first high potential dummy pattern 87 includes a first connection portion 92 connected to the first high potential wiring 33. The position of the first connection portion 92 is arbitrary. As a result, the first high potential dummy pattern 87 is fixed to the same potential as the multiple high potential coils 23.

[0202] Specifically, the first high potential dummy pattern 87 includes a first pattern 93 formed in a first region 89, a second pattern 94 formed in a second region 90, and a third pattern 95 formed in a third region 91. As a result, the first high potential dummy pattern 87 suppresses the electric field leaking to the upper side of the high potential coil 23 in the first region 89, the second region 90, and the third region 91, and suppresses electric field concentration on the multiple adjacent high potential coils 23.

[0203] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed to the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated as long as they are fixed to the same potential.

[0204] 12 and 15, the first pattern 93 is connected to the first high potential wiring 33 via the first connection portion 92. The first pattern 93 is routed in a dense line shape so as to cover a part of the first region 89 in a plan view. The first pattern 93 is formed in the first region 89 at a distance from the high potential terminal 12 (the fifth high potential terminal 12E) in a plan view, and does not face the high potential terminal 12 in the normal direction Z. The first pattern 93 is also formed at a distance from the low potential connection wiring 72 in a plan view, and does not face the low potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the first pattern 93 and the low potential connection wiring 72, and increases the dielectric strength of the insulating layer 51.

[0205] The first pattern 93 includes a first circumferential line 96, a second circumferential line 97, and a plurality of first intermediate lines 98. The first circumferential line 96 extends in a band shape along the periphery of the high potential coil 23 of the first transformer 21A. In this embodiment, the first circumferential line 96 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the first circumferential line 96 is less than the width of the high potential coil 23 along the second direction Y.

[0206] The width of the first circumferential line 96 may be 0.1 μm or more and 5 μm or less. The width of the first circumferential line 96 is preferably 1 μm or more and 3 μm or less. The width of the first circumferential line 96 is defined by the width in a direction perpendicular to the direction in which the first circumferential line 96 extends. The width of the first circumferential line 96 is preferably equal to the width of the high potential coil 23. The width of the first circumferential line 96 being equal to the width of the high potential coil 23 means that the width of the first circumferential line 96 falls within a range of ±20% of the width of the high potential coil 23.

[0207] The first pitch between the first outer circumferential line 96 and the high potential coil 23 (first transformer 21A) may be 0.1 μm or more and 5 μm or less. The first pitch is preferably 1 μm or more and 3 μm or less. The first pitch is preferably equal to the second winding pitch of the high potential coil 23. The first pitch being equal to the first winding pitch means that the first pitch falls within a range of ±20% of the first winding pitch.

[0208] The second circumferential line 97 extends in a band shape along the periphery of the high potential coil 23 of the second transformer 21B. In this embodiment, the second circumferential line 97 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the second circumferential line 97 is less than the width of the high potential coil 23 along the second direction Y. The open end of the second circumferential line 97 faces the open end of the first circumferential line 96 along the first direction X.

[0209] The width of the second circumferential line 97 may be 0.1 μm or more and 5 μm or less. The width of the second circumferential line 97 is preferably 1 μm or more and 3 μm or less. The width of the second circumferential line 97 is defined by the width in a direction perpendicular to the direction in which the second circumferential line 97 extends. The width of the second circumferential line 97 is preferably equal to the width of the high potential coil 23. The width of the second circumferential line 97 being equal to the width of the high potential coil 23 means that the width of the second circumferential line 97 falls within a range of ±20% of the width of the high potential coil 23.

[0210] The second pitch between the second outer circumferential line 97 and the high potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. The second pitch is preferably 1 μm or more and 3 μm or less. The second pitch is preferably equal to the second winding pitch of the high potential coil 23. The second pitch being equal to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0211] The multiple first intermediate lines 98 extend in a band shape in the region between the first circumferential line 96 and the second circumferential line 97 in the first region 89. The multiple first intermediate lines 98 include at least one (in this embodiment, one) first connection line 99 that electrically connects the first circumferential line 96 and the second circumferential line 97.

[0212] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple first intermediate lines 98 include only one first connection line 99. The position of the first connection line 99 is arbitrary. At least one of the multiple first intermediate lines 98 is formed with a slit 100 that interrupts the current loop circuit. The position of the slit 100 is appropriately adjusted depending on the design of the multiple first intermediate lines 98.

[0213] The multiple first intermediate lines 98 are preferably formed in a band shape extending along the opposing direction of the multiple high potential coils 23. In this embodiment, the multiple first intermediate lines 98 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The multiple first intermediate lines 98 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0214] The multiple first intermediate lines 98 specifically include multiple first lead-out portions 101 and multiple second lead-out portions 102. The multiple first lead-out portions 101 are drawn out in stripes from the first periphery line 96 toward the second periphery line 97. The tips of the multiple first lead-out portions 101 are formed at intervals from the first periphery line 96 toward the second periphery line 97.

[0215] The multiple second drawer portions 102 are drawn out in a striped pattern from the second outer periphery line 97 toward the first outer periphery line 96. The tips of the multiple second drawer portions 102 are formed at intervals from the second outer periphery line 97 toward the first outer periphery line 96. In this embodiment, the multiple second drawer portions 102 are formed alternately with the multiple first drawer portions 101 at intervals in the second direction Y in a manner that sandwiches one first drawer portion 101 therebetween.

[0216] The multiple second lead portions 102 may sandwich the multiple first lead portions 101. Also, a group including the multiple second lead portions 102 may be formed adjacent to a group including the multiple first lead portions 101. The slits 100, the multiple first lead portions 101, and the multiple second lead portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0217] The width of the first intermediate line 98 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the first intermediate line 98 is preferably 1 μm or more and 3 μm or less. The width of the first intermediate line 98 is preferably equal to the width of the high potential coil 23. The width of the first intermediate line 98 being equal to the width of the high potential coil 23 means that the width of the first intermediate line 98 falls within a range of ±20% of the width of the high potential coil 23.

[0218] The third pitch between two adjacent first intermediate lines 98 may be 0.1 μm or more and 5 μm or less. The third pitch is preferably 1 μm or more and 3 μm or less. The third pitch is defined by the distance between adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. The third pitch being equal to each other means that the third pitch falls within a range of ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high potential coil 23. The third pitch being equal to the second winding pitch means that the third pitch falls within a range of ±20% of the second winding pitch.

[0219] 12 and 16, the second pattern 94 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the first high potential wiring 33 (the fifth high potential terminal 12E) via a second peripheral line 97 of the first pattern 93. The second pattern 94 is routed in a dense line shape so as to cover the second region 90.

[0220] The second pattern 94 includes the second circumferential line 97, the third circumferential line 103, and a plurality of second intermediate lines 104. The third circumferential line 103 extends in a band shape along the periphery of the high potential coil 23 of the third transformer 21C. In this embodiment, the third circumferential line 103 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the third circumferential line 103 is less than the width of the high potential coil 23 of the third transformer 21C along the second direction Y.

[0221] The width of the third circumferential line 103 may be 0.1 μm or more and 5 μm or less. The width of the third circumferential line 103 is preferably 1 μm or more and 3 μm or less. The width of the third circumferential line 103 is defined by the width in a direction perpendicular to the direction in which the third circumferential line 103 extends. The width of the third circumferential line 103 is preferably equal to the width of the high potential coil 23. The width of the third circumferential line 103 being equal to the width of the high potential coil 23 means that the width of the third circumferential line 103 falls within a range of ±20% of the width of the high potential coil 23.

[0222] The fourth pitch between the third outer circumferential line 103 and the high potential coil 23 (third transformer 21C) may be 0.1 μm or more and 5 μm or less. The fourth pitch is preferably 1 μm or more and 3 μm or less. The fourth pitch is preferably equal to the second winding pitch of the high potential coil 23. The fourth pitch being equal to the second winding pitch means that the fourth pitch falls within a range of ±20% of the second winding pitch.

[0223] The multiple second intermediate lines 104 extend in a band shape in the region between the second circumferential line 97 and the third circumferential line 103 in the second region 90. The multiple second intermediate lines 104 include at least one (in this embodiment, one) second connection line 105 that electrically connects the second circumferential line 97 and the third circumferential line 103.

[0224] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple second intermediate lines 104 include only one second connection line 105. The second connection line 105 may have a width greater than the width of the other second intermediate lines 104. The position of the second connection line 105 is arbitrary. At least one of the multiple second intermediate lines 104 has a slit 106 formed therein to interrupt the current loop circuit. The position of the slit 106 is adjusted as appropriate depending on the design of the multiple second intermediate lines 104.

[0225] The second intermediate lines 104 are preferably formed in a band shape extending along the opposing direction of the high potential coils 23. In this embodiment, the second intermediate lines 104 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The second intermediate lines 104 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0226] The second intermediate lines 104 specifically include a plurality of third lead-out portions 107 and a plurality of fourth lead-out portions 108. The third lead-out portions 107 are drawn out in stripes from the second periphery line 97 toward the third periphery line 103. The tips of the third lead-out portions 107 are formed at intervals from the third periphery line 103 toward the second periphery line 97.

[0227] The multiple fourth drawer portions 108 are drawn out in stripes from the third periphery line 103 toward the second periphery line 97. The tips of the multiple fourth drawer portions 108 are formed at intervals from the second periphery line 97 toward the third periphery line 103. In this embodiment, the multiple fourth drawer portions 108 are formed alternately with the multiple third drawer portions 107 at intervals in the second direction Y in a manner that sandwiches one third drawer portion 107 therebetween.

[0228] The plurality of fourth lead portions 108 may sandwich the plurality of third lead portions 107. Also, a group including the plurality of fourth lead portions 108 may be formed adjacent to a group including the plurality of third lead portions 107. The slits 106, the plurality of third lead portions 107, and the plurality of fourth lead portions 108 suppress the formation of a current loop circuit in the second pattern 94.

[0229] The width of the second intermediate line 104 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the second intermediate line 104 is preferably 1 μm or more and 3 μm or less. The width of the second intermediate line 104 is preferably equal to the width of the high potential coil 23. The width of the second intermediate line 104 being equal to the width of the high potential coil 23 means that the width of the second intermediate line 104 falls within a range of ±20% of the width of the high potential coil 23.

[0230] The fifth pitch between two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. The fifth pitch is preferably 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between adjacent second intermediate lines 104 in the second direction Y. The fifth pitches are preferably equal to each other. The fifth pitches being equal to each other means that the fifth pitch falls within a range of ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high potential coil 23. The fifth pitch being equal to the second winding pitch means that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0231] 12 and 17, the third pattern 95 is electrically connected to the first high potential wiring 33. In this embodiment, the third pattern 95 is electrically connected to the first high potential wiring 33 via the second pattern 94 and the first pattern 93. The third pattern 95 is laid out in a dense line shape so as to cover a part of the third region 91. The third pattern 95 is formed in the third region 91 at a distance from the high potential terminal 12 (sixth high potential terminal 12F) in a plan view, and does not face the high potential terminal 12 in the normal direction Z.

[0232] The third pattern 95 is formed at a distance from the low potential connecting wiring 72 in a plan view, and does not face the low potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the third pattern 95 and the low potential connecting wiring 72 in the normal direction Z, and increases the dielectric strength of the insulating layer 51.

[0233] The third pattern 95 includes the third periphery line 103, the fourth periphery line 109, and a plurality of third intermediate lines 110. The fourth periphery line 109 extends in a band shape along the periphery of the high potential coil 23 of the fourth transformer 21D. In this embodiment, the fourth periphery line 109 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the fourth periphery line 109 is less than the width of the high potential coil 23 of the fourth transformer 21D along the second direction Y. The open end of the fourth periphery line 109 faces the open end of the third periphery line 103 along the first direction X.

[0234] The width of the fourth circumferential line 109 may be 0.1 μm or more and 5 μm or less. The width of the fourth circumferential line 109 is preferably 1 μm or more and 3 μm or less. The width of the fourth circumferential line 109 is defined by the width in a direction perpendicular to the direction in which the fourth circumferential line 109 extends. The width of the fourth circumferential line 109 is preferably equal to the width of the high potential coil 23. The width of the fourth circumferential line 109 being equal to the width of the high potential coil 23 means that the width of the fourth circumferential line 109 falls within a range of ±20% of the width of the high potential coil 23.

[0235] The sixth pitch between the fourth outer circumferential line 109 and the high potential coil 23 (fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. The sixth pitch is preferably 1 μm or more and 3 μm or less. The sixth pitch is equal to the second winding pitch of the high potential coil 23. The sixth pitch being equal to the second winding pitch means that the sixth pitch falls within a range of ±20% of the second winding pitch.

[0236] The multiple third intermediate lines 110 extend in a band shape in the region between the third circumferential line 103 and the fourth circumferential line 109 in the third region 91. The multiple third intermediate lines 110 include at least one (in this embodiment, one) third connection line 111 that electrically connects the third circumferential line 103 and the fourth circumferential line 109.

[0237] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple third intermediate lines 110 include only one third connection line 111. The position of the third connection line 111 is arbitrary. At least one of the multiple third intermediate lines 110 has a slit 112 that interrupts the current loop circuit. The position of the slit 112 is appropriately adjusted depending on the design of the multiple third intermediate lines 110.

[0238] The multiple third intermediate lines 110 are preferably formed in a band shape extending along the opposing direction of the multiple high potential coils 23. In this embodiment, the multiple third intermediate lines 110 are each formed in a band shape extending in the first direction X, and are formed at intervals in the second direction Y. The multiple third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0239] In this embodiment, the third intermediate lines 110 include a plurality of fifth lead portions 113 and a plurality of sixth lead portions 114. The fifth lead portions 113 are drawn out in stripes from the third periphery line 103 toward the fourth periphery line 109. The tips of the fifth lead portions 113 are formed at intervals from the fourth periphery line 109 toward the third periphery line 103.

[0240] The multiple sixth lead portions 114 are drawn out in a striped pattern from the fourth periphery line 109 toward the third periphery line 103. The tips of the multiple sixth lead portions 114 are formed at intervals from the third periphery line 103 toward the fourth periphery line 109. In this embodiment, the multiple sixth lead portions 114 are formed alternately with the multiple fifth lead portions 113 at intervals in the second direction Y in a manner that sandwiches one fifth lead portion 113 therebetween.

[0241] The plurality of sixth lead portions 114 may sandwich the plurality of fifth lead portions 113. Furthermore, a group including the plurality of sixth lead portions 114 may be formed adjacent to a group including the plurality of fifth lead portions 113. The slits 112, the plurality of fifth lead portions 113, and the plurality of sixth lead portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0242] The width of the third intermediate line 110 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the third intermediate line 110 is preferably 1 μm or more and 3 μm or less. The width of the third intermediate line 110 is preferably equal to the width of the high potential coil 23. The width of the third intermediate line 110 being equal to the width of the high potential coil 23 means that the width of the third intermediate line 110 falls within a range of ±20% of the width of the high potential coil 23.

[0243] The seventh pitch between two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. The seventh pitch is preferably 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between adjacent third intermediate lines 110 in the second direction Y. The seventh pitches are preferably equal to each other. The seventh pitches being equal to each other means that the seventh pitch falls within a range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high potential coil 23. The seventh pitch being equal to the second winding pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0244] 12 to 17, in this embodiment, the second high potential dummy pattern 88 is electrically connected to the high potential terminal 12 via the first high potential dummy pattern 87. The second high potential dummy pattern 88 specifically includes a second connection portion 115 connected to the first high potential dummy pattern 87. The position of the second connection portion 115 is arbitrary. As a result, the second high potential dummy pattern 88 is fixed to the same potential as the multiple high potential coils 23.

[0245] The second high potential dummy pattern 88 suppresses the electric field leaking above the high potential coil 23 in the area outside the first area 89, the second area 90, and the third area 91, and suppresses electric field concentration on the multiple high potential coils 23. In this embodiment, the second high potential dummy pattern 88 collectively surrounds the area including the multiple high potential coils 23 and the multiple high potential terminals 12A to 12F in a planar view. In this embodiment, the second high potential dummy pattern 88 is formed in an oval ring shape (elliptical ring shape) in a planar view.

[0246] As a result, the second high potential dummy pattern 88 is interposed in a region between the multiple low potential terminals 11A-11F and the multiple high potential coils 23 in a plan view. The second high potential dummy pattern 88 is also interposed in a region between the multiple low potential terminals 11A-11F and the multiple high potential terminals 12A-12F in a plan view.

[0247] The second high potential dummy pattern 88 includes a plurality of (six in this embodiment) high potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high potential lines is adjusted according to the electric field to be relaxed. The multiple high potential lines 116A to 116F are formed in this order at intervals in a direction away from the multiple high potential coils 23.

[0248] The multiple high potential lines 116A to 116F collectively surround the multiple high potential coils 23 in a planar view. Specifically, the multiple high potential lines 116A to 116F collectively surround an area including the multiple high potential coils 23 and the multiple high potential terminals 12A to 12F in a planar view. In this embodiment, the multiple high potential lines 116A to 116F are formed in an oval ring shape (elliptical ring shape) in a planar view.

[0249] Each of the high potential lines 116A to 116F includes a slit 117 that interrupts a current loop circuit. The position of the slit 117 is appropriately adjusted depending on the design of the high potential lines 116A to 116F.

[0250] The width of the high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The width of the high potential lines 116A to 116F is preferably 1 μm or more and 3 μm or less. The width of the high potential lines 116A to 116F is defined by the width in a direction perpendicular to the direction in which the high potential lines 116A to 116F extend. The width of the high potential lines 116A to 116F is preferably equal to the width of the high potential coil 23. The width of the high potential lines 116A to 116F being equal to the width of the high potential coil 23 means that the width of the high potential lines 116A to 116F falls within a range of ±20% of the width of the high potential coil 23.

[0251] The eighth pitch between two adjacent high potential lines 116A-116F may be 0.1 μm or more and 5 μm or less. The eighth pitch is preferably 1 μm or more and 3 μm or less. The eighth pitches are preferably equal to each other. The eighth pitches being equal to each other means that the eighth pitch falls within a range of ±20% of the eighth pitch.

[0252] The ninth pitch between the adjacent first high potential dummy pattern 87 and second high potential dummy pattern 88 may be 0.1 μm or more and 5 μm or less. The ninth pitch is preferably 1 μm or more and 3 μm or less. The ninth pitch is preferably equal to the second winding pitch of the high potential coil 23. The ninth pitch being equal to the second winding pitch means that the ninth pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be relaxed.

[0253] 12 to 17, dummy pattern 85 includes floating dummy pattern 121 formed in an electrically floating state in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view. Floating dummy pattern 121 is formed in a pattern (discontinuous pattern) different from high potential coil 23 and low potential coil 22, and is independent of transformers 21A to 21D. In other words, floating dummy pattern 121 does not function as transformers 21A to 21D.

[0254] In this embodiment, the floating dummy pattern 121 is laid out in a dense line shape so as to partially cover and partially expose the area around the high potential coil 23 in a plan view. The floating dummy pattern 121 may be formed to have ends or to have no ends.

[0255] The floating dummy pattern 121 is routed at a line density per unit area equal to that of the high potential coil 23. The line density of the floating dummy pattern 121 being equal to that of the high potential coil 23 means that the line density of the floating dummy pattern 121 falls within a range of ±20% of the line density of the high potential coil 23.

[0256] Moreover, the floating dummy pattern 121 is routed at a line density per unit area equal to that of the high potential dummy pattern 86. The line density of the floating dummy pattern 121 being equal to that of the high potential dummy pattern 86 means that the line density of the floating dummy pattern 121 falls within a range of ±20% of the line density of the high potential dummy pattern 86.

[0257] The floating dummy pattern 121 shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D, and suppresses electric field concentration on the high potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking above the high potential coil 23 in a direction away from the high potential coil 23. This makes it possible to suppress electric field concentration on the high potential coil 23.

[0258] Furthermore, the floating dummy pattern 121 disperses the electric field leaking out above the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This makes it possible to suppress electric field concentration on the high-potential dummy pattern 86 and, at the same time, to appropriately suppress electric field concentration on the high-potential coil 23.

[0259] The depth position of the floating dummy pattern 121 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The floating dummy pattern 121 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. The floating dummy pattern 121 being closer to the high potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z is less than the distance between the floating dummy pattern 121 and the low potential coil 22.

[0260] In this case, it is possible to appropriately suppress electric field concentration on the high potential coil 23. The smaller the distance between the floating dummy pattern 121 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. It is preferable that the floating dummy pattern 121 is formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high potential coil 23.

[0261] The floating dummy pattern 121 is preferably interposed in a region between the low potential terminal 11 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential coil 23 caused by electric field concentration in the high potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably interposed in a region between the low potential terminal 11 and the high potential terminal 12 in a plan view. In this case, undesired conduction between the low potential terminal 11 and the high potential terminal 12 caused by electric field concentration in the high potential coil 23 can be suppressed.

[0262] In this embodiment, the floating dummy pattern 121 is formed along the multiple high potential coils 23 in a planar view. Specifically, the floating dummy pattern 121 collectively surrounds an area including the multiple high potential coils 23 and the multiple high potential terminals 12 in a planar view. In this embodiment, the floating dummy pattern 121 collectively surrounds an area including the multiple high potential coils 23 and the multiple high potential terminals 12 across the high potential dummy pattern 86 (second high potential dummy pattern 88) in a planar view.

[0263] As a result, the floating dummy pattern 121 is interposed in a region between the plurality of low potential terminals 11A-11F and the plurality of high potential coils 23 in a plan view. The floating dummy pattern 121 is also interposed in a region between the plurality of low potential terminals 11A-11F and the plurality of high potential terminals 12A-12F in a plan view.

[0264] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. In this embodiment, the floating dummy pattern 121 includes a plurality of (six in this embodiment) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The plurality of floating lines 122A to 122F are formed in this order at intervals in a direction away from the plurality of high potential coils 23.

[0265] The floating lines 122A-122F collectively surround the high potential coils 23 in plan view. More specifically, the floating lines 122A-122F collectively surround an area including the high potential coils 23 and the high potential terminals 12A-12F across the high potential dummy pattern 86 in plan view. In this embodiment, the floating lines 122A-122F are formed in an oval ring shape in plan view.

[0266] The width of the floating lines 122A-122F may be 0.1 μm or more and 5 μm or less. The width of the floating lines 122A-122F is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A-122F is defined by the width in a direction perpendicular to the direction in which the floating lines 122A-122F extend.

[0267] The tenth pitch between two adjacent floating lines 122A-122F may be 0.1 μm or more and 5 μm or less. The tenth pitch is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A-122F is preferably equal to the width of the high potential coil 23. The width of the floating lines 122A-122F being equal to the width of the high potential coil 23 means that the width of the floating lines 122A-122F falls within a range of ±20% of the width of the high potential coil 23.

[0268] The 11th pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 (second high potential dummy pattern 88) may be 0.1 μm or more and 5 μm or less. The 11th pitch is preferably 1 μm or more and 3 μm or less. The 11th pitches are preferably equal to each other. The 11th pitches being equal to each other means that the 11th pitch falls within a range of ±20% of the 11th pitch.

[0269] The 11th pitch is preferably equal to the second winding pitch of the high potential coil 23. The 11th pitch between the floating lines 122A-122F being equal to the second winding pitch means that the 11th pitch falls within a range of ±20% of the second winding pitch. For clarity, Figs. 10-12 show an example in which the 11th pitch exceeds the second winding pitch.

[0270] The 12th pitch between the floating dummy pattern 121 and the high potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple floating lines 122A-122F are adjusted according to the electric field to be relaxed, and are not limited to specific values.

[0271] 13 and 14, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed by utilizing a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIGS. 8 and 9, the second functional device 60 is shown in a simplified manner by a dashed line drawn on the surface layer portion of the first main surface 42.

[0272] The second functional device 60 is electrically connected to the low potential terminal 11 via a low potential wiring, and is electrically connected to the high potential terminal 12 via a high potential wiring. The low potential wiring has a similar structure to the first low potential wiring 31 (second low potential wiring 32) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high potential wiring has a similar structure to the first high potential wiring 33 (second high potential wiring 34) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A specific description of the low potential wiring and high potential wiring related to the second functional device 60 will be omitted.

[0273] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. 。 The second functional device 60 may include circuitry that selectively combines any two or more of passive devices, semiconductor rectifying devices, and semiconductor switching devices. The circuitry may form part or all of an integrated circuit.

[0274] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0275] 13 and 14, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0276] The device region 62 is a region including the first functional device 45 (multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0277] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (the multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0278] The sealing conductor 61 is disposed on the insulating side wall 53 in a plan view. A ~53D. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0279] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending between the upper end and the lower end in a wall shape. In this embodiment, the upper end of the seal conductor 61 is formed on the semiconductor chip 41 side with a gap therebetween from the insulating principal surface 52, and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed on the upper end side with a gap therebetween from the semiconductor chip 41.

[0280] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the multiple low potential terminals 11 and the multiple high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (multiple transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0281] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or a plurality (a plurality in this embodiment) of seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0282] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 matches the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0283] As long as one annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless shape (annular shape).

[0284] The multiple seal via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the seal plug conductor 64. The multiple seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or greater than the planar area of ​​the seal plug conductor 64.

[0285] The width of the sealing conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the sealing conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction perpendicular to the direction in which the sealing conductor 61 extends.

[0286] 13, 14 and 18, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0287] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0288] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0289] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body portion 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0290] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. Specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 with a gap therebetween from the chip sidewalls 44A to 44D.

[0291] The main body portion 130C has a flat surface extending approximately parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may take various forms in addition to the field insulating film 131.

[0292] 13 and 14, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0293] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may include silicon oxide. The first inorganic insulating layer 141 preferably includes USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may include silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high potential coil 23 can be increased.

[0294] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of the USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0295] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0296] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0297] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0298] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. According to these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0299] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0300] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose the plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that rises onto the periphery (overlap portion) of the high potential pad opening 144.

[0301] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the multiple high potential coils 23, the multiple high potential terminals 12, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0302] If the organic insulating layer 145 is not formed, the filler contained in the package body 2 (mold resin) may cause damage to the multiple high potential coils 23, the multiple high potential terminals 12, the seal conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121. This type of damage is called a filler attack.

[0303] The organic insulating layer 145 protects the multiple high potential coils 23, the multiple high potential terminals 12, the seal conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121 from the filler contained in the package body 2 (molded resin). The slit between the first portion 146 and the second portion 147 functions as an anchor portion for the package body 2 (molded resin).

[0304] A part of the package body 2 (molded resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140. This enhances the adhesion of the package body 2 (molded resin) to the semiconductor device 5. Of course, the first portion 146 and the second portion 147 may be integrally formed. The organic insulating layer 145 may include only one of the first portion 146 and the second portion 147. In this case, however, attention must be paid to filler attack.

[0305] The embodiment of the present invention can be embodied in further other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which the first functional device 45 is not included and only the second functional device 60 is included may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0306] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the sealing conductor 61. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the sealing conductor 61.

[0307] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0308] In the above embodiment, an example has been described in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required, and may be removed.

[0309] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type device including a plurality of transformers 21. However, a first functional device 45 of a single-channel type device including a single transformer 21 may be adopted.

[0310] <Summary> The various embodiments described above will now be summarized.

[0311] For example, the signal transmission device disclosed in this specification is configured (first configuration) to have a first pulse detector that receives a differential input of a first received pulse signal appearing on a secondary winding of a first transformer and a second received pulse signal appearing on a secondary winding of a second transformer, a second pulse detector that receives a differential input of the first received pulse signal and the second received pulse signal with an input polarity opposite to that of the first pulse detector, and a logic unit that generates a received pulse signal based on the output signals of the first pulse detector and the second pulse detector.

[0312] In the pulse receiving circuit of the first configuration described above, the first pulse detector and the second pulse detector may each be a comparator having an input offset (second configuration).

[0313] Furthermore, the pulse receiving circuit of the first or second configuration may be configured (third configuration) further including a first switch and a second switch connected between both ends of the secondary windings of the first transformer and the second transformer, respectively, and a timer that turns on the first switch and the second switch for a predetermined mask period from the pulse detection timing of the first pulse detector and the second pulse detector, respectively.

[0314] In addition, the pulse receiving circuit of any of the first to third configurations may be configured (fourth configuration) further including a first electrostatic protection element and a second electrostatic protection element connected between both ends of the secondary windings of the first transformer and the second transformer, respectively.

[0315] Furthermore, in the pulse receiving circuit of any of the above first to fourth configurations, the logic section may be configured (fifth configuration) to set the received pulse signal to a first logic level in response to the first received pulse signal, and to set the received pulse signal to a second logic level in response to the second received pulse signal.

[0316] Furthermore, for example, the signal transmission device disclosed in this specification is configured (sixth configuration) to include a pulse transmitting circuit that generates a first transmission pulse signal and a second transmission pulse signal in response to an input pulse signal, a first transformer and a second transformer that transmit the first transmission pulse signal and the second transmission pulse signal as a first reception pulse signal and a second reception pulse signal, respectively, to a subsequent stage while insulating between input and output, a pulse receiving circuit having any of the first to fifth configurations described above and generating the reception pulse signal in response to the first reception pulse signal and the second reception pulse signal, and a driver that generates an output pulse signal in response to the reception pulse signal.

[0317] In addition, in the signal transmission device of the sixth configuration described above, the pulse transmission circuit may be configured (seventh configuration) to pulse-drive either the first transmission pulse signal or the second transmission pulse signal depending on the logical level of the input pulse signal.

[0318] In addition, in the signal transmission device of the sixth or seventh configuration, the pulse transmitting circuit may be integrated into a first chip, the pulse receiving circuit and the driver may be integrated into a second chip, and the first transformer and the second transformer may be integrated into a third chip (eighth configuration).

[0319] Furthermore, in the signal transmission device of the above-mentioned eighth configuration, the third chip may be configured to have a first terminal to which a first end of a primary winding forming the first transformer is connected, a second terminal to which a second end of the primary winding forming the first transformer and a first end of a primary winding forming the second transformer are connected, a third terminal to which a second end of the primary winding forming the second transformer is connected, a fourth terminal to which a first end of a secondary winding forming the first transformer is connected, a fifth terminal to which a second end of the secondary winding forming the first transformer and a first end of a secondary winding forming the second transformer are connected, and a sixth terminal to which a second end of the secondary winding forming the second transformer is connected (ninth configuration).

[0320] Furthermore, the signal transmission device according to any one of the sixth to ninth configurations may be configured to have a plurality of pairs of the first transformer and the second transformer (tenth configuration).

[0321] <Other Modifications> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiments. For example, bipolar transistors and MOS field effect transistors can be replaced with each other, and the logic levels of various signals can be inverted as desired. In other words, the above-mentioned embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Industrial Applicability]

[0322] The invention disclosed in this specification can be used, for example, in general applications that require signal transmission while maintaining electrical isolation between input and output (e.g., insulated gate drivers, motor drivers, isolators, and other ICs that handle high voltages). [Explanation of symbols]

[0323] 5. Semiconductor Devices 11 Low potential terminal 12 High potential terminal 21 Transformer 22 Low potential coil 23 High potential coil 41 Semiconductor Chip 42 First main surface 44A First chip side wall 44B 2nd chip side wall 44C 3rd chip sidewall 44D 4th chip sidewall 45 First Functional Device 51 Insulating layer 53A First insulating side wall 53B Second insulating side wall 53C 3rd insulating side wall 53D 4th insulating side wall 60 Second Function Device 61 Sealed Conductor 85 Dummy Pattern 130 Separation structure 131 Field Insulation Film 140 Inorganic insulating layer 145 Organic Insulating Layer 200 Signal transmission device 210 Controller chip (first chip) 211, 211A, 211B, 211(1), 211(2) Schmitt buffer 211C AND Gate 212 Pulse transmission circuit 212a Logic section 212b, 212c Buffer 212d, 212e Diodes (electrostatic protection elements) 213 Low voltage protection circuit 220 Driver Chip (2nd Chip) 221 Pulse receiving circuit 221a, 221b Diode (electrostatic protection element) 221c, 221d, 221e, 221f buffers 221g, 221h Delay section 221i, 221j AND gates 221k Logic section 221A, 221B Diode (electrostatic protection element) 221C, 221D N-channel MOS field effect transistor (switch) 221E, 221F Comparator (Pulse Detector) 221G Timer 221H Logic section 222, 222(1), 222(2) Driver 222H P-channel MOS field effect transistor 222L N-channel MOS field effect transistor 223 Low voltage protection circuit 230 Trans Chip (3rd Chip) 230a 1st layer (lower layer) 230b 2nd layer (upper layer) 231, 232, 233, 234 transformers 231p, 232p Primary winding 231s, 232s Secondary Winding C1, C2 capacitors GND1, GND2 Ground terminal IN, IN1, IN2, INA, INB input terminals N1 N-channel MOS field effect transistor OUT, OUT1, OUT2 output terminals R1 Resistor T11~T18, T21~T26, T31~T36 terminals VCC1, VCC2 power supply pins X21, X22, X23 internal terminals Y21, Y22, Y23 wiring Z21, Z22, Z23 vias

Claims

1. a first pulse detector that receives a differential input of a first received pulse signal appearing on a secondary winding of a first transformer and a second received pulse signal appearing on a secondary winding of a second transformer; a second pulse detector that receives a differential input of the first received pulse signal and the second received pulse signal with an input polarity opposite to that of the first pulse detector; a logic unit that generates a received pulse signal based on the output signals of the first pulse detector and the second pulse detector; a first switch and a second switch respectively connected across both ends of a secondary winding of the first transformer and the second transformer; a timer that turns on the first switch and the second switch for a predetermined mask period from a pulse detection timing of each of the first pulse detector and the second pulse detector; A pulse receiving circuit comprising:

2. 2. The pulse receiving circuit of claim 1, wherein the first pulse detector and the second pulse detector are each a comparator having an input offset.

3. 3. The pulse receiving circuit according to claim 1, further comprising a first electrostatic protection element and a second electrostatic protection element connected across both ends of a secondary winding of each of the first transformer and the second transformer, respectively.

4. The pulse receiving circuit according to any one of claims 1 to 3, wherein the logic section sets the received pulse signal to a first logic level in response to the first received pulse signal, and sets the received pulse signal to a second logic level in response to the second received pulse signal.

5. a pulse transmission circuit that generates a first transmission pulse signal and a second transmission pulse signal in response to an input pulse signal; a first transformer and a second transformer which transmit the first transmission pulse signal and the second transmission pulse signal to a subsequent stage as a first reception pulse signal and a second reception pulse signal, respectively, while insulating input from output; a pulse receiving circuit according to any one of claims 1 to 4, which generates the received pulse signal in response to the first received pulse signal and the second received pulse signal; a driver for generating an output pulse signal in response to the received pulse signal; A signal transmission device having the following features.

6. 6. The signal transmission device according to claim 5, wherein the pulse transmission circuit outputs a single pulse or multiple pulses to either the first transmission pulse signal or the second transmission pulse signal depending on a logic level of the input pulse signal.

7. the pulse transmitting circuit is integrated into a first chip; the pulse receiving circuit and the driver are integrated into a second chip; the first transformer and the second transformer are integrated into a third chip; 7. A signal transmission device according to claim 5 or 6.

8. The third chip is a first terminal to which a first end of a primary winding forming the first transformer is connected; a second terminal to which a second end of a primary winding forming the first transformer and a first end of a primary winding forming the second transformer are connected; a third terminal to which a second end of a primary winding forming the second transformer is connected; a fourth terminal to which a first end of a secondary winding forming the first transformer is connected; a fifth terminal to which a second end of a secondary winding forming the first transformer and a first end of a secondary winding forming the second transformer are connected; a sixth terminal to which a second end of a secondary winding forming the second transformer is connected; The signal transmission device according to claim 7 , further comprising:

9. 9. The signal transmission device according to claim 5, further comprising a plurality of pairs of the first transformer and the second transformer.

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