Semiconductor Device

Abstract

To provide a semiconductor device having improved reliability.SOLUTION: A semiconductor device 100 includes: a first metal layer 31 connected to a first main terminal P in a first connection region 31x; a second metal layer 32 connected to a second main terminal N in a second connection region 32x; a third metal layer 33 connected to an output terminal AC; a plurality of first semiconductor chips 11 including a first upper electrode 11a, a first lower electrode connected to the first metal layer, and a first gate electrode 11c, the first semiconductor chips being aligned in a first direction; a plurality of second semiconductor chips 21 including a second upper electrode 21a, a second lower electrode connected to the third metal layer, and a second gate electrode 21c, the second semiconductor chips being aligned in the first direction; a first connection wire 44 connecting the first upper electrode to the third metal layer; and a second connection wire 46 connecting the second upper electrode to the second metal layer. The angle between a third direction that connects the first connection region to the second connection region and the first direction is 20° or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap three times larger, breakdown electric field strength about ten times larger, and thermal conductivity about three times larger. By utilizing these characteristics, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high breakdown voltage, low loss, and can operate at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a body diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, the body diode allows a return current to flow even when the MOSFET is off.

[0004] However, when a return current is passed through the body diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which increases the on-resistance of the MOSFET, resulting in a decrease in the reliability of the MOSFET.

[0005] There are MOSFETs with built-in unipolar Schottky barrier diodes (SBDs). By using an SBD instead of a bipolar pn junction diode to pass the return current, the growth of stacking faults is suppressed, improving the reliability of the MOSFET. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2020-155501 A Summary of the Invention [Problem to be solved by the invention]

[0007] A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer provided on the insulating substrate, having a first connection region and electrically connected to the first main terminal at the first connection region, a second metal layer provided on the insulating substrate, having a second connection region and electrically connected to the second main terminal at the second connection region, a third metal layer provided on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region and electrically connected to the output terminal at the third connection region, a first upper electrode, a first lower electrode, and a first gate electrode. a first silicon carbide layer, a first Schottky barrier diode, the first lower electrode being electrically connected to the first metal layer, and a plurality of first semiconductor chips arranged in a first direction; a second semiconductor chip including a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, a second Schottky barrier diode, the second lower electrode being electrically connected to the third metal layer, and a plurality of second semiconductor chips arranged in the first direction; a first connection line electrically connecting the first upper electrode and the third metal layer; and a second connection line electrically connecting the second upper electrode and the second metal layer. a fourth metal layer provided on the insulating substrate, between the first metal layer and the third metal layer, and electrically connected to the first gate electrode; and a fifth metal layer provided on the insulating substrate, between the second metal layer and the third metal layer, and electrically connected to the second gate electrode; the second semiconductor chip is present in a second direction perpendicular to a first direction of the first semiconductor chip and parallel to the insulating substrate, an angle between a third direction connecting the first connection region and the second connection region and the first direction is 20 degrees or less, an angle between an extension direction of the first connection line and the second direction is 20 degrees or less, and an angle between an extension direction of the second connection line connected to the second upper electrode of the second semiconductor chip that is closest to the first metal layer in the first direction among the multiple second semiconductor chips is 20 degrees or less. [Means for solving the problem]

[0008] A semiconductor device according to one aspect of the present invention includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer provided on the insulating substrate, having a first connection region and electrically connected to the first main terminal at the first connection region, a second metal layer provided on the insulating substrate, having a second connection region and electrically connected to the second main terminal at the second connection region, a third metal layer provided on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region and electrically connected to the output terminal at the third connection region, a first upper electrode, a first lower electrode, a first gate electrode, and a first silicon carbide layer, and includes a first Schottky barrier diode, the first lower electrode being electrically connected to the first metal layer, a plurality of first semiconductor chips arranged in a first direction, a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, the second lower electrode being electrically connected to the third metal layer, a first connecting line electrically connecting the first upper electrode and the third metal layer, and a second connecting line electrically connecting the second upper electrode and the second metal layer, the second semiconductor chips being arranged in the first direction, the second semiconductor chips being arranged in a second direction perpendicular to the first direction of the first semiconductor chips and parallel to the insulating substrate, the angle between the first direction and a third direction connecting the first connection region and the second connection region is 20 degrees or less, the angle between the extension direction of the first connecting line and the second direction is 20 degrees or less, and the angle between the extension direction of the second connecting line connected to the second upper electrode of the second semiconductor chip closest to the first metal layer in the first direction among the multiple second semiconductor chips is 20 degrees or less. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic top view of a semiconductor device according to an embodiment; [Diagram 2] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Diagram 3] FIG. 2 is an equivalent circuit diagram of the semiconductor device according to the embodiment. [Figure 4] FIG. 13 is a schematic top view of a semiconductor device of a comparative example. [Diagram 5] 11A and 11B are diagrams illustrating problems in a semiconductor device of a comparative example. [Figure 6] 5A to 5C are diagrams illustrating the operation and effect of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In this specification, the same or similar components are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0011] In this specification, the upward direction of the drawing may be described as "upper" and the downward direction of the drawing may be described as "lower" in order to indicate the positional relationship of parts, etc. In this specification, the concepts of "upper" and "lower" do not necessarily refer to the direction of gravity.

[0012] The semiconductor device of the embodiment includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer provided on the insulating substrate, having a first connection region and electrically connected to the first main terminal at the first connection region, a second metal layer provided on the insulating substrate, having a second connection region and electrically connected to the second main terminal at the second connection region, a third metal layer provided on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region and electrically connected to the output terminal at the third connection region, a first upper electrode, a first lower electrode, a first gate electrode, and a first carbonization electrode. The semiconductor device includes a silicon layer, a first Schottky barrier diode, a first lower electrode electrically connected to the first metal layer, and a plurality of first semiconductor chips arranged in a first direction, a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, a second Schottky barrier diode, a second lower electrode electrically connected to the third metal layer, and a plurality of second semiconductor chips arranged in the first direction, a first connecting line electrically connecting the first upper electrode and the third metal layer, and a second connecting line electrically connecting the second upper electrode and the second metal layer. A second semiconductor chip is present in a second direction perpendicular to the first direction of the first semiconductor chip and parallel to the insulating substrate, and an angle between a third direction connecting the first connection region and the second connection region and the first direction is 20 degrees or less, an angle between an extension direction of the first connection line and the second direction is 20 degrees or less, and an angle between an extension direction of a second connection line connected to a second upper electrode of the second semiconductor chip that is closest to the first metal layer in the first direction among the multiple second semiconductor chips and the second direction is 20 degrees or less.

[0013] Fig. 1 is a schematic top view of the semiconductor device of the embodiment. Fig. 2 is a schematic cross-sectional view of the semiconductor device of the embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1. Fig. 3 is an equivalent circuit diagram of the semiconductor device of the embodiment.

[0014] The semiconductor device of the embodiment is a power semiconductor module 100. As shown in Fig. 3, the power semiconductor module 100 of the embodiment is a so-called "2-in-1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 100 has three half-bridge units connected in parallel. For example, a three-phase inverter circuit can be configured by using three power semiconductor modules of the embodiment.

[0015] 3, the power semiconductor module 100 includes a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), a plurality of high-side MOSFETs 11 (first semiconductor chips), and a plurality of low-side MOSFETs 21 (second semiconductor chips). Each MOSFET incorporates a Schottky barrier diode (SBD) in addition to a pn junction diode. The SBD has a function of passing a return current, for example.

[0016] A plurality of high-side MOSFETs 11 are connected in parallel. A plurality of low-side MOSFETs 21 are connected in parallel. A plurality of high-side MOSFETs 11 and a plurality of low-side MOSFETs 21 are connected in series.

[0017] 1 to 3 show an example in which there are three high-side MOSFETs 11 and three low-side MOSFETs 21. FIG.

[0018] As shown in FIGS. 1 and 2 , the power semiconductor module 100 of the embodiment includes a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), a plurality of high-side MOSFETs 11 (first semiconductor chips), a plurality of low-side MOSFETs 21 (second semiconductor chips), a resin case 24, a lid 26, a metal base 28, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36 (fourth metal layer), a second gate metal layer 37 (fifth metal layer), a back surface metal layer 40, a first gate terminal 41, a second gate terminal 42, a first bonding wire 44 (first connecting wire), a second bonding wire 46 (second connecting wire), a gate bonding wire 48, and a sealing resin 50.

[0019] Each of the multiple high-side MOSFETs 11 (first semiconductor chips) includes a first source electrode 11a (first upper electrode), a first drain electrode 11b (first lower electrode), a first gate electrode 11c, a first silicon carbide layer 11x, and a first Schottky barrier diode 11y.

[0020] Each of the multiple low-side MOSFETs 21 (second semiconductor chips) includes a second source electrode 21a (second upper electrode), a second drain electrode 21b (second lower electrode), a second gate electrode 21c, a second silicon carbide layer 21x, and a second Schottky barrier diode 21y.

[0021] The first metal layer 31 has a first connection region 31x, the second metal layer 32 has a second connection region 32x, and the third metal layer 33 has a third connection region 33x.

[0022] FIG. 1 is a top view of the power semiconductor module 100 with the lid 26 and the sealing resin 50 removed.

[0023] The metal base 28 is made of, for example, copper. For example, when the power semiconductor module 100 is mounted on a product, a heat sink (not shown) is connected to the rear surface of the metal base 28.

[0024] The insulating substrate 30 is provided on the metal base 28. The insulating substrate 30 is provided between the metal base 28 and the high-side MOSFET 11 and between the metal base 28 and the low-side MOSFET 21.

[0025] The insulating substrate 30 serves to electrically isolate the metal base 28 from the high-side MOSFET 11 and the metal base 28 from the low-side MOSFET 21 .

[0026] The insulating substrate 30 is, for example, a ceramic, aluminum oxide, aluminum nitride, or silicon nitride.

[0027] A first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36, and a second gate metal layer 37 are provided on the surface of the insulating substrate 30. The first metal layer 31, the second metal layer 32, the third metal layer 33, the first gate metal layer 36, and the second gate metal layer 37 are made of, for example, copper.

[0028] A back metal layer 40 is provided on the back surface of the insulating substrate 30. The back metal layer 40 is, for example, copper. The back metal layer 40 is bonded to the metal base 28 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0029] The resin case 24 is provided around the metal base 28 and the insulating substrate 30. A portion of the resin case 24 is provided on the metal base 28. The resin case 24 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0030] A lid 26 is provided on the resin case 24. The lid 26 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0031] The multiple high-side MOSFETs 11 are provided on the first metal layer 31. Each of the multiple high-side MOSFETs 11 includes a first source electrode 11a, a first drain electrode 11b, a first gate electrode 11c, a first silicon carbide layer 11x, and a first Schottky barrier diode 11y. The first source electrode 11a is an example of a first upper electrode. The first drain electrode 11b is an example of a first lower electrode.

[0032] The first source electrode 11a is electrically connected to the third metal layer 33. The first source electrode 11a and the third metal layer 33 are electrically connected to each other, for example, by using a first bonding wire 44. The first drain electrode 11b is electrically connected to the first metal layer 31. The first drain electrode 11b is electrically connected to the first metal layer 31 by using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0033] The multiple high-side MOSFETs 11 are arranged in a first direction parallel to the insulating substrate 30.

[0034] The low-side MOSFETs 21 are provided on the third metal layer 33. Each of the low-side MOSFETs 21 includes a second source electrode 21a, a second drain electrode 21b, a second gate electrode 21c, a second silicon carbide layer 21x, and a second Schottky barrier diode 21y. The second source electrode 21a is an example of a second upper electrode. The second drain electrode 21b is an example of a second lower electrode.

[0035] The second source electrode 21a is electrically connected to the second metal layer 32. The second source electrode 21a and the second metal layer 32 are electrically connected to each other, for example, by using a second bonding wire 46. The second drain electrode 21b is electrically connected to the third metal layer 33. The second drain electrode 21b is electrically connected to the third metal layer 33, for example, by using a solder layer or a silver nanoparticle layer (not shown).

[0036] The low-side MOSFETs 21 are arranged in a first direction parallel to the insulating substrate 30 .

[0037] The sealing resin 50 is filled into the resin case 24. The sealing resin 50 is surrounded by the resin case 24. The sealing resin 50 covers the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0038] The sealing resin 50 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30. It also has a function of insulating the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0039] The sealing resin 50 includes a resin. The sealing resin 50 is, for example, a silicone gel. For the sealing resin 50, other resins such as an epoxy resin or a polyimide resin can also be used.

[0040] The positive terminal P is provided on one end side of the insulating substrate 30. For example, in Fig. 1, the positive terminal P is provided on the right side of the insulating substrate 30. The positive terminal P has a wiring connection hole.

[0041] The positive terminal P is electrically connected to the first metal layer 31 at the first connection region 31x. In the first connection region 31x, the first metal layer 31 and the positive terminal P are connected using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0042] For example, a positive voltage is applied from the outside to the positive terminal P. The positive terminal P is made of a metal. For example, the positive terminal P is made of copper.

[0043] The negative terminal N is provided on one end side of the insulating substrate 30. The negative terminal N is provided on the same side of the insulating substrate 30 as the positive terminal P. The negative terminal N has a wiring connection hole.

[0044] The negative terminal N is electrically connected to the second metal layer 32 at the second connection region 32x. In the second connection region 32x, the second metal layer 32 and the negative terminal N are connected using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0045] For example, a negative voltage is applied from the outside to the negative terminal N. The negative terminal N is made of a metal. For example, the negative terminal N is made of copper.

[0046] The AC output terminal AC is provided on one end side of the insulating substrate 30. The AC output terminal AC is provided on the same side of the insulating substrate 30 as the positive terminal P and the negative terminal N. The AC output terminal AC has a wiring connection hole.

[0047] The AC output terminal AC is electrically connected to the third metal layer 33 at the third connection region 33x. In the third connection region 33x, the third metal layer 33 and the AC output terminal AC are connected using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0048] The AC output terminal AC outputs an output current of the half-bridge circuit. The AC output terminal AC is made of a metal. For example, the AC output terminal AC is made of copper.

[0049] The first gate terminal 41 is electrically connected to the first gate electrode 11c of the high-side MOSFET 11. The first gate terminal 41 is electrically connected to the first gate electrode 11c using, for example, the first gate metal layer 36 and a gate bonding wire 48.

[0050] The second gate terminal 42 is electrically connected to the second gate electrode 21c of the low-side MOSFET 21. The second gate terminal 42 is electrically connected to the second gate electrode 21c using, for example, the second gate metal layer 37 and a gate bonding wire 48.

[0051] The first metal layer 31 is provided on the insulating substrate 30. The first metal layer 31 has a first connection region 31x. The first metal layer 31 is electrically connected to the positive terminal P at the first connection region 31x.

[0052] The second metal layer 32 is provided on the insulating substrate 30. The second metal layer 32 has a second connection region 32x. The second metal layer 32 is electrically connected to the negative terminal N at the second connection region 32x. The second metal layer 32 is electrically connected to the second source electrode 21a of the low-side MOSFET 21.

[0053] The third metal layer 33 is provided on the insulating substrate 30. The third metal layer 33 includes a third connection region 33x. The third metal layer 33 is electrically connected to the AC output terminal AC at the third connection region 33x. The third metal layer 33 is electrically connected to the first source electrode 11a of the high-side MOSFET 11.

[0054] One low-side MOSFET 21 among the multiple low-side MOSFETs 21 is present in a second direction perpendicular to the first direction and parallel to the insulating substrate 30 for each of the multiple high-side MOSFETs 11. In other words, the high-side MOSFET 11 is provided adjacent to the low-side MOSFET 21 in the second direction.

[0055] The direction connecting the first connection region 31x and the second connection region 32x is defined as a third direction. The third direction is the direction of the line segment connecting the first connection region 31x and the second connection region 32x at the shortest distance. The angle between the third direction and the first direction is 20 degrees or less.

[0056] 1, for example, the third direction is parallel to the first direction. The angle between the third direction and the first direction is 0 degrees. Therefore, the multiple high-side MOSFETs 11 are arranged in the third direction. Also, the multiple low-side MOSFETs 21 are arranged in the third direction.

[0057] The angle between the extension direction of the first bonding wire 44 and the second direction is 20 degrees or less. For example, when multiple first bonding wires 44 are connected to one high-side MOSFET 11, the angle between the extension direction of at least one of the multiple first bonding wires 44 and the second direction is 20 degrees or less. The angle between the extension direction of a first bonding wire 44 connected to any one of the multiple high-side MOSFETs 11 and the second direction is 20 degrees or less.

[0058] The angle between the extension direction of the first bonding wire 44 and the third direction is 70 degrees or more and 90 degrees or less. For example, when multiple first bonding wires 44 are connected to one high-side MOSFET 11, the angle between the extension direction of at least one of the multiple first bonding wires 44 and the third direction is 70 degrees or more and 90 degrees or less. The angle between the extension direction of the first bonding wire 44 connected to any one of the multiple high-side MOSFETs 11 and the third direction is 70 degrees or more and 90 degrees or less.

[0059] The extension direction of the first bonding wire 44 is, for example, the direction of a line segment connecting the position where the first bonding wire 44 contacts the first source electrode 11a and the position where the first bonding wire 44 contacts the third metal layer 33.

[0060] For example, the angle between the extension directions of all first bonding wires 44 included in the semiconductor module 100 and the second direction is 20 degrees or less. Fig. 1 shows a case where the angle between the extension directions of all first bonding wires 44 included in the semiconductor module 100 and the second direction is 0 degree.

[0061] The angle between the extension direction of the second bonding wire 46 and the second direction is 20 degrees or less. For example, when multiple first bonding wires 44 are connected to one low-side MOSFET 21, the angle between the extension direction of at least one second bonding wire 46 among the multiple second bonding wires 46 and the second direction is 20 degrees or less. The angle between the extension direction of the second bonding wire 46 connected to any one low-side MOSFET 21 among the multiple low-side MOSFETs 21 and the second direction is 20 degrees or less.

[0062] The angle between the extension direction of the second bonding wire 46 connected to the second source electrode 21a of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21 and the second direction is 20 degrees or less. That is, in FIG. 1, the angle between the extension direction of the second bonding wire 46 connected to the second source electrode 21a of the low-side MOSFET 21 that is located at the bottom among the multiple low-side MOSFETs 21 and the second direction is 20 degrees or less.

[0063] The angle between the extension direction of the second bonding wire 46 and the third direction is 70 degrees or more and 90 degrees or less. For example, when multiple second bonding wires 46 are connected to one low-side MOSFET 21, the angle between the extension direction of at least one second bonding wire 46 among the multiple second bonding wires 46 and the third direction is 70 degrees or more and 90 degrees or less. The angle between the extension direction of the second bonding wire 46 connected to any one low-side MOSFET 21 among the multiple low-side MOSFETs 21 and the third direction is 70 degrees or more and 90 degrees or less.

[0064] The extension direction of the second bonding wire 46 is, for example, the direction of a line segment connecting the position where the second bonding wire 46 contacts the second source electrode 21a and the position where the second bonding wire 46 contacts the second metal layer 32.

[0065] For example, the angle between the extension directions of all the second bonding wires 46 included in the semiconductor module 100 and the second direction is 20 degrees or less. Fig. 1 shows a case where the angle between the extension directions of all the second bonding wires 46 included in the semiconductor module 100 and the second direction is 0 degree.

[0066] For example, the second metal layer 32 is present in the second direction of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21. That is, in FIG. 1, the second metal layer 32 is present in the second direction of the low-side MOSFET 21 that is located at the bottom among the multiple low-side MOSFETs 21.

[0067] For example, the second metal layer 32 is present in the second direction of the contact (C1 and C2 in FIG. 1) between the second source electrode 21a and the second bonding wire 46 of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21. For example, the second metal layer 32 is present in the second direction of the contact (C2 in FIG. 1) that is closest to the first metal layer 31 among the low-side MOSFETs 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21.

[0068] For example, the end (E1 in FIG. 1) of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction, which is closer to the first metal layer 31, has the second metal layer 32 in the second direction.

[0069] For example, a first distance in a first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side (d1 in FIG. 1) is greater than a second distance in the first direction between the end of the low-side MOSFET 21 closest to the first metal layer 31 in the first direction, the end farther from the first metal layer 31, and the end of the second metal layer 32 on the first metal layer 31 side, among the multiple low-side MOSFETs 21.

[0070] For example, a first distance (d1 in FIG. 1) in a first direction between the second connection region 32x and the end of the second metal layer 32 on the side of the first metal layer 31 is greater than a third distance (d3 in FIG. 1) in the first direction between the second connection region 32x and the end of the second metal layer 32 opposite the first metal layer 31.

[0071] Next, the operation and effects of the semiconductor device of the embodiment will be described.

[0072] A vertical MOSFET using silicon carbide has a pn junction diode as a body diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, the body diode allows a return current to flow even when the MOSFET is off.

[0073] However, when a return current is passed through the body diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which increases the on-resistance of the MOSFET, resulting in a decrease in the reliability of the MOSFET.

[0074] There are MOSFETs with built-in unipolar Schottky barrier diodes (SBDs). By using an SBD instead of a bipolar pn junction diode to pass the return current, the growth of stacking faults is suppressed, improving the reliability of the MOSFET.

[0075] Even in a power semiconductor module that includes multiple MOSFETs with built-in SBDs, it is important to suppress the operation of the pn junction diode of each MOSFET in order to improve the reliability of the power semiconductor module.

[0076] 4 is a schematic top view of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a power semiconductor module 900. An equivalent circuit diagram of the power semiconductor module 900 is similar to that of FIG.

[0077] 4, the power semiconductor module 900 differs from the power semiconductor module 100 of the embodiment in that the first direction in which the multiple high-side MOSFETs 11 are arranged is perpendicular to the third direction. Also, the power semiconductor module 900 differs from the power semiconductor module 100 of the embodiment in that the first direction in which the multiple low-side MOSFETs 21 are arranged is perpendicular to the third direction. The third direction is a direction connecting the first connection region 31x and the second connection region 32x.

[0078] The power semiconductor module 900 also differs from the power semiconductor module 100 of the embodiment in that the extension direction of the first bonding wires 44 and the angle formed by the third direction are parallel to each other as shown in Fig. 4. The power semiconductor module 900 also differs from the power semiconductor module 100 of the embodiment in that the extension direction of the second bonding wires 46 and the angle formed by the third direction are parallel to each other as shown in Fig. 4.

[0079] It has become clear that, during switching operation of the power semiconductor module 900, variations occur in the current flowing through the diodes included in the multiple high-side MOSFETs 11 or the diodes included in the multiple low-side MOSFETs 21. It has become clear that when the variation in the current flowing through the diodes becomes large, the current exceeds the amount of current that a Schottky barrier diode can pass, and this may cause the pn junction diode to operate.

[0080] 5 is a diagram illustrating the problem of the semiconductor device of the comparative example, and is a schematic top view of a power semiconductor module 900.

[0081] 5, three paths, namely, a path X9, a path Y9, and a path Z9, which run from the positive terminal P through the MOSFET to the negative terminal N are shown by dotted arrows. The paths X9, Y9, and Z9 are paths that run from the first connection region 31x to the second connection region 32x.

[0082] As a result of investigations by the inventors, it has become clear that the variation in the current flowing through the diode during the switching operation of the power semiconductor module 900 depends on the variation in the lengths of the path X9, the path Y9, and the path Z9.

[0083] For example, of the three paths, path X9 is the shortest path and path Z9 is the longest path. The current flowing through the MOSFET diode on path X9, which is the shortest path, is the largest. Also, the current flowing through the MOSFET diode on path Z9, which is the longest path, is the smallest.

[0084] For example, consider a case where the power semiconductor module 900 is connected to an external inductive load, and a current flows with the multiple high-side MOSFETs 11 in the OFF state and the multiple low-side MOSFETs 21 in the ON state. From this state, the multiple high-side MOSFETs 11 are switched to the ON state and the multiple low-side MOSFETs 21 are switched to the OFF state. At this time, the multiple low-side MOSFETs 21 are in the reverse conducting state, and a reflux current flows through the diode built into the low-side MOSFET 21.

[0085] At this time, the current flowing through the diode of the low-side MOSFET 21 on the path X9, which is the shortest path, is the largest, and the current flowing through the diode of the low-side MOSFET 21 on the path Z9, which is the longest path, is the smallest.

[0086] When the return current flowing through the diode of the low-side MOSFET 21 present on the path X9 exceeds the allowable current range of the second Schottky barrier diode 21y included in the low-side MOSFET 21, the pn junction diode operates. When the pn junction diode operates, the reliability of the low-side MOSFET 21 present on the path X9 decreases. As a result, the reliability of the power semiconductor module 900 decreases.

[0087] 6 is a diagram for explaining the operation and effect of the semiconductor device according to the embodiment. FIG. 6 is a schematic top view of the power semiconductor module 100.

[0088] 6, three paths, namely, path X1, path Y1, and path Z1, which run from the positive terminal P through the MOSFET to the negative terminal N are shown by dotted arrows. The paths X1, Y1, and Z1 are paths which run from the first connection region 31x to the second connection region 32x.

[0089] The power semiconductor module 100 of the first embodiment is different from the power semiconductor module 900 of the comparative example in that the arrangement direction of the MOSFETs and the extension direction of the bonding wires are changed to suppress variations in the lengths of the paths X1, Y1, and Z1.

[0090] Specifically, the multiple high-side MOSFETs 11 are arranged along a third direction connecting the first connection region 31x and the second connection region 32x. The multiple low-side MOSFETs 21 are also arranged along the third direction. The angle between the third direction and the first direction in which the multiple high-side MOSFETs 11 and the multiple low-side MOSFETs 21 are arranged is 20 degrees or less.

[0091] Moreover, the angle between the extending direction of the first bonding wire 44 and the second direction is 20 degrees or less. The angle between the extending direction of the second bonding wire 46 and the second direction is 20 degrees or less.

[0092] In the power semiconductor module 100 of the embodiment, the above configuration suppresses the variation in the lengths of the path X1, the path Y1, and the path Z1. Therefore, the variation in the current flowing through the diode during the switching operation of the power semiconductor module 100 is suppressed. Therefore, the operation of the pn junction diode included in the MOSFET is suppressed. Therefore, the reliability of the power semiconductor module 100 is improved.

[0093] The angle between the third direction and the first direction in which the multiple high-side MOSFETs 11 and the multiple low-side MOSFETs 21 are arranged is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degree. By reducing the angle, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0094] It is also preferable that the angle between the extension direction of all first bonding wires 44 included in the semiconductor module 100 and the second direction is 20 degrees or less. It is also preferable that the angle between the extension direction of all second bonding wires 46 included in the semiconductor module 100 and the second direction is 20 degrees or less. With the above configuration, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0095] Moreover, the angle between the extension direction of the first bonding wire 44 and the second direction is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degrees. The angle between the extension direction of the second bonding wire 46 and the second direction is preferably 10 degrees or less, more preferably 5 degrees or less, and most preferably 0 degrees. By reducing the above angle, the variation in the lengths of the path X1, the path Y1, and the path Z1 is further suppressed.

[0096] It is preferable that the second metal layer 32 is present in the second direction of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21. That is, it is preferable that the second metal layer 32 is present in the second direction of the low-side MOSFET 21 that is located at the bottom among the multiple low-side MOSFETs 21 in Fig. 1. With the above configuration, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0097] It is preferable that the second metal layer 32 is present in the second direction of the contact (C1 and C2 in FIG. 1) between the second source electrode 21a and the second bonding wire 46 of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the plurality of low-side MOSFETs 21. It is preferable that the second metal layer 32 is present in the second direction of the contact (C2 in FIG. 1) that is closest to the first metal layer 31 among the contacts between the second source electrode 21a and the second bonding wire 46 of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the plurality of low-side MOSFETs 21. With the above configuration, the variation in the lengths of the path X1, the path Y1, and the path Z1 is further suppressed.

[0098] It is preferable that the second metal layer 32 is present in the second direction at the end (E1 in FIG. 1) closer to the first metal layer 31 of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction among the multiple low-side MOSFETs 21. With the above configuration, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0099] A first distance (d1 in FIG. 1) in the first direction between the second connection region 32x and the end of the second metal layer 32 on the first metal layer 31 side is preferably greater than a second distance (d2 in FIG. 1) in the first direction between an end of the low-side MOSFET 21 that is closest to the first metal layer 31 in the first direction, among the multiple low-side MOSFETs 21, that is farther from the first metal layer 31, and an end of the second metal layer 32 on the first metal layer 31 side. With the above configuration, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0100] A first distance (d1 in FIG. 1) in the first direction between the second connection region 32x and the end of the second metal layer 32 on the side of the first metal layer 31 is preferably greater than a third distance (d3 in FIG. 1) in the first direction between the second connection region 32x and the end of the second metal layer 32 opposite the first metal layer 31. With the above configuration, the variation in the lengths of the paths X1, Y1, and Z1 is further suppressed.

[0101] In the embodiment, the case where the number of power semiconductor chips arranged in parallel is three has been described as an example, but the number of power semiconductor chips may be two or four or more.

[0102] In the embodiment, the power semiconductor module has been described as a "2-in-1" type module, but the power semiconductor module may have other circuit configurations, such as a "4-in-1" type or a "6-in-1" type.

[0103] The first connection line and the second connection line may be linear bonding wires or ribbon bonding wires, and may be, for example, plate-shaped conductors as long as they have the function of providing electrical connection.

[0104] In the embodiment, a case has been described where a part of a terminal such as the positive terminal P is directly connected to a metal layer, but for example, the terminal and the metal layer may be connected by, for example, a bonding wire.

[0105] In the embodiment, an example has been described in which the positive terminal, the negative terminal, and the AC output terminal are all provided at the same end of the power semiconductor module, but the positions of the positive terminal, the negative terminal, and the AC output terminal are not limited to the above-mentioned positions.

[0106] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0107] 11 High-side MOSFET (first semiconductor chip) 11a: first source electrode (first upper electrode) 11b first drain electrode (first lower electrode) 11c first gate electrode 11x first silicon carbide layer 11y First Schottky Barrier Diode 21 Low-side MOSFET (second semiconductor chip) 21a: second source electrode (second upper electrode) 21b Second drain electrode (second lower electrode) 21c second gate electrode 21x second silicon carbide layer 21y Second Schottky Barrier Diode 30 Insulating substrate 31 First metal layer 31x First Connection Area 32 Second Metal Layer 32x Secondary Connection Area 33 Third Metal Layer 33x 3rd connection area 36 First gate metal layer (fourth metal layer) 37 Second gate metal layer (fifth metal layer) 41 First gate terminal 42 Second gate terminal 44 First bonding wire (first connection wire) 46 Second bonding wire (second connection wire) 100 Power semiconductor module (semiconductor device) AC output terminal (output terminal) C1 Contact C2 Contact N Negative terminal (second main terminal) P Positive terminal (first main terminal) d1 First distance d2 Second distance d3 The third distance

Claims

1. An insulating substrate; A first main terminal; A second main terminal; An output terminal; a first metal layer provided on the insulating substrate, the first metal layer having a first connection region and electrically connected to the first main terminal at the first connection region; a second metal layer provided on the insulating substrate, the second metal layer having a second connection region and electrically connected to the second main terminal at the second connection region; a third metal layer provided on the insulating substrate, located between the first metal layer and the second metal layer, having a third connection region, and electrically connected to the output terminal at the third connection region; a first semiconductor chip including a first upper electrode, a first lower electrode, a first gate electrode, and a first silicon carbide layer, the first semiconductor chip including a first Schottky barrier diode, the first lower electrode being electrically connected to the first metal layer, the first semiconductor chip being arranged in a first direction; a plurality of second semiconductor chips including a second upper electrode, a second lower electrode, a second gate electrode, and a second silicon carbide layer, the second Schottky barrier diode being electrically connected to the third metal layer, the second lower electrode being arranged in the first direction; a first connection line electrically connecting the first upper electrode and the third metal layer; a second connection line electrically connecting the second upper electrode and the second metal layer; a fourth metal layer provided on the insulating substrate, between the first metal layer and the third metal layer, and electrically connected to the first gate electrode; a fifth metal layer provided on the insulating substrate, between the second metal layer and the third metal layer, and electrically connected to the second gate electrode; Equipped with the second semiconductor chip is present in a second direction perpendicular to the first direction of the first semiconductor chip and parallel to the insulating substrate; an angle between a third direction connecting the first connection region and the second connection region and the first direction is 20 degrees or less; A semiconductor device, wherein the angle between the extension direction of the second connection line connected to the second upper electrode of the second semiconductor chip that is closest to the first metal layer in the first direction among a plurality of the second semiconductor chips and the second direction is 20 degrees or less.

2. 2. The semiconductor device according to claim 1, wherein the second metal layer is present in the second direction of the second semiconductor chip that is closest to the first metal layer in the first direction among the plurality of second semiconductor chips.

3. 3. A semiconductor device as described in claim 1 or claim 2, wherein the second metal layer is present in the second direction of the contact point between the second upper electrode and the second connection line of the second semiconductor chip that is closest to the first metal layer in the first direction among the multiple second semiconductor chips.

4. 4. A semiconductor device as claimed in claim 1, wherein the second metal layer is present in the second direction at the end closer to the first metal layer of the second semiconductor chip that is closest to the first metal layer in the first direction among the multiple second semiconductor chips.

5. 5. A semiconductor device as claimed in any one of claims 1 to 4, wherein a first distance in the first direction between the second connection region and an end of the second metal layer on the side of the first metal layer is greater than a second distance between an end of a second semiconductor chip, among the plurality of second semiconductor chips, that is closest to the first metal layer in the first direction, that is farther from the first metal layer, and the end of the second metal layer on the side of the first metal layer.

6. 6. A semiconductor device as claimed in any one of claims 1 to 5, wherein a first distance in the first direction between the second connection region and an end of the second metal layer on the side of the first metal layer is greater than a third distance in the first direction between the second connection region and an end of the second metal layer opposite the first metal layer.

7. 7. The semiconductor device according to claim 1, wherein an angle between an extending direction of the first connection line and the second direction is 20 degrees or less.

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