MEMORY WITH SINGLE-ENDED SENSING USING RESET-SET LATCH - Patent application

Abstract

Various implementations provide systems and methods for reading data from a memory bitcell. An exemplary implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bitline signal. The single-ended output and the virtual bitline signal provide complementary inputs to the RS latch, which stores the sensed bit, and the sensed bit can be driven onto a data bus.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of U.S. patent application Ser. No. 17 / 456,773, filed Nov. 29, 2021, the entire disclosure of which is incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] This application relates generally to memory read circuits, and more particularly to single-ended memory read circuits employing reset-set latches. [Background technology]

[0003]

[0003] An exemplary memory may include a number of memory bit cells (also called memory cells) arranged in columns, with the bit cells in a given column sharing a bit line. The bit line may be driven by a memory write circuit and may be read by a sense amplifier coupled to a latch. For example, some differential read circuits may use a reset-set (RS) latch that receives as inputs a value derived from a bit line and a value derived from a complementary bit line. In contrast, some single-ended read circuits may use a clocked latch. An exemplary single-ended read circuit does not include a complementary value that may be derived from a bit line and a complementary bit line. Single-ended read circuits that use a clocked latch may suffer from excessive dynamic power.

[0004]

[0004] Therefore, there is a need in the art for a technique for reading data from a bitcell that not only supports single-ended operation, but also has lower power consumption. Summary of the Invention

[0005]

[0005] Various implementations provide systems and methods for reading data from memory bit cells. Exemplary implementations include a single-ended sensing scheme that includes virtual complementary bit line signals. A value derived from the bit line and a value derived from the virtual complementary bit line signals can be input to a Reset-Set (RS) latch, where the value can be stored.

[0006]

[0006] According to one implementation, the memory includes a first bit line coupled to a bit cell, a second bit line coupled to the first bit line, a first logic gate coupled to the second bit line, and a reset-set (RS) latch having a first input and a second input, the first input coupled to the second bit line and the second input coupled to the second bit line via the first logic gate.

[0007]

[0007] According to one implementation, a method for reading data from a bit cell includes sensing a state, including causing a first bit line to assume a state according to a digital bit stored in the bit cell and causing a second bit line coupled to the first bit line to assume a single-ended digital value based at least in part on the digital bit, generating a virtual bit line value, receiving the single-ended digital value and the virtual bit line value in a reset-set (RS) latch, and storing the digital bit in the RS latch.

[0008]

[0008] According to one implementation, a memory device includes means for storing bits of data, means for sensing a state of a bit line coupled to the means for storing bits of data, means for generating a virtual bit line value from an output of the means for sensing, and a reset-set (RS) latch having a first input coupled to the means for sensing and a second input coupled to the means for generating the virtual bit line value.

[0009]

[0009] According to one implementation, a system includes a memory device coupled to a processor and configured to perform read and write operations in response to the processor, a plurality of bit cells arranged in rows and columns within the memory device, and a read circuit coupled to a first one of the bit cells, the read circuit including a bit line pair coupled to a first logic gate and to the first one of the bit cells, a reset-set (RS) latch having a first input coupled to an output of the first logic gate, and a second logic gate coupled to a second input of the RS latch, the second logic gate further coupled to the output of the first logic gate and a control signal. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a conceptual block diagram illustrating an example of a processing system, according to one implementation. [Diagram 2]

[0011] 2 is a schematic diagram of an exemplary implementation of memory cells of a memory bank, according to one implementation. [Diagram 3]

[0012] FIG. 1 is a diagram of an exemplary memory system using single-ended sensing and RS latches, according to one implementation. [Figure 4] FIG. 1 is a diagram of an exemplary memory system using single-ended sensing and RS latches, according to one implementation. [Diagram 5]

[0013] FIG. 5 is an example timing diagram of the system of FIGS. 3 and 4 according to one implementation. [Figure 6]

[0014] FIG. 2 is a diagram of an exemplary cross-coupled NOR gate that provides voltage level shifting, according to one implementation. [Figure 7]

[0015] 1 illustrates an exemplary method for operating a semiconductor device such as a write driver circuit, according to one implementation. [Figure 8]

[0016] FIG. 7 is a diagram of an exemplary system-on-chip (SoC) that may include a memory such as those of FIGS. 2-6, according to one implementation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0017] An exemplary implementation includes a memory with a single-ended sensing architecture that employs a reset-set (RS) latch to receive and store bits of sensed data. Focusing on a given bit cell to be read, the bit cell includes a pair of bit lines, a bit line and a complementary bit line. One of the bit lines can be coupled to a local bit line that feeds a global bit line at the sensing stage of the memory system.

[0012]

[0018] The sensing stage may include a pair of upper and lower bit lines, which are coupled to a local bit line, for example, via the upper bit line. A logic gate, such as a NAND gate, may receive the pair of lower and upper bit lines as inputs and provide an output on a global bit line. The global bit line may include one or more inverters in series with the output of the logic gate. The global bit line may take a value derived from one of the bit lines of the bit cell's bit line pair. For example, if the local bit line is coupled to the bit cell's complementary bit line, the value of the global bit line may depend at least in part on the value of the complementary bit line.

[0013]

[0019] Continuing with this example, the memory system may further include a logic gate coupled to a second bit line, e.g., a global bit line. In one implementation, the logic gate may include a NOR gate that receives as inputs the global bit line and a control signal. For example, the control signal may include any suitable signal, but in some implementations may be a periodic signal having a desired period and duty cycle. The output of the logic gate may then be used as a virtual bit line (or bit line bar) signal that is input to the RS latch. The RS latch may include a pair of cross-coupled NOR gates. A first one of the cross-coupled NOR gates receives as inputs the output of the logic gate (the virtual bit line or bit line bar signal) and an output from a second one of the cross-coupled NOR gates. The second cross-coupled NOR gate may include as its inputs the output of the first cross-coupled NOR gate as well as the global bit line. The output of the system may be obtained from the output of the second cross-coupled NOR gate.

[0014]

[0020] Various implementations may also include a method. An exemplary method includes sensing a value from a bit cell, the bit cell storing a data value. An exemplary method may include outputting a single-ended value from a logic gate, such as a NAND gate, from a sensing stage. The output from the sensing stage may correspond to a global bit line, providing the value to be latched. The method may further include latching the value from the sensing stage by employing an RS latch. One exemplary action of the method may include generating a virtual bit line (or bit line bar) signal for use as an input to the RS latch, where another input may include the value on the global bit line. The RS latch then stores the value sensed in the sensing stage.

[0015]

[0021] High power consumption is a concern for systems on chips (SoCs), central processing units (CPUs), graphics processing units (GPUs), and the like. The circuits and methods discussed herein can be implemented in SoCs, CPUs, GPUs, and other circuits, including memory systems. For example, some implementations may include a multi-port memory that provides two reads and one write (2R+1W) per clock cycle, which may occupy a large portion of the GPU (768 instances). In some conventional GPUs, the dynamic power coming from the memory (e.g., read and write operations) may be as high as 15% of the total GPU power. Traditionally, multi-port memories may have single-ended sensing followed by a latch controlled by a local clock signal. However, a single-ended sensing scheme with a clocked latch may contribute to undesirable excess input / output (IO) read dynamic power from the local clock and control signals. In contrast, various implementations described herein can instead use single-ended sensing with RS latches, which may be a lower power solution than clocked latches in other systems.

[0016]

[0022] Moreover, another advantage of various implementations is that the RS latch can be used for voltage level shifting. For example, some implementations may include different power domains for the sensing stage and the latch stage. As described in more detail below, the latch stage can provide level shifting to interface between the two power domains. Furthermore, various implementations described herein break the mold by using an RS latch with two inputs to interface with a global bit line that has a single-ended value. The single-ended value is accommodated by the use of a virtual bit line or bit line bar signal such that the RS latch receives two inputs.

[0017]

[0023] Next, various aspects of memory are presented in the context of static random access memory (SRAM). SRAM is a volatile memory that requires power to retain data. However, as will be readily appreciated by those skilled in the art, such aspects can be extended to other memories and / or circuit configurations. Examples of other memories include random access memory (RAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate RAM (DDRAM), read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), general purpose registers on a processor, processor cache, flash memory, or any other suitable memory. Thus, any reference to SRAM is intended only to illustrate an exemplary aspect of memory, and it will be understood that such aspects can be extended to a wide range of applications.

[0018]

[0024] FIG. 1 is a conceptual block diagram illustrating an example of a processing system 100 according to one implementation. The processing system 100 includes a processor 102 and a memory 104. The processor 102 can be a microprocessor, a microcontroller, a digital signal processor (DSP), a programmable logic implementing a processor, or other processing circuitry. The memory 104 can be a multi-bank memory, such as a static random access memory (SRAM), or any other multi-bank component capable of retrieving and storing information. As described in more detail with respect to FIG. 3 and FIG. 4, the memory 104 can include multiple single-ended sensing stages latched by RS latches.

[0019]

[0025] The processor 102 shown in FIG. 1 is connected to a memory 104. The connections between the processor 102 and the memory 104 may include an address bus 106, a write data bus 108, a read data bus 110, and a control bus 112. The write data bus 108 may be used to write data from the processor 102 to the memory 104. The control bus 112 may include signals used to control the writing of data from the processor 102 to the memory 104. The read data bus 110 may be used to read data from the memory 104 to the processor 102. The control bus 112 may include signals used to control the reading of data from the memory 104 to the processor 102. For example, the control bus 112 may include signals such as a read signal and a write signal. The read signal may be a single signal line, e.g., a single bit, that indicates when the memory is to be read by the processor 102. The write signal may be a single signal line that indicates when the memory is to be written by the processor 102. In some embodiments, control bus 112 may also include byte enable signals. The byte enable signals may be a group of signal lines that indicate the size of the data, e.g., 8, 16, 32, 64 bytes, etc. However, in some embodiments, the size of the data may be fixed, e.g., 8, 16, 32, 64 bytes, etc. Thus, the byte enable signals may be optional on control bus 112.

[0020]

[0026] The control bus 112 may include read and write signals. The read and write signals may be used to generate read and write enables, respectively, in the memory 104. The address bus 106 may be used to indicate where in the memory 104 the processor is to read or write. For example, if the processor 102 wants to read a location in the memory 104, the processor 102 may output the address of that location on the address bus 106. Furthermore, the processor 102 may actively drive a read signal, which may be part of the control bus 112. The memory 104 may then output the data in the location indicated by the address bus 106 on the read data bus 110. Similarly, if the processor 102 wants to write to a location in the memory 104, the processor 102 may output the address of the location to be written on the address bus 106. Furthermore, the processor 102 may actively drive a write signal, which may be part of the control bus 112. The processor 102 may drive a write data bus 108 with data to be written to the memory 104 .

[0021]

[0027] The write data bus 108 and the read data bus 110 are shown as separate buses in FIG. 1. However, in other embodiments, a single bidirectional data bus can be used to write data from the processor 102 to the memory 104 and to read data from the memory 104 to the processor 102. In an exemplary implementation, bits of data to be read from the memory 104 are stored in RS latches and then driven onto the read data bus 110 by one or more data drivers (not shown). Of course, the range of implementations is not limited to those shown in FIG. 1. For example, in an implementation that includes a processor cache, there may be different connections between the processor 102 and the memory 104 than those shown in FIG. 1. However, the concepts discussed herein may be applied to any suitable implementation.

[0022]

[0028] FIG. 2 is a schematic diagram of an exemplary implementation of a memory cell 214 of a memory bank. For example, the memory 104 of FIG. 1 may include multiple memory banks, each of which includes multiple memory cells (also called bit cells) arranged in rows and columns. FIGS. 3 and 4 (described in more detail below) show exemplary circuits for reading bits of data from the memory cell 214 using a sensing stage and an RS latch stage. The memory cell 214 shown in FIG. 2 is a six-transistor (6T) configuration. However, it will be appreciated that any suitable architecture can be used for the memory cell 214, such as a four-transistor (4T), eight-transistor (8T), ten-transistor (10T), or other suitable architecture.

[0023]

[0029] A memory cell 214 is shown having two inverters 202, 204. The first inverter 202 includes a positive channel metal oxide semiconductor field effect (PMOS) transistor 206 and a negative channel metal oxide semiconductor field effect (NMOS) transistor 208. The second inverter 204 includes a PMOS transistor 210 and an NMOS transistor 212. In the described embodiment, the inverters 202 and 204 are powered by VDD and have a return power rail VSS (e.g., ground). The first inverter 202 and the second inverter 204 are interconnected to form a cross-coupled latch. A first NMOS access transistor 217 couples an output node 216 from the first inverter 202 to a bit line bl, and a second NMOS transistor 218 couples an output node 220 from the second inverter 204 to a bit line blb 224 (whose value is the opposite or inverse of the bit line bl 222). The gates of NMOS access transistors 214, 218 are coupled to word line WWL.

[0024]

[0030] A write operation can be performed by setting the bit lines bl222 and blb224 to the values ​​to be written to the memory cell 214 and asserting the word line WWL. The word line WWL can be asserted before the values ​​to be written (e.g., write data) are provided to the bit lines bl222 and blb224. A high value, e.g., logic level "1", can be written to the memory cell 214 by setting the bit line bl to logic level "0" and setting the bit line blb224 to logic level "1". The logic level "0" on the bit line bl222 is applied to the second inverter 204 through the first NMOS transistor 214, thereby forcing the output node 220 of the second inverter 204 to VDD. The output node 220 of the second inverter 204 is applied to the input of the first inverter 202, thereby forcing the output node 216 of the first inverter 202 to VSS. A logic level "0" can be written to memory cell 214 by reversing the values ​​on bit lines bl222 and blb224.

[0025]

[0031] Once the write operation is complete, the word line WWL is deasserted, causing the NMOS access transistors 214 and 218 to disconnect the bit lines bl222 and blb224 from the two inverters 202, 204. The cross-coupling between the two inverters 202, 204 maintains the state of the inverter outputs as long as power is applied to the memory cell 214.

[0026]

[0032] The memory cell 214 stores data according to the data values ​​stored at the output nodes 216 and 220. If the memory cell 214 stores a logic high (i.e., "1"), the output node 216 is at a logic high and the output node 220 is at a logic low (i.e., "0"). If the memory cell 214 stores a logic low, the output node 216 is at a logic low and the output node 220 is at a logic high. During a read operation, the differential bit lines bl 222 and blb 224 can be precharged by a precharge circuit. Then, the word line WWL is asserted to turn on the NMOS transistors 214, 218. The timing of the precharge and the assertion of the word line WWL can be controlled by the row decoder 204 (not shown).

[0027]

[0033] If the memory cell 214 stores a logic high, the bit line bl remains charged through the first NMOS access transistor 214 and the complementary bit line blb 224 is discharged through the second NMOS transistor 218. If the memory cell 214 stores a logic low, the bit line bl 222 is discharged through the first NMOS transistor 214 and the complementary bit line blb 224 remains charged through the second NMOS transistor 218.

[0028]

[0034] Figures 3 and 4 together show a memory system for reading data according to one implementation. Figure 3 shows an architecture including a memory cell 214. A complementary bit line blb 224 is coupled to the gate of an NMOS transistor 303. A read word line (RWL) is coupled to the gate of an NMOS transistor 302. A local bit line rbl 301 is coupled to the drain of the NMOS transistor 302. Although not shown in Figure 3, rbl 301 is coupled to an upper bit line (UBL) in Figure 4 in a local data path (LDP) for single-ended sensing in a NAND gate 401.

[0029]

[0035] The upper bit line UBL and the lower bit line LBL are precharged through transistors 402 and 403, respectively. For example, when signals upre_n and lpre_n are low, PMOS transistors 402, 403 turn on, thereby charging the upper and lower bit lines to logic 1 in power domain MX. The local data paths in FIG. 4 show various local data paths contained within each memory bank of a multi-bank memory system. It will be understood that other local data paths in other memory banks have similar architectures and operate similarly to those described in FIG. 4.

[0030]

[0036] The output of the NAND gate 401 is provided to a global bit line 410. In other words, the local bit line rbl 301 of FIG. 3 is coupled to the global bit line 410 of FIG. 4 through the NAND gate 401, and the digital value on the global bit line 410 is at least partially determined by the digital value on the local bit line rbl 301. The global bit line 410 can be forced to a logic level 0 by asserting a reset signal at the gate of the NMOS transistor 404. The global bit line 410 includes two inverters 405, 406 coupled in series in this embodiment. The signal after the first inverter 405 is referred to as grbl_1, and the signal after the second inverter 406 is referred to as grbl_2.

[0031]

[0037] Signal grbl_2 is a first bit line signal, which in this embodiment is complemented and complemented by virtual bit line signal q. In this embodiment, the virtual bit line signal is used like a bit line signal in the RS latch, but is not a bit line signal itself, since it is derived from grbl_2 and delayed_pre after single-ended sensing. The virtual bit line signal is generated by logic gate 411, which in this embodiment is a NOR gate. NOR gate 411 receives grbl_2 as well as signal delayed_pre as inputs. Signal delayed_pre is a control signal, which is shown in more detail in FIG. 5 and can be generated by any suitable circuit. In this embodiment, delayed_pre is a periodic control signal (i.e., a signal that repeats according to a period) with a duty cycle configured to generate a virtual bit line signal q complementary to grbl_2 during a read operation.

[0032]

[0038] The NOR gates 412, 413 are cross-coupled and together form an RS latch for temporarily storing the bit resulting from the single-ended sensing provided by the NAND gate 401. The NOR gates 412, 413 are described in more detail with respect to FIG. 6. Briefly, the NOR gate 412 receives as input the virtual bit line signal q and the output sro of the NOR gate 413. The NOR gate 413 receives as input grbl_2 (also called qb) and the output sro_n of the NOR gate 412. The output sro of the NOR gate 413 is input to serially connected inverters 414, 416, which generate a data output signal dout. The data output signal dout can then be transmitted to another component, such as a processor, by a bus and one or more signal drivers (not shown). Various implementations can use other logic gates to build the RS latch. For example, some RS latches can be made with cross-coupled NAND gates, such as by replacing NOR gates 412, 413 with NAND gates. However, cross-coupled NAND gate RS latches may not support level shifting from VDDMX to VDDCX, which is discussed below as an advantage of the RS latch shown in FIG.

[0033]

[0039] Next, an example of reading logic 0 and logic 1 will be discussed with respect to FIG. 5, which shows a timing diagram according to the implementation of FIGS. 2-4. Prior to a read-read operation of logic 0, the local bit line rbl, as well as the upper bit line (ubl) and the lower bit line (lbl) are precharged to 1. At time T0, the read word line (RWL) goes high, pulling rbl to 0 and pulling ubl from 1 to 0, which causes the output of NAND gate 401 to be logic 1. This causes grbl_2 (qb) to become a logic 1 value at time t1. This logic 1 value is input to NOR gate 413, which outputs a logic 0 on sro. The logic 1 on grbl_2 also disables NOR gate 411 for the generation of the virtual bit line, forcing NOR gate 411 to output a logic 0 on node q at time t2. Note that delayed_pre toggles during the period T2-T3, which is entirely within the window defined by T1-T4, so that the value of delayed_pre is not propagated to dout.

[0034]

[0040] The output sro_n of NOR gate 412 in the latch is already at logic 1. At this point, ubl is precharged back to logic 1 from time T3 to T4, which causes the output of NAND gate 401 to become logic 0, causing grbl_2(qb) to be returned to logic 0 at time T4. At this point, both NOR gates 412, 413 have inputs of 0, thereby retaining the value in the latch.

[0035]

[0041] Read logic 1 - Again, the bitlines are precharged. The read wordline (RWL) goes high at time T5, and both ubl and lbl remain high. At this point, grbl_2(qb) is 0. The signal delayed_pre goes to 0 at time T6, causing NOR gate 411 to receive both logic 0s as inputs, which pulls node q from 0 to 1 at time T7. A logic 1 at the output of NOR gate 411 is similar to a virtual bitline value of logic 1. At this point, the output sro_n of NOR gate 412 is a logic 0, and the output sro of NOR gate 413 is a logic 1. The signal delayed_pre returns to logic 1 at time T8, which returns node q to logic 0 at time T9, at which point both q and qb are logic 0, causing the latch to hold its value.

[0036]

[0042] 6 is a transistor-level view of NOR gates 412, 413, according to an example implementation. Focusing first on NOR gate 413, NOR gate 413 outputs a signal sro. NOR gate 413 includes two PMOS transistors 601, 602 and two NMOS transistors 603, 604. A signal grbl_2 at node qb is applied to the gates of transistors 602 and 603. A cross-coupled output from transistor 412 is applied to the gates of transistors 601, 604.

[0037]

[0043] Table 1 is the truth table for NOR gate 413:

[0038] [Table 1]

[0039]

[0044] NOR gate 412 is similarly constructed. NOR gate 412 has two PMOS transistors 611 and 612 and two NMOS transistors 613, 614. The virtual bit line signal at node q is applied to the gates of transistors 612, 613, and the cross-coupled output of transistor 413 is applied to the gates of transistors 611, 614. Table 2 is the truth table for NOR gate 412:

[0040] [Table 2]

[0041]

[0045] An advantageous result of using NOR gates 412, 413 as RS latches is that they can provide voltage level shifting without modification. For example, in this embodiment, there are two power domains, namely CX and MX, as shown in FIG. 4. Furthermore, in this embodiment, MX is at a lower voltage level than CX, but the scope of implementations may include vice versa. The inputs at nodes q and qb are associated with power domain MX, while the outputs sro and sro_n are associated with power domain CX. Furthermore, the PMOS stacks (i.e., transistors 601, 602, and 611, 612) in FIG. 6 ensure that the outputs sro, sro_n are isolated from VDD when the inputs to those PMOS transistors are high, which is true even if the power domains have different voltage levels. For example, the outputs sro, sro_n in this example may have higher voltage levels than seen at nodes q, qb, and these higher voltage levels are applied to the transistors 601, 611 that are physically closest to VDD, which have gate-source voltages that bring them into an off state and reduce the amount of leakage current that might otherwise occur. As mentioned above, other implementations can build an RS latch from transistors in other combinations or configurations (e.g., arranging the transistors as cross-coupled NAND gates instead). However, such other transistor configurations may not support the voltage level shifting of the implementation of FIG. 6.

[0042]

[0046] Some implementations include a method, such as method 700 of Figure 7. Method 700 is an example method for operating a memory system such as those described in Figures 1-6. Although the example actions are described with respect to read circuitry, it will be understood that the read circuitry may be under the control, directly or indirectly, of other logic, such as a memory controller.

[0043]

[0047] At action 710, the system stores a digital bit in a bit cell. An exemplary bit cell is shown in FIG. 2. The digital bit is stored using cross-coupled inverters, but the range of implementations may include any suitable bit cell. The example of FIG. 2 shows a pair of bit lines, one bit line and one complementary bit line. Readout is controlled by a read word line, such as RWL in FIG. 3.

[0044]

[0048] In action 720, the first bit line is forced to assume a state according to the digital bit. In the example of Figures 2 and 3, a logic 0 stored in bit cell 214 results in a logic 1 on the complementary bit line (e.g., rbl). Similarly, a logic 1 stored in bit cell 214 results in a logic 0 on the complementary bit line.

[0045]

[0049] In action 730, the state of the bit line (e.g., rbl) is sensed. In the embodiment of FIG. 3, FIG. 4, NAND gate 401 receives precharge voltage lbl, and ubl assumes a voltage value associated with the voltage value of rbl. The output of NAND gate 401 causes a second bit line (e.g., bit line 410) to assume a single-ended digital value (grbl_2) based at least in part on the digital bit. If a logic 0 is stored in the bit cell, it causes the second bit line to assume a logic 1 value, and vice versa. In this embodiment, the second bit line (e.g., bit line 410) is coupled to the first bit line (e.g., rbl) via NAND gate 401.

[0046]

[0050] At action 740, the method includes generating a virtual bitline value. In the example of Figure 4, the virtual bitline is output at node q as an input to NOR gate 412. The virtual bitline value may be generated by a logic gate, such as NOR gate 411, that receives a single-ended digital value and a periodic control signal. In the example of Figure 5, the periodic control signal is shown as delayed_pre. The virtual bitline value in this example allows the single-ended digital value to be stored in a multi-input latch, such as an RS latch.

[0047]

[0051] In action 750, the single-ended digital value is received at an RS latch. The RS latch also receives the virtual bitline value. In the embodiment of FIG. 4, the RS latch includes cross-coupled NOR gates 412, 413. The output from NOR gate 413 is used as the latch output, although a range of implementations may include using the output from NOR gate 412. The RS latch has four inputs. Two of the inputs are the cross-coupled outputs, and the other two inputs are the single-ended digital value (grbl_2) and the virtual bitline value.

[0048]

[0052] The digital bit is stored in the RS latch in action 760. Action 760 may include placing the RS latch in a stable state by forcing the single-ended digital values ​​in the virtual bitline values ​​to both be zero.

[0049]

[0053] Action 760 may further include level shifting from one power domain to another. For example, the latch itself may operate in a different power domain (CX) than the power domain (MX) of the sensing stage. As explained above with respect to Figure 6, cross-coupled NOR gates allow for voltage level shifting, and the architecture of Figure 4 utilizes the level shifting property to interface between the two power domains.

[0050]

[0054] The scope of implementations is not limited to the specific actions illustrated in FIG. 7. Rather, other implementations may add, omit, reorder, or modify one or more actions. In one embodiment, actions 710-760 may be repeated an appropriate number of times to read data from a bank of memory cells. Moreover, while actions 710-760 are described with respect to a single memory bank, it will be understood that the scope of implementations may include multiple read circuits that include the same or similar actions to read data from other memory banks.

[0051]

[0055] Various implementations described herein may be suitable for use in a system on a chip (SoC). One example of an SoC is a semiconductor chip having multiple processing devices therein, including a graphics processing unit (GPU), a central processing unit (CPU), a modem unit, a camera unit, etc. In some embodiments, the SoC may be included in a chip package, may be implemented on a printed circuit board, and may be disposed in a portable device such as a smartphone or tablet computer. However, the scope of implementations is not limited to a chip implemented in a tablet computer or smartphone, as other applications are possible.

[0052]

[0056] FIG. 8 is a diagram of an exemplary SoC 800 according to one implementation. In this example, the SoC 800 is implemented on a semiconductor die and includes multiple system components 810-890. Specifically, in this example, the SoC 800 includes a CPU 810, which is a multi-core general-purpose processor having four processor cores, core 0-core 3. Of course, the scope of the implementation is not limited to any particular number of cores, as other implementations may include two cores, eight cores, or any other suitable number of cores in the CPU 810. The SoC 800 further includes other system components, such as a first digital signal processor (DSP) 840, a second DSP 850, a modem 830, a GPU 820, a video subsystem 860, a wireless local area network (WLAN) transceiver 870, and a video front-end (VFE) subsystem 880. SoC 800 also includes a RAM memory unit 890, which can act as system RAM for any of components 810-880.

[0053]

[0057] The RAM memory unit 890 may include read circuitry, such as that described above with respect to Figures 2-6. The RAM memory unit 890 may receive data and instructions from any of the components 810-880 in the same or similar manner as described above with respect to Figure 1. Additionally, the RAM memory unit 890 may read data from memory cells in one or more memory banks by performing the actions of Figure 7.

[0054]

[0058] Further, in this embodiment, GPU 820 includes memory 821. Memory 821 may be implemented as a local memory for GPU 820. In one implementation, memory 821 may be a single-bank memory or a multi-bank memory having the architecture described above with respect to Figures 2-6 and performing the actions described above with respect to Figure 7. Memory 821 may be implemented as an alternative to or in addition to RAM 190.

[0055]

[0059] As will be appreciated by those skilled in the art at present, and depending on the specific application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, arrangements, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, and as the specific embodiments illustrated and described herein are merely by way of example of some of the same, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the following appended claims and their functional equivalents.

[0056]

[0060] Example implementations are described in the following numbered clauses.

[0061] 1. A memory, comprising: a first bit line coupled to the bit cell; a second bit line coupled to the first bit line; a first logic gate coupled to the second bit line; a reset-set (RS) latch having a first input and a second input, the first input coupled to a second bit line and the second input coupled to the second bit line via a first logic gate.

[0062] 2. The memory of claim 1, wherein the first logic gate comprises a NOR gate.

[0063] 3. The memory of claim 2, wherein the first logic gate is further coupled to a periodic control signal.

[0064] 4. The memory of clauses 1-3, wherein the second bit line is implemented as an upper and lower bit line pair and is coupled to the first input via a NAND gate.

[0065] 5. The memory of clauses 1-4, wherein the RS latch includes a second logic gate and a third logic gate, the second logic gate including a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain, and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain.

[0066] 6. The memory of clause 5, wherein the third logic gate includes a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to a first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain.

[0067] 7. The memory of clause 5, wherein the first power domain has a lower voltage level than the second power domain.

[0068] 8. The memory of any one of clauses 1-7, wherein the first bit line comprises a local bit line and the second bit line comprises a global bit line.

[0069] 9. The memory of any one of clauses 1-8, wherein the second bit line is associated with a first power domain and the RS latch is associated with a second power domain.

[0070] 10. A method of reading data from a bit cell, comprising: forcing a first bit line to assume a state according to a digital bit stored in the bit cell; sensing a state including causing a second bit line coupled to the first bit line to assume a single-ended digital value based at least in part on the digital bit; generating a virtual bitline value; receiving a single-ended digital value and a virtual bit line value in a reset-set (RS) latch; storing the digital bit in an RS latch.

[0071] 11. Generating a virtual bit line value comprises: receiving a single-ended digital value at a logic gate; receiving a periodic control signal at a logic gate; and outputting the virtual bit line value from the logic gate.

[0072] 12. The method of claim 11, wherein the logic gate includes a NOR gate coupled to an input of an RS latch, the RS latch receiving a single-ended digital value as an additional input.

[0073] 13. Sensing the state coupling the first bit line to a precharged third bit line, the precharged third bit line being coupled to an input of the logic gate and the precharged fourth bit line being coupled to an additional input of the logic gate; and outputting a single-ended digital value from the logic gate.

[0074] 14. The method of claim 13, wherein the logic gate comprises a NAND gate.

[0075] 15. The method of any one of clauses 10 to 14, wherein the virtual bit line value and the single-ended digital value correspond to a first power domain and the output of the RS latch corresponds to a second power domain, and further wherein the second power domain has a lower voltage level than the first power domain.

[0076] 16. performing a voltage level shift in the RS latch between a first power domain and a second power domain, where the virtual bit line value and the single-ended digital value correspond to the first power domain and the output of the RS latch corresponds to the second power domain; The method according to clauses 10 to 15.

[0077] 17. and driving a digital bit from the output of the RS latch onto a data bus. The method according to clauses 10 to 16.

[0078] 18. A memory device comprising: means for storing bits of data; means for sensing a state of a bit line coupled to the means for storing a bit of data; means for generating a virtual bit line value from an output of the means for sensing; a reset-set (RS) latch having a first input coupled to the means for sensing and a second input coupled to the means for generating a virtual bit line value.

[0079] 19. The memory device of clause 18, wherein the means for generating the virtual bit line value comprises a NOR gate.

[0080] 20. The memory device of clause 19, wherein the NOR gate is further coupled to a periodic control signal.

[0081] 21. The memory device of clauses 18-20, wherein the means for sensing includes a pair of upper and lower bit lines coupled to the RS latch via a NAND gate.

[0082] 2. The memory device of any one of clauses 18-21, wherein the RS latch includes a first logic gate and a second logic gate, the first logic gate including a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain, and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain.

[0083] 23. The memory device of clause 22, wherein the second logic gate includes a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to a first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain.

[0084] 24. The memory device of clause 22, wherein the first power domain has a lower voltage level than the second power domain.

[0085] 25. A system comprising: a memory device coupled to the processor and configured to perform read and write operations in response to the processor; a plurality of bit cells arranged in rows and columns in the memory device; a read circuit coupled to a first one of the bit cells, a bit line pair coupled to the first logic gate and to a first one of the bit cells; a reset-set (RS) latch having a first input coupled to the output of the first logic gate; and a read circuit including a second logic gate coupled to a second input of the RS latch, the second logic gate further coupled to the output of the first logic gate and to a control signal.

[0086] 26. The system of clause 25, wherein the processor includes a graphics processing unit (GPU) and the memory device is included within the GPU.

[0087] 27. The system of clauses 25 and 26, wherein the bit line pair includes a precharged upper bit line and a lower bit line, and either the upper bit line or the lower bit line is coupled to the bit line bar of a first one of the bit cells.

[0088] 28. The system of any one of clauses 25-27, wherein the second logic gate comprises a NOR gate and the control signal comprises a periodic control signal.

[0089] 29. An RS latch including a third logic gate and a fourth logic gate, the third logic gate including a first p-type metal oxide semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain, and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain; The system of any one of clauses 25-28, wherein the fourth logic gate includes a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to the first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain.

[0090] 30. The system of clause 29, wherein the first power domain has a lower voltage level than the second power domain. The invention as described in the claims of the present application as originally filed is set forth below. [C1] A memory, a first bit line coupled to the bit cell; a second bit line coupled to the first bit line; a first logic gate coupled to the second bit line; a reset-set (RS) latch having a first input and a second input, the first input coupled to the second bit line and the second input coupled to the second bit line via the first logic gate; [C2] The memory of C1, wherein the first logic gate comprises a NOR gate. [C3] The memory of C2, wherein the first logic gate is further coupled to a periodic control signal. [C4] The memory of C1, wherein the second bit line is implemented as an upper and lower bit line pair and is coupled to the first input through a NAND gate. [C5] 2. The memory of claim 1, wherein the RS latch includes a second logic gate and a third logic gate, the second logic gate including a first p-type metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain. [C6] 8. The memory of claim 7, wherein the third logic gate comprises a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to the first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain. [C7] The memory of C5, wherein the first power domain has a lower voltage level than the second power domain. [C8] The memory of C1, wherein the first bit lines comprise local bit lines and the second bit lines comprise global bit lines. [C9] The memory of C1, wherein the second bit line is associated with a first power domain and the RS latch is associated with a second power domain. [C10] 1. A method for reading data from a bit cell, comprising the steps of: forcing a first bit line to assume a state according to a digital bit stored in the bit cell; sensing the state includes causing a second bit line coupled to the first bit line to assume a single-ended digital value based at least in part on the digital bit; generating a virtual bitline value; receiving the single-ended digital value and the virtual bit line value in a reset-set (RS) latch; storing the digital bit in the RS latch. [C11] generating the virtual bit line value, receiving the single-ended digital value at a logic gate; receiving a periodic control signal at the logic gate; and outputting the virtual bit line value from the logic gate. [C12] The method of C11, wherein the logic gate comprises a NOR gate coupled to an input of the RS latch, the RS latch receiving the single-ended digital value as an additional input. [C13] Sensing the condition comprises: coupling the first bit line to a precharged third bit line, the precharged third bit line being coupled to an input of a logic gate and a precharged fourth bit line being coupled to an additional input of the logic gate; and outputting the single-ended digital value from the logic gate. [C14] The method of C13, wherein the logic gate comprises a NAND gate. [C15] The method of C10, wherein the virtual bitline value and the single-ended digital value correspond to a first power domain and the output of the RS latch corresponds to a second power domain, and further wherein the second power domain has a lower voltage level than the first power domain. [C16] performing a voltage level shift in the RS latch between a first power domain and a second power domain, the virtual bit line value and the single-ended digital value corresponding to the first power domain and an output of the RS latch corresponding to the second power domain. The method according to C10. [C17] and driving the digital bit from the output of the RS latch onto a data bus. The method according to C10. [C18] 1. A memory device comprising: means for storing bits of data; means for sensing a state of a bit line coupled to said means for storing said bit of data; means for generating a virtual bit line value from an output of said means for sensing; a reset-set (RS) latch having a first input coupled to the means for sensing and a second input coupled to the means for generating the virtual bit line value. [C19] The memory device of C18, wherein the means for generating the virtual bit line value includes a NOR gate. [C20] The memory device of C19, wherein the NOR gate is further coupled to a periodic control signal. [C21] The memory device of C18, wherein the means for sensing includes a pair of upper and lower bit lines coupled to the RS latch via a NAND gate. [C22] 19. The memory device of claim 18, wherein the RS latch includes a first logic gate and a second logic gate, the first logic gate including a first p-type metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain. [C23] 2. The memory device of claim 1, wherein the second logic gate includes a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to the first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain. [C24] The memory device of C22, wherein the first power domain has a lower voltage level than the second power domain. [C25] 1. A system comprising: a memory device coupled to the processor and configured to perform read and write operations in response to the processor; a plurality of bit cells arranged in rows and columns within the memory device; a read circuit coupled to a first one of the bit cells, a bit line pair coupled to a first logic gate and to the first one of the bit cells; a reset-set (RS) latch having a first input coupled to an output of the first logic gate; a read circuit including a second logic gate coupled to a second input of the RS latch, the second logic gate further coupled to the output of the first logic gate and to a control signal. [C26] The system of C25, wherein the processor includes a graphics processing unit (GPU) and the memory device is contained within the GPU. [C27] The system of C25, wherein the bit line pair includes a precharged upper bit line and a lower bit line, and either the upper bit line or the lower bit line is coupled to a bit line bar of the first one of the bit cells. [C28] The system of C25, wherein the second logic gate comprises a NOR gate and the control signal comprises a periodic control signal. [C29] the RS latch includes a third logic gate and a fourth logic gate, the third logic gate including a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain; 23. The system of claim 25, wherein the fourth logic gate includes a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to the first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain. [C30] The system of C29, wherein the first power domain has a lower voltage level than the second power domain.

Claims

1. A memory, a first bit line coupled to the bit cell; a second bit line coupled to the first bit line; a first logic gate coupled to the second bit line; a reset-set (RS) latch having a first input and a second input, the first input coupled to the second bit line and the second input coupled to the second bit line through the first logic gate; Equipped with The memory, wherein the second bit line is associated with a first power domain and the RS latch is associated with a second power domain.

2. The memory of claim 1 , wherein the first logic gate comprises a NOR gate.

3. The memory of claim 2 , wherein the first logic gate is further coupled to a periodic control signal.

4. 2. The memory of claim 1, wherein the second bit lines are implemented as upper and lower bit line pairs and are coupled to the first input through a NAND gate.

5. 2. The memory of claim 1, wherein the RS latch comprises a second logic gate and a third logic gate, the second logic gate comprising a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor arranged in series, the first PMOS transistor being gate-coupled to a first control voltage associated with a first power domain and the second PMOS transistor being gate-coupled to a second control voltage associated with a second power domain.

6. 6. The memory of claim 5, wherein the third logic gate comprises a third PMOS transistor and a fourth PMOS transistor arranged in series, the third PMOS transistor being gate-coupled to the first control voltage and the fourth PMOS transistor being gate-coupled to a voltage associated with the second power domain.

7. The memory of claim 5 , wherein the first power domain has a lower voltage level than the second power domain.

8. 2. The memory of claim 1, wherein the first bit lines comprise local bit lines and the second bit lines comprise global bit lines.

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