Digital protection relay and abnormality monitoring method thereof

Abstract

To provide a digital protection relay capable of more accurately monitoring characteristic fluctuations of an analog filter.SOLUTION: In a digital protection relay 10, a monitoring signal generation unit 30 generates a monitoring signal Vsup having a frequency different from the fundamental wave frequency f0 of a power system. The monitoring signal Vsup includes a first signal component with a frequency lower than the fundamental wave frequency f0. A first analog filter 23 passes a low frequency region including the fundamental wave frequency f0 to a composite signal Vsum obtained by superimposing the monitoring signal Vsup on an analog electric signal V0 detected from the electric power system. A signal extraction unit 41 extracts the signal component of the fundamental wave frequency f0 and a first signal component from the digitally converted composite signal Vsum. A defect determination unit 43 determines whether the first analog filter 23 is defective using the extracted first signal component.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a digital protective relay and an abnormality monitoring method thereof. [Background technology]

[0002] A commonly used method for monitoring anomalies in the analog input circuit of a digital protection relay is to superimpose a harmonic signal on an electrical signal detected from a power system. The electrical signal on which the harmonic signal is superimposed is input to an analog input circuit, where it is filtered and converted into analog form. The superimposed harmonic signal is then extracted, and a determination is made as to whether there is an anomaly in the analog input circuit, particularly the analog filter, based on the change in amplitude of the extracted harmonic signal.

[0003] The digital protection relay disclosed in JP 2012-065398 A (Patent Document 1) superimposes a plurality of harmonic signals with different frequencies on an electric signal detected from a power system. This digital protection relay identifies circuit elements that have characteristic fluctuations among the circuit elements that configure the analog input circuit, based on the amount of fluctuation in the amplitude value of each superimposed harmonic signal. More specifically, the circuit elements that have characteristic fluctuations are identified based on the positive / negative and frequency dependency of the relative error (see paragraphs

[0048] to

[0062] of Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-065398 A Summary of the Invention [Problem to be solved by the invention]

[0005] The abnormality monitoring method described in the above-mentioned JP 2012-065398 A (Patent Document 1) judges abnormalities based on changes in the attenuation characteristics of a low-pass filter, and therefore cannot quantitatively grasp changes in the characteristics of the passband that includes the most important fundamental frequency.

[0006] The present disclosure has been made in consideration of the above problems, and an object of one aspect is to provide a digital protection relay that can more accurately monitor characteristic fluctuations of an analog filter. [Means for solving the problem]

[0007] A digital protection relay in one aspect includes a monitoring signal generating unit, a first analog filter, an analog-digital converter, a signal extracting unit, a relay calculation unit, and a fault determining unit. The monitoring signal generating unit generates a monitoring signal having a frequency component different from a fundamental frequency of a power system. The monitoring signal includes a first signal component having a frequency lower than the fundamental frequency. The first analog filter passes a low frequency region including the fundamental frequency of a composite signal in which the monitoring signal is superimposed on an analog electrical signal detected from the power system. The analog-digital converter digitally converts the composite signal that has passed through the first analog filter. The signal extracting unit extracts a signal component of the fundamental frequency and a first signal component from the digitally converted composite signal. The relay calculation unit performs relay calculation using the extracted signal component of the fundamental frequency. The fault determining unit uses the extracted first signal component to determine whether the first analog filter is faulty or not. Effect of the Invention

[0008] According to the digital protection relay of the above aspect, the monitoring signal superimposed on the analog electrical signal detected from the power system includes a first signal component having a frequency lower than the fundamental frequency of the power system. Then, by using the extracted first signal component to determine whether the first analog filter is defective, it is possible to more accurately monitor the characteristic fluctuation of the analog filter. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an overall configuration of a digital protection relay according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of a first-order low-pass filter. [Diagram 3] 3 is a diagram showing changes in gain characteristics when the characteristics of the resistor elements R1, R2 and the capacitor C1 in FIG. 2 are changed. [Figure 4] 10A and 10B are diagrams for explaining changes in gain characteristics of a low-pass filter. [Diagram 5] 10 is a flowchart showing a procedure for determining whether an analog filter is defective. [Figure 6] 6 is a flowchart showing a procedure for determining whether the gain characteristic is normal / abnormal in step S110 of FIG. 5. [Figure 7] FIG. 11 is a block diagram showing the overall configuration of a digital protection relay according to a second embodiment. [Figure 8] FIG. 11 is a block diagram showing the overall configuration of a digital protection relay according to a third embodiment. [Figure 9] FIG. 11 is a block diagram showing a configuration of a monitoring signal extraction unit 45 in a digital protection relay according to a fourth embodiment. [Figure 10] 10 is a diagram for explaining the operation of the smoothing filter in FIG. [Figure 11] FIG. 10 is a diagram showing the gain characteristic of the first-stage digital filter in FIG. [Figure 12] FIG. 10 is a diagram illustrating the gain characteristic of the second-stage digital filter in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, each embodiment will be described in detail with reference to the drawings. Note that the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0011] Embodiment 1 [Overall configuration of digital protection relay] Fig. 1 is a block diagram showing an overall configuration of a digital protection relay according to embodiment 1. Referring to Fig. 1, a digital protection relay 10 includes an analog input circuit 20, a monitoring signal generating unit 30, and a digital arithmetic circuit 40.

[0012] The analog input circuit 20 includes a voltage transformer (VT) 21, an adder 22, an analog filter (AF) 23, and an analog-to-digital converter (ADC) 24.

[0013] A voltage signal from a voltage transformer or a current signal from a current transformer provided in the power system is input to the voltage transformer 21. The voltage transformer 21 is an auxiliary transformer for converting the input voltage signal or current signal into a signal with a voltage level suitable for signal processing in the digital protection relay 10. The electrical signal V0 output from the voltage transformer 21 includes a fundamental frequency (e.g., 50 Hz or 60 Hz) component. Hereinafter, the electrical signal V0 is also referred to as a fundamental signal V0.

[0014] The supervisory signal generating unit 30 generates a supervisory signal Vsup to be superimposed on the fundamental wave signal V0. The supervisory signal Vsup includes a plurality of frequency components different from the fundamental wave frequency. As will be described in detail later, the supervisory signal Vsup includes signal components with frequencies lower than the fundamental wave frequency and signal components with frequencies higher than the cutoff frequency fc of the analog filter 23. The amplitude of each signal component of the supervisory signal Vsup is about 1 / 10 of that of the fundamental wave signal V0.

[0015] The monitoring signal generating unit 30 may be configured as an analog oscillator, or may be configured to generate the monitoring signal Vsup by digital-to-analog (DA) conversion of a digital signal, or may be configured to generate the monitoring signal Vsup by utilizing pulse width modulation (PWM).

[0016] The adder 22 generates a composite signal Vsum by superimposing the supervisory signal Vsup on the fundamental signal V0.

[0017] The analog filter 23 is a low-pass filter that passes the low-frequency range including the fundamental frequency f0 of the composite signal Vsum and attenuates the high-frequency range.

[0018] The ADC 24 samples the composite signal Vsum that has passed through the analog filter 23, and converts the sampled composite signal Vsum into a digital value.

[0019] The digital arithmetic circuit 40 may be configured based on a microcomputer including a central processing unit (CPU), a random access memory (RAM), and a read only memory (ROM). Alternatively, the digital arithmetic circuit 40 may be configured with a field programmable gate array (FPGA) or a dedicated circuit such as an application specific integrated circuit (ASIC). Alternatively, the digital arithmetic circuit 40 may be configured with a combination of at least two of the CPU, the FPGA, and the dedicated circuit.

[0020] The digital arithmetic circuit 40 functions as a signal extracting section 41, a relay arithmetic section 42, and a defect determining section 43. These functions are realized, for example, by a CPU operating according to a program.

[0021] The signal extraction unit 41 extracts the signal component V0 of the fundamental signal V0 from the digitally converted composite signal Vsum, and detects the amplitude of the signal component of the supervisory signal Vsup. For example, the signal extraction unit 41 extracts the signal component of the fundamental signal V0 by attenuating the signal component of the supervisory signal Vsup using a filter. The signal extraction unit 41 also detects the amplitude of the signal component of the supervisory signal Vsup from the result of performing a digital Fourier transform on the composite signal Vsum. Alternatively, the signal extraction unit 41 may detect the amplitude of the signal component of the supervisory signal Vsup by extracting the signal component of the supervisory signal Vsup from the composite signal Vsum using a digital filter.

[0022] The relay calculation unit 42 performs relay calculation on the extracted signal component of the fundamental wave signal V0 to determine whether or not a fault has occurred in the power system.

[0023] The defect determination unit 43 determines whether or not the analog filter 23 is defective based on the amplitude of the detected signal component of the monitoring signal Vsup. The procedure for defect determination by the defect determination unit 43 will be described in detail later.

[0024] [Changes in gain characteristics of a first-order low-pass filter] Below, we will explain the change in gain characteristics when the characteristics of the circuit elements change, using a first-order low-pass filter as an example.

[0025] Fig. 2 is a circuit diagram showing a configuration of a first-order low-pass filter. Referring to Fig. 2, the first-order low-pass filter includes an operational amplifier OA, resistor elements R1 and R2, and a capacitor C1.

[0026] As shown in Fig. 2, the resistor R2 is connected between the input terminal N1 of the low-pass filter and the inverting input terminal N3 of the operational amplifier OA. The resistor R2 and the capacitor C1 are connected in parallel with each other between the inverting input terminal N3 of the operational amplifier OA and the output terminal N4 of the operational amplifier OA. The non-inverting input terminal N5 of the operational amplifier OA is connected to the ground GND. The output terminal N4 of the operational amplifier OA is connected to the output terminal N2 of the low-pass filter.

[0027] The resistance values ​​of the resistor elements R1 and R2 are R 1 ,R 2 Let the capacitance of the capacitor C1 be C 1 The input voltage of input terminal N1 is V in The output voltage of the output terminal N2 is V out The output voltage V out and the input voltage V in The ratio to is expressed by the following equation (1): In the following equation (1), the imaginary unit is j and the angular frequency is ω.

[0028]

number

[0029] Fig. 3 is a diagram showing changes in gain characteristics when the characteristics of the resistor elements R1, R2 and capacitor C1 in Fig. 2 change. Fig. 3(A) shows a case where the resistance value of resistor element R1 changes, Fig. 3(B) shows a case where the capacitance value of capacitor C1 changes, and Fig. 3(C) shows a case where the resistance value of resistor element R2 changes.

[0030] With reference to Figure 3(A), the solid line shows the gain characteristics when the resistance value of resistor element R1 is at its initial value. In this case, the gain at the fundamental frequency (50 Hz) is normalized to 1. The dashed line shows the gain characteristics when the resistance value of resistor element R1 increases by 20% from its initial value. The dashed line shows the gain characteristics when the resistance value of resistor element R1 decreases by 20% from its initial value. The resistance value of resistor element R2 and the capacitance value of capacitor C1 remain at their initial values.

[0031] As shown in Figure 3(A), in the low frequency region below the fundamental frequency (50 Hz), the gain increases as the resistance value of resistor element R1 increases. On the other hand, in the high frequency region, the gain hardly changes regardless of the change in the resistance value of resistor element R1. The cutoff frequency decreases as the resistance value of resistor element R1 increases.

[0032] With reference to Figure 3(B), the solid line shows the gain characteristics when the capacitance value of capacitor C1 is at its initial value. In this case, the gain at the fundamental frequency (50 Hz) is normalized to 1. The dashed line shows the gain characteristics when the capacitance value of capacitor C1 increases by 20% from its initial value. The dashed line shows the gain characteristics when the capacitance value of capacitor C1 decreases by 20% from its initial value. The resistance values ​​of resistor elements R1 and R2 remain at their initial values.

[0033] As shown in Figure 3(B), in the frequency range lower than the fundamental frequency (50 Hz), the gain hardly changes regardless of the change in the capacitance value of capacitor C1. On the other hand, in the high frequency range, the gain decreases as the capacitance value of capacitor C1 increases. The cutoff frequency decreases as the capacitance value of capacitor C1 increases.

[0034] With reference to Figure 3(C), the solid line shows the gain characteristics when the resistance value of resistor element R2 is at its initial value. In this case, the gain at the fundamental frequency (50 Hz) is normalized to 1. The dashed line shows the gain characteristics when the resistance value of resistor element R2 increases by 20% from its initial value. The dashed line shows the gain characteristics when the resistance value of resistor element R2 decreases by 20% from its initial value. The resistance value of resistor element R1 and the capacitance value of capacitor C1 remain at their initial values.

[0035] 3C, the gain decreases as the resistance value of the resistor R2 increases over the entire frequency range, and the cutoff frequency does not change regardless of the change in the resistance value of the resistor R2.

[0036] As described above, by focusing on the gain change in the low frequency region lower than the fundamental frequency and the gain change in the high frequency region higher than the cutoff frequency (for example, about 5 to 10 times the cutoff frequency), it is possible to distinguish and monitor the characteristic changes of the individual elements constituting the low-pass filter. Furthermore, by focusing on the gain change in the low frequency region lower than the fundamental frequency, it is possible to quantitatively grasp whether or not there is a change in the gain characteristics of the passband near the fundamental frequency. This will be further explained using mathematical expressions below.

[0037] Fig. 4 is a diagram for explaining changes in the gain characteristics of a low-pass filter. In Fig. 4, the gain characteristics of a first-order low-pass filter are conceptually shown. The gain near the fundamental frequency f0 of the power system and at a frequency f1 lower than the fundamental frequency f0 is defined as k1. The gain at a frequency f2 higher than the cutoff frequency fc (for example, about 5 to 10 times the cutoff frequency fc) is defined as k2.

[0038] In the above-mentioned equation (1), since it can be approximated that ω=0 at the low frequency f1, the gain k1 is expressed by the following equation (2).

[0039]

number

[0040] On the other hand, in the above equation (1), at high frequency f2, 1≪|jωC 1 R 1 Therefore, equation (1) can be approximated as equation (3A) below. Therefore, the gain k2 is expressed by equation (3B) below.

[0041]

number

[0042] From the above equations (2) and (3B), the time constant C 1 R 1 is expressed by the following equation (4A): Also, the cutoff frequency fc is expressed by the following equation (4B):

[0043]

number

[0044] According to the above equations (2), (3B), and (4B), as the resistance value of the resistor element R1 increases, the gain k1 at low frequency f1 increases, but the gain k2 at high frequency f2 does not change, and the cutoff frequency fc decreases. As the resistance value of the resistor element R2 increases, both the gain k1 at low frequency f1 and the gain k2 at high frequency f2 decrease, but the cutoff frequency fc does not change. As the capacitance value of the capacitor C1 increases, the gain k1 at low frequency f1 does not change, but the gain k2 at high frequency f2 decreases, and the cutoff frequency fc decreases.

[0045] Furthermore, according to the above formula (3B), the gain k2 in the attenuation region can be corrected so as to remove the influence of the change in the gain k1 in the pass region of the analog filter 23. For example, if the gain k1 in the pass region changes to α times its initial value, the gain k2 in the attenuation region can be reduced by dividing it by α to remove the influence of the change in the gain k1 in the attenuation region.

[0046] In the actual analog filter 23, a higher order low-pass filter may be used, or low-pass filters of multiple orders may be used in combination, so the above results are not necessarily applicable. However, by using a monitoring signal Vsup with a frequency lower than the fundamental frequency f0, it is possible to quantitatively determine whether or not there is a change in the gain characteristics of the passband near the fundamental frequency. Furthermore, by also using a monitoring signal Vsup with a frequency higher than the cutoff frequency fc (for example, about 5 to 10 times the cutoff frequency fc), it is possible to more accurately determine the gain fluctuation of the analog filter 23.

[0047] [Procedure for determining whether an analog filter is defective] The procedure for determining whether or not the analog filter 23 of the digital protection relay 10 is defective will now be described, summarizing the above explanation.

[0048] Fig. 5 is a flow chart showing a procedure for determining whether an analog filter is defective. In Fig. 5, when an abnormality in the gain characteristic of the analog filter 23 is detected a set number of times in succession, the analog filter 23 is determined to be defective. This makes it possible to prevent erroneous determinations caused by noise.

[0049] In step S100 in FIG. 5, the defect determination unit 43 in FIG. 1 initializes to 0 the count value of a counter for counting the number of times an abnormality is detected.

[0050] In the next step S110, the defect determination unit 43 determines whether the gain characteristics of the analog filter 23 are normal or abnormal, using the monitoring signal Vsup extracted from the composite signal Vsum by the signal extraction unit 41. The detailed procedure of step S110 will be described with reference to FIG.

[0051] When the defect determination unit 43 determines that the gain characteristic is normal (YES in step S120), the process proceeds to step S130. In step S130, the defect determination unit 43 resets the count value of the counter to 0, and returns the process to step S110.

[0052] On the other hand, if the defect determination unit 43 determines that the gain characteristic is abnormal (NO in step S120), the process proceeds to step S140. In step S140, the defect determination unit 43 increments the count value of the counter by +1.

[0053] Then, in the next step S150, the defect determination unit 43 determines whether the count value has reached the set value, and if the count value is less than the set value (YES in step S150), the process returns to step S110. If the count value has reached the set value (NO in step S150), the defect determination unit 43 determines in the next step S160 that the analog filter 23 is defective, and ends the process.

[0054] FIG. 6 is a flowchart showing the procedure for determining whether the gain characteristic is normal / abnormal in step S110 of FIG.

[0055] In step S200 of FIG. 6, the signal extracting unit 41 extracts the signal component of the supervisory signal Vsup of the low frequency f1 from the digitally converted composite signal Vsum.

[0056] In the next step S210, the defect determination unit 43 determines whether or not the gain fluctuation amount at the low frequency f1 is within a specified range based on the amplitude change of the extracted signal component of the low frequency f1. If the gain fluctuation amount at the low frequency f1 is not within the specified range (NO in step S210), the defect determination unit 43 determines that the gain characteristic of the analog filter 23 is abnormal (step S260).

[0057] On the other hand, if the amount of gain fluctuation at the low frequency f1 is within the specified range (YES in step S210), the defect determination unit 43 proceeds to step S220. In step S220, the signal extraction unit 41 extracts the signal component of the supervisory signal Vsup at the high frequency f2 from the digitally converted composite signal Vsum.

[0058] In the next step S230, the defect determination unit 43 corrects the gain fluctuation amount at the high frequency f2 based on the amplitude change of the extracted signal component at the high frequency f2, using the gain fluctuation amount at the low frequency f1, thereby making it possible to remove the influence of the gain fluctuation amount at the low frequency f1 included in the gain fluctuation amount at the high frequency f2.

[0059] In the next step S240, the defect determination unit 43 determines whether the amount of gain variation after correction at the high frequency f2 is within a specified range. If the amount of gain variation after correction at the high frequency f2 is not within the specified range (NO in step S240), the defect determination unit 43 determines that the gain characteristics of the analog filter 23 are abnormal (step S260).

[0060] On the other hand, if the amount of gain variation after correction at high frequency f2 is within the specified range (YES in step S240), the defect determination unit 43 determines that the gain characteristics of the analog filter 23 are normal (step S250). This completes step S110 of determining whether the gain characteristics of the analog filter 23 are normal or abnormal.

[0061] [Advantages of the first embodiment] As described above, according to the digital protection relay 10 of the first embodiment, the monitoring signal Vsup superimposed on the fundamental signal V0 detected from the power system includes a signal component (frequency f1) having a lower frequency than the fundamental frequency f0 and a signal component (frequency f2) having a higher frequency than the cutoff frequency fc of the analog filter 23. By focusing on the amplitude change of the signal component of the low frequency f1, the change in the gain characteristic of the analog filter 23 at the fundamental frequency f0 can be quantitatively grasped. Furthermore, by also using the amplitude change of the signal component of the high frequency f2 (i.e., the characteristic change in the attenuation region of the analog filter 23), the change in the gain characteristic of the analog filter 23 can be more accurately grasped.

[0062] Embodiment 2 In the digital protection relay 10 of the first embodiment, since the monitoring signal Vsup contains a signal component of a frequency f1 lower than the fundamental frequency f0, it is not easy to extract the fundamental signal V0 from the composite signal Vsum by a digital filter. Therefore, the signal extraction unit 41A of the digital protection relay 10A of the second embodiment performs a process of directly subtracting the superimposed monitoring signal Vsup from the composite signal Vsum. This makes it possible to extract the fundamental signal V0 from the composite signal Vsum with high accuracy. This will be described in detail below with reference to the drawings.

[0063] [Digital protection relay configuration] Fig. 7 is a block diagram showing an overall configuration of a digital protection relay according to embodiment 2. Referring to Fig. 7, a digital protection relay 10A according to embodiment 2 includes an analog input circuit 20A, a digital arithmetic circuit 40A, and a monitoring signal generating unit 30.

[0064] The analog input circuit 20A in Fig. 7 differs from the analog input circuit 20 in Fig. 1 in that it includes an analog filter 25 and an ADC 26 dedicated to the monitoring signal Vsup. The analog filter 25 is a low-pass filter with the same specifications as the analog filter 23. Note that, by using a multiplexer without providing the ADC 26, the ADC 24 may perform digital conversion of both the composite signal Vsum and the monitoring signal Vsup. The monitoring signal Vsupd that has passed through the analog filter 25 and been digitally converted by the ADC 26 is input to a signal extraction unit 41A of the digital arithmetic circuit 40A.

[0065] Next, a description will be given of the digital arithmetic circuit 40A in Fig. 7. As shown in Fig. 7, the signal extracting section 41A includes a subtractor 44 and a monitoring signal extracting section 45.

[0066] The subtractor 44 extracts the fundamental signal V0 by subtracting the monitoring signal Vsupd, which has passed through the analog filter 25 and then been digitally converted by the ADC 26, from the composite signal Vsum. That is, the subtractor 44 performs the calculation expressed by the following equation (5). In the following equation (5), n represents the sampling count, and dt represents the sampling interval.

[0067]

number

[0068] Based on the digitally converted composite signal Vsum, the monitoring signal extraction unit 45 detects the amplitude of the signal component of the monitoring signal Vsup after passing through the analog filter 23. For example, the monitoring signal extraction unit 45 may detect the amplitude of the signal component of the monitoring signal Vsup from the result of performing a digital Fourier transform on the composite signal Vsum. Alternatively, the monitoring signal extraction unit 45 may detect the amplitude of the signal component of the monitoring signal Vsup by extracting the signal component of the monitoring signal Vsup from the composite signal Vsum using a digital filter.

[0069] Other configurations in FIG. 7 are similar to those in FIG. 1, so the same or corresponding parts are given the same reference characters and descriptions thereof will not be repeated.

[0070] [Effects of the second embodiment] According to the configuration of the digital protection relay 10A shown in Fig. 7, the fundamental signal V0 is extracted by directly subtracting the superimposed monitoring signal Vsup from the composite signal Vsum, so that the fundamental signal V0 can be extracted more accurately than when a digital filter is used. Since it is necessary to provide an analog filter 23 dedicated to the monitoring signal Vsup in the analog input circuit 20, more hardware resources are used than in the first embodiment, but the design difficulty is low and it can be realized relatively easily.

[0071] Embodiment 3 In the third embodiment, the characteristics of the analog filter 23 are simulated by digital processing to generate a digitally converted supervisory signal Vsupd. This eliminates the need to provide an analog filter 23 dedicated to the supervisory signal Vsup. This will be described in detail below with reference to the drawings.

[0072] [Digital protection relay configuration] Fig. 8 is a block diagram showing the overall configuration of a digital protection relay according to embodiment 3. Referring to Fig. 8, a digital protection relay 10B according to embodiment 3 includes an analog input circuit 20 having the same configuration as in Fig. 1, a digital arithmetic circuit 40A having the same configuration as in Fig. 7, and a monitoring signal generating unit 30A.

[0073] The monitoring signal generating unit 30A in Fig. 8 includes a digital-to-analog converter (DAC) 32 and a digital processing circuit 33. The DAC 32 generates a monitoring signal Vsup by performing digital-to-analog conversion of the monitoring signal data 31. The digital processing circuit 33 generates a digital monitoring signal Vsupd by performing digital processing on the monitoring signal data 31 that simulates the analog filter 23. This makes it possible to generate a signal equivalent to the monitoring signal Vsupd in Fig. 7 that has passed through the analog filter 25 and then been digitally converted by the ADC 26.

[0074] [Effects of the third embodiment] According to the digital protection relay 10B of the third embodiment, the same processing as in the second embodiment can be realized without increasing hardware resources such as the analog filter 25 and the ADC 26.

[0075] Embodiment 4 In the fourth embodiment, the frequency of each signal component of the supervisory signal Vsup is limited to a frequency that is an even fraction of the fundamental frequency f0 and a frequency that is an even multiple of the fundamental frequency f0. This simplifies the configuration of the digital filter that constitutes the supervisory signal extraction unit 45 shown in Figures 7 and 8. This will be described in detail below with reference to the drawings.

[0076] [Monitoring signal frequency setting] The frequency f1 of the low-frequency signal component of the supervisory signal Vsup is set to 1 / 2m (m is an integer equal to or greater than 1) of the fundamental frequency f0 (for example, 50 Hz or 60 Hz), that is, f0 / (2m).

[0077] Furthermore, the frequency f2 of the high-frequency signal component of the supervisory signal Vsup is set to 2n times the fundamental frequency f0 (n is an integer equal to or greater than 1), that is, f0×2n. However, n is selected so that f0×2n is a higher frequency than the cutoff frequency fc of the analog filter 23 (for example, about 5 to 10 times the cutoff frequency fc).

[0078] The amplitude of each signal component of the supervisory signal Vsup is about 1 / 10 of the amplitude of the fundamental signal V0.

[0079] [Configuration and operation of monitoring signal extraction unit] Fig. 9 is a block diagram showing a configuration of a monitoring signal extracting unit 45 in the digital protection relay of the embodiment 4. Referring to Fig. 9, the monitoring signal extracting unit 45 includes a smoothing filter 46 and two stages of digital filters 47 and 48.

[0080] The smoothing filter 46 extracts low-frequency signal components with a fundamental frequency f0 divided by 2m from the composite signal Vsum. The smoothing filter 46 is a moving average filter with a window length of m / f0 (i.e., a half period of the low-frequency signal components). This makes it possible to remove the signal components with the fundamental frequency f0 and the even harmonic signal components from the composite signal Vsum.

[0081] Figure 10 is a diagram for explaining the operation of the smoothing filter in Figure 9. Figure 10 shows signal waveforms having frequencies f0, f0 / 2, 2·f0, 4·f0, and 6·f0, where the fundamental frequency f0 is 50 Hz. It can be seen that by performing moving average processing with a window length of half the wavelength of the frequency f0 / 2 (i.e., 0.02 seconds), it is possible to remove the fundamental and even harmonics other than the signal component of frequency f0 / 2.

[0082] Two-stage digital filters 47 and 48 extract high-frequency signal components having a frequency 2n times the fundamental frequency f0.

[0083] Specifically, the first-stage digital filter 47 adds the composite signal Vsum at the sampling time 180 electrical degrees earlier to the composite signal Vsum at each sampling time. That is, the signal Vtmp passed through the digital filter 47 is expressed by the following equation (6A). In this case, the transfer function by z-transform when the sampling interval dt is 30 degrees is expressed by the following equation (6B).

[0084]

number

[0085] Instead of the filter processing expressed by the above formulas (6A) and (6B), filter processing using a transfer function obtained by squaring the right-hand side of formula (6B) may be performed. That is, the first-stage digital filter 47 performs filter processing expressed by the difference formula of the following formula (7A) or the transfer function of the following formula (7B). Specifically, as shown in the following formula (7A), the first-stage digital filter 47 adds to the composite signal Vsum twice the composite signal Vsum at the sampling time 180 electrical degrees earlier, and adds the composite signal Vsum at the sampling time 360 ​​electrical degrees earlier, at each sampling time.

[0086]

number

[0087] Fig. 11 is a diagram showing the gain characteristics of the first-stage digital filter in Fig. 9. Fig. 11(A) shows the gain characteristics of the filter processing expressed by the above expressions (6A) and (6B), and Fig. 11(B) shows the gain characteristics of the filter processing expressed by the above expressions (7A) and (7B).

[0088] As shown in FIG. 11(A), the first-stage digital filter 47 in FIG. 9 removes the fundamental frequency f0 component from the composite signal Vsum and passes the harmonic signal components of the fundamental frequency f0 (i.e., frequency components that are an integer multiple of the fundamental frequency f02 or more).

[0089] The gain characteristic shown in Fig. 11(B) is almost the same as that shown in Fig. 11(A), but the attenuation rate in the vicinity of the fundamental frequency f0 (50 Hz) is larger. Therefore, when considering the fluctuation of the fundamental frequency f0 of the power system, the filter processing shown in the above equations (7A) and (7B) is more preferable.

[0090] 9 again, the second-stage digital filter 48 of the monitoring signal extraction unit 45 is a band-pass filter that passes a desired frequency (i.e., a frequency component that is 2n times the fundamental frequency f0). For example, the transfer function of the digital filter 48 is expressed by the following equation (8). In the following equation (8), ω0 is the center angular frequency to be passed, and τ / 2 is the Q value.

[0091]

number

[0092] FIG. 12 is a diagram showing the gain characteristic of the second-stage digital filter in FIG. 9. In FIG. 12, in equation (8), ω 0 The cases shown are / (2π)=100[Hz] and τ=0.01.

[0093] [Effects of the fourth embodiment] In order to avoid adverse effects on relay calculations that use the fundamental signal V0, the amplitude of each signal component of the supervisory signal Vsup is often set to about 1 / 10 of the amplitude of the fundamental signal V0. Therefore, conversely, when extracting each signal component of the supervisory signal Vsup, it is affected by the fundamental signal V0.

[0094] Therefore, in the digital protection relay of the fourth embodiment, the frequency of the low-frequency signal component of the monitoring signal Vsup is limited to one even multiple of the fundamental frequency f0, and the frequency of the high-frequency signal component of the monitoring signal Vsup is limited to an even multiple of the fundamental frequency f0. This makes it possible to extract the low-frequency signal component with high accuracy by using the smoothing filter 46. Furthermore, by performing the filter processing represented by the formula (6) or (7), the fundamental signal V0 is attenuated and the harmonic signal component can be extracted with high accuracy. Furthermore, by using a band-pass filter, the desired harmonic signal component can be extracted.

[0095] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0096] 10,10A,10B digital protection relay, 20,20A analog input circuit, 21 voltage transformer, 22 adder, 23,25 analog filter, 24,26 ADC, 30,30A monitoring signal generation section, 31 monitoring signal data, 32 DAC, 33 digital processing circuit, 40,40A digital calculation circuit, 41,41A signal extraction section, 42 relay calculation section, 43 fault judgment section, 44 subtractor, 45 monitoring signal extraction section, 46 smoothing filter, 47,48 digital filter, V0 fundamental signal, Vsum composite signal, Vsup,Vsupd monitoring signal, f0 fundamental frequency, f1 low frequency, f2 high frequency, fc cutoff frequency.

Claims

1. A digital protection relay comprising: a monitoring signal generating unit that generates a monitoring signal having a frequency different from a fundamental frequency of a power system, the monitoring signal including a first signal component having a frequency lower than the fundamental frequency; The digital protection relay further comprises: a first analog filter that passes a low frequency range including the fundamental frequency of a composite signal obtained by superimposing the monitoring signal on the analog electrical signal detected from the power system; an analog-to-digital converter that digitally converts the composite signal that has passed through the first analog filter; A digital arithmetic circuit is provided. The digital arithmetic circuit includes: a signal extraction unit that extracts a signal component of the fundamental frequency and the first signal component from the digitally converted composite signal; a relay calculation unit that performs a relay calculation using the extracted signal component of the fundamental wave frequency; a defect determination unit that determines whether or not the first analog filter is defective by using the extracted first signal component, The monitoring signal generating unit a digital-to-analog converter that generates the monitoring signal by digital-to-analog converting monitoring signal data on which the monitoring signal is based; a digital processing circuit provided separately from the digital arithmetic circuit and configured to generate a simulation signal by performing signal processing simulating the first analog filter on the monitoring signal data; The signal extraction unit of the digital arithmetic circuit includes: a supervisory signal extractor configured to extract the first signal component from the digitally converted composite signal; a subtractor for extracting the signal component at the fundamental frequency by subtracting the simulation signal from the digitally converted composite signal.

2. the monitoring signal further includes a second signal component having a frequency higher than a cutoff frequency of the first analog filter; The signal extraction unit further extracts the second signal component from the digitally converted composite signal; The digital protection relay according to claim 1 , wherein the fault determination unit determines whether or not the first analog filter is faulty by using the extracted first signal component and the extracted second signal component.

3. the defect determination unit calculates a gain fluctuation amount in a pass region of the first analog filter based on the extracted first signal component, and calculates a gain fluctuation amount in an attenuation region of the first analog filter based on the extracted second signal component; The digital protection relay according to claim 2, wherein the defect determination unit corrects a gain variation amount of the attenuation region using a gain variation amount of the pass region, and determines whether or not the first analog filter is defective using the gain variation amount of the pass region and the corrected gain variation amount of the attenuation region.

4. A digital protection relay comprising: a monitoring signal generating unit that generates a monitoring signal having a frequency different from a fundamental frequency of the power system; a first analog filter that passes a low frequency range including the fundamental frequency of a composite signal obtained by superimposing the monitoring signal on the analog electrical signal detected from the power system, the monitoring signal includes a first signal component having a frequency lower than the fundamental wave frequency and a second signal component having a frequency higher than a cutoff frequency of the first analog filter, The digital protection relay further comprises: an analog-to-digital converter that digitally converts the composite signal that has passed through the first analog filter; a signal extraction unit that extracts a signal component of the fundamental frequency, the first signal component, and the second signal component from the digitally converted composite signal; a relay calculation unit that performs a relay calculation using the extracted signal component of the fundamental wave frequency; a defect determination unit that determines whether or not the first analog filter is defective by using the extracted first signal component and the extracted second signal component, the defect determination unit calculates a gain fluctuation amount in a pass region of the first analog filter based on the extracted first signal component, and calculates a gain fluctuation amount in an attenuation region of the first analog filter based on the extracted second signal component; The defect judgment unit corrects a gain fluctuation amount of the attenuation region using a gain fluctuation amount of the pass region, and judges whether or not the first analog filter is defective using the gain fluctuation amount of the pass region and the corrected gain fluctuation amount of the attenuation region.

5. the frequency of the first signal component is an even multiple of the fundamental frequency; The digital protection relay according to any one of claims 2 to 4, wherein the frequency of the second signal component is an even multiple of the fundamental wave frequency.

6. The digital protection relay according to claim 5, wherein the signal extraction unit includes a smoothing filter that extracts the first signal component by performing moving average processing on the digitally converted combined signal with a window length of half a period of the first signal component.

7. The digital protection relay according to claim 5 or 6, wherein the signal extraction unit includes a first digital filter that attenuates a signal component of the fundamental frequency of the digitally converted composite signal and passes a harmonic component of the fundamental frequency.

8. The digital protection relay according to claim 7 , wherein the first digital filter adds, for each sampling time, the composite signal at a sampling time 180 electrical degrees earlier to the digitally converted composite signal.

9. 8. The digital protection relay according to claim 7, wherein the first digital filter adds, at each sampling time, to the digitally converted composite signal, twice the composite signal at a sampling time 180 electrical degrees earlier, and adds the composite signal at a sampling time 360 ​​electrical degrees earlier.

10. The signal extraction unit further includes a second digital filter that passes a band having a center frequency of the frequency of the second signal component of the composite signal that has passed through the first digital filter. The digital protection relay according to any one of claims 7 to 9.

11. A method for monitoring an abnormality in a digital protective relay, comprising: The digital protection relay comprises: a first analog filter that passes a low frequency range including a fundamental frequency of the power system; an analog-to-digital converter that digitally converts the signal that has passed through the first analog filter; The abnormality monitoring method includes: A digital-to-analog converter performs digital-to-analog conversion on the monitoring signal data to generate a monitoring signal having a frequency different from the fundamental frequency; a step of generating a simulation signal by performing signal processing simulating the first analog filter on the monitoring signal data by a digital processing circuit; inputting a composite signal in which the monitoring signal is superimposed on an analog electrical signal detected from the power system to the first analog filter; the monitoring signal includes a first signal component having a frequency lower than the fundamental frequency, The abnormality monitoring method further includes: said analog-to-digital converter digitally converting said composite signal that has passed through said first analog filter; A digital arithmetic circuit provided separately from the digital processing circuit extracts the first signal component from the digitally converted composite signal; a step in which the digital arithmetic circuit extracts a signal component of the fundamental frequency by subtracting the simulation signal from the digitally converted composite signal; The digital calculation circuit performs a relay calculation using the extracted signal component of the fundamental wave frequency; and a step in which the digital arithmetic circuit uses the extracted first signal component to determine whether or not the first analog filter is defective.

12. A method for monitoring an abnormality in a digital protective relay, comprising: The digital protection relay comprises: a first analog filter that passes a low frequency range including a fundamental frequency of the power system; an analog-to-digital converter that digitally converts the signal that has passed through the first analog filter; The abnormality monitoring method includes: inputting a composite signal obtained by superimposing a monitoring signal having a frequency different from the fundamental wave frequency on an analog electrical signal detected from the power system to the first analog filter; the monitoring signal includes a first signal component having a frequency lower than the fundamental wave frequency and a second signal component having a frequency higher than a cutoff frequency of the first analog filter, The abnormality monitoring method further includes: converting the composite signal that has passed through the first analog filter into a digital signal by the analog-to-digital converter; A digital arithmetic circuit extracts the fundamental frequency signal component, the first signal component, and the second signal component from the digitally converted composite signal; The digital calculation circuit performs a relay calculation using the extracted signal component of the fundamental wave frequency; and determining whether the first analog filter is defective by the digital arithmetic circuit using the extracted first signal component and the extracted second signal component; The determining step includes: calculating a gain fluctuation amount in a passband of the first analog filter based on the extracted first signal component, and calculating a gain fluctuation amount in an attenuation band of the first analog filter based on the extracted second signal component; correcting a gain variation amount of the attenuation region using the gain variation amount of the pass region, and determining whether or not the first analog filter is defective using the gain variation amount of the pass region and the corrected gain variation amount of the attenuation region.

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