Imaging device and electronic device

Abstract

Provided are an imaging device and an electronic apparatus with which it is possible to reduce the delay of a control signal depending on the horizontal position of pixels. A time code generating unit (104) is provided on the side of a first side of a pixel array (150), a signal processing unit (105) is provided on the side of a second side opposite the first side with respect to the pixel array, a timing generating circuit (120) is provided on the side of the second side with respect to the pixel array, each of a plurality of transfer units (110) is disposed from the side of the first side to the side of the second side through the pixel array, and a control line (130) for transferring a timing signal generated in the timing signal generating unit to the time code generating unit is provided for each of two or more transfer units among the plurality of transfer units.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] There is known an image sensor using an in-pixel ADC architecture, which has an ADC (Analog to Digital Converter) in a pixel that converts an analog pixel signal to a digital signal. In this in-pixel ADC architecture, control signal lines for controlling the circuits are wired from timing generation circuits arranged on both ends of the pixel array in the horizontal direction to circuit blocks for controlling pixels, such as the ADC and a time code generator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO 16 / 136448 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventionally, a linear sensor that detects a movement in a specific direction is known. When this linear sensor is configured using an imaging device, the imaging element has a structure in which the number of pixels is greater in the horizontal direction in which a control signal to each pixel is transferred than in the vertical direction in which a pixel signal is transferred. When the above-mentioned in-pixel ADC architecture is applied to such an imaging device, the control signal line wired from the timing generation circuit becomes longer, and the load on the control signal line increases. As a result, a propagation delay occurs in the control signal line in the horizontal direction of the imaging element.

[0005] The delay time due to this propagation delay becomes larger the farther away from the timing generation circuit. Therefore, a difference in perspective occurs in the timing of the control signal propagated through the control signal line depending on the distance from the timing generation circuit, and this difference in perspective leads to shading in the captured image. In addition, since the delay time itself becomes large, high-speed responsiveness deteriorates, making it difficult to increase the frame rate.

[0006] An object of the present disclosure is to provide an imaging device and electronic device capable of suppressing delays in control signals according to the horizontal position of a pixel. [Means for solving the problem]

[0007] The imaging device according to the present disclosure includes a pixel array in which pixels each including a light receiving element that generates an electric charge by photoelectric conversion in response to received light, a pixel circuit that reads out an electric charge from the light receiving element and outputs an analog signal in response to the electric charge, and a conversion circuit that compares the analog signal with a reference signal whose voltage changes with time and converts the analog signal into pixel data, which is a digital signal, based on a time code whose value is updated every unit time in accordance with the comparison result, are arranged in a matrix form, a time code generation unit that generates the time code, a signal processing unit that performs signal processing on the pixel data, and a timing controller that controls the generation of the time code at least in the time code generation unit. The pixel array includes a timing signal generating unit that generates a timing signal to control the pixel data, and a plurality of transfer units that transfer a time code to each pixel and transfer the pixel data to a signal processing unit, wherein the time code generating unit is provided on a first side of the pixel array, the signal processing unit is provided on a second side opposite the first side with respect to the pixel array, the timing generation circuit is provided on the second side with respect to the pixel array, and the plurality of transfer units are each arranged through the pixel array from the first side to the second side, and a control line is provided in each of two or more of the plurality of transfer units for transferring the timing signal generated in the timing signal generating unit to the time code generating unit. [Brief description of the drawings]

[0008] [Figure 1]FIG. 1 is a block diagram showing a configuration of an example of an electronic device applicable to an embodiment of the present disclosure. [Diagram 2] 1A to 1C are schematic diagrams illustrating examples of use of an electronic device applicable to an embodiment. [Diagram 3] 1 is a diagram illustrating an example of a layered structure of a solid-state imaging element as an imaging device applicable to an embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a configuration of a pixel applicable to the embodiment. [Diagram 5] 1 is a schematic diagram showing an example layout of a solid-state imaging element according to an embodiment; [Figure 6] 1 is a schematic diagram illustrating a configuration of an example of a solid-state imaging element according to an embodiment. [Figure 7] 2 is a block diagram showing in more detail a configuration of an example of a timing generation circuit according to the embodiment; FIG. [Figure 8] 1 is a block diagram showing a configuration of an example of a timing generation circuit including a delay amount adjustment unit that adjusts a delay according to an embodiment. [Figure 9] FIG. 2 is a circuit diagram illustrating a configuration of an example of a transfer circuit applicable to an embodiment. [Figure 10A] 10A and 10B are schematic diagrams illustrating an example of access to a pixel array unit by a transfer circuit applicable to the embodiment. [Figure 10B] FIG. 13 is a schematic diagram showing how a time code is written. [Figure 11A] FIG. 13 is a schematic diagram showing how a time code is read out. [Figure 11B] 10 is a timing chart showing an example of timing relating to reading of a time code. [Figure 12] 5A and 5B are schematic diagrams illustrating an example of the layout of control lines according to the embodiment. [Figure 13] 1 is a schematic diagram illustrating an example of a shield for a control line 130 disposed in a transfer circuit 110 according to an embodiment. FIG. [Figure 14A] FIG. 1 is a diagram showing an example of a layout of a solid-state imaging element according to existing technology. [Figure 14B] 1 is a diagram showing an example of a layout of a solid-state imaging element according to an embodiment; [Figure 15] 4 is a schematic diagram showing an example of a configuration of a solid-state imaging element according to a first modified example of the embodiment. FIG. [Figure 16A] 13 is a schematic diagram illustrating an example of a configuration of a solid-state imaging element according to a second modified example of the embodiment. FIG. [Figure 16B] FIG. 11 is a block diagram showing in more detail the configuration of an arbitrary unit among the units according to a second modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0010] Hereinafter, embodiments of the present disclosure will be described in the following order. 1. Configurations Applicable to the Embodiments 2. Configuration according to the embodiment 2-1. Timing generation circuit 2-2.Transfer circuit 2-3.Shield structure 2-4. Effects of the embodiment 3. First Modification of the Embodiment 4. Second Modification of the Embodiment

[0011] [1. Configuration applicable to the embodiment] First, a configuration applicable to an embodiment of the present disclosure will be described. Fig. 1 is a block diagram showing a configuration of an example of an electronic device 1000 applicable to an embodiment of the present disclosure. The electronic device 1000 is a device for capturing image data, and includes an optical unit 2000, a solid-state image sensor 10, a storage unit 2001, a control unit 2002, and a communication unit 2003.

[0012] The optical unit 2000 collects incident light and guides it to the solid-state imaging device 10. The solid-state imaging device 10 includes a pixel array in which pixels that output pixel signals in response to incident light are arranged in a matrix, and captures an image in response to the incident light and outputs image data. The solid-state imaging device 10 supplies the image data of the captured image output to the storage unit 2001 via a signal line 2005.

[0013] The storage unit 2001 can store image data supplied from the solid-state imaging element 10. The control unit 2002 controls the solid-state imaging element 10 to execute imaging processing. The control unit 2002 supplies various synchronization signals for controlling imaging timing and the like to the solid-state imaging element 10 via, for example, a signal line 2004.

[0014] The communication unit 2003 performs communication between the electronic device 1000 and an external device, and can transmit image data read from the storage unit 2001 to the outside, for example.

[0015] 2 is a schematic diagram for explaining a usage example of the electronic device 1000 applicable to the embodiment. As shown in FIG. 2, the electronic device 1000 can be used in a factory where a belt conveyor 510 is installed.

[0016] Belt conveyor 510 moves subject 511 in a predetermined direction at a constant speed. Electronic device 1000 is fixed near belt conveyor 510 and captures an image of subject 511 to generate image data. The image data is used, for example, to inspect for the presence or absence of defects. This realizes FA (Factory Automation).

[0017] 2, an example in which electronic device 1000 captures an image of subject 511 moving at a constant speed has been described, but the use example of electronic device 1000 is not limited to this example. For example, electronic device 1000 may be configured to capture an image by moving at a constant speed relative to a subject, such as in aerial photography.

[0018] 3 is a diagram showing an example of a stacked structure of a solid-state imaging element 10 as an imaging device applicable to the embodiment. The solid-state imaging element 10 includes a circuit chip 301 and a light-receiving chip 300 laminated on the circuit chip 301. The light-receiving chip 300 and the circuit chip 301 are electrically connected through a connection portion such as a via. The light-receiving chip 300 and the circuit chip 301 can be electrically connected by a Cu-Cu joint or a bump in addition to the via.

[0019] 4 is a block diagram showing an example of a configuration of a pixel 11 applicable to the embodiment. As shown in FIG. 4, the pixel 11 includes a pixel circuit 100 and an ADC (Analog to Digital Converter) 102.

[0020] The pixel circuit 100 outputs a charge signal according to the amount of received light as an analog pixel signal SIG to the ADC 102. The pixel circuit 100 includes a photodiode as a light receiving element, a drain transistor that adjusts the exposure time by discharging the charge accumulated in the photodiode according to a signal OFG, a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion layer (FD) according to a signal TRG, and a reset transistor that resets the FD according to a signal RST.

[0021] In the pixel circuit 100, exposure is started by turning on the discharge transistor with a signal OFG to discharge the charge accumulated in the photodiode. After turning on the reset transistor with a signal RST to reset the FD, the transfer transistor is turned on with a signal TRG, and the charge accumulated in the photodiode by exposure is transferred to and stored in the FD. The charge accumulated in the FD is read out from the FD and converted into a voltage, which is output from the pixel circuit 100 as an analog pixel signal SIG.

[0022] The ADC 102 converts the analog pixel signal SIG supplied from the pixel circuit 100 into a digital signal. The ADC 102 includes a comparison circuit 51 and a data storage unit 52. The comparison circuit 51 compares the pixel signal SIG with a reference signal REF supplied from a DAC (Digital to Analog Converter) 101, and outputs an output signal VCO as a comparison result signal indicating the comparison result. The comparison circuit 51 inverts the output signal VCO when the reference signal REF and the pixel signal SIG become the same (at the same voltage).

[0023] The comparison circuit 51 includes a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback circuit 63. The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 100 in the pixel 11 with the reference signal REF output from the DAC 101, and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF. The voltage conversion circuit 62 converts the current of the signal output from the differential input circuit 61 into a signal based on a voltage. Based on the signal output from the voltage conversion circuit 62, it outputs a comparison result signal that is inverted when the pixel signal SIG is higher than the reference signal REF. The output of this positive feedback circuit 63 is supplied to the data storage unit 52 as the above-mentioned output signal VCO.

[0024] In addition to receiving the output signal VCO from the comparison circuit 51, the data storage unit 52 is supplied with a signal WR indicating a write operation of a pixel signal, a signal RD indicating a read operation of a pixel signal, and a signal WORD for controlling the read timing of the pixel 11 during a read operation of a pixel signal, all from a pixel drive circuit 103, which will be described later with reference to Fig. 5. In addition, a time code generated by a time code generator 104, which will be described later with reference to Fig. 5, is also supplied via a time code transfer unit 23.

[0025] The data storage unit 52 includes a latch control circuit 71 that controls the write and read operations of the time code based on signals WR and RD, and a latch storage unit 72 that stores the time code.

[0026] In the time code write operation, the latch control circuit 71 stores the time code, which is supplied from the time code transfer unit 23 and updated every unit time, in the latch storage unit 72 while the output signal VCO in a high state is being input from the comparison circuit 51. When the reference signal REF and the pixel signal SIG become the same (at the same voltage) and the output signal VCO supplied from the comparison circuit 51 is inverted to a low state, the latch control circuit 71 stops writing (updating) the supplied time code and causes the latch storage unit 72 to hold the time code finally stored in the latch storage unit 72. The time code stored in the latch storage unit 72 represents the time when the pixel signal SIG and the reference signal REF became equal, and represents data indicating that the pixel signal SIG was the reference voltage at that time, i.e., a digitized light intensity value.

[0027] After the sweep of the reference signal REF is completed and the time codes are stored in the latch storage units 72 of all the pixels 11 in the pixel array, the operation of the pixels 11 is changed from a write operation to a read operation.

[0028] In the time code read operation, when the pixel 11 reaches its own read timing based on a signal WORD that controls the read timing, the latch control circuit 71 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 72 to the time code transfer unit 23. The time code transfer unit 23 sequentially transfers the supplied time codes in the column direction (vertical direction) and supplies them to a signal processing circuit 105, which will be described later with reference to FIG. 5.

[0029] 4, among the components included in the pixel 11, the components related to analog signals, i.e., the pixel circuit 100 and a part of the ADC 102 (e.g., a part of the differential input circuit 61), are provided in a photosensor chip 300 shown in Fig. 3. Furthermore, the components related to digital signals included in the pixel 11, for example, another part of the comparator circuit 51 including another part of the differential input circuit 61, the DAC 101, and the time code transfer unit 23, are provided in a circuit chip 301 shown in Fig. 3.

[0030] Fig. 5 is a schematic diagram showing an example of the layout of the solid-state imaging element 10 according to the embodiment. More specifically, Fig. 5 shows an example of the layout of the circuit chip 301 of the solid-state imaging element 10. In Fig. 5 and the following similar figures, the left-right direction of the figure is the horizontal direction, and the up-down direction is the vertical direction.

[0031] 5, in the circuit chip 301, the output interface 106, the signal processing circuit 105, and the timing generation circuit 120 are arranged from the bottom end toward the top. Also, the DAC 101, the pixel drive circuit 103, and the time code generator 104 are arranged from the top end toward the bottom. The pixel array unit 150 is arranged between the timing generation circuit 120 and the time code generator 104.

[0032] The pixel array unit 150 includes a plurality of pixels 11 arranged in a matrix. At this time, as described above, a portion of the ADC 102 in the pixel 11, excluding a portion of the differential input circuit 61 arranged on the light receiving chip 300, for example, is arranged on the circuit chip 301. Therefore, in Fig. 5, a configuration of the ADC 102 in Fig. 4 excluding a portion of the differential input circuit 61 arranged on the light receiving chip 300 is shown as the ADC 102. This is also common to the following similar drawings.

[0033] A plurality of transfer circuits 110 are arranged at predetermined intervals in the horizontal direction from the upper end side (first side) to the lower end side (second side) of the pixel array unit 150. That is, assuming that the arrangement of the ADCs 102 (pixels 11) in the horizontal direction in the pixel array unit 150 is a row and the arrangement of the ADCs (pixels 11) in the vertical direction is a column, each transfer circuit 110 is arranged along the column direction in the pixel array unit 150.

[0034] 5, each transfer circuit 110 is configured such that one ADC 102 is connected to the left and one to the right in each row. That is, in the example of Fig. 5, the pixel array unit 150 has a number of transfer circuits 110 equal to "the number of pixels in the row direction / 2".

[0035] Each transfer circuit 110 includes the above-mentioned time code transfer unit 23. In addition, each transfer circuit 110 also serves as a path through which image data output from each pixel 11 of the pixel array unit 150 is transferred to the signal processing circuit 105.

[0036] Moreover, the pixel array section 150 according to the embodiment has an extremely elongated shape in the horizontal direction, with several thousand pixels in the row direction and several tens of pixels in the column direction, for example. In other words, the aspect ratio of the pixel array section 150 is extremely large.

[0037] 5 and the following similar drawings, each transfer circuit 110 is shown to be disposed between two ADCs 102 for the purpose of explanation. In reality, each ADC 102 (pixels 11) is disposed in an equally spaced lattice pattern, and each transfer circuit 110 is disposed in a layer different from each ADC 102. That is, each transfer circuit 110 is disposed so as to have an overlapping portion with each ADC 102 (pixel 11) in the layer direction in the laminated structure.

[0038] (2. Configuration according to the embodiment) Next, a configuration according to an embodiment of the present disclosure will be described. FIG. 6 is a schematic diagram showing an example of a configuration of a solid-state imaging device 10 according to an embodiment. As shown in FIG. 6, in the embodiment, a control line 130 is arranged for each transfer circuit 110, and each control line 130 connects a timing generation circuit 120 to a configuration arranged on the opposite side of the pixel array unit 150 with respect to the timing generation circuit 120. The timing generation circuit 120 generates various timing signals for driving the solid-state imaging device 10. The timing generation circuit 120 has a function as a timing signal generation unit that generates a timing signal that controls the timing at which the time code generator 104 generates a time code.

[0039] More specifically, the control line 130 includes a plurality of control lines 130a, 130b, 130c, and 130d. The timing generation circuit 120 can output different timing signals to the control lines 130a, 130b, 130c, and 130d, respectively.

[0040] 6, the control line 130a is a control line for supplying the timing signal generated by the timing generation circuit 120 to the pixel drive circuit 103. The pixel drive circuit 103 generates drive signals (for example, the above-mentioned signals OFG, TRG, and RST) for driving each pixel 11 in the pixel circuit 100 based on the timing signal supplied via the control line 130a. The pixel drive circuit 103 supplies each generated drive signal to each pixel 11 via the transfer circuit 110.

[0041] The control line 130b is a control line for supplying the timing signal generated by the timing generation circuit 120 to the time code generator 104. The time code generator 104 generates a time code whose value is updated every unit time based on the timing signal supplied via the control line 130b. The time code generator 104 supplies the generated time code to each pixel 11 via the transfer circuit 110.

[0042] The control line 130c is a control line for supplying timing signals generated by the timing generation circuit 120 to each ADC 102. The timing signals include, for example, the above-mentioned signals WR, RD, and WORD, and the ADCs 102 are driven by these timing signals.

[0043] Moreover, the control line 130d is a control line for supplying the timing signal generated by the timing generating circuit 120 to the DAC 101. In response to this timing signal, the DAC 101 starts sweeping, for example, the reference signal REF.

[0044] In the embodiment, the timing generation circuit 120 is configured to be able to suppress delays between the transfer circuits 110 in the timing signals output to the control lines 130a, 130b, 130c, and 130d arranged in the transfer circuits 110, respectively.

[0045] In the following description, when there is no need to particularly distinguish between the control lines 130a, 130b, 130c, and 130d, these control lines 130a, 130b, 130c, and 130d will be collectively referred to as the control line 130.

[0046] (2-1. Timing generation circuit) Next, the timing generation circuit 120 according to the embodiment will be described in more detail.

[0047] 7 is a block diagram showing a more specific configuration of an example of the timing generation circuit 120 according to the embodiment. In FIG. 7, the timing generation circuit 120 includes a plurality of timing generation circuits 1201, 1202, ..., 120 N In the example of FIG. 7, each of the timing generation circuits 1201, 1202, ..., 120 N supplies a common timing signal to each of the control lines 130 of the two transfer circuits 110. When the effect of delays between the control lines 130 on the characteristics can be ignored, it is possible to supply timing signals to multiple control lines 130 from one timing generation circuit 1201 in this manner.

[0048] Here, as shown in FIG. 7, a plurality of timing generation circuits 1201, 1202, . . . , 120 N Consider the case where an external sync signal serving as a reference for the timing signal is input from, for example, the timing generating circuit 1201 at the end.

[0049] The timing generation circuit 1201 generates a timing signal based on the input external synchronizing signal and outputs it to the control line 130, and also transmits a synchronizing signal 1211 based on the external synchronizing signal to the next-stage timing generation circuit 1202. The timing generation circuit 1202 generates a timing signal based on the input synchronizing signal 1211 and outputs it to the control line 130, and also transmits the synchronizing signal 1211 as a synchronizing signal 1212 to the next timing generation circuit. In this way, the synchronizing signals 1211, 1212, ... based on the external synchronizing signal are transmitted in sequence to the next timing generation circuit.

[0050] In this case, for example, in FIG. 7, a synchronous signal 1211 is transmitted from the timing generation circuit 1201 on the left side to the timing generation circuit 1202, and a synchronous signal 1212 is transmitted from the timing generation circuit 1203 on the right side. N Due to the effect of delay, a deviation in synchronization occurs between the synchronization signal transmitted to the

[0051] Each of the timing generation circuits 1201, 1202, ..., 120 N In the case where the synchronization of the supplied synchronous signal is lost, the timing generating circuits 1201, 1202, . . . , 120 N A difference in perspective occurs in the timing of the timing signals transmitted by the control lines 130 connected to the optical axis 110 depending on the deviation in synchronization, and this difference in perspective leads to shading in the captured image.

[0052] Therefore, in this embodiment, each of the timing generation circuits 1201, 1202, . . . imparts a predetermined delay to each of the timing signals generated based on the input synchronization signals 1211, 1212, .

[0053] 8 is a block diagram showing an example of a configuration of a timing generation circuit including a delay amount adjustment unit that adjusts a delay according to an embodiment. In FIG. 8, a timing generation circuit 1201 includes a timing generation unit 1221 and a delay amount adjustment unit 1231. Each of the timing generation circuits 1202, ..., 120 N Similarly, the timing generation units 1222, . . . , 122 N and delay amount adjustment units 1232, . . . , 123 N Including,

[0054] Here, in the timing generation circuit 1201 arranged at the left end, an external synchronization signal is input to the delay amount adjustment unit 1231. In this case, if we simply consider the horizontal distance, the delay of the timing generation circuit 1201 at the left end to which the external synchronization signal is input is set to approximately zero, while the delay of the timing generation circuit 1201 arranged at the right end far from the input position of the external synchronization signal is set to approximately zero. N Therefore, the delay of each of the timing generation circuits 1201, 1202, ..., 120 NThe amount of delay given to the timing generator 1201 on the left side to which the reference external synchronizing signal is supplied is set to be maximum, and the amount of delay given to the timing generator 120 on the right side, which is the furthest from the position to which the external synchronizing signal is supplied, is set to be maximum. N So let's make it the minimum.

[0055] In the example of Fig. 8, an external synchronization signal is supplied to the leftmost timing generation circuit 1201 and input to the delay adjustment unit 1231. The delay adjustment unit 1231 supplies a synchronization signal based on the input external synchronization signal to the next-stage timing generation circuit 1202, and also supplies a synchronization signal obtained by giving a predetermined delay to the external synchronization signal to the timing generation unit 1221. Here, the delay given by the delay adjustment unit 1231 is the delay of each of the timing generation circuits 1201, 1202 included in the timing generation circuit 120. 、 …, 120 N This is the maximum delay among the delays given in each of the above.

[0056] The timing generation unit 1221 generates a timing signal based on the synchronization signal to which a delay has been given by the delay amount adjustment unit 1231 , and outputs the generated timing signal to the control line 130 .

[0057] In the timing generation circuit 1202, the delay adjustment unit 1232 supplies the inputted synchronization signal 1211 as a synchronization signal 1212 to the next-stage timing generation circuit (not shown), and also supplies a synchronization signal obtained by delaying the synchronization signal 1211 by giving a predetermined delay to the timing generation unit 1222. Here, the timing generation circuit 1202 is farther from the position where the external synchronization signal is supplied than the timing generation circuit 1201. Therefore, the delay given by the delay adjustment unit 1232 in the timing generation circuit 1202 is smaller than the delay given by the delay adjustment unit 1231 in the preceding timing generation circuit 1201.

[0058] Furthermore, the timing generation circuit 120, which is the furthest from the position where the external synchronization signal is supplied, N In the delay amount adjustment unit 123 NThe delay amount provided by each of the timing generation circuits 1201, 1202, . . . , 120 N It will be the smallest of the three.

[0059] In this manner, each of the timing generation circuits 1201, 1202, . . . , 120 N In each of the timing generating circuits 1201, 1202, ..., 120 N The delay amounts of the timing signals output from the timing devices 10 and 11 are made uniform, thereby suppressing the occurrence of perspective differences due to synchronization errors and preventing the occurrence of shading in captured images.

[0060] (2-2. Transfer circuit) Next, the transfer circuit 110 according to the embodiment will be described in more detail.

[0061] 9 is a circuit diagram showing an example of a configuration of a transfer circuit 110 applicable to the embodiment. The transfer circuit 110 applicable to the embodiment is a shift register having a D-FF (flip-flop) 1110 as a core, and includes an MCK clock transfer unit 1101, an FF data transfer unit 1102, and an REN (read enable) signal transfer unit 1103. The REN signal transfer units 1103 are provided on the left and right sides of the transfer circuit 110 to transfer the read enable signal RENL on the left side of the figure and the read enable signal RENR on the right side.

[0062] Each of the circuit blocks 11001, 11002, ..., 1100 is equivalent to one stage of the D-FF 1110. M In this embodiment, read / write bidirectional buffers 1111L and 1111R (hereinafter, bidirectional buffers 1111L, 1111R) are provided on the left and right of the FF output stage data line (hereinafter, MBL) connected to the output of the D-FF 1110, and an nMOS (n-Metal Oxide Semiconductor) transistor 1112 for REPINI (transfer circuit initialize) for initializing the MBL and fixing it to a low level is connected.

[0063] In the example of FIG. 9, the transfer circuit 110 includes bit-by-bit transfer circuits 1101, 1102, . . . , 110 n-1 11001, 11002, ..., 1100 M The pixels 11 included in the pixel array unit 150 are divided into circuit blocks 11001 to 1100 in units called clusters each including a predetermined number of pixels 11. M The access to read pixels is controlled every time.

[0064] The signal MCK is an operation clock signal for the D-FF 1110. The D-FF 1110 is connected to the transfer circuits 1101, 1102, . . . , 1103 for each bit line of the circuit block 11001, i.e., for each bit. n-1 The bidirectional buffers 1111L and 1111R are controlled by a write enable signal WEN and a read enable signal REN, and are arranged in the respective circuit blocks 11001 to 1100. M In this case, it acts as a buffer when writing from the MBL to a local bit line (hereinafter, LBL) or as a buffer when reading from the LBL to the MBL.

[0065] The signal WEN is fixed to a high level when the transfer circuit 110 is used as a write transfer circuit, and is fixed to a low level when the transfer circuit 110 is used as a read transfer circuit. By using this circuit configuration, the transfer circuit 110 can be used in common as a write transfer circuit and a read transfer circuit.

[0066] By providing LBL-L and LBL-R on the left and right of the MBL, including the bidirectional buffers 1111L and 1111R, it is possible to conceal the signal transition of data read by the signal WORD in the timing of operating the D-FF 1110. Accordingly, the read enable signal REN is also input to the left and right of the MBL as the read enable signals REN-L and REN-R.

[0067] 10A is a schematic diagram showing an example of access to a pixel array unit 150 by a transfer circuit 110 applicable to the embodiment. The pixel array unit 150 is divided into units called clusters 140 each including a predetermined number of pixels 11, and each of the circuit blocks 11001, 11002, ..., 11000 of the transfer circuit 110 is connected one-to-one to each of the clusters 140. M are associated with each other.

[0068] For example, as illustrated on the right side of Fig. 10A, the cluster 140 includes 64 pixels, 4 pixels horizontally by 16 pixels vertically, and the transfer circuit 110 is arranged along a central portion 110' in the row direction of the cluster 140. One circuit block (for example, circuit block 11001) of the transfer circuit 110 transfers (writes) the time code and transfers (reads) the pixel data for these 64 pixels, with the pixels 11 designated to the left and right of the central portion 110' in the order of the numbers shown on the pixels 11 in the figure.

[0069] In addition, in FIG. 10A, for the purpose of explanation, the transfer circuit 110 is shown to be arranged for the column of the cluster 140 at the right end of the pixel array section 150, but in reality, the transfer circuit 110 is arranged for each column of the cluster 140 included in the pixel array section 150.

[0070] 10B is a schematic diagram showing how the time codes are written. The time codes generated by the time code generator 104 are written to each of the circuit blocks 11001, 11002, ..., 1100 M The signal is propagated to each pixel 11 of the corresponding cluster 140 via a shift register consisting of:

[0071] Fig. 11A is a schematic diagram showing how the time code is read. Fig. 11B is a timing chart showing an example of the timing of reading the time code. A read pixel to be read is selected from the pixels 11 included in the cluster 140 by a predetermined read pixel selection signal, and the time code stored in the latch memory unit 72 of the selected read pixel is read and transferred to the signal processing circuit 105.

[0072] For example, when pixel 11 numbered "0" is specified by the read pixel selection signal, since pixel 11 numbered "0" is the pixel on the left side of cluster 140, the left read enable signal RENL is set to a high state and the clock MCK is pulsed for, for example, four clocks as shown in frame B in FIG. 11B, to cause the transfer circuit 110 to operate as a shift register. The time code read out from pixel 11 numbered "0" is passed to MBL via the bidirectional buffer 1111L and transferred to the signal processing circuit 105.

[0073] The same is true when pixel 11 numbered "1" is specified by the read pixel selection signal. Since pixel 11 numbered "1" is a pixel on the right side of cluster 140, the right read enable signal RENR is set to a high state and the clock MCK is pulsed, for example, four times, to cause the transfer circuit 110 to operate as a shift register. The time code read out from pixel 11 numbered "1" is passed to MBL via the bidirectional buffer 1111R and transferred to the signal processing circuit 105.

[0074] In the embodiment, the control lines 130a to 130d are arranged in the transfer circuit 110 that performs such an operation. Fig. 12 is a schematic diagram showing an example of the layout of the control lines 130a to 130d according to the embodiment. In the example of Fig. 12, the control line 130a is arranged inside the REN signal transfer unit 1103 on the left side of the figure, and the control line 130b is arranged inside the MCK clock transfer unit 1101. In addition, the control line 130d is arranged inside the REN signal transfer unit 1103 on the right side of the figure. Furthermore, the control line 130c is arranged further inside the control line 130d.

[0075] Of the control lines 130a to 130d, the control lines 130a, 130b, and 130d pass through the transfer circuit 110 to supply timing signals generated by the timing generation circuit 120 to the pixel drive circuit 103, the time code generator 104, and the DAC 101, which are arranged outside the pixel array unit 150. On the other hand, the control line 130c for supplying timing signals to each ADC 102 branches out to the left and right within the area of ​​the transfer circuit 110, for example.

[0076] (2-3. Shield structure) Next, a shielding structure for the control line 130 according to the embodiment will be described. In the transfer circuit 110, that is, when the control line 130 is arranged with a portion overlapping with the transfer circuit 110 in the layer direction of the stack, it is necessary to consider interference between the digital signal transmitted by the control line 130 and the analog signal handled in the pixel circuit 100 or the differential input circuit 61. In the embodiment, the control line 130 arranged in the transfer circuit 110 is shielded by using a low resistance wiring (e.g., a power supply wiring). This makes it possible to suppress interference of the digital signal transmitted by the control line 130 with analog signals such as the outputs of the pixel circuit 100 or the differential input circuit 61.

[0077] 13 is a schematic diagram illustrating an example of a shield for a control line 130 disposed in a transfer circuit 110 according to an embodiment. Section (a) of FIG. 13 is an example of a cross-sectional view taken along line A-A' illustrated in section (b) of FIG.

[0078] The light receiving chip 300 includes a first substrate 13 and a wiring layer 14 provided on the first substrate 13. In the light receiving chip 300, the pixel circuits 100 and a part of the differential input circuit 61 in the ADC 102 are arranged on the first substrate 13. The wiring layer 14 has each wire 17 provided thereon.

[0079] The circuit chip 301, like the photosensor chip 300, includes a second substrate 15 and a wiring layer 16 provided on the second substrate. In the circuit chip 301, the second substrate 15 is provided with the elements 19, and also has another part of the differential input circuit 61 in the ADC 102, a data storage unit 52, a voltage conversion circuit 62, and a positive feedback circuit 63 arranged thereon. The wiring layer 16 is provided with the wires 17 and a control line 130.

[0080] The light-receiving chip 300 and the circuit chip 301 are bonded together by a surface of the wiring layer 14 and a surface of the wiring layer 16. More specifically, the light-receiving chip 300 and the circuit chip 301 are bonded together by using the surface of the wiring layer 14 opposite to the first substrate 13 and the surface of the wiring layer 16 opposite to the second substrate 15 as bonding surfaces, thereby forming the solid-state imaging element 10.

[0081] At this time, the photosensor chip 300 and the circuit chip 301 are electrically connected through the wiring 17 of the wiring layers 14 and 16 via the bonding portion 18 such as a Cu-Cu bond.

[0082] Here, in the solid-state imaging device 10 according to the embodiment, the shield 1200 is provided between the control line 130 and the bonding surface in the circuit chip 301. As described above, the shield 1200 is configured using low-resistance wiring such as power wiring, and a predetermined potential is applied to the shield 1200. The shield 1200 between the control line 130 and the bonding surface can suppress interference of the digital signal transmitted to the control line 130 with the analog signal in the light receiving chip 300.

[0083] Moreover, the shield 1200 between the control line 130 and the bonding surface also functions as a light-shielding film that blocks light emitted from the second substrate 15 in the circuit chip 301 .

[0084] 13, shields 1200 are also provided on both sides of the control line 130. This makes it possible to suppress interference of the digital signal transmitted to the control line 130 with the wiring 17 in the circuit chip 301.

[0085] (2-4. Effects of the embodiment) Next, the effect of the configuration according to the embodiment will be described with reference to Figures 14A and 14B. As an example, it will be shown to what extent the delay of the pixel control signal can be suppressed by passing the control line 130 through the transfer circuit 110.

[0086] 14B, the horizontal length of the pixel area of ​​the pixel array unit 150 is 10 [cm] and the vertical length is 500 [μm]. The vertical length of the time code generator 104 is 200 [μm], the vertical length of the transfer circuit 110 is 300 [μm], and the delay time per 1 [cm] is delay time ΔT.

[0087] Fig. 14A shows an example of the layout of the solid-state imaging device 10 according to the existing technology. In the example of Fig. 14A, timing generation circuits 120a and 120b are arranged on the left and right sides, i.e., on both ends in the horizontal direction, of the pixel array section 150, and output timing signals to control lines 132a and 132b arranged parallel to the horizontal direction of the pixel array section 150.

[0088] In this way, in the existing technology, the control lines 132a and 132b are wired from the two timing generation circuits 120a and 120b on the left and right, so that the left timing generation circuit 120a controls the left half of the pixel array section 150, and the right timing generation circuit 120b controls the right half of the pixel array section 150. In other words, the delay time difference between the left and right is "5 x ΔT" since the delay time per 1 [cm] is ΔT. This delay time difference becomes shading. In addition, since the timing signal is transmitted along the long side of the pixel array section 150, which has a very large aspect ratio, the delay time itself is large, making it difficult to achieve a high frame rate.

[0089] FIG. 14B shows an example of the layout of the solid-state imaging device 10 according to the embodiment. In the embodiment, the length of the control line 130 from the timing generation circuit 120 to the pixel driving circuit 103 is the sum of the vertical lengths of the transfer circuit 110 and the time code generator 104, and is therefore 300 [μm] + 200 [μm] = 500 [μm]. This distance does not vary depending on the position in the pixel array section 150, and no distance difference occurs in the timing signal transmitted by the control line 130. In addition, the delay time of the timing signal is (500 [μm] / 1 [cm]) × ΔT = 0.05 × ΔT, which is 1 / 100 of the example of the existing technology. This enables high-speed response and achieves a high frame rate.

[0090] Furthermore, in the existing technology, the longer the horizontal length, the longer the control lines 132a and 132b become, and the longer the delay time becomes. On the other hand, in the configuration of the embodiment, the length of the control line 130 is the sum of the vertical lengths of the transfer circuit 110 and the time code generator 104 described above, and is constant. In other words, the longer the horizontal length, the greater the effect of improving the delay time compared to the existing technology.

[0091] (3. First Modification of the Embodiment) Next, a first modified example of the embodiment will be described. The first modified example of the embodiment is an example in which the configuration of the control line 130 arranged for the transfer circuit 110 or the timing signal transmitted by the control line 130 is varied according to the function of the supply destination to which each of the control lines 130a to 130d included in the control line 130 supplies the timing signal.

[0092] In the following, a case where the configuration of the control line 130 arranged for the transfer circuit 110 is changed will be described.

[0093] 15 is a schematic diagram showing an example of a configuration of a solid-state imaging device 10 according to a first modified example of an embodiment. For example, a pixel driving circuit 103 is provided for each column. Also, an ADC 102 is provided for each pixel 11. Therefore, since the pixel driving circuit 103 and the ADC 102 require high-speed operation, a control line 130a that supplies a timing signal to the pixel driving circuit 103 and a control line 130c that supplies a timing signal to each ADC 102 are provided in all transfer circuits 110.

[0094] In contrast, the time code generator 104 is not required to operate at such high speed compared to the pixel drive circuit 103 and each ADC 102. Therefore, the time code generator 104 can be provided for every several columns, for example. In the example of Fig. 15, the control line 130d that supplies a timing signal to the time code generator 104 is arranged in every other transfer circuit 110, thinning out the transfer circuits 110 one by one.

[0095] For example, one or two DACs 101 may be provided in the pixel array unit 150. When only one DAC 101 is provided, one reference signal REF is commonly used by all pixels 11 in the pixel array unit 150. When two DACs 101 are provided, the reference signals REF generated by the two DACs 101 may be merged, or the pixel array unit 150 may be divided into regions, and the reference signals REF generated by the two DACs 101 may be supplied to the respective regions.

[0096] In this way, no higher speed operation is required for the DAC 101. Fig. 15 shows an example in which two DACs 101 are provided in the pixel array unit 150, and the control lines 130b that supply timing signals to the DACs 101 are arranged in every third transfer circuit 110 by thinning out the transfer circuits 110 by three.

[0097] In this way, by varying the configuration of the control line 130 arranged relative to the transfer circuit 110, effects such as reduction in power consumption and suppression of noise caused by the timing signal transmitted by the control line 130 can be expected.

[0098] (4. Second Modification of the Embodiment) Next, a second modified example of the embodiment will be described. The second modified example of the embodiment has a unit configuration in which the pixel area of ​​the pixel array unit 150 is divided and a timing signal is transmitted for each divided area. In other words, the unit is a divided pixel array unit obtained by dividing the pixel area of ​​the pixel array unit 150.

[0099] 16A is a schematic diagram showing an example of a configuration of a solid-state imaging device 10 according to a second modified example of the embodiment. In FIG. 16A, the solid-state imaging device 10 includes a plurality of units 2001, 2002, ..., 200 N Each unit includes 2001, 2002, ..., 200 N The pixel array section 150 is divided into units 2001 to 200 N The divided pixel array sections 1521 to 152 are divided according to the number of N In FIG. 16A, each of the units 2001, 2002, ..., 200 N are also denoted as Unit #1, Unit #2, ..., Unit #N, respectively.

[0100] Each unit 2001~200 N Each of these is DAC1011~101 N , pixel driving circuits 1031 to 103 N , Time Code Generator 1041~104 N , timing generation circuit 120 10 ~120 1N , signal processing circuits 1051 to 105 N The output interface 106 includes each of the units 2001 to 200. N A common circuit is provided for all of the above.

[0101] FIG. 16B shows units 2001 to 200 according to a second modified example of the embodiment. N Any 200 units X 16B is a block diagram showing the configuration of unit 200 (unit #X) in more detail. X DAC101 X and the pixel driving circuit 103X and the divided pixel array section 152 X and a timing generation circuit 120 X and the signal processing circuit 105 X In the example of FIG. 16B, the unit 200 X 4 transfer circuits 110 11 , 110 12 , 110 13 and 110 14 are placed.

[0102] Timing generation circuit 120 X For example, if the unit to the left #(X-1) receives a sync signal of 121, X-1 and receives the sync signal 121 X-1 and generates and outputs a timing signal based on the synchronization signal 121. X-1 Sync signal 121 X For example, pass it to the unit to the right #(X+1).

[0103] Timing generation circuit 120 X The timing signal generated by the control circuit 110 is transmitted to the control line 130. The control line 130 is branched into four control lines 1301, 1302, 1303, and 1304, each of which is connected to each of the transfer circuits 110. 11 , 110 12 , 110 13 and 110 14 The control lines 1301, 1302, 1303, and 1304 include control lines 130a, 130b, 130c, and 130d, respectively, which are not shown.

[0104] The timing signal is transmitted to the DAC 101 via these control lines 1301, 1302, 1303 and 1304. X , pixel driving circuit 103 X and time code generator 104 X At this time, as described in the first modification of the embodiment, each transfer circuit 110 11 , 110 12 , 110 13 and 110 14In this case, each of the timing signals transmitted through the control lines 130a to 130d can be appropriately thinned out.

[0105] The pixel data read from each pixel 11 is transferred to the corresponding transfer circuit 110. 11 , 110 12 , 110 13 and 110 14 via the signal processing circuit 105 X are supplied to.

[0106] In this way, by configuring the generation and transmission of timing signals for each unit, even if the number of effective pixels in the pixel array section 150 increases or decreases, for example, the increase or decrease can be handled by increasing or decreasing it on a unit basis, making it easier to develop derivative products.

[0107] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0108] The present technology can also be configured as follows. (1) a light receiving element that generates electric charges by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge; a conversion circuit that compares the analog signal with a reference signal whose voltage changes over time, and converts the analog signal into pixel data, which is a digital signal, based on a time code whose value is updated every unit time according to a comparison result; a pixel array in which pixels each including a time code generating unit for generating the time code; A signal processing unit that performs signal processing on the pixel data; a timing signal generating unit that generates a timing signal that controls the timing at which the time code is generated by at least the time code generating unit; a plurality of transfer units for transferring the time codes to the respective pixels and transferring the pixel data to the signal processing unit; Equipped with the time code generating unit is provided on a first side of the pixel array, the signal processing unit is provided on a second side opposite to the first side with respect to the pixel array, the timing generation circuit is provided on the second side with respect to the pixel array, The plurality of transfer units are respectively arranged through the pixel array from the first side to the second side, a control line for transferring the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transfer units; Imaging device. (2) the first side is a side along a row direction in the array, The plurality of transfer units are provided along a column direction in the array, The imaging device according to (1) above. (3) A control line for transmitting the timing signal generated by the timing signal generation unit to the pixel circuit is further provided to two or more of the transfer units. The imaging device according to (1) or (2). (4) A reference signal generating circuit that generates the reference signal is further provided. a control line for transmitting the timing signal generated by the timing signal generating unit to the reference signal generating circuit is further provided to two or more of the plurality of transfer units; The imaging device according to any one of (1) to (3). (5) The timing signal generation unit a delay adjustment unit that adjusts a delay between each of the control lines of the timing signal transmitted through each of the control lines provided in two or more of the plurality of transfer units; The imaging device according to any one of (1) to (4). (6) The timing signal generation unit transmitting the common timing signal by each of the control lines provided in two or more of the plurality of transfer units; The imaging device according to any one of (1) to (5). (7) The timing signal generation unit transmitting the timing signal through each of the control lines provided in the remaining transfer units obtained by thinning out a predetermined number of transfer units from the plurality of transfer units; The imaging device according to any one of (1) to (6). (8) The timing signal generation unit transmitting the timing signal through each of the control lines provided in the remaining transfer units that have been thinned out according to the accuracy required for the timing signal at a transfer destination from the plurality of transfer units; The imaging device according to (7) above. (9) a divided pixel array obtained by dividing the pixel array in a direction of the first side; a time code generating unit provided on the first side of the divided pixel array and configured to generate the time code for the divided pixel array; the signal processing unit that is provided on the second side of the divided pixel array and that performs the signal processing on the pixel data output from the divided pixel array; a timing signal generating unit that generates a timing signal for the divided pixel array to control a timing at which the time code is generated by at least the time code generating unit; one or more transfer units arranged from the first side to the second side of the divided pixel array; Multiple units including The imaging device according to any one of (1) to (8). (10) a first chip including a first substrate on which the light receiving element, the pixel circuit, and a part of the conversion circuit are arranged, and a first wiring layer provided on the first substrate; a second chip including: a second substrate on which another part of the conversion circuit, the signal processing section, and the timing generation circuit are arranged; and a second wiring layer provided on the second substrate and including the control line, the second chip being attached to a surface of the first wiring layer opposite the second substrate; having a shielding layer is provided between a bonding surface where the first chip and the second chip are bonded and the control line; The imaging device according to any one of (1) to (9) above. (11) a light receiving element that generates electric charges by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge; a conversion circuit that compares the analog signal with a reference signal whose voltage changes over time, and converts the analog signal into pixel data, which is a digital signal, based on a time code whose value is updated every unit time according to a comparison result; a pixel array in which pixels each including a time code generating unit for generating the time code; A signal processing unit that performs signal processing on the pixel data; a timing signal generating unit that generates a timing signal that controls the timing at which the time code is generated by at least the time code generating unit; a plurality of transfer units for transferring the time code to each of the pixels and transferring the pixel data to the signal processing unit; An imaging unit having an optical unit that collects incident light and guides it to the light receiving element; a storage unit that stores the pixel data that has been signal-processed by the signal processing unit; Equipped with The imaging unit includes: the time code generating unit is provided on a first side of the pixel array, the signal processing unit is provided on a second side opposite to the first side with respect to the pixel array, the timing generation circuit is provided on the second side with respect to the pixel array, The plurality of transfer units are respectively arranged through the pixel array from the first side to the second side, a control line for transferring the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transfer units; electronic equipment. [Explanation of symbols]

[0109] 10 Solid-state imaging element 11 pixels 13 First board 14,16 wiring layer 15 Second board 17 Wiring 61 Differential Input Circuit 100 pixel circuit 101,1011,101 N DAC 102 ADC 103,1031,103 N Pixel driving circuit 104,1041,104 N Time Code Generator 105,1051,105 N Signal Processing Circuit 106 Output Interface 110,1101,1102,110 n-1 Transfer Circuit 120,1201,1202,120 N ,120 10 ,120 1N , 120a, 120b Timing generation circuit 1221,1222,122 N Timing Generation Section 1231,1232,123 N Delay Adjustment Section 130, 1301, 1302, 1303, 1304, 130a, 130b, 130c, 130d control line 140 Clusters 150 Pixel array section 1521,152 N ,152 X Divided pixel array section 2001,2002,200 N unit 300 Photodetector chip 301 Circuit Chip 1000 electronic equipment 1101 MCK clock transfer unit 1102 FF data transfer section 1103 REN signal transmission unit 1200 Shield

Claims

1. a light receiving element that generates electric charges by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge; a conversion circuit that compares the analog signal with a reference signal whose voltage changes over time, and converts the analog signal into pixel data, which is a digital signal, based on a time code whose value is updated every unit time according to a comparison result; a pixel array in which pixels each including a time code generating unit for generating the time code; A signal processing unit that performs signal processing on the pixel data; a timing signal generating unit that generates a timing signal that controls the timing at which the time code is generated by at least the time code generating unit; a plurality of transfer units for transferring the time codes to the respective pixels and transferring the pixel data to the signal processing unit; Equipped with the time code generating unit is provided on a first side of the pixel array, the signal processing unit is provided on a second side opposite to the first side with respect to the pixel array, the timing signal generation unit is provided on the second side with respect to the pixel array, The plurality of transfer units are respectively arranged through the pixel array from the first side to the second side, a control line for transferring the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transfer units; Imaging device.

2. the first side is a side along a row direction in the array, The plurality of transfer units are provided along a column direction in the array, The imaging device according to claim 1 .

3. a control line for transmitting the timing signal generated by the timing signal generation unit to the pixel circuit is further provided to two or more of the transfer units; The imaging device according to claim 1 .

4. A reference signal generating circuit that generates the reference signal is further provided. a control line for transmitting the timing signal generated by the timing signal generating unit to the reference signal generating circuit is further provided to two or more of the plurality of transfer units; The imaging device according to claim 1 .

5. The timing signal generation unit a delay adjustment unit that adjusts a delay between each of the control lines of the timing signal transmitted through each of the control lines provided in two or more of the plurality of transfer units; The imaging device according to claim 1 .

6. The timing signal generation unit transmitting the common timing signal by each of the control lines provided in two or more of the plurality of transfer units; The imaging device according to claim 1 .

7. The timing signal generation unit transmitting the timing signal through each of the control lines provided in the remaining transfer units obtained by thinning out a predetermined number of transfer units from the plurality of transfer units; The imaging device according to claim 1 .

8. The timing signal generation unit transmitting the timing signal through each of the control lines provided in the remaining transfer units that have been thinned out according to the accuracy required for the timing signal at a transfer destination from the plurality of transfer units; The imaging device according to claim 7.

9. a divided pixel array obtained by dividing the pixel array in the direction of the first side; a time code generating unit provided on the first side of the divided pixel array and configured to generate the time code for the divided pixel array; the signal processing unit that is provided on the second side of the divided pixel array and that performs the signal processing on the pixel data output from the divided pixel array; a timing signal generating unit that generates a timing signal for the divided pixel array to control a timing at which the time code is generated by at least the time code generating unit; one or more transfer units arranged from the first side to the second side of the divided pixel array; Multiple units including The imaging device according to claim 1 .

10. a first chip including a first substrate on which the light receiving element, the pixel circuit, and a part of the conversion circuit are arranged, and a first wiring layer provided on the first substrate; a second chip including: a second substrate on which another part of the conversion circuit, the signal processing unit, and the timing signal generating unit are arranged; and a second wiring layer provided on the second substrate and including the control lines, the second substrate being bonded to a surface of the first wiring layer opposite the first substrate; having a shielding layer is provided between a bonding surface where the first chip and the second chip are bonded and the control line; The imaging device according to claim 1 .

11. a light receiving element that generates electric charges by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge; a conversion circuit that compares the analog signal with a reference signal whose voltage changes over time, and converts the analog signal into pixel data, which is a digital signal, based on a time code whose value is updated every unit time according to a comparison result; a pixel array in which pixels each including a time code generating unit for generating the time code; A signal processing unit that performs signal processing on the pixel data; a timing signal generating unit that generates a timing signal that controls the timing at which the time code is generated by at least the time code generating unit; a plurality of transfer units for transferring the time code to each of the pixels and transferring the pixel data to the signal processing unit; An imaging unit having an optical unit that collects incident light and guides it to the light receiving element; a storage unit that stores the pixel data that has been signal-processed by the signal processing unit; Equipped with The imaging unit includes: the time code generating unit is provided on a first side of the pixel array, the signal processing unit is provided on a second side opposite to the first side with respect to the pixel array, the timing signal generation unit is provided on the second side with respect to the pixel array, The plurality of transfer units are respectively arranged through the pixel array from the first side to the second side, a control line for transferring the timing signal generated by the timing signal generating unit to the time code generating unit is provided in each of two or more of the plurality of transfer units; electronic equipment.

Images