Circuit information integrity verification system and circuit information integrity verification method

Abstract

A CPU (100) of a circuit information integrity verification system (1) has, in an enclave (130), both a signature verification unit (132) that verifies the signature of circuit information (11) signed by a development PC (10) and sent to the CPU (100), and a signature replacement unit (135) that replaces the signature verified by the signature verification unit (132) using a key of the CPU (100) before sending the circuit information 11 to the FPGA (200) side. When an input value (12) is sent from the CPU (100) to the FPGA (200), the FPGA (200) performs a calculation on the basis of the input value (12) to produce an output value, adds, to the output value, hash values of the input value (12) and the circuit information (11) and a signature, and sends the resulting value to the CPU (100).

Description

[Technical field]

[0001] The present invention relates to a system and method for verifying the integrity of circuit information between a CPU and an accelerator. [Background technology]

[0002] There are an increasing number of cases where part of the processing of a software application (hereafter referred to as APL) is offloaded to accelerators such as GPUs (Graphics Processing Units) and FPGAs (Field Programmable Gate Arrays) to achieve performance and power efficiency that cannot be achieved by software (CPU processing) alone. It is anticipated that accelerators like those described above will be applied to large-scale server clusters, such as data centers that make up NFV (Network Functions Virtualization) and SDN (Software Defined Network).

[0003] As a technology for ensuring integrity, a protected area (enclave) is set up in the CPU-side memory and important information is stored in this protected area (enclave), which can prevent attacks that compromise the OS / drivers / BIOS / VMM. In addition, APL can move from trusting the OS and VMM to trusting only the protected area of ​​the hardware, which is a more limited area, thereby reducing the burden on APL.

[0004] One possible threat when exchanging circuit information for customization in the FPGA (in the case of a GPU, the circuit information is algorithm information) and information about the calculation process between the CPU-side protected area (enclave) and the GPU or FPGA device that performs processing is tampering. Examples of information that may be tampered with include circuit information for performing calculations on an FPGA, values sent from the CPU to the FPGA for calculation, and values sent from the FPGA to the CPU. Regarding the information that may be tampered with, it is necessary to confirm and detect that it has not been tampered with.

[0005] The conventional communication between an Enclave-GPU and an FPGA will be described (see Non-Patent Document 1). <Communication System between Enclave and FPGA> FIG. 26 is a schematic configuration diagram of a communication system between an Enclave and an FPGA. The FPGA is taken as an example of the accelerator. As shown in FIG. 26, the communication system between an Enclave and an FPGA includes a development PC 10, an input value generator 20, a CPU 30, and an FPGA 40 which is an accelerator that executes offloaded calculations. The development PC (Personal Computer) 10 is operated by the function manager 2, and uses PC resources to create circuit information 11 that is set in advance for offloading calculations on the FPGA. The input value generator 20 generates input values 12 required for offloading.

[0006] The CPU 30 includes an off-Enclave memory 31, a protected area (enclave) 32, and an FPGA transfer function program 33. The FPGA transfer function program 33 is a function program executed by the CPU 30. In the following description, the notation in which the FPGA transfer function program 33 is mainly described is a convenient description of the function in which the CPU 30 executes the FPGA transfer function program 33.

[0007] In FIG. 26, circuit information 11 is input from the development PC 10 to the off-Enclave memory 31 (see S1), and input values 12 (input values required for offloading) are input from the input value generator 20 (see S2). Also, the off-Enclave memory 31 stores the input circuit information 11.

[0008] The protected area (enclave) 32 has a management and verification program 34 for preventing tampering. In Fig. 23, the protected area (enclave) 32 stores circuit information 11 and input values ​​12.

[0009] The FPGA transfer function program 33 inputs information in the enclave external memory 31 (see S3) and transfers it to the protected area (enclave) 32 (see S4). Here, the FPGA transfer function program 33 transfers the circuit information 11 and the input value 12 to the protected area (enclave) 32. The FPGA transfer function program 33 reads out information (here, the input value 12) from the protected area (enclave) 32 (see S5).

[0010] The FPGA transfer function program 33 transmits important information (here, circuit information 11, input value 12) stored in the protected area (enclave) 32 on the CPU 30 side to the FPGA 40 (see S6, S7), and receives the calculation result (output value 13, which is the result of offloading the calculation and outputting) using the arithmetic circuit 41 from the FPGA 40 (see S8).

[0011] The CPU 30 transmits circuit information 11 to the FPGA 40 to cause the FPGA 40 to form an arithmetic circuit 41, and offloads part of the APL processing to the FPGA 40. The FPGA 40 performs calculations using the arithmetic circuit 41 for the offloaded APL processing, and transfers the calculation results to the CPU 30.

[0012] The FPGA 40 includes a calculation circuit 41 and a RAM 42. The calculation circuit 41 calculates the offloaded APL processing (see S8), and outputs an output value 13, which is the calculation result, to the RAM 42. The RAM 42 temporarily stores information (circuit information 11, input values ​​12) from the CPU 30 transferred by the FPGA transfer function program 33, and also temporarily stores the calculation results (output values ​​13) using the arithmetic circuit 41 to be transferred to the CPU 30.

[0013] <Possibility of tampering> A possible threat when exchanging circuit information 11 or information related to the calculation process (for example, input value 12) between the protected area (enclave) 32 on the CPU 30 side and the FPGA 40 that performs the processing is tampering (see symbols a and b in Figure 26). Possible information that may be subject to tampering includes circuit information 11 for performing calculations in FPGA 40, tampering with values ​​(circuit information 11, input values ​​12) sent from the CPU to the FPGA for calculations (see symbols c and d in Figure 26), and tampering with values ​​(output values ​​13) sent from the FPGA to the CPU (see symbol e in Figure 26). It is necessary to be able to confirm and detect that information that may be subject to tampering has not been tampered with.

[0014] <Enclave-FPGA communication system that addresses the possibility of tampering> The following are prerequisites for building an Enclave-FPGA communication system that addresses the possibility of tampering: The FPGA 40 is capable of verifying the reliability of the circuit information 11 and input values ​​12 transferred from the protected area (enclave) 32 on the CPU 30 side. The CPU 30 is able to check the reliability of the output value 13 transferred from the FPGA 40. As shown by symbols ad in FIG. 26, it is assumed that the circuit information 11, the input value 12, and the output value 13 are tampered with in each communication path. The function user 2 trusts the protected area (enclave) 32 in the CPU 30.

[0015] Fig. 27 is a schematic diagram of a communication system between Enclave and FPGA that deals with the possibility of tampering. The same components as those in Fig. 26 are given the same reference numerals. Fig. 28 is a diagram explaining a signature given by a signature giver 50 to circuit information 11 using a private key (signature giver) 51. As shown in FIG. 27, the Enclave-FPGA communication system that addresses the possibility of tampering further includes a signature provider 50 (signature provider) in addition to the Enclave-FPGA communication system of FIG. The signature assigner 50 is an input terminal device used by a person who assigns a signature to the circuit information 11 . The signature grantor 50 has a private key (signature grantor) 51 , a public key (signature grantor) 52 , and a signature (signature grantor) 53 . 28, the signature granter 50 generates a signature for the circuit information 11 by using a private key (signature granter) 51. The signature granter 50 grants the private key (signature granter) 51, a public key (signature granter) 52, and a signature (signature granter) 53 to the development PC 10 (see S11).

[0016] The development PC 10 shown in FIG. 27 sends the circuit information 11 to which the public key (signature giver) 52 and the signature (signature giver) 53 have been given to the Enclave external memory 31 of the CPU 30 (see S1).

[0017] The FPGA transfer function program 33 of the CPU 30 shown in FIG. 27 transfers the circuit information 11 and input value 12 to which the public key (signature granter) 52 and signature (signature granter) 53 have been granted, to the protected area (enclave) 32 (see S1).

[0018] The FPGA transfer function program 33 transmits important information (here, circuit information 11 and input value 12 to which a public key (signature granter) 52 and a signature (signature granter) 53 have been assigned) stored in the protected area (enclave) 32 on the CPU 30 side to the FPGA 40 (see S6 and S7), and receives the calculation result (here, output value 13) using the arithmetic circuit 41 from the FPGA 40 (see S8).

[0019] The RAM 42 temporarily stores information (circuit information 11 with a public key (signature giver) 52 and a signature (signature giver) 53, and input value 12) from the CPU 30 transferred by the FPGA transfer function program 33, and also temporarily stores the calculation result (output value 13) using the arithmetic circuit 41 to be transferred to the CPU 30. [Prior art documents] [Non-patent literature]

[0020] [Non-Patent Document 1] Elrabaa, MES et al. “Secure Computing Enclaves Using FPGAs.” IEEE Transactions on Dependable and Secure Computing 18 (2021): 593-604. Summary of the Invention [Problem to be solved by the invention]

[0021] In the prior art, as shown in Fig. 26, the CPU 30 has a protected area (enclave) 32 for preventing tampering. However, when circuit information 11 or information related to a calculation process is exchanged between the protected area on the CPU 30 side and the FPGA 40 that performs processing, there is a possibility that the information may be tampered with during the exchange (see symbol ae in Fig. 26). In this case, there is a problem in that it is not possible to confirm or detect that the information has not been tampered with.

[0022] 27, when signature verification is performed using a public key or the like, there is a problem that the processing load on the FPGA 40 side becomes large. Signature verification (tracing whether the public key is correct) is performed by the FPGA 40 (see FIG. 27), which places a burden on the FPGA 40. Also, complex processing (signature verification, management of multiple public keys, etc.) is difficult for the FPGA 40 to perform. Furthermore, as shown by symbol g in FIG. 27, signature verification is a process that places a burden on the FPGA, and there is an issue that the burden increases further when the verification of the input value 12 used in the calculation is also taken into consideration. It takes time for the FPGA to output the result. Although it is conceivable that the FPGA 40 verifies the signature regarding the circuit information 11, the processing load increases when multiple input values ​​are taken into consideration.

[0023] The present invention has been made in view of the above background, and an object of the present invention is to enable confirmation of the integrity of circuit information, etc., that it has not been tampered with, and to enable reduction in the processing load of the FPGA. [Means for solving the problem]

[0024] In order to solve the above-mentioned problems, the present invention provides a circuit information integrity verification system that verifies the integrity of circuit information between the CPU and the accelerator, the system having a CPU and an accelerator that executes specific processing of an application offloaded from the CPU, the CPU having a protected area to prevent tampering, the protected area including a signature verification unit that verifies a signature of the circuit information signed on a development PC and sent to the CPU, and a signature replacement unit that replaces the signature verified by the signature verification unit with a key of the CPU before sending the circuit information to the accelerator, and when an input value is sent from the CPU, the accelerator performs a calculation based on the input value, and adds a hash value of the input value and the circuit information and a signature to the output value and sends the output value to the CPU. Effect of the Invention

[0025] According to the present invention, it is possible to confirm the integrity of circuit information and the like, that it has not been tampered with, and also to reduce the processing load on the FPGA. [Brief description of the drawings]

[0026] [Figure 1] 1 is a diagram illustrating an example of a configuration of a circuit information integrity verification system according to an embodiment of the present invention. [Diagram 2] FIG. 11 is an explanatory diagram of an operation of <writing circuit information (CPU side)> of the circuit information integrity verification system according to the embodiment of the present invention. [Diagram 3] 1 is a diagram for explaining signature verification of circuit information by a signature verification unit of a CPU of the circuit information integrity verification system according to an embodiment of the present invention; [Figure 4]FIG. 3 is a control sequence diagram of <writing circuit information (CPU side)> of the circuit information integrity verification system of FIG. 2. [Diagram 5] FIG. 11 is an explanatory diagram of the operation of <writing circuit information into FPGA> of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 6] 10A and 10B are diagrams illustrating generation of a hash value by a CPU of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 7] 10 is a diagram for explaining a signature of the circuit information by a private key (CPU) of a signature generating unit of a CPU of the circuit information integrity verification system according to the embodiment of the present invention. FIG. [Figure 8] FIG. 2 is a diagram for explaining signature verification of an FPGA in the circuit information integrity verification system according to the embodiment of the present invention. [Figure 9] 1 is a diagram for explaining generation of a hash value of an FPGA in the circuit information integrity verification system according to an embodiment of the present invention; [Figure 10] FIG. 7 is a control sequence diagram of <writing circuit information to FPGA> in the circuit information integrity verification system of FIG. 5. [Figure 11] 10A and 10B are diagrams for explaining a signature of a random number by a private key (FPGA) of an FPGA of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 12] FIG. 11 is an explanatory diagram of the operation of the circuit information integrity verification system according to the embodiment of the present invention <start-up after writing>. [Figure 13] FIG. 11 is an explanatory diagram of the operation of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 14] 1 is a diagram for explaining a signature of an input value by a private key (input value source) of an input value source of the circuit information integrity verification system according to an embodiment of the present invention. FIG. [Figure 15] FIG. 2 is a diagram for explaining signature verification of an FPGA in the circuit information integrity verification system according to the embodiment of the present invention. [Figure 16] FIG. 11 is a control sequence diagram of <Start-up after writing-output of calculation result using circuit> of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 17] 1 is a diagram for explaining a signature of an input value by a private key (input value source) of an input value source of the circuit information integrity verification system according to an embodiment of the present invention. FIG. [Figure 18] 10A and 10B are diagrams for explaining a signature of a random number by a private key (FPGA) of an FPGA of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 19] FIG. 11 is an explanatory diagram of an operation of <output result transmission> of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 20] FIG. 2 is a diagram for explaining key pair generation of a public key (FPGA) and a private key (FPGA) of an FPGA in the circuit information integrity verification system according to the embodiment of the present invention. [Figure 21] 1 is a diagram for explaining generation of a hash value of an FPGA in the circuit information integrity verification system according to an embodiment of the present invention; [Figure 22] 3A to 3C are diagrams illustrating an input value, a hash value of circuit information, and a signature of an output value of an FPGA in the circuit information integrity verification system according to the embodiment of the present invention. [Diagram 23] 1 is an explanatory diagram of circuit information and hash value verification of an input value in the circuit information integrity verification system according to an embodiment of the present invention; [Figure 24] FIG. 11 is a control sequence diagram of <output result transmission> of the circuit information integrity verification system according to the embodiment of the present invention. [Diagram 25] FIG. 13 is a diagram for explaining signature verification of a signature (FPGA) added to an output value using a public key (FPGA) of a CPU of the circuit information integrity verification system according to the embodiment of the present invention. [Figure 26] FIG. 1 is a schematic diagram of a conventional Enclave-FPGA communication system. [Figure 27] FIG. 1 is a schematic diagram of a conventional communication system between an Enclave and an FPGA that addresses the possibility of tampering. [Figure 28] 28 is a diagram for explaining a signature for circuit information using a private key of a signature granter (signature granter) in the communication system between the Enclave and FPGA in FIG. 27. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, a network system and the like in an embodiment for carrying out the present invention (hereinafter, referred to as "the present embodiment") will be described with reference to the drawings. (Embodiment) In this embodiment, an FPGA is used as an example of an accelerator, and a CPU is used as an example of a general-purpose server. [Configuration of circuit information integrity verification system 1] 1 is a diagram showing an example of the configuration of a system 1 for verifying the integrity of circuit information between a CPU and an accelerator according to an embodiment of the present invention. The same components as those in FIGS. 26 and 27 are given the same reference numerals.

[0028] 1 includes a CPU 100, an FPGA 200 (accelerator), and an input value source 300. A development PC 10 is connected to the CPU 100, and a signature granter 50 is connected to the development PC 10.

[0029] <Development PC 10> The development PC 10 creates circuit information 11 that is set in advance to offload calculations to the FPGA, and sends it to the signature granter 50 (not shown). In <Writing circuit information (CPU side)>, the development PC 10 sends the circuit information 11, public key (signature granter) 52, and signature (signature granter) 53 to the CPU 100.

[0030] <Signer 50> The signature assigner 50 assigns a signature to the circuit information 11 created by and sent from the development PC 10, and sends it to the development PC 10 (see S11). The signature assigner 50 generates a signature for the circuit information 11 using a private key (signature assigner) 51. The signature assigner 50 assigns the private key (signature assigner) 51, a public key (signature assigner) 52, and a signature (signature assigner) 53 to the development PC 10.

[0031] <cpu100> The CPU 100 includes an external enclave memory 110, an FPGA transfer function program 120, and a protected area (enclave) 130 for preventing tampering. The Enclave external memory 110 is a normal area in which normal applications etc. run. The CPU 100 uses the Enclave external memory 110 to execute application programs. The FPGA transfer function program 120 is a program for transferring data between the CPU and the accelerator (CPU 100-FPGA 200). The FPGA transfer function program 120 may be called an FPGA transfer function unit or an FPGA transfer management unit.

[0032] In <Writing Circuit Information (CPU Side)>, the CPU 100 receives the circuit information 11, the public key (signature giver) 52, and the signature (signature giver) 53 sent from the development PC 10, and performs signature verification of the circuit information 11 sent from the development PC 10. The signature verification is performed using the public key (signature giver) 52.

[0033] In <Writing circuit information to FPGA>, the CPU 100 checks the signature of the information sent to the FPGA 200 and replaces the signature.

[0034] The CPU 100 receives the input value, the hash value of the circuit information, and the output value with a signature sent from the FPGA 200, and verifies the hash value and the signature. At this time, the CPU 100 confirms (attestes) that the FPGA 200 is trustworthy based on the certificate and signature of the FPGA 200.

[0035] <Protected area 130> The protected area (enclave) 130 is a protected area on the hardware to prevent attacks that could compromise the OS / drivers / Basic Input / Output System (BIOS) / Virtual Machine Manager (VMM). The protected area (enclave) 130 is provided on the CPU 100 side. The protected area (enclave) 130 is a secure area that confines the public key, private key, circuit information 11, etc. within the CPU 100. By providing the protected area (enclave) 130, an application can move from trusting the OS and VMM to trusting only the protected area of ​​the hardware.

[0036] Here, the protected area (enclave) 130 is an execution environment isolated from general application programs, and data and computation are protected. It is executed in the privileged mode of the CPU or OS (Operating System), and only specific programs or specific procedures can call programs in the protected area (enclave) 130 or access data.

[0037] The protected area (enclave) 130 stores a signature receiving unit 131, a signature verifying unit 132, a key pair generating unit 133, a signature generating unit 134, a signature replacing unit 135, and a signature delivering unit 136.

[0038] The signature receiving unit 131 receives the circuit information 11, the public key (signature granter) 52, and the signature (signature granter) 53 transmitted from the development PC 10.

[0039] The signature verification unit 132 verifies the signature of the signature (signature granter) 53 received by the signature reception unit 131 . The signature verification unit 132 verifies the signature of the circuit information 11 that has been signed by the development PC 10 and sent to the CPU 100 .

[0040] Moreover, the signature verification unit 132 verifies the signature of the input value 12 that was signed by the source of the input value 12 and sent to the CPU 100 .

[0041] Furthermore, the signature verification unit 132 performs signature verification by comparing the hash value (CPU) 152 of the circuit information 11 with the hash value calculated by the signature assigner 50 (calculated from the received signature (CPU) 403 and public key (CPU) 401).

[0042] Furthermore, the signature verification unit 132 verifies the hash value and the signature sent from the FPGA 200 .

[0043] Furthermore, the signature verification unit 132 calculates a hash value (bit string) using a hash function algorithm such as MD5 (message digest algorithm 5) or SHA (Secure Hash Algorithm). This hash algorithm needs to be the same for both the CPU 100 and the FPGA 200.

[0044] The key pair generating unit 133 generates a key pair based on a public key (CPU) 401 and a private key (CPU) 402 .

[0045] The signature generating unit 134 calculates a hash value (CPU) 152 of the circuit information 11, and then generates a signature (signature (CPU) 403) using the hash value (CPU) 152 and a private key (CPU) 402.

[0046] The signature replacement unit 135 assigns the signature (CPU) 403 and the public key (CPU) 401 generated by the signature generation unit 134 to the circuit information 11. That is, the signature replacement unit 135 checks the signature of the information sent to the FPGA 200 side, and replaces the signature with the key of the CPU.

[0047] Before sending the circuit information 11 to the FPGA 200 side, the signature replacement unit 135 replaces the signature verified by the signature verification unit 132 with the key of the CPU 100 .

[0048] Furthermore, before sending the input value 12 to the FPGA 200 side, the signature replacement unit 135 replaces the signature verified by the signature verification unit 132 with the key of the CPU 100 .

[0049] The signature delivery unit 136 delivers the circuit information 11, the CPU's public key (CPU) 401, and the CPU's signature (CPU) 403 to the FPGA 200. Based on this, the FPGA 200 verifies the signature and generates a hash value.

[0050] <fpga200> The FPGA 200 is an accelerator provided on an accelerator board (not shown). In this embodiment, an FPGA is used as an example of an accelerator, but an accelerator such as a GPU may also be used. When the FPGA 200 receives the input value 12 from the CPU 100, the FPGA 200 executes a calculation based on the input value 12, and sends the output value to the CPU 100 after adding a hash value of the input value 12 and the circuit information 11 and a signature.

[0051] The FPGA 200 generates a key pair. The FPGA 200 generates a hash value of the input value. In addition, the FPGA 200 pre-registers the public key of the public key and private key generated by the CPU 100, and verifies the signature of the circuit information 11 signed by the CPU 100 and sent to the FPGA 200 using the registered public key.

[0052] The FPGA 200 sends the input value, the hash value of the circuit information, and the output value with a signature to the CPU 100. In Fig. 1, the FPGA 200 adds a hash value (circuit information) 232, a hash value (input value) 231, and a signature (FPGA) 233 to the output result (output value 13) and sends it to the CPU 100. The CPU 100 verifies the hash value and signature received from the FPGA 200.

[0053] <Input value source 300> The input value source 300 sends a public key (input value source) 301, a private key (input value source) 301, and a signature (input value source) 303 to the Enclave external memory 110 of the CPU 100 (see S22).

[0054] Hereinafter, a method for verifying the integrity of circuit information by the circuit information integrity verification system 1 configured as described above will be described. The gist of the present invention is that the circuit information 11 developed by the development PC 10 is not sent to the FPGA 200 as is, but is verified by the CPU 100 before being sent to the FPGA 200. The circuit information 11, the circuit information 11, the public key (signature granter) 52, and the signature (signature granter) 53 are stored in a protected area (enclave) 130 and verified on the CPU 100 side. After the verification, the input value 12 and the output value 13 are verified using only the public key of the key pair of the CPU 100. The signature and public key are not the original signature (signature granter) 53 and public key (public key (signature granter) 52), but are changed by the CPU 100 to the signature (CPU) 403 and public key (public key (CPU) 401) of the CPU 100 and sent to the FPGA 200. When the FPGA 200 receives an input value 12 from the CPU 100, it performs a calculation based on the input value 12, and sends the output value 13 to the CPU 100, adding a hash value of the input value 12 and the circuit information 11 and a signature (signature (FPGA) 233). By verifying this, the CPU 100 can determine that it is authentic and has not been tampered with.

[0055] The circuit information integrity verification system 1 shown in Figure 1 will be divided into stages of <writing circuit information (CPU side)>, <writing circuit information to FPGA>, <writing circuit information (FPGA side)>, <start-up after writing>, <output of calculation results using circuit>, <start-up after writing-output of calculation results using circuit> and <sending output results>, and will be explained with reference to operation diagrams and control sequence diagrams of the devices used at each stage.

[0056] In the following control sequence diagrams, for convenience of explanation, the processes between the CPU 100 and the FPGA 200 are summarized in one flow. Therefore, the processes in the CPU 100 and the FPGA 200 are performed asynchronously. The processes between the CPU 100 and the FPGA 200 are performed after notifications and permission from each of them.

[0057] <Writing circuit information (CPU side)> The writing of circuit information (CPU side) will be explained. 2 is a diagram for explaining the operation of <writing of circuit information (CPU side)> in the system 1 for verifying the integrity of circuit information between the CPU and FPGA 200. FIG. 3 is a diagram for explaining signature verification of the circuit information 11 by the signature verification unit 132 of the CPU 100.

[0058] 2, in the <Write Circuit Information (CPU Side)> operation, the development PC 10 creates circuit information 11 and sends it to a signature granter 50. The signature granter 50 generates a signature for the circuit information 11 using a private key (signature granter) 51, as shown by symbol g in Fig. 27. The signature granter 50 grants the private key (signature granter) 51, public key (signature granter) 52, and signature (signature granter) 53 to the development PC 10 (see S11).

[0059] A signature assigner 50 guaranteed by a trusted third party (CA: Certificate Authority, public key certificate authority or certification authority) signs the circuit information 11, and by assigning that signature to the circuit information 11, the destination CPU 30 can verify that the circuit information 11 has not been tampered with.

[0060] The development PC 10 sends the circuit information 11 to which the public key (signature giver) 52 and the signature (signature giver) 53 have been given to the Enclave external memory 110 of the CPU 100 (see S21).

[0061] The FPGA transfer function program 120 of the CPU 100 sends the circuit information 11 to which the public key (signature grantor) 52 and the signature (signature grantor) 53, which are temporarily stored in the memory outside the Enclave 110, to the signature verification unit 132 of the CPU 100 (see S27 and S28). The signature verification unit 132, as indicated by the symbol h in FIG. 3, uses the signature (signature granter) 53 to verify the signature of the circuit information 11 encrypted with the public key (signature granter) 52.

[0062] FIG. 4 is a control sequence diagram of <Writing of Circuit Information (CPU Side)> in the integrity verification system 1 for circuit information between the CPU and accelerator in FIG. The development PC 10 inputs the original data of the circuit information 11 and creates the circuit information 11 (see S101). The development PC 10 sends the created circuit information 11 to the signature provider 50 (see S102).

[0063] On the other hand, the signature granter 50 inputs a private key (signature granter) 51 and a public key (signature granter) 52 (see S103). The signature assigner 50 generates a signature by assigning a signature (signature assigner) to the circuit information 11 sent from the development PC 10 using a private key (signature assigner) 51 (see S104). The signature granter 50 sends the public key (signature granter) 52 used to generate the signature and the signature (signature granter) 53 to the developer PC 10 (see S105).

[0064] The development PC 10 compiles the created circuit information 11, the public key (signature grantor) 52 and the signature (signature grantor) 53 generated by the signature grantor 50 (see S106). The development PC 10 sends this circuit information 11, the public key (signature grantor) 52 and the signature (signature grantor) 53 to the CPU 100 (sends the circuit information and signature) (see S107).

[0065] The CPU 100 performs signature verification of the circuit information 11 (see S108) by the signature verification unit 132 (see FIG. 2) arranged in the protected area (enclave) 130. That is, the signature verification unit 132 performs signature verification of the circuit information 11 encrypted with the public key (signature granter) 52 by using the signature (signature granter) 53, as shown by the symbol h in FIG. The above is a description of <Writing Circuit Information (CPU Side)>.

[0066] <Writing circuit information to FPGA> This section explains how to write circuit information to FPGA. Fig. 5 is a diagram for explaining the operation of <writing circuit information to FPGA> of the circuit information integrity verification system 1. Fig. 6 is a diagram for explaining hash value generation by the CPU 100. Fig. 7 is a diagram for explaining the signature of the circuit information 11 by the private key (CPU) 402 of the signature generation unit 134 of the CPU 100. Fig. 8 is a diagram for explaining signature verification by the FPGA 200. Fig. 9 is a diagram for explaining hash value generation by the FPGA 200.

[0067] As shown in Fig. 5, in the <Write circuit information to FPGA> operation, the signature verification unit 132 of the CPU 100 verifies the signature of the signature granter 50 in the signature reception unit 131. Specifically, it is as follows. As shown in Fig. 6, the signature verification unit 132 inputs the circuit information 11, the public key (CPU) 401, and the signature (CPU) 402, and generates a hash value (circuit information) 152 using a hash function (CPU) 151. The signature verification unit 132 performs signature verification by comparing the hash value (circuit information) 152 of the circuit information 11 with the hash value calculated by the signer (calculated from the received signature (signature granter) 53 and the public key (signature granter) 52).

[0068] The key pair generation unit 133 of the CPU 100 generates a key pair of a public key (CPU) 401 and a private key (CPU) 402 . The signature generation unit 134 of the CPU 100 signs the circuit information 11 (see FIG. 7). As indicated by the symbol i in FIG. 7, after the signature verification unit 132 calculates the hash value of the circuit information 11, the signature generation unit 134 performs a calculation using the hash value and a private key (CPU) 402 to sign (CPU) the circuit information 11.

[0069] The signature replacement unit 135 of the CPU 100 assigns the signature (CPU) 402 and the public key (CPU) 401 generated by the signature generation unit 134 to the circuit information 11. That is, the signature replacement unit 135 checks the signature of the information to be sent to the FPGA 200 side, and replaces the signature with the key of the CPU 100. In FIG. 5, the signature (signature grantor) 53 of the signature grantor 50 verified and confirmed in <Writing circuit information (CPU side)> shown in FIGS. 2 to 4 is replaced (re-signed) with the key of the CPU 100 (public key (CPU) 401) to become signature (CPU) 403.

[0070] The CPU 100 confirms (attests) between itself and the FPGA 200 that the FPGA 200 is trustworthy based on the certificate and signature of the FPGA 200.

[0071] The signature delivery unit 136 of the CPU 100 delivers the circuit information 11, the public key (CPU) 401 of the CPU 100, and the signature (CPU) 403 of the CPU 100 to the FPGA 200 (see S31).

[0072] In the FPGA 200, the signature and hash function unit 211 of the arithmetic circuit 210 verifies the signature and generates a hash value. More specifically, the process is as follows. First, of the public key (CPU) 401 and private key (CPU) 402 generated by the CPU 100, the public key (CPU) 401 is registered in advance in the RAM 220 of the FPGA 200. As shown in FIG. 8, the signature and hash function unit 211 performs signature verification by comparing the hash value (circuit information) 152 of the circuit information 11 with the hash value calculated by the CPU 100 (calculated from the received signature (CPU) 403 and public key (CPU) 401). As shown in FIG. 9, the signature and hash function unit 211 receives the circuit information 11, a public key (CPU) 401, and a signature (CPU) 403, and generates a hash value (circuit information) 162 using a hash function (FPGA calculation) 161.

[0073] As described above, the hash function (FPGA calculation) 161 calculates a hash value (bit string) by using a hash function algorithm such as MD5, SHA, etc. The same hash algorithm is used by both the CPU 100 and the FPGA 200.

[0074] Fig. 10 is a control sequence diagram of <writing circuit information to FPGA> of the integrity verification system 1 of the circuit information between the CPU and FPGA 200 in Fig. 5. Fig. 11 is a diagram for explaining the signature of the random number 501 by the private key (FPGA) 223 of the FPGA 200. The CPU 100 receives the circuit information 11, the public key (signature grantor) 52, and the signature (signature grantor) 53 sent from the development PC 10 (see FIG. 2) at a signature receiving unit 131 (see FIG. 5) arranged in the protected area (enclave) 130 (see S201).

[0075] The key pair generating unit 133 of the CPU 100 (see FIG. 5) generates a key pair of a public key (CPU) 401 and a private key (CPU) 402 (see S202). As indicated by symbol i in FIG. 7, after the signature verification unit 132 (see FIG. 5) calculates the hash value of the circuit information 11, the signature generation unit 134 (see FIG. 5) of the CPU 100 signs the circuit information 11 by performing a calculation using the hash value and the private key (CPU) 402 (see S203).

[0076] The signature replacement unit 135 of the CPU 100 (see FIG. 5) replaces the signature (CPU) 402 with the public key (CPU) 401 of the CPU 100 by adding the signature (CPU) 402 and public key (CPU) 401 generated by the signature generation unit 134 to the circuit information 11.

[0077] Meanwhile, the FPGA 200 generates a key pair of a public key (FPGA) 222 and a private key (FPGA) 223 (see S204).

[0078] <attestation> As indicated by the dashed-line box k in FIG. 10, the CPU 100 performs attestation between the counterpart FPGA 200 and the FPGA 200 that the FPGA is trustworthy, based on the certificate and signature of the FPGA 200. First, the CPU 100 sends a random number 501 to the FPGA 200 (see S205). As indicated by reference character l in FIG. 11, the FPGA 200 performs calculations using the random number 501 sent from the CPU 100 and the private key (FPGA) 223 to sign the random number 501 and generate a signature (FPGA) 502 (see S206).

[0079] The FPGA 200 sends the signature (FPGA) 502 and the public key (FPGA) 222 to the CPU 100 (see S207).

[0080] The CPU 100 confirms that the FPGA is trustworthy by verifying the public key (FPGA) 222 and the signature (FPGA) 502 (see S208). Up to this point, the attestation is completed.

[0081] The CPU 100 sends the circuit information 11, the public key (CPU) 401 of the CPU 100, and the signature (CPU) 402 of the CPU 100 to the FPGA 200 that has been confirmed to be a trustworthy FPGA (see S209).

[0082] 8, the FPGA 200 performs signature verification by comparing the hash value (circuit information) 152 of the circuit information 11 with the hash value calculated by the CPU 100 (calculated from the received signature (CPU) 402 and public key (CPU) 401) (see S210). As shown in Fig. 9, the FPGA 200 receives the circuit information 11, the public key (CPU) 401, and the signature (CPU) 403, and generates the hash value (circuit information) 162 using the hash function (FPGA operation) 161 (see S211).

[0083] In the arithmetic circuit 210 of the FPGA 200, the signature and hash function unit 211 verifies the signature and generates a hash value. More specifically, this is as follows. First, of the public key (CPU) 401 and private key (CPU) 402 generated by the CPU 100, the public key (CPU) 401 is registered in advance in the RAM 220 of the FPGA 200. The signature and hash function unit 211 receives the circuit information 11, the public key (CPU) 401, and the signature (CPU) 403, and generates a hash value (circuit information) 162 using a hash function (FPGA calculation) 161. The signature and hash function unit 211 compares the hash value (circuit information) 162 of the circuit information 11 with a hash value calculated by the CPU 100 (calculated from the received signature (CPU) 402 and public key (CPU) 401) to perform signature verification. The above describes <Writing circuit information into FPGA>.

[0084] <Start after writing> The start-up after writing will be described. FIG. 12 is a diagram for explaining the operation of the <start-up after writing> of the system 1 for verifying the integrity of circuit information between the CPU and accelerator. When the FPGA 200 uses an external memory for storage, a start-up procedure after writing shown in FIG. 12 is added. The FPGA transfer function program 120 of the CPU 100 reads out the circuit information 11 from the signature replacement unit 135 arranged in the protected area (enclave) 130, and sends it to the FPGA 200 (see S41). The FPGA 200 has a circuit set based on the circuit information 11 sent from the CPU 100 when the power is turned on.

[0085] <Output of calculation results using a circuit> The output of the calculation result using the circuit will be explained. Fig. 13 is a diagram for explaining the operation of <output of calculation result using a circuit> of the integrity verification system 1 for circuit information between the CPU and FPGA 200. Fig. 14 is a diagram for explaining the signature of the input value 12 by the private key (input value source) 302 of the input value source 300. Fig. 15 is a diagram for explaining the signature verification of the FPGA 200.

[0086] 13, input value source 300 has input value 12, public key (input value source) 301, private key (input value source) 301, and signature (input value source) 303. The existence of a trusted third party such as input value source 300 can significantly reduce the confirmation process of whether the public key is trustworthy. In other words, when no third party exists, in addition to entities confirming whether they can trust each other, it is necessary to exchange public keys. When a third party exists, each entity only needs to confirm the public key of the trusted third party.

[0087] In the operation of <writing circuit information into FPGA>, the input value source 300 signs the input value 12 using the private key (input value source) 302, as indicated by the symbol m in FIG.

[0088] The input value source 300 sends the input value 12, the public key (input value source) 301, and the signature (input value source) 303 to the Enclave external memory 110 of the CPU 100 (see S51).

[0089] The signature receiving unit 131 of the CPU 100 receives the input value 12 , the public key (input value source) 301 , and the signature (input value source) 303 sent from the input value source 300 .

[0090] The signature verification unit 132 of the CPU 100 performs signature verification of the input value 12. That is, the signature verification unit 132 performs signature verification of the input value 12 encrypted with the public key (input value source) 52 using the signature (input value source) 303.

[0091] As indicated by symbol m in FIG. 14, the signature generation unit 134 of the CPU 100 signs the input value 12 sent from the input value source 300 using the private key (input value source) 302 to generate a signature (CPU) 403.

[0092] The signature replacement unit 135 of the CPU 100 signs the input value 12 with the key of the CPU 100. That is, the signature replacement unit 135 replaces the signature of the input value 12 in the same manner as the circuit information 11 shown in FIG.

[0093] The signature sending unit 136 of the CPU 100 uses the FPGA transfer function program 120 to send the input value 12, whose signature has been replaced by the signature replacing unit 135, and the signature (CPU) 403 to the FPGA 200 (see S52).

[0094] In the arithmetic circuit 210 of the FPGA 200, the signature verification is performed by the signature and hash function unit 211. More specifically, the process is as follows. As indicated by the symbol n in FIG. 15, the signature and hash function unit 211 performs signature verification by comparing the hash value calculated by the CPU 100 (calculated from the received signature (CPU) 403 and public key (CPU) 401).

[0095] The calculation circuit 210 of the FPGA 200 is set based on the circuit information 11 sent from the CPU 100, and uses this circuit to calculate an output value 13 based on an input value 12. The calculation result using the circuit is temporarily stored in the RAM 220 together with the output value 13, the hash value (circuit information) 232, and the public key (CPU) 401 of the CPU 100. The above is a description of <output of calculation results using a circuit>.

[0096] <Starting after writing - Outputting the calculation results using the circuit> The output of the calculation result using the startup circuit after writing will now be explained. Fig. 16 is a control sequence diagram of <Start after writing-output of calculation result using circuit> of the integrity verification system 1 for circuit information between the CPU and FPGA 200. Fig. 17 is a diagram for explaining the signature of the input value 12 by the private key (input value source) 302 of the input value source 300. Fig. 18 is a diagram for explaining the signature of the random number 501 by the private key (FPGA) 223 of the FPGA 200.

[0097] In the operation <Startup after writing--output of calculation result using circuit>, input value source 300 outputs public key (input value source) 301 and private key (input value source) 302 (see S301).

[0098] The input value source 300 signs the input value 12 using the signature (input value source) 302 (see S302). The input value source 300 generates a signature for the input value 12 (see S303).

[0099] The input value source 300 sends the input value 12, the public key (input value source) 301, and the signature (input value source) 303 to the CPU 100 (see S304).

[0100] Meanwhile, the CPU 100 receives the circuit information 11, public key (signature grantor) 52, signature (signature grantor) 53, public key (CPU) 401, private key (CPU) 402, and signature (CPU) 403 sent from the development PC 10 (see FIG. 2) at the signature receiving unit 131 (see FIG. 5) arranged in the protected area (enclave) 130 (see S305).

[0101] When the power is turned on (see S306), the CPU 100 sends the circuit information 11 to the FPGA 200 (see S307).

[0102] As indicated by the symbol o in FIG. 17, the CPU 100 performs signature verification of the public key (input value source) 301 using the signature (input value source) 303 (see S308).

[0103] As indicated by the symbol p in FIG. 18, the CPU 100 signs the input value 12 using the private key (CPU) 402 (see S309).

[0104] The CPU 100 re-signs (replaces) the input value 12 using the signature (CPU) 403 (see S310).

[0105] This section explains re-signing in the protected area. Re-signatures in the protected area include "circuit information," "circuit information + input value," and "circuit information + input value + output value." The effects of re-signing are as follows. In other words, it has the effect of reducing the number of public keys managed by FPGA200. If re-signing is not done, FPGA200 will need to verify using various public keys. If the method for checking the reliability of a public key is "whether it is a public key contained in a certificate that can be traced back to a root CA that the recipient trusts," it will also be necessary to trace the certificate back to the root CA. Also, since certificates may be invalidated after being issued, a revocation check will also be necessary. In this way, verifying that a certificate is trustworthy places a burden on FPGA200.

[0106] The CPU 100 sends the re-signed input value 12 and signature (CPU) 403 to the FPGA 200 .

[0107] On the other hand, the FPGA 200 receives the public key (FPGA) 222, the private key (FPGA) 223, the hash value (circuit information) 232, and the public key (CPU) 401 sent from the CPU 100 (see S312).

[0108] The FPGA 200 performs signature verification and calculation using a circuit (see S312) based on the public key (FPGA) 222, private key (FPGA) 223, hash value (circuit information) 232, and public key (CPU) 401, as well as the re-signed circuit information 11 sent from the CPU 100 (see S307), and the re-signed input value 12 and signature (CPU) 403 sent from the CPU 100 (see S311). The signature verification in S312 is a signature verification in which the hash value calculated by the CPU 100 (calculated from the received signature (CPU) 402 and public key (CPU) 401) is compared, as indicated by the symbol n in Fig. 15.

[0109] The FPGA 200 outputs the output value 13, and ends the <Start after writing-output of calculation result using circuit> sequence. The above describes <Start-up after writing - output of calculation result using a circuit>.

[0110] <Send output results> The output result transmission will be described. Fig. 19 is an explanatory diagram of the operation of <output result transmission> of the integrity verification system 1 for circuit information between a CPU and an accelerator. Fig. 20 is a diagram explaining the generation of a key pair of a public key (FPGA) 222 and a private key (FPGA) 223 of the FPGA 200. Fig. 21 is a diagram explaining the generation of a hash value of the FPGA 200. Fig. 22 is a diagram explaining the input value of the FPGA 200, the hash value of the circuit information, and the signature of the output value. Fig. 23 is an explanatory diagram of hash value verification of the circuit information 11 and the input value 12.

[0111] As shown in Fig. 19, in the <output result transmission> operation, the FPGA 200 generates a key pair and generates a hash value of the input value 12. More specifically, this is as follows. In the FPGA 200, the signature / hash function unit 211 of the arithmetic circuit 210 generates a key pair of a public key (FPGA) 222 and a private key (FPGA) 223 as shown in Fig. 20. As shown in FIG. 21, a signature / hash function unit 211 of an arithmetic circuit 210 generates a hash value (input value) 214 using a hash function (input value) 212 .

[0112] There are two ways to implement these hash values ​​and key generation functions on the FPGA200 side as circuit information of the FPGA200, or to build the circuits into the integrated circuit of the FPGA200 or other parts in advance (meaning that they cannot be changed later), and either method can be used. When using current products, there are cases where the former method is the only way to achieve this, but ideally there are also cases where it is better not to be able to modify such security functions later.

[0113] The calculation result by the calculation circuit 210 is output to the RAM 220 (see S61). The RAM 220 temporarily stores the hash value (input value) 231, the hash value (circuit information) 232, the output value 13, and the signature (FPGA). The RAM 220 also temporarily stores the input value 12, the public key (CPU) 401 of the CPU 100, the public key (FPGA) 222 of the FPGA 200, and the private key (FPGA) 223 of the FPGA 200.

[0114] As indicated by symbol q in FIG. 22, the FPGA 200 uses a private key (FPGA) 233 to sign a hash value (input value) 231, which is a hash value of the input value and circuit information, a hash value (circuit information) 232, and an output value 13. The FPGA 200 sends the hash value (input value) 231, the hash value (circuit information) 232, the signature (FPGA) 223 added to the output value 13, and the public key (FPGA) 222 to the CPU 100 (see S62).

[0115] The CPU 100 verifies the hash value and the signature. Specifically, the hash value verification is as follows. As shown in Fig. 23, the CPU 100 inputs an input value 12, circuit information 11, a public key (CPU) 401, and a signature (CPU) 402, and generates a hash value (input value) 142 and a hash value (circuit information) 143 using a hash function (CPU) 141. When verifying the hash value and the signature, attestation may be performed to confirm that the CPU 100 is a trustworthy FPGA.

[0116] Fig. 24 is a control sequence diagram of <output result transmission> of the integrity verification system 1 for circuit information between the CPU and accelerator in Fig. 19. Fig. 25 is a diagram for explaining signature verification of the signature (FPGA) 223 added to the output value 13 using the public key (FPGA) 222 of the CPU 100.

[0117] In the <output result transmission> operation, FPGA 200 receives public key (FPGA) 222, private key (FPGA) 223, circuit information 11, hash value (circuit information) 232, public key (CPU) 401, input value 12, and output value 13 (see S401). As indicated by symbol q in FIG. 22, the FPGA 200 uses a private key (FPGA) 233 to sign a hash value (input value) 231, which is a hash value of the input value and circuit information, a hash value (circuit information) 232, and an output value 13 (see S402).

[0118] As shown in FIG. 21, the FPGA 200 generates a hash value (input value) 214 using a hash function (input value) 212 (see S403).

[0119] The FPGA 200 sends the hash value (input value) 231, the hash value (circuit information) 232, the signature (FPGA) 223 added to the output value 13, and the public key (FPGA) 222 to the CPU 100 (see S404).

[0120] Meanwhile, the CPU 100 receives the circuit information 11, public key (signature grantor) 52, signature (signature grantor) 53, input value 12, public key (input value source) 301, and signature (input value source) 303 sent from the development PC 10 (see FIG. 2) at the signature receiving unit 131 (see FIG. 5) arranged in the protected area (enclave) 130 (see S405).

[0121] As indicated by the symbol r in FIG. 25, the CPU 100 uses the public key (FPGA) 222 to verify the signature (FPGA) 223 added to the output value 13 (see S406). As shown in FIG. 23, the CPU 100 inputs an input value 12, circuit information 11, a public key (CPU) 401 and a signature (CPU) 402, and uses a hash function (CPU) 141 to generate a hash value (input value) 142 and a hash value (circuit information) 143 (see S407). The above is a description of <Output result transmission>.

[0122] [effect] As described above, the system for verifying the integrity of circuit information 11 includes a CPU 100 and an FPGA 200 that executes specific processing of an application offloaded from the CPU 100, and verifies the integrity of circuit information 11 between the CPU 100 and the FPGA 200. The CPU 100 has a protected area (enclave) 130 for preventing tampering, and the protected area (enclave) 130 includes a signature verification unit 140 that verifies the signature of the circuit information 11 that was signed by the development PC 10 and sent to the CPU 100. 32, and a signature replacement unit 135 that replaces the signature (signature assigner) 53 verified by the signature verification unit 132 with a signature (CPU) 402 by the public key (public key (CPU) 401) of the CPU 100 before sending the circuit information 11 to the FPGA 200 side. When an input value 12 is sent from the CPU 100, the FPGA 200 performs a calculation based on the input value 12, and adds a hash value of the input value 12 and the circuit information 11 and a signature (signature (FPGA) 233) to the output value and sends it to the CPU 100.

[0123] In this way, the number of public keys managed by the FPGA 200 can be reduced by replacing the signature in the CPU 100, and the processing load of the FPGA 200 can also be reduced. Furthermore, the CPU 100 can verify the results from the FPGA 200, and therefore can confirm the integrity of the circuit information 11 and the like, that they have not been tampered with. In other words, the CPU 100 can verify the correctness of important information (whether the calculated values ​​are correct, and whether communication between the protected area (enclave) 130 and the FPGA 200 has been tampered with).

[0124] In the CPU 100 of the circuit information integrity verification system 1, the signature verification unit 132 verifies the signature of the input value 12 signed by the input value source 300 and sent to the CPU 100, and the signature replacement unit 135 replaces the signature verified by the signature verification unit 132 with the key of the CPU 100 (public key (CPU) 401) before sending the input value 12 to the FPGA 200 side.

[0125] In this way, it is possible to confirm the completeness of the circuit information 11 and the like, that is, that the circuit information has not been tampered with.

[0126] In the circuit information integrity verification system 1, a development PC 10 has a signature provider 50, guaranteed by a trusted third party (CA), sign the circuit information 11.

[0127] In this way, it is possible to confirm the completeness of the circuit information 11 and the like, that it has not been tampered with, and also to reduce the processing load on the FPGA.

[0128] The circuit information integrity verification system 1 includes a signature generation unit 134 that calculates a hash value (CPU) 152 of the circuit information 11, and then generates a signature (signature (CPU) 403) using the hash value (CPU) 152 and a private key (CPU) 402. The signature verification unit 132 performs signature verification by comparing the hash value (CPU) 152 of the circuit information 11 with a hash value calculated by the signature assigner 50 (calculated from the received signature (CPU) 403 and public key (CPU) 401).

[0129] In this manner, the signature verification unit 132 performs signature verification by comparing the hash value (CPU) 152 of the circuit information 11 with the hash value calculated by the signature assigner 50, thereby enabling the signature replacement unit 135 to confirm the integrity of the replacement itself, that is, that it has not been tampered with, prior to the replacement of the signature (CPU) 402 by the signature replacement unit 135.

[0130] In the circuit information integrity verification system 1, the signature verification unit 132 verifies the hash value and the signature sent from the FPGA 200.

[0131] In this way, it is possible to confirm the completeness of the circuit information 11 and the like, that is, that the circuit information has not been tampered with.

[0132] In the circuit information integrity verification system 1, the FPGA 200 pre-registers the public key of the public key and private key generated by the CPU 100, and verifies the signature of the circuit information 11 signed by the CPU 100 and sent to the FPGA 200 using the registered public key.

[0133] In this way, the processing load on the FPGA 200 can be reduced.

[0134] [others] Among the processes described in the above principle explanation and the embodiment, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by a known method. In addition, the information including the processing procedures, control procedures, specific names, various data and parameters shown in the above documents and drawings can be changed arbitrarily unless otherwise specified. In addition, each component of each device shown in the figure is a functional concept, and does not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads, usage conditions, etc.

[0135] In addition, each of the above configurations, functions, processing units, processing means, etc. may be realized in hardware, for example, by designing a part or all of them as an integrated circuit. In addition, each of the above configurations, functions, etc. may be realized by software for a processor to interpret and execute a program that realizes each function. Information on the program, table, file, etc. that realizes each function can be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disk. In addition, in this specification, a processing step that describes a chronological process includes not only a process that is performed chronologically according to the described order, but also a process that is not necessarily processed chronologically but is performed in parallel or individually (for example, parallel processing or object processing). [Explanation of symbols]

[0136] 1 Circuit information integrity verification system 10 Development PC 11 Circuit Information 12 Input Values 13 Output Value 50 Signature granter (signature granting device) 52 Public key (signer) 53 Signature (signer) 100 CPU 130 enclave 131 Signature Receiving Department 132 Signature Verification Unit 133 Key Pair Generation Unit 134 Signature generation section 135 Signature Replacement Section 136 Signature Sending Section 152 Hash value of circuit information 200 FPGA (accelerator) 210 Arithmetic circuit 211 Hash Function Unit 212,231 hash value (input value) 222 Public Key (FPGA) 223 Private Key (FPGA) 232 Hash value (circuit information) 233 Signature (FPGA) 300 Input value source 401 Public key (CPU) 402 Private key (CPU) 403 Signature (CPU)< / attestation>

Claims

1. A circuit information integrity verification system including a CPU and an accelerator that executes a specific process of an application offloaded from the CPU, the system verifying the integrity of circuit information between the CPU and the accelerator, The CPU has a protected area to prevent tampering, a signature verification unit that verifies a signature of the circuit information that is signed by a development PC and sent to the CPU in the protected area; a signature replacement unit that replaces the signature verified by the signature verification unit with a key of the CPU before transmitting the circuit information to the accelerator side; The accelerator comprises: When an input value is sent from the CPU, a calculation is performed based on the input value, and the input value and the hash value of the circuit information and a signature are added to the output value, and the result is sent to the CPU. A circuit information integrity verification system comprising:

2. The signature verification unit verifies a signature of an input value that is signed by an input value source and sent to the CPU, The signature replacement unit replaces the signature verified by the signature verification unit with a key of the CPU before sending the input value to the accelerator side.

2. The circuit information integrity verification system according to claim 1.

3. The development PC is a device for signing the circuit information, the signing device being certified by a trusted third party.

2. The circuit information integrity verification system according to claim 1.

4. a signature generating unit that calculates a hash value of the circuit information and then generates a signature using the hash value and a private key; The signature verification unit performs signature verification by comparing a hash value of the circuit information with a hash value calculated by the signature assignment device.

4. The circuit information integrity verification system according to claim 3.

5. The signature verification unit verifies the hash value and the signature sent from the accelerator.

2. The circuit information integrity verification system according to claim 1.

6. the accelerator registers in advance the public key of the public key and the private key generated by the CPU, The signature of the circuit information signed by the CPU and sent to the accelerator is verified using the registered public key.

2. The circuit information integrity verification system according to claim 1.

7. A method for verifying the integrity of circuit information comprising a CPU and an accelerator that executes a specific process of an application offloaded from the CPU, the method comprising: a step of verifying, by the CPU, a signature of the circuit information that has been signed by a development PC and sent to the CPU in a protection area for preventing tampering; and before transmitting the circuit information to the accelerator side, replacing the verified signature with a key of the CPU. The accelerator includes a step of, when an input value is sent from the CPU, executing a calculation based on the input value, adding a hash value of the input value and the circuit information and a signature to the output value, and sending the output value to the CPU.

2. A method for verifying the integrity of circuit information comprising the steps of:

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