Non-volatile memory including a decision memory cell string and method of operating same - Patents.com

Abstract

To provide a non-volatile memory including a determination memory cell string, and an operation method thereof.SOLUTION: A non-volatile memory includes a memory array and a controller. Each of a main memory cell string MS, a first determination memory cell string PS, and a second determination memory cell string ES of the memory array includes a plurality of main memory cells MC0, MC1, MC2, and MC31, a plurality of first determination memory cells PC0, PC1, PC2, and PC31, and a plurality of second determination memory cells EC0, EC1, EC2, and EC31, respectively. During a program operation, the controller decides a data level of the corresponding first determination memory cell based on the data level of each main memory cell, decides a data level of the corresponding second determination memory cell level based on the data level of each of the first determination memory cell and the previous first determination memory cell, and decides whether or not a preprogram operation is executed based on the decision during an erase operation.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to memory devices and methods of operation thereof, and more particularly to non-volatile memories including decision memory cell strings and methods of operation thereof. [Background technology]

[0002] For a typical NAND flash memory, when performing an erase operation on memory cells, the shallow erase problem can be avoided by performing a pre-program operation on all pages before applying an initial erase voltage, where the voltage strength of the pre-program operation is lower than that of a normal program operation and is used to raise the threshold voltage of erased memory cells but does not change the erased memory cells to a programmed state. Summary of the Invention [Problem to be solved by the invention]

[0003] Performing a pre-program operation before an erase operation can put additional strain on memory cells, resulting in a significant increase in erase time after multiple program / erase cycling compared to the situation without a pre-program operation, which means more damage to memory cells and a shorter lifespan.

[0004] In advanced processes, device scaling down reduces the program / erase cycle performance: if every page is pre-programmed in the traditional way, the number of program / erase cycles that can be performed is reduced, resulting in a shorter lifetime. [Means for solving the problem]

[0005] The present invention relates to a non-volatile memory and a method of operating the same that are suitable for determining whether a memory cell to be erased has only experienced a program voltage in an isolated state, and based thereon, deciding whether to perform a pre-program operation.

[0006] The present invention provides a non-volatile memory including a memory array and a controller. The memory array includes a plurality of blocks. Each of the blocks includes a plurality of main memory cell strings, a first decision memory cell string, and a second decision memory cell string. Each of the main memory cell strings includes a plurality of main memory cells connected in series, the first decision memory cell string includes a plurality of first decision memory cells connected in series, and the second decision memory cell string includes a plurality of second decision memory cells connected in series. The controller is coupled to the memory array. During a program operation, the controller determines a data level of a corresponding first decision memory cell based on a data level of each main memory cell, and determines a data level of a corresponding second decision memory cell based on a data level of each first decision memory cell and the previous first decision memory cell. During an erase operation, the controller determines whether to perform a pre-program operation based on a data level of the second decision memory cell.

[0007] The present invention provides a method for operating a non-volatile memory suitable for the above non-volatile memory, which includes the following steps: during a program operation, determine a data level of a corresponding first decision memory cell according to a data level of each main memory cell, and determine a data level of a corresponding second decision memory cell according to data levels of each first decision memory cell and the previous first decision memory cell; during an erase operation, determine whether to perform a pre-program operation according to the data level of the second decision memory cell. Effect of the Invention

[0008] As described above, the nonvolatile memory of the present invention is suitable for performing a pre-programming operation before erasing data only when it is determined that the memory cell to be erased has only experienced a program voltage in an isolated state. In this way, the pre-programming operation is performed when it is actually necessary, so that the number of pre-programming operations is reduced, the damage to the memory cell is reduced, the erasing efficiency is improved, and the number of program / erase cycles is increased, thereby achieving the effect of extending the life of the memory cell. [Brief description of the drawings]

[0009] The accompanying drawings are included to provide a further understanding of the principles of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0010] [Figure 1] 1 is a schematic block diagram of a non-volatile memory according to one embodiment of the present invention; [Diagram 2] 2 is a schematic structural diagram of a memory cell string in a block of the memory array according to the embodiment of FIG. 1; [Figure 3A] 4 illustrates data levels of a second decision memory cell according to one embodiment of the present invention. [Figure 3B] 4 illustrates data levels of a second decision memory cell according to one embodiment of the present invention. [Figure 3C] 4 illustrates data levels of a second decision memory cell according to one embodiment of the present invention. [Figure 4] 4 is a step flow chart of a program operation of a non-volatile memory according to one embodiment of the present invention. [Diagram 5] 4 is a step flow chart of an erase operation of a non-volatile memory according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the present invention, when a program voltage is applied to a word line and the same program voltage is not applied to the adjacent word lines on both sides, the particular word line is called an "isolation word line". That is, the memory cells connected to the isolated word line experience the program voltage in an isolated state. With respect to NAND-type flash memory, when an erase operation is performed on a block (or page) of memory cells that have only experienced the program voltage in an isolated state, the memory cells connected to the isolated word line are likely to suffer from a shallow erase problem. In order to solve the shallow erase problem and extend the life of the flash memory, the present invention determines whether the memory cell to be erased has only experienced the program voltage in an isolated state, and based on this, determines whether to perform a pre-program operation. In particular, the pre-program operation is performed only when it is determined that the memory cell to be erased has only experienced the program voltage in an isolated state.

[0012] 1 and 2, a nonvolatile memory 100 according to an embodiment of the present invention is, for example, a NAND flash memory. The nonvolatile memory 100 includes a memory array 110, a controller 120, a sensing circuit 130, a word line selection circuit 140, and a counter 150. The memory array 110 includes m blocks BLK_0 to BLK_m-1 arranged along a column direction, where m is a positive integer equal to or greater than 1. Each of the blocks BLK_0 to BLK_m-1 includes a plurality of main memory cell strings MS, a first decision memory cell string PS, and a second decision memory cell string ES.

[0013] The memory array 110 is formed by arranging a plurality of memory cells in a matrix. As shown in Fig. 2, each main memory cell string MS includes a plurality of main memory cells MC0 to MC31 connected in series, a bit line side selection transistor MTD, and a source line side selection transistor MTS. The first decision memory cell string PS includes a plurality of first decision memory cells PC0 to PC31 connected in series, a bit line side selection transistor PTD, and a source line side selection transistor PTS. The second decision memory cell string ES includes a plurality of second decision memory cells EC0 to EC31 connected in series, a bit line side selection transistor ETD, and a source line side selection transistor ETS.

[0014] The gates of the main memory cells MC0 to MC31 are connected to the word lines WL0 to WL31, respectively. The gates of the first decision memory cells PC0 to PC31 and the gates of the second decision memory cells EC0 to EC31 are also connected to the word lines WL0 to WL31, respectively. The drains of the bit line side select transistors MTD, PTD, and ETD are connected to the corresponding bit lines BL, and the gates of the bit line side select transistors MTD, PTD, and ETD are connected to a select gate line SGD. The sources of the source line side select transistors MTS, PTS, and ETS are connected to a common source line SL, and the gates of the source line side select transistors MTS, PTS, and ETS are connected to a select gate line SGS.

[0015] 1, the sensing circuit 130 is coupled between the memory array 110 and the controller 120. The sensing circuit 130 is connected to all bit lines BL and can read the data levels of the main memory cells MC0-MC31, the first decision memory cells PC0-PC31, and the second decision memory cells EC0-EC31. The sensing circuit 130 can include, for example, a sensing amplifier and a page buffer, which can be implemented by the framework of an application memory circuit well known to engineers in the field of integrated circuits, but the present invention is not limited thereto.

[0016] The word line selection circuit 140 is coupled between the memory array 110 and the controller 120. The word line selection circuit 140 can be used to drive the word lines WL0-WL31 connected to the main memory cells MC0-MC31, the first decision memory cells PC0-PC31, and the second decision memory cells EC0-EC31, and the select gate lines SGD and SGS. The word line selection circuit 140 can drive the main memory cells MC0-MC31, the first decision memory cells PC0-PC31, and the second decision memory cells EC0-EC31 through the word lines WL0-WL31 to perform each operation. Furthermore, the word line selection circuit 140 can drive the bit line side select transistors MTD, PTD, ETD and the source line side select transistors MTS, PTS, ETS through the select gate lines SGD and SGS to select a block and a page. The word line selection circuit 140 can be implemented by the framework of an application memory circuit well known to engineers in the field of integrated circuits, but the present invention is not limited thereto.

[0017] The counter 150 is coupled to the controller 120. The controller 120 can be configured to increment the count value after an erase operation passes an erase verify. The count value of the counter 150 can be used to perform a pre-program operation on some pages, which will be described in more detail later.

[0018] The controller 120 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device, or a combination of these devices. The controller 120 may be coupled to the memory array 110 via the word line selection circuit 140. In this embodiment, during a program operation, the controller 120 may determine a data level of a corresponding first decision memory cell (e.g., PC1) based on a data level of each main memory cell (e.g., MC1). Furthermore, the controller 120 may determine a data level of a second decision memory cell (e.g., EC1) corresponding to each first decision memory cell (e.g., PC1) based on a data level of each first decision memory cell (e.g., PC1) and its previous first decision memory cell (e.g., PC0).

[0019] Specifically, during a program operation, the controller 120 can program a main memory cell MCn selected from the main memory cells MC0 to MC31, and then program a first decision memory cell PCn corresponding to the selected main memory cell MCn based on the program. In this embodiment, the so-called "corresponding" refers to a relationship of commonly connecting the same word line, where n is a positive integer between 1 and 31.

[0020] The controller 120 can then determine whether the first decision memory cell PCn-1 before the first decision memory cell PCn has a programming level, i.e., determine whether the first decision memory cell PCn-1 before the first decision memory cell PCn has been programmed. In this embodiment, the programming level is, for example, a low logic level (representing a binary value 0) after the memory cell is programmed.

[0021] If the previous first decision memory cell PCn-1 has a programming level, it means that the corresponding main memory cell MCn-1 has also been programmed. That is, the word lines WLn and WLn-1 connected to the main memory cells MCn and MCn-1 are applied with the programming voltage Vpgm. That is, the selected block of the memory array has at least the word line WLn and is not an isolated word line, so the shallow erase problem in the subsequent erase operation is not serious. In this case, the controller 120 can also program the second decision memory cell ECn corresponding to the selected main memory cell MCn and the first decision memory cell PCn to change it to a programming level for recording.

[0022] If the previous first decision memory cell PCn-1 does not have a programming level, it means that the corresponding main memory cell MCn-1 is not programmed. That is, the program voltage Vpgm is applied only to the word line WLn connected to the main memory cell MCn, and the word line WLn-1 connected to the main memory cell MCn-1 is not programmed. That is, since the program voltage Vpgm is applied to the word line WLn in an isolated state, a shallow erase problem is likely to occur in a subsequent erase operation. In this case, the controller 120 does not program the selected main memory cell MCn and the second decision memory cell ECn corresponding to the first decision memory cell PCn (that is, the logical value of the second decision memory cell ECn is "1"). The program voltage Vpgm is, for example, 15 volts to 20 volts.

[0023] The program operation of this embodiment will be described with reference to the following specific example. FIG. 3A shows the data levels of the second decision memory cells EC0-EC31 after the main memory cells MC0 and MC10 are programmed. In this embodiment, a program voltage Vpgm is applied to the word lines WL0 and WL10 connected to the main memory cells MC0 and MC10 to program the main memory cells MC0 and MC10 and the first decision memory cells PC0 and PC10 to logic "0". Since the word line WL0 is the first word line, there is no previous word line, and it is not necessary to determine the state of the previous word line and the previous first decision memory cell. That is, since the word line WL0 is an isolated word line, the second decision memory cell EC0 maintains logic "1". Since the program voltage Vpgm is not applied to the word line WL9 preceding the word line WL10, the first decision memory cell PC9 corresponding to the word line WL9 maintains logic "1". That is, since the word line WL10 is an isolated word line, the second decision memory cell EC10 still maintains logic "1". In this manner, based on a logic "1" read result from the second determination memory cell string ES, it can be determined that the memory cells in the selected block of the memory array have only experienced the program voltage in an isolated state.

[0024] FIG. 3B shows the data levels of the second decision memory cells EC0-EC31 after the main memory cells MC0-MC2 and MC10 are programmed. In this embodiment, a program voltage Vpgm is applied to the word lines WL0-WL2 and WL10 connected to the main memory cells MC0-MC2 and MC10 to program the main memory cells MC0-MC2 and MC10 and the first decision memory cells PC0-PC2 and PC10 to logic "0". As described above, since the word line WL0 is the first word line, the second decision memory cell EC0 maintains logic "1". Since the program voltage Vpgm is not applied to the word line WL9 preceding the word line WL10, the first decision memory cell PC9 corresponding to the word line WL9 maintains logic "1", and the second decision memory cell EC10 still maintains logic "1".

[0025] Furthermore, the first decision memory cell PC0 connected to the word line WL0 preceding the word line WL1 is programmed as logic "0", so that the second decision memory cell EC1 connected to the word line WL1 is also programmed as logic "0". The first decision memory cell PC1 connected to the word line WL1 preceding the word line WL2 is programmed as logic "0", so that the second decision memory cell EC2 connected to the word line WL2 is also programmed as logic "0". That is, in the selected block of the memory array, there is a group of adjacent word lines WL0-WL2 to which the program voltage Vpgm is applied. In this way, based on the read result of logic "0" from the second decision memory cell string ES, it can be determined that at least one memory cell in the selected block of the memory array has experienced the program voltage in a non-isolated state.

[0026] FIG. 3C shows the data levels of the second decision memory cells EC0-EC31 after the main memory cells MC0 and MC30-MC31 are programmed. In this embodiment, a program voltage Vpgm is applied to the word lines WL0 and WL30-WL31 connected to the main memory cells MC0 and MC30-MC31 to program the main memory cells MC0, MC30-MC31 and the first decision memory cells PC0 and PC30-PC31 to logic "0". As described above, since the word line WL0 is the first word line, the second decision memory cell EC0 maintains logic "1". Since the program voltage Vpgm is not applied to the word line WL29 preceding the word line WL30, the first decision memory cell PC29 corresponding to the word line WL29 maintains logic "1", and the second decision memory cell EC30 still maintains logic "1".

[0027] Furthermore, since the first decision memory cell PC30 connected to the word line WL30 preceding the word line WL31 is programmed as logic "0", the second decision memory cell EC31 connected to the word line WL31 is also programmed as logic "0". That is, in the selected block of the memory array, there is a group of adjacent word lines WL30-WL31 to which the program voltage Vpgm is applied, and the second decision memory cell string ES in this case is considered to be in a logic 0 state. In this way, based on the read result of logic "0" from the second decision memory cell string ES, it can be determined that at least one memory cell in the selected block of the memory array has experienced the program voltage in a non-isolated state.

[0028] After the above program operation, during an erase operation, the controller 120 can determine whether to perform a pre-program operation before applying an erase voltage based on the data levels of the second decision memory cells EC0-EC31 (e.g., logic values ​​read from the second decision memory cell string ES). Specifically, during an erase operation, the controller 120 can determine whether the second decision memory cell string ES includes any second decision memory cells having a programming level by a reverse read. When the second decision memory cell string ES includes second decision memory cells having a programming level (logic "0" is read from the second decision memory cell string ES), the controller 120 does not perform a pre-program operation before applying an erase voltage, and directly erases the selected block of the memory array 110. When the second decision memory cell string ES does not include second decision memory cells having a programming level (logic "1" is read from the second decision memory cell string ES), the controller 120 performs a pre-program operation on some pages in the selected block of the memory array before applying an erase voltage to prevent a shallow erase problem.

[0029] During the reverse read, the controller 120 can apply a charging voltage to the source line SL connected to the second decision memory cell string ES, and can apply a test voltage lower than the charging voltage to the word lines WL0 to WL31 connected to the second decision memory cell string ES via the word line selection circuit 140 to turn on the bit line side selection transistor ETD and the source line side selection transistor ETS. Then, the sensing circuit 130 can determine whether the equivalent capacitance of the second decision memory cell string ES has increased in response to the charging voltage. If it has increased, it means that the second decision memory cell string ES is in a logic "1" state. If it has not increased, it means that the second decision memory cell string ES is in a logic "0" state. The charging voltage is, for example, 2.2 volts to 2.4 volts, and the test voltage is, for example, 0.7 volts to 0.9 volts.

[0030] Furthermore, the voltages required for read, program, and erase operations may be provided by internal voltage generation circuits within non-volatile memory 100, for example.

[0031] In one embodiment of the present invention, for the pre-program operation performed on some pages, the controller 120 can select some corresponding pages to perform the pre-program operation based on the count value of the counter 150. The count value of the counter 150 is incremented after the erase operation passes the erase verification. In this way, the controller 120 can dynamically adjust the addresses corresponding to the some pages to perform the pre-program operation according to the number of erases.

[0032] For example, when a logic "1" is read from the second determination memory cell string ES, if the controller 120 determines that the count value of the counter 150 is 0, it means that a first erase operation will be performed soon, and the corresponding pre-programmed pages are pages 0 to 7. After performing a pre-program operation on pages 0 to 7, a first erase operation is performed on the selected block, and when the first erase operation is completed, the count value of the counter 150 is increased to 1. Furthermore, when an erase operation is performed twice, the count value of the counter 150 is 1. Therefore, when a logic "1" is read from the second determination memory cell string ES, the controller 120 performs a pre-program operation on pages 8 to 15. Similarly, when an erase operation is performed three times, the count value of the counter 150 is 2, and the corresponding pre-programmed pages are pages 16 to 23, and so on.

[0033] As described above, since each block of the memory array 110 of the present invention includes the first decision memory cell string PS and the second decision memory cell string ES, it is possible to determine whether the memory cell to be erased has only experienced a program voltage in an isolated state based on the operation method of the present invention. Furthermore, during the erase operation, the state of the second decision memory cell string ES is first determined using a reverse read, and the pre-program operation is performed only when it is determined that the memory cell to be erased has only experienced a program voltage in an isolated state, thereby reducing the effect of shallow erase. Furthermore, the page range in which the pre-program operation is performed is adjusted according to the number of erases based on the count value of the counter 150, thereby increasing the number of program / erase cycles and extending the service life of the non-volatile memory 100.

[0034] 4 is a step flow chart of a program operation of a non-volatile memory according to an embodiment of the present invention. The program operation of this embodiment is applied to the non-volatile memory 100 shown in FIG. 1, so please refer to FIG. 1 and FIG. 4 at the same time.

[0035] After the non-volatile memory 100 receives the program command, in step S402, the controller 120 determines whether the first decision memory cell PCn-1 before the first decision memory cell PCn corresponding to the selected main memory cell MCn has a programming level. When the first decision memory cell PCn-1 before the first decision memory cell PCn has a programming level, the controller 120 executes a program on the selected main memory cell MCn, the corresponding first decision memory cell PCn, and the corresponding second decision memory cell ECn (step S404). Then, in step S406, the controller 120 determines whether the program verification is passed. If it is passed, the program operation is terminated, and the program of the next page or block can continue. If it is not passed (the verification is failed), in step S408, the controller 120 increases the program voltage (e.g., 0.4 volts) by incremental step pulse programming (ISPP), and then returns to step S404 to repeatedly apply the adjusted program voltage until the program verification is passed.

[0036] When the previous first decision memory cell PCn-1 does not have the programming level, the controller 120 programs the selected main memory cell MCn and the corresponding first decision memory cell PCn (step S410). Then, in step S412, the controller 120 determines whether the program verify is passed. If it is passed, the program operation is finished and the program of the next page or block can continue. If it is not passed, in step S414, the controller 120 increases the program voltage by incremental step pulse programming (ISPP), and then returns to step S410 to repeatedly apply the adjusted program voltage until the program verify is passed.

[0037] 5 is a step flow chart of an erase operation of a non-volatile memory according to an embodiment of the present invention. The erase operation of this embodiment is applied to the non-volatile memory 100 shown in FIG. 1, so please refer to FIG. 1 and FIG. 5 at the same time.

[0038] First, in step S502, the controller 120 determines whether the second decision memory cell string ES includes a second decision memory cell having a programming level by reverse reading. When the second decision memory cell string ES includes a second decision memory cell having a programming level (the second decision memory cell string ES is in a logic "0" state), the controller 120 directly erases the block of the memory array 110 (step S512). Next, in step S514, the controller 120 determines whether the erase verify is passed. If it is passed, the erase operation is finished and the erase of the next block can continue. If it is not passed (the verification is failed), in step S516, the controller 120 increases the erase voltage by incremental step pulse erase, and then returns to step S512 to repeatedly apply the adjusted erase voltage until the erase verify is passed.

[0039] When the second decision memory cell string ES does not include the second decision memory cell having the programming level (the second decision memory cell string ES is in the logic "1" state), the controller 120 first performs the pre-program operation on some pages (step S510). Also, step S512 is not performed until the pre-program operation on some pages is completed.

[0040] As described above, the non-volatile memory of the present invention is suitable for performing a pre-program operation before erasure only when it is determined that the memory cell to be erased has only experienced a program voltage in an isolated state. In this way, the pre-program operation is performed when it is actually necessary, so that the number of pre-program operations can be reduced and damage to the memory cell can be reduced. At the same time, the page range for performing the pre-program operation can be adjusted according to the number of erasures, that is, by dynamically changing the address for performing the pre-program operation, thereby increasing the number of program / erase cycles, improving the reliability of program / erase cycles and high-temperature data retention (HTDR), and extending the life of the non-volatile memory 100. In addition, the erasure efficiency can be improved even if the memory cell experiences many program / erase cycles.

[0041] The present invention is suitable for making miniaturized non-volatile memories, such as NAND flash memory devices, which can increase the total number of dies on a wafer. Therefore, the production cost and energy consumption in manufacturing a single IC is reduced, and the production energy consumption of the subsequent packaging is also reduced, which can reduce the carbon emissions in the process of producing non-volatile memories. Furthermore, the reliability and durability of the non-volatile memory of the present invention are improved, so that the present invention provides a sustainable non-volatile memory.

[0042] Additionally, the non-volatile memory of the present invention can be used in automotive electronics such as Advanced Driver Assistance Systems (ADAS), Instrument Clusters, and Infotainment. The flash memory devices of the present invention can be used in space-constrained applications including wearables, MP3 players, smart watches, games, digital radios, toys, cameras, digital photo albums, GPS, Bluetooth, and WiFi modules. The non-volatile memory of the present invention can be used in IoT and mobile electronic devices. [Industrial Applicability]

[0043] The non-volatile memory including the decision memory cell string of the present invention and its method of operation can be applied to memory cells. [Explanation of symbols]

[0044] 100 Non-volatile memory 110 Memory Array 120 Controller 130 Sensing Circuit 140 Word line selection circuit 150 Counter BL bit line BLK_0, BLK_1, BLK_m-1 blocks EC0, EC1, EC2, EC10, EC30, EC31 Second decision memory cell ES Second judgment memory cell string ETD, MTD, PTD Bit line side selection transistor ETS, MTS, PTS Source line side selection transistor MC0, MC1, MC2, MC31 Main memory cells MS Main memory cell string PC0, PC1, PC2, PC31 First decision memory cell PS First judgment memory cell string SGD, SGS Select gate lines SL Source Line Vpgm Program voltage WL0, WL1, WL2, WL10, WL30, WL31 word lines S402~S414, S502~S516 steps

Claims

1. a memory array including a plurality of blocks, each of the blocks including a plurality of main memory cell strings, a first determination memory cell string, and a second determination memory cell string, each of the main memory cell strings including a plurality of main memory cells connected in series, the first determination memory cell string including a plurality of first determination memory cells connected in series, and the second determination memory cell string including a plurality of second determination memory cells connected in series; a controller coupled to the memory array and configured to determine a data level of the corresponding first decision memory cell based on a data level of each of the main memory cells during a program operation, and to determine a data level of the corresponding second decision memory cell based on a data level of each of the first decision memory cells and each previous first decision memory cell; and during an erase operation, the controller is configured to determine whether to perform a pre-program operation based on a data level of the second decision memory cell.

2. During the erase operation, the controller determines whether the second decision memory cell string includes any of the second decision memory cells having a programming level by reverse reading; 2. The non-volatile memory of claim 1, wherein when the second decision memory cell string includes the second decision memory cell having the programming level, the controller does not perform the pre-program operation before applying an erase voltage.

3. 3. The non-volatile memory of claim 2, wherein during the reverse read, the controller is configured to apply a charging voltage to a source line connected to the second determination memory cell string, apply a test voltage lower than the charging voltage to a plurality of word lines connected to the second determination memory cell string, and determine whether an equivalent capacitance of the second determination memory cell string has increased in response to the charging voltage.

4. 3. The non-volatile memory of claim 2, wherein the controller performs the pre-program operation on a portion of a page before applying the erase voltage when the second decision memory cell string does not include the second decision memory cell having the programming level.

5. 2. The non-volatile memory of claim 1, wherein when the erase operation fails erase verification, the controller repeatedly performs erase by incremental step pulse erase until the erase verification passes.

6. a counter coupled to the controller and configured to increment a count value after an erase verify of the erase operation is passed; The non-volatile memory of claim 1 , wherein the controller selects a portion of corresponding pages based on the count value to perform the pre-program operation.

7. 2. The non-volatile memory of claim 1, further comprising a sensing circuit coupled between the memory array and the controller and configured to read the data levels of the main memory cell, the first decision memory cell, and the second decision memory cell.

8. 2. The non-volatile memory of claim 1, further comprising a word line selection circuit coupled between the memory array and the controller and configured to drive a plurality of word lines connected to the main memory cells, the first decision memory cells, and the second decision memory cells.

9. During the program operation, the controller determines whether the first decision memory cell preceding the first decision memory cell corresponding to a selected main memory cell has a programming level; when the previous first decision memory cell has the programming level, the controller applies a program voltage to the selected main memory cell, the corresponding first decision memory cell, and the corresponding second decision memory cell; 2. The non-volatile memory of claim 1, wherein the controller applies the program voltage to the selected main memory cell and the corresponding first decision memory cell when the previous first decision memory cell does not have the programming level.

10. 10. The non-volatile memory of claim 9, wherein when the program verification of the program operation fails and when the previous first decision memory cell has the programming level, the controller repeatedly applies adjusted program voltages to the selected main memory cell, the corresponding first decision memory cell, and the corresponding second decision memory cell by incremental step pulse programming until the program verification passes.

11. 1. A method of operating a non-volatile memory, the non-volatile memory comprising: a plurality of main memory cell strings, a first determination memory cell string, and a second determination memory cell string, each of the main memory cell strings comprising a plurality of main memory cells connected in series, the first determination memory cell string comprising a plurality of first determination memory cells connected in series, and the second determination memory cell string comprising a plurality of second determination memory cells connected in series; The method comprises: During a program operation, determining a data level of the corresponding first decision memory cell based on a data level of each of the main memory cells, and determining a data level of the corresponding second decision memory cell based on a data level of each of the first decision memory cells and each previous first decision memory cell; determining whether to perform a pre-program operation based on the data level of the second decision memory cell during an erase operation; A method of operating a non-volatile memory comprising:

12. determining whether to perform the pre-program operation based on the data level of the second decision memory cell; during the erase operation, determining whether the second decision memory cell string includes any of the second decision memory cells having a programming level by reverse reading; not performing the pre-program operation prior to applying an erase voltage when the second decision memory cell string includes the second decision memory cell having the programming level; The method of claim 11 , comprising:

13. determining whether the second decision memory cell string includes any of the second decision memory cells having the programming level by reverse reading; applying a charging voltage to a source line connected to the second determination memory cell string and applying a test voltage lower than the charging voltage to a plurality of word lines connected to the second determination memory cell string; determining whether an equivalent capacitance of the second determination memory cell string increases in response to the charging voltage; The method of claim 12, comprising:

14. determining whether to perform the pre-program operation based on the data level of the second decision memory cell; 13. The method of claim 12, further comprising: performing the pre-program operation on a portion of pages before applying the erase voltage when the second decision memory cell string does not include the second decision memory cell having the programming level.

15. 12. The method of claim 11, further comprising, when the erase operation fails erase verify, repeatedly performing erase with an incremental step pulse erase until the erase verify passes.

16. incrementing a count value after the erase operation passes erase verify; Selecting a portion of corresponding pages based on the count value to perform the pre-program operation; The method of claim 11 further comprising:

17. determining the data level of the corresponding second decision memory cell based on the data level of each of the first decision memory cells and each of the previous first decision memory cells; determining whether the first decision memory cell preceding the first decision memory cell corresponding to a selected main memory cell during the program operation has a programming level; applying a program voltage to the selected main memory cell, the corresponding first decision memory cell, and the corresponding second decision memory cell when the previous first decision memory cell has the programming level; applying the program voltage to the selected main memory cell and the corresponding first decision memory cell when the previous first decision memory cell does not have the programming level; The method of claim 11 , comprising:

18. 20. The method of claim 17, further comprising: when the program verification of the program operation fails and when the previous first decision memory cell has the programming level, repeatedly applying adjusted program voltages to the selected main memory cell, the corresponding first decision memory cell, and the corresponding second decision memory cell by incremental step pulse programming until the program verification passes.

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