Image display device manufacturing method and image display device

Abstract

A method for manufacturing an image display device according to an embodiment comprises: a step for preparing a first substrate including a circuit and a first insulating film covering the circuit, the circuit including a circuit element formed on an optically transmissive substrate; a step for forming on the first insulating film a layer including graphene; a step for forming on the layer including the graphene a semiconductor layer including a light-emitting layer; a step for forming a light-emitting element by etching the semiconductor layer; a step for forming a second insulating film covering the layer including the graphene, the light-emitting element, and the first insulating film; a step for forming a via penetrating through the first insulating film and the second insulating film; and a step for electrically connecting the light-emitting element with the circuit element through the via on a light-emitting surface of the light-emitting element opposite a surface thereof on the first insulating film side.

Description

[Technical field]

[0001] An embodiment of the present invention relates to a manufacturing method for an image display device and an image display device. [Background technology]

[0002] There is a demand for a thin image display device that has high brightness, a wide viewing angle, high contrast, and low power consumption. In order to meet such market demands, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is expected as a self-emitting element. As a manufacturing method for display devices using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a driving circuit has been introduced. However, as the number of micro LED elements increases with the trend toward higher image quality such as full high definition, 4K, 8K, etc., the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and sequentially transferred to a substrate on which a driving circuit, etc. is formed. Furthermore, there is a risk of poor connection between the micro LEDs and the driving circuit, etc., resulting in a decrease in yield.

[0004] A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a driving circuit is formed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-141492 A [Non-patent literature]

[0006] [Non-Patent Document 1] H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foil", SCIENTIFIC REPORTS, 7:2112, 18 May 2017 [Non-Patent Document 2] JW Shon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes on amorphous substrates by pulsed sputtering", SCIENTIFIC REPORTS, 4:5325, 23 June 2014 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0008] A manufacturing method of an image display device according to one embodiment of the present invention includes the steps of: preparing a first substrate including a circuit including a circuit element formed on a light-transmitting substrate and a first insulating film covering the circuit; forming a layer including graphene on the first insulating film; forming a semiconductor layer including a light-emitting layer on the layer including graphene; etching the semiconductor layer to form a light-emitting element; forming a second insulating film covering the layer including graphene, the light-emitting element, and the first insulating film; forming a via that penetrates the first insulating film and the second insulating film; and electrically connecting the light-emitting element and the circuit element through the via on a light-emitting surface of the light-emitting element that faces the surface of the light-emitting element on the side of the first insulating film.

[0009] An image display device according to one embodiment of the present invention comprises a light-transmissive substrate having a first surface, a circuit element provided on the first surface, a first wiring layer provided on the circuit element and electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer on the first surface, a first portion including graphene provided on the first insulating film, a light-emitting element provided on the first portion, a second insulating film covering at least a portion of the light-emitting element, the first portion, and the first insulating film, a second wiring layer provided on the second insulating film and electrically connected to a light-emitting surface of the light-emitting element that faces the surface of the light-emitting element facing the first insulating film, and a first via that penetrates the first insulating film and the second insulating film and electrically connects the first wiring layer and the second wiring layer.

[0010] An image display device according to one embodiment of the present invention includes a flexible substrate having a first surface, a circuit element provided on the first surface, a first wiring layer provided on the circuit element and electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer on the first surface, a first portion including graphene provided on the first insulating film, a light-emitting element provided on the first portion, a second insulating film covering at least a portion of the light-emitting element, the first portion, and the first insulating film, a second wiring layer provided on the second insulating film and electrically connected to a light-emitting surface of the light-emitting element that faces the surface of the light-emitting element facing the first insulating film, and a first via that penetrates the first insulating film and the second insulating film and electrically connects the first wiring layer and the second wiring layer.

[0011] an insulating film covering the first surface of the first semiconductor layer; a first semiconductor layer having a first conductivity type provided on the first semiconductor layer; a light-emitting layer provided on the first semiconductor layer; a second semiconductor layer having a second conductivity type different from the first conductivity type provided on the light-emitting layer; a second insulating film covering the first semiconductor layer, the first insulating film, the light-emitting layer, and the first semiconductor layer and covering at least a portion of the second semiconductor layer; a second wiring layer connected to transparent electrodes provided on a plurality of light-emitting surfaces of the second semiconductor layer that are exposed from the second insulating film according to the plurality of transistors; and a plurality of vias that penetrate the first insulating film and the second insulating film and electrically connect the wiring of the first wiring layer and the wiring of the second wiring layer, respectively. Effect of the Invention

[0012] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer process of light emitting elements and improves yield. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. [Figure 2A] 10 is a schematic cross-sectional view illustrating a part of a modified example of the image display device according to the first embodiment. FIG. [Figure 2B] 10 is a schematic cross-sectional view illustrating a part of a modified example of the image display device according to the first embodiment. FIG. [Diagram 3] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 4] FIG. 2 is a schematic plan view illustrating a portion of the image display device according to the first embodiment. [Figure 5A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 5B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 6A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 6B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 7A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 7B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8A] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 8B] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 9A] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 9B] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 10]2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11D] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 12] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a second embodiment. [Figure 13] FIG. 11 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 14A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 14B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 15A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 15B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 16] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a third embodiment. [Figure 17A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 17B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 18] FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fourth embodiment. [Figure 19A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 19B]10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 19C] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 20A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 20B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 21A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 21B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 22A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 22B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 23] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the fourth embodiment. [Figure 24A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fourth embodiment. [Figure 24B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fourth embodiment. [Diagram 25] 1 is a graph illustrating the characteristics of a pixel LED element. [Figure 26] FIG. 13 is a block diagram illustrating an image display device according to a fifth embodiment. [Figure 27] FIG. 13 is a block diagram illustrating an image display device according to a modified example of the fifth embodiment. [Figure 28] FIG. 1 is a perspective view illustrating image display devices according to first to fourth embodiments and their modified examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed description thereof will be omitted as appropriate.

[0015] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of an image display device according to an embodiment. Fig. 1 shows a schematic configuration of sub-pixel 20-1 of the image display device of this embodiment. A pixel constituting an image displayed on the image display device is made up of a plurality of sub-pixels. Fig. 1 also shows a part of the configuration of sub-pixel 20-2 in addition to sub-pixel 20-1.

[0016] In the following, the three-dimensional coordinate system of XYZ may be used for explanation. The sub-pixels 20-1 and 20-2 are arranged on a two-dimensional plane. The two-dimensional plane on which the sub-pixels 20-1 and 20-2 are arranged is defined as the XY plane. The sub-pixels 20-1 and 20-2 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line AA' in FIG. 4, which will be described later, and is a cross section obtained by connecting cross sections in a plurality of planes perpendicular to the XY plane into one. In other figures, as in FIG. 1, the X-axis and Y-axis are not shown in the cross sections in a plurality of planes perpendicular to the XY plane, and only the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z-axis is defined as the XY plane.

[0017] The sub-pixels 20-1 and 20-2 have light-emitting surfaces 153S1 and 153S2 that are substantially parallel to the XY plane, respectively. The light-emitting surfaces 153S1 and 153S2 mainly emit light in the positive direction of the Z axis that is substantially perpendicular to the XY plane.

[0018] As shown in FIG. 1, subpixel 20-1 of the image display device of this embodiment includes a substrate 102, a transistor (circuit element) 103, a first wiring layer (first wiring layer) 110, a first interlayer insulating film (first insulating film) 112, a graphene sheet 140-1, a light-emitting element 150-1, a second interlayer insulating film (second insulating film) 156, a plurality of vias 161d, 161k, 161k-1, and a second wiring layer (second wiring layer) 160.

[0019] In this embodiment, the image display device includes a subpixel 20-2. For example, the subpixel 20-2 is disposed adjacent to the subpixel 20-1. The subpixel 20-2 includes a substrate 102, a first wiring layer 110, a first interlayer insulating film 112, a second interlayer insulating film 156, a via 161k, and a second wiring layer 160, which are shared with the subpixel 20-1. Although a transistor for the subpixel 20-2 is not shown in FIG. 1, a transistor for driving the light-emitting element 150-2 is provided separately.

[0020] In this embodiment, the substrate 102 on which the circuit elements including the transistors 103 are formed is a light-transmitting substrate, for example a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface that is substantially parallel to the XY plane. The transistors 103 are thin film transistors (TFTs) and are formed on the first surface 102a. The light-emitting elements 150-1 and 150-2 are driven by the TFTs formed on the glass substrate. The process of forming the circuit elements including the TFTs on a large glass substrate has been established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage that an existing plant can be used.

[0021] The sub-pixels 20-1 and 20-2 further include a color filter 180. The color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin-film adhesive layer 188. The surface resin layer 170 is provided on the interlayer insulating film 156 and the wiring layer 160.

[0022] The configuration of the sub-pixels 20-1 and 20-2 will now be described in detail. The transistor 103 is formed on a TFT lower layer film 106 formed on the first surface 102a of the substrate 102. The TFT lower layer film 106 is provided for the purposes of ensuring flatness when the transistor 103 is formed and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is, for example, SiO2.

[0023] On the substrate 102, in addition to the transistor 103 for driving the light emitting element 150-1, a transistor for driving the light emitting element 150-2, other transistors, capacitors and other circuit elements are formed, and a circuit 101 is configured by wiring etc. For example, the transistor 103 corresponds to the driving transistor 26 shown in Fig. 3 described later.

[0024] In the following description, the circuit 101 includes the TFT channel 104, the insulating layer 105, the insulating film 108, the vias 111s and 111d, and the wiring layer 110. The circuit board 100 may be collectively referred to as including the substrate 102, the TFT underlayer film 106, the circuit 101, and other components such as the interlayer insulating film 112.

[0025] The transistor 103 is a p-channel TFT in this example. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT is preferably formed by a low temperature polysilicon (LTPS) process. The TFT channel 104 is a region of polycrystalline Si formed on the substrate 102, and is polycrystallized and activated by annealing a region formed as amorphous Si with laser irradiation. The TFT formed by the LTPS process has a sufficiently high mobility.

[0026] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the regions 104s and 104d. The regions 104s and 104d are doped with boron ions (B + ) and boron fluoride ion (BF2 + ) and is doped with p-type impurities and is in ohmic contact with the vias 111s and 111d.

[0027] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate the gate 107 from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, thereby making it possible to control the current flowing between the regions 104s and 104d.

[0028] The insulating layer 105 is, for example, SiO2. The insulating layer 105 may also be a multi-layer insulating layer including SiO2, Si3N4, etc. depending on the area covered.

[0029] The gate 107 is made of, for example, polycrystalline Si. The polycrystalline Si film of the gate 107 can generally be formed by a CVD (Chemical Vapor Deposition) process.

[0030] In this example, the gate 107 and the insulating layer 105 are covered with an insulating film 108. The insulating film 108 is, for example, SiO2, Si3N4, or the like. The insulating film 108 functions as a planarizing film for forming the wiring layer 110. The insulating film 108 is, for example, a multi-layer insulating film including SiO2, Si3N4, or the like.

[0031] The vias 111s and 111d are provided penetrating the insulating film 108. A first wiring layer (first wiring layer) 110 is formed on the insulating film 108. The first wiring layer 110 includes a plurality of wirings having different potentials, including wirings 110s, 110d, and 110k. In the wiring layers in the cross-sectional views of FIG. 1 and subsequent figures, the reference symbol for the wiring layer is indicated next to one of the wirings included in the wiring layer to which the reference symbol should be applied.

[0032] The via 111s is provided between the wiring 110s and the region 104s to electrically connect them, and the via 111d is provided between the wiring 110d and the region 104d to electrically connect them.

[0033] In this example, the wiring 110s electrically connects the region 104s, which is the source region of the transistor 103, to a power line 3 shown in Fig. 3, which will be described later. The wiring 110d is electrically connected to the p-type semiconductor layer 153-1 on the light emitting surface 153S1 side of the light emitting element 150-1 through a via 161d, a wiring 160a-1, and a light-transmitting electrode 159a1, as will be described later.

[0034] In this example, the wiring 110k is connected to a ground line 4 shown in Fig. 3 described later through a via 161k, the wiring 160k, and a light-transmitting electrode 159k. The wiring 110k is not limited to being connected to the ground line 4, and may be connected to a power line 3 or another potential, or may not be connected to any potential.

[0035] The wiring (second portion) 110k is provided below the light emitting elements 150-1 and 150-2, and functions as a light reflection plate that reflects the light emitted downward by the light emitting elements 150-1 and 150-2. The periphery of the wiring 110k is set to include the entire periphery of the light emitting elements 150-1 and 150-2 when the light emitting elements 150-1 and 150-2 are projected onto the wiring 110k in the XY plane view. By appropriately selecting the material of the wiring 110k, the light scattering downward from the light emitting elements 150-1 and 150-2 can be reflected toward the light emitting surfaces 153S1 and 153S2, improving the light emitting efficiency.

[0036] The wiring 110k reflects the downward scattering of light from the light-emitting element 150-1 toward the light-emitting surface 153S1 side, and therefore can prevent the emitted light from the light-emitting element 150-1 from reaching the transistor 103. The wiring 110k also reflects the downward scattering of light from the light-emitting element 150-2 toward the light-emitting surface 153S2 side, and therefore can prevent the emitted light from the light-emitting element 150-2 from reaching the transistor that drives the light-emitting element 150-2. The wiring 110k blocks the downward scattering light from the light-emitting elements 150-1 and 150-2, thereby suppressing the scattered light from reaching the circuit elements including the transistor 103, and thus preventing malfunction of the circuit elements.

[0037] The wiring layer 110 and the vias 111s, 111d are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0038] An interlayer insulating film 112 is provided on the insulating film 108 and the wiring layer 110. The interlayer insulating film (first insulating film) 112 is an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass). The interlayer insulating film 112 insulates each circuit element in the circuit 101 formed on the circuit board 100, and provides a flat surface for providing the graphene sheets 140-1 and 140-2. The interlayer insulating film 112 also functions as a protective film that protects the surface of the circuit board 100.

[0039] The graphene sheets 140-1 and 140-2 are provided above the wiring 110k via the interlayer insulating film 112. The light emitting element 150-1 is provided on the graphene sheet (first portion including graphene) 140-1, and the light emitting element 150-2 is provided on the graphene sheet 140-2. The outer periphery of the graphene sheet 140-1 approximately coincides with the outer periphery of the light emitting element 150-1. The outer periphery of the graphene sheet 140-2 approximately coincides with the outer periphery of the light emitting element 150-2.

[0040] The light emitting element 150-1 includes an n-type semiconductor layer (first semiconductor layer) 151-1, a light emitting layer 152-1, and a p-type semiconductor layer (second semiconductor layer) 153-1. The n-type semiconductor layer 151-1, the light emitting layer 152-1, and the p-type semiconductor layer 153-1 are laminated in this order from the interlayer insulating film 112 side toward the light emitting surface 153S1 side. The lower part of the n-type semiconductor layer 151-1 has a step portion 151a-1. The step portion 151a-1 is provided so as to protrude toward the light emitting element 150-2 side. The step portion 151a-1 is provided to connect the n-type semiconductor layer 151-1 to the via 161k-1.

[0041] The light emitting element 150-2 includes an n-type semiconductor layer 151-2, a light emitting layer 152-2, and a p-type semiconductor layer 153-2. The n-type semiconductor layer 151-2, the light emitting layer 152-2, and the p-type semiconductor layer 153-2 are laminated in this order from the interlayer insulating film 112 side toward the light emitting surface 153S2 side. The lower part of the n-type semiconductor layer 151-2 has a step portion 151a-2. The step portion 151a-2 is provided so as to protrude toward the light emitting element 150-1 side. The step portion 151a-2 is provided to connect the n-type semiconductor layer 151-2 to the via 161k-2.

[0042] The area of ​​the light emitting element in the XY plane view is set according to the emission color of the red, green, and blue subpixels. The area of ​​the light emitting element 150-1, 150-2 in the XY plane view is appropriately set according to the luminosity factor and the conversion efficiency of the color conversion unit 182 of the color filter 180. In this example, the areas of the two light emitting elements 150-1, 150-2 in the XY plane view are different. Since the light emitting element 150-1, 150-2 is mounted on the wiring 110k having a surface almost parallel to the XY plane, the area in the XY plane view is the area of ​​the region surrounded by the periphery of the light emitting element 150-1, 150-2 projected onto the XY plane. Hereinafter, the area in the XY plane view is simply referred to as the area. In this example, the area of ​​the light emitting element 150-1 is smaller than the area of ​​the light emitting element 150-2.

[0043] In this example, the light emitting elements 150-1 and 150-2 have step portions 151a-1 and 151a-2, respectively. The step portions 151a-1 and 151a-2 are formed by processing the n-type semiconductor layers 151-1 and 151-2, and therefore do not directly contribute to light emission. Therefore, the area of ​​the light emitting elements 150-1 and 150-2 refers to the area of ​​the light emitting layers 152-1 and 152-2 in the XY plane view.

[0044] The light emitting elements 150-1 and 150-2 have, for example, a substantially square or rectangular shape in the XY plane view, but the corners may be rounded. The light emitting element 150 may have, for example, an elliptical or circular shape in the XY plane view. By appropriately selecting the shape and arrangement of the light emitting elements in the plan view, the degree of freedom of layout is improved.

[0045] The light emitting elements 150-1 and 150-2 are, for example, In X Al Y Ga 1-X-Y A gallium nitride compound semiconductor including a light emitting layer such as N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150-1, 150-2 in one embodiment of the present invention is a so-called light emitting diode, and the wavelength of light emitted by the light emitting element 150-1, 150-2 is, for example, about 467 nm±20 nm. The wavelength of light emitted by the light emitting element 150-1, 150-2 may be blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 150-1, 150-2 is not limited to the above-mentioned value, and may be any appropriate value.

[0046] The second interlayer insulating film 156 covers the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light emitting elements 150-1 and 150-2. The interlayer insulating film 156 is formed of an organic insulating material or the like. The interlayer insulating film 156 covers the light emitting elements 150-1 and 150-2 and the graphene sheets 140-1 and 140-2, etc., thereby protecting them from the surrounding environment, such as dust and humidity. The interlayer insulating film 156 covers the light emitting elements 150 and the graphene sheets 140-1 and 140-2, etc., thereby insulating them from other conductive materials. The surface of the interlayer insulating film 156 only needs to be flat enough to allow the wiring layer 160 to be formed on the interlayer insulating film 156.

[0047] The organic insulating material used for the interlayer insulating film 156 is preferably a white resin. The interlayer insulating film 156 made of a white resin reflects light emitted in the lateral direction of the light emitting elements 150-1 and 150-2 and return light caused by the interface of the color filter 180, etc., and can substantially improve the light emitting efficiency of the light emitting elements 150-1 and 150-2.

[0048] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass) or a novolac-type phenol-based resin. The particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting elements 150-1 and 150-2. Particles having a diameter of about 1 / 2 the wavelength of the light are preferably used as the scattering particles. For example, such scattering particles include TiO2, Al2SO3, and ZnO. Alternatively, the white resin can be formed by utilizing a large number of fine voids dispersed in the transparent resin. In the interlayer insulating film 156, instead of SOG or the like, for example, a SiO2 film formed by ALD (Atomic-layer-deposition) or CVD may be used to whiten the film.

[0049] The second interlayer insulating film 156 may be a black resin. By making the interlayer insulating film 156 a black resin, scattering of light in the sub-pixels 20-1 and 20-2 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display sharper images.

[0050] The via 161k-1 is provided so as to penetrate the second interlayer insulating film 156. One end of the via 161k-1 is connected to the step portion 151a-1. 2 is provided penetrating the second interlayer insulating film 156. One end of the via 161k-2 is connected to the step portion 151a-2.

[0051] The via (second via) 161k is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the via 161k is connected to the wiring 110k.

[0052] The via (first via) 161d is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the via 161d is connected to the wiring 110d.

[0053] The wiring layer 160 is provided on the interlayer insulating film 156. The wiring layer 160 includes wirings 160a-1 and 160k. The wiring 160a-1 is connected to the other end of the via 161d.

[0054] The transparent electrode 159a1 is provided over the wiring 160a-1. The transparent electrode 159a1 is provided over the light-emitting surface 153S1 of the light-emitting element 150-1. The transparent electrode 159a1 is provided between the wiring 160a-1 and the light-emitting surface 153S1, and electrically connects the wiring 160a-1 and the p-type semiconductor layer 153-1. Therefore, the p-type semiconductor layer 153-1, which is the anode electrode of the light-emitting element 150-1, is electrically connected to the channel region 104d, which is the drain electrode of the transistor 103, via the transparent electrode 159a1, the wiring 160a-1, the via 161d, and the wiring 110d.

[0055] The transparent electrode 159a2 is provided over the light-emitting surface 153S2 of the light-emitting element 150-2. As in the case of the light-emitting element 150-1, the light-emitting surface 153S2 is electrically connected to a transistor that drives the light-emitting element 150-2 through the transparent electrode 159a2, the wiring included in the wiring layer 160, and vias penetrating the interlayer insulating films 112 and 156. Both of the light-emitting surfaces 153S1 and 153S2 are roughened.

[0056] The wiring 160k is connected to the other ends of the vias 161k, 161k-1, and 161k-2. The transparent electrode 159k is provided over the wiring 160k. The wiring 160k and the transparent electrode 159k are connected to the ground line 4 shown in FIG. 3, which will be described later. Therefore, the n-type semiconductor layers 151-1 and 151-2 are connected to the ground line 4 through the vias 161k-1 and 161k-2, the wiring 160k, and the transparent electrode 159k. In this example, the wiring 110k is connected to the ground line 4 together with the n-type semiconductor layers 151-1 and 151-2.

[0057] A region 104s of the TFT channel 104, which is the source electrode of the transistor 103, is electrically connected to the power supply line 3 shown in FIG. 3 via a wiring 110s.

[0058] The surface resin layer 170 covers the second interlayer insulating film 156, the second wiring layer 160, and the translucent electrodes 159a1, 159a2, and 159k. The surface resin layer 170 is a transparent resin, and protects the second interlayer insulating film 156, the wiring layer 160, and the translucent electrodes 159a1, 159a2, and 159k, and provides a flat surface for bonding the color filter 180.

[0059] The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is a light-emitting surface 153S of the light-emitting elements 150-1 and 150-2. 1, 153S2 in accordance with the shapes of the light emitting surfaces 153S1, 153S2. In the color filter 180, the portion other than the color conversion portion 182 is made into a light shielding portion 181. The light shielding portion 181 is a so-called black matrix, and reduces blurring caused by color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a sharp image.

[0060] Color conversion section 182 is made of one layer or two layers. FIG. 1 shows a two-layer portion. Whether it is a one-layer or two-layer structure is determined by the color, i.e., the wavelength, of the light emitted by sub-pixels 20-1 and 20-2. When the emission color of sub-pixels 20-1 and 20-2 is red or green, color conversion section 182 is preferably made of two layers, including color conversion layer 183 and filter layer 184, which will be described later. When the emission color of sub-pixels 20-1 and 20-2 is blue, color conversion section 182 is preferably made of one layer.

[0061] When color conversion section 182 has two layers, the first layer closer to light emitting elements 150-1 and 150-2 is color conversion layer 183, and the second layer is filter layer 184. That is, filter layer 184 is laminated on color conversion layer 183.

[0062] Color conversion layer 183 is a layer that converts the wavelength of light emitted by light emitting elements 150-1 and 150-2 into a desired wavelength. For example, when the subpixel emits red light, color conversion layer 183 converts light of 467 nm±20 nm, which is the wavelength of light emitting element 150-1, into light of a wavelength of, for example, about 630 nm±20 nm. When the subpixel emits green light, color conversion layer 183 converts light of 467 nm±20 nm, which is the wavelength of the light emitting element, into light of a wavelength of, for example, about 532 nm±20 nm.

[0063] Filter layer 184 blocks the wavelength component of blue emitted light that remains without being color converted by color conversion layer 183 .

[0064] When the color of light emitted by a subpixel is blue, the light emitting element of that subpixel may output light via color conversion layer 183, or may output light directly without passing through color conversion layer 183. When the wavelength of light emitted by the light emitting element is about 467 nm±20 nm, the light emitting element of that subpixel may output light without passing through color conversion layer 183. When the wavelength of light emitted by the light emitting element is 410 nm±20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm±20 nm.

[0065] Even in the case of a blue subpixel, the subpixel may have a filter layer 184. By providing the filter layer 184 to the blue subpixel, minute external light reflection occurring on the surface of the light-emitting element of the subpixel is suppressed.

[0066] (Modification) A modification of the sub-pixel configuration will now be described. 2A and 2B are schematic cross-sectional views illustrating a part of a modified example of the image display device of this embodiment. Fig. 2A shows one light-emitting element 150-1 of the two light-emitting elements 150-1 and 150-2 shown in Fig. 1. The configuration including the two light-emitting elements 150-1 and 150-2 is the same, and the following description of this modification includes the configuration including the light-emitting element 150-1. Also in Fig. 2B, the configuration including one light-emitting element 150a-1 of the two light-emitting elements will be described.

[0067] In the cross-sectional views of the subpixels in Fig. 2A and subsequent figures, the surface resin layer 170 and the color filter 180 are omitted to avoid complexity. In the subsequent figures, unless otherwise specified, the surface resin layer 170 and the color filter 180 are provided on the second interlayer insulating films 156, 256 and the second wiring layer 160. Similarly, in the cases of other embodiments and their modified examples described later, the surface resin layer 170 and the color filter 180 are omitted.

[0068] 2A, the method of connecting the light emitting element 150-1 and the wiring 160a1-1 is different from that in the first embodiment. The same components are denoted by the same reference numerals and detailed description will be omitted as appropriate. 2A, the subpixel 20a-1 includes a wiring 160a1-1. The wiring 160a1-1 extends to the light-emitting surface 153S1 of the light-emitting element 150-1, and one end of the wiring 160a1-1 is electrically connected to the surface of the p-type semiconductor layer 153-1 including the light-emitting surface 153S1. The light-emitting surface 153S1 and the surface including the light-emitting surface 153S1 are on the same plane.

[0069] As in the above-described embodiment, the light-emitting surface 153S1 is preferably roughened as in this example. When the light-emitting surface 153S1 of the light-emitting element 150-1 is roughened, the light extraction efficiency can be improved.

[0070] In the subpixel 20b-1 of FIG. 2B, the light-emitting element 150a-1 differs from that in the first embodiment in that it includes a p-type semiconductor layer 153a-1 that is not roughened. In the subpixel 20b-1, the method of connecting the light-emitting element 150a-1 and the wiring 160a2-1 differs from that in the first embodiment. The subpixel 20b-1 of this modification includes a second interlayer insulating film (second insulating film) 256 that is different from that in the first embodiment.

[0071] As shown in FIG. 2B, in the subpixel 20b-1, the second interlayer insulating film 256 is a resin having light-transmitting properties, preferably a transparent resin. Examples of the transparent resin material include silicon-based resin such as SOG and novolac-type phenol-based resin. The light-emitting element 150a-1 emits light from the light-emitting surface 153S1 through the transparent interlayer insulating film 256. The light-emitting surface 153S1 is connected to the wiring 160a2-1 of the second wiring layer 160 through a contact hole.

[0072] In the subpixel 20b-1 of this modified example, the light-emitting element 150a-1 emits light from the light-emitting surface 153S1 through the interlayer insulating film 256, so that the process of forming an opening in the interlayer insulating film 256 and the process of roughening the light-emitting surface 153S1 can be omitted.

[0073] This embodiment may include any of the configurations of the sub-pixels 20-1, 20a-1, and 20b-1 described above.

[0074] FIG. 3 is a schematic block diagram illustrating the image display device according to the present embodiment. 3, the image display device 1 of this embodiment includes a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged, for example, in a lattice pattern. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

[0075] A pixel 10 includes a number of sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 20R, 20G, and 20B emitting light at a desired brightness.

[0076] One pixel 10 includes three sub-pixels 20R, 20G, and 20B, which are arranged linearly on the X-axis, as in the example shown in Fig. 3. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or sub-pixels of different colors may be arranged in each column, as in this example.

[0077] The image display device 1 further includes a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and supply power to each sub-pixel 20 from a DC power supply connected between a power supply terminal 3a and a GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with respect to the GND terminal 4a.

[0078] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction arrangement of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction arrangement of the sub-pixels 20.

[0079] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0080] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0081] The subpixel 20 includes a light emitting element 22, a select transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3, the select transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0082] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and an anode electrode connected to the p-type semiconductor layer of the light-emitting element 22 is connected to a drain electrode, which is a main electrode of the driving transistor 26. A series circuit of the light-emitting element 22 and the driving transistor 26 is connected between a power supply line 3 and a ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1 and the like, and the light-emitting element 22 corresponds to the light-emitting elements 150, 150a in FIG. 1 and the like. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a luminance according to the current flowing therethrough.

[0083] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a power line 3.

[0084] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light with a luminance corresponding to the current passing through the light-emitting element 22.

[0085] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned sub-pixels 20, causing them to emit light. Each pixel 10 emits light with a color and brightness determined by the color and brightness emitted by the RGB sub-pixels 20, and an image is displayed in the display area 2.

[0086] FIG. 4 is a schematic plan view illustrating a part of the image display device of the present embodiment. In this embodiment, as described in FIG. 1, the light emitting element 150-1 (light emitting element 22 in FIG. 3) and the driving transistor 103 (driving transistor 26 in FIG. 3) are stacked in the Z-axis direction. The anode electrode of the light emitting element 150-1 is electrically connected to the drain electrode of the transistor 103 by a via 161d. The cathode electrode of the light emitting element 150-1 is electrically connected to the ground line 4 shown in FIG. 3 by a via 161k-1. Similarly, the anode electrode and the cathode electrode of the light emitting element 150-2 are electrically connected to a predetermined circuit through vias. FIG. 4 shows a schematic diagram of the three-dimensional configuration broken down into two plan views.

[0087] In the upper part of FIG. 4, a plan view of the I layer is typically shown, and in the lower part, a plan view of the II layer is typically shown. In FIG. 4, the I layer is denoted as "I" and the second layer is denoted as "II". The I layer is a layer in which the light emitting elements 150-1 and 150-2 are formed. That is, the I layer indicates an element on the positive side of the Z axis from the first interlayer insulating film 112 in FIG. 1, and the element shown in FIG. 4 is a layer from the graphene sheets 140-1 and 140-2 to the second wiring layer 160. The second interlayer insulating film 156 is not shown in FIG. 4.

[0088] 1, the II layer indicates an element on the positive side of the Z axis from the TFT lower film 106, and the elements shown in Fig. 4 are layers from the transistor 103 to the first interlayer insulating film 112. In Fig. 4, the substrate 102, the insulating layer 105, the insulating film 108, and the first interlayer insulating film 112 are not shown.

[0089] The cross-sectional view of FIG. 1 is a cross-section taken along line AA' shown by a dashed broken line in each of layers I and II of FIG.

[0090] In this embodiment, the wiring 160k of the I layer is provided extending along the Y-axis direction, passing between the light emitting elements 150-1 and 150-2. The wiring 110s of the II layer extends in the positive direction of the Y-axis on substantially the same X coordinate as the wiring 160k. The wiring 110s is bent in the X-axis direction to avoid the wiring 110k, extends in the X-axis direction along the outer periphery of the wiring 110k, and then bent again in the Y-axis direction. After being bent in the Y-axis direction, the wiring 110s extends in the positive direction of the Y-axis along the outer periphery of the wiring 110k.

[0091] The line AA' crosses the wiring 160k, the translucent electrode 159k, and the wiring 110s on the negative side in the Y-axis direction of the light emitting elements 150-1 and 150-2 and the wiring 110k. That is, in Fig. 1, the wiring 160k, the translucent electrode 159k, and the wiring 110s should be shown on the A side of the line AA', but in order to avoid complicating the drawing, the wiring 160k and the translucent electrode 159k are omitted from the drawing in the B region. The same applies to other embodiments described below.

[0092] As shown in Fig. 4, the light emitting elements 150-1 and 150-2 are provided above the wiring 110k. The wiring 110k is connected to the via 161k shown in Fig. 1 in the II layer. The via 161k is connected to the wiring 160k by a via hole 162k.

[0093] One end of the via 161k-1 shown in FIG. 1 is connected to the step portion 151a-1 of the light emitting element 150-1. The other end of the via 161k-1 is connected to the wiring 160k through a via hole 162k-1. One end of the via 161k-2 shown in FIG. 1 is connected to the step portion 151a-2 of the light emitting element 150-2. The other end of the via 161k-2 is connected to the wiring 160k through a via hole 162k-2. The translucent electrode 159k is provided over the wiring 160k, and the wiring 160k and the translucent electrode 159k are connected to the ground line 4.

[0094] The light emitting element 150-1 has an opening 158-1 provided in the interlayer insulating film 156 shown in FIG. 1. In this example, the via 161d is provided adjacent to the light emitting element 150-1, spaced apart in the negative direction of the X-axis. The via 161d is shown in FIG. 4 by a two-dot chain line. In the I layer, the via 161d is connected to the wiring 160a-1 by a contact hole 162d1. The transparent electrode 159a1 is provided over the light emitting element 150-1 and the wiring 160a-1 exposed from the opening 158-1, and electrically connects the light emitting element 150-1 and the via 161d. In the II layer, the via 161d is connected to the wiring 110d by a contact hole 162d2.

[0095] 1 through a contact hole 111c1 opened in the insulating film 108 shown in FIG. 1, and is connected to the drain electrode provided on the TFT channel 104 of the transistor 103.

[0096] In this manner, the via 161d penetrating the two interlayer insulating films 112, 156 electrically connects the light emitting element 150-1 formed in the layer I to the wiring 110d formed in the layer II, which is a layer different from the layer I, and electrically connects the light emitting element 150-1 to the transistor 103. Similarly, the interlayer connection between the light emitting element 150-2 and the transistor that drives the light emitting element 150-2 is also made via a via provided penetrating the two interlayer insulating films.

[0097] The arrangement of the wiring 110k and the light emitting elements 150-1 and 150-2 in the case where the wiring 110k reflects the downward scattered light of the light emitting elements 150-1 and 150-2 toward the light emitting surfaces 153S1 and 153S2 will be described with reference to FIG. The wiring 110k is rectangular with a length L1 in the X-axis direction and a length W1 in the Y-axis direction in the XY plane. Meanwhile, the light emitting element 150-1 has a rectangular bottom surface with a length L21 in the X-axis direction and a length W2 in the Y-axis direction in the XY plane. The light emitting element 150-2 has a rectangular bottom surface with a length L22 in the X-axis direction and a length W2 in the Y-axis direction in the XY plane.

[0098] The length of each part is set so that L1>L21, L1>L22, and W1>W2. That is, the area of ​​the wiring 110k is set to be larger than the sum of the areas of the light-emitting elements 150-1 and 150-2. The wiring 110k is provided directly below the light-emitting elements 150-1 and 150-2, and the periphery of the wiring 110k includes the entire periphery of the light-emitting elements 150-1 and 150-2. It is sufficient that the periphery of the wiring 110k includes the entire periphery of the light-emitting elements 150-1 and 150-2, and the shape of the wiring 110k is not limited to a square shape and can be any appropriate shape depending on the layout on the circuit board 100, etc.

[0099] The light emitting elements 150-1 and 150-2 emit light upward, and also emit light downward, and there is reflected light and scattered light at the interface between the interlayer insulating film 112 and the surface resin layer 170. The wiring layer 110 includes wiring 110k. Since the wiring layer 110 is formed of a conductor such as metal, the wiring 110k has light reflectivity according to the material. Therefore, the scattered light downward from the light emitting elements 150-1 and 150-2 is reflected upward by the wiring 110k. Therefore, the proportion of the light emitted from the light emitting elements 150-1 and 150-2 that is distributed toward the light emitting surfaces 153S1 and 153S2 increases, and the substantial light emitting efficiency of the light emitting elements 150-1 and 150-2 is improved. Furthermore, by providing the wiring 110k in this manner, the light reaching the lower side of the light emitting elements 150-1 and 150-2 is suppressed. Therefore, even when the circuit elements are disposed immediately below and in the vicinity of the light emitting elements 150-1 and 150-2, the influence of light on the circuit elements is reduced.

[0100] As described above, the wiring 110k is not limited to being connected to the ground line 4, but may be connected to another potential such as the potential of the power supply line 3 depending on the circuit configuration and circuit layout.

[0101] A method for manufacturing the image display device 1 of this embodiment will be described. 5A to 7B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. 5A, in the manufacturing method of the image display device 1 of this embodiment, a circuit board 1100 is prepared. The circuit board (first board) 1100 includes the circuit 101 described in FIG. 1 and the like. The circuit 101 includes a first wiring layer 110, and the wiring layer 110 includes wirings 110s, 110d, and 110k. In the circuit board 1100, a first interlayer insulating film 112 is provided so as to cover the wiring layer 110.

[0102] As shown in FIG. 5B, a graphene layer 1140 is formed on an interlayer insulating film (first insulating film) 112. The graphene layer 1140 is a layer containing graphene, and is preferably formed by stacking a single layer of graphene. The graphene layer 1140 cut to an appropriate size and shape is bonded onto the interlayer insulating film 112, for example, by an adhesive. In this case, the graphene layer 1140 is preferably cut to a size sufficiently larger than the area of ​​the light emitting elements 150-1 and 150-2 formed on the graphene layer 1140 and bonded onto the interlayer insulating film 112. In order to form the light emitting elements 150-1 and 150-2 on the graphene layer 1140, for example, the outer periphery of the graphene layer 1140 is set to a sufficient size including the outer periphery of the wiring 110k.

[0103] As shown in FIG. 6A, the semiconductor layer 1150 is formed over the graphene layer 1140 that is cut to an appropriate size and shape and attached to the interlayer insulating film 112. The semiconductor layer 1150 is formed in the order of an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153 from the graphene layer 1140 side toward the positive direction of the Z axis. In the initial stage of growth of the semiconductor layer 1150, crystal defects due to mismatching of crystal lattices are likely to occur, and crystals mainly composed of GaN generally exhibit n-type semiconductor characteristics. Therefore, by growing the n-type semiconductor layer 1151 on the graphene layer 1140, it is possible to improve the yield.

[0104] The semiconductor layer 1150 is formed by physical vapor deposition such as evaporation, ion beam deposition, molecular beam epitaxy (MBE) or sputtering, and preferably by low-temperature sputtering. In the low-temperature sputtering, the temperature can be lowered by using light or plasma as an assist during film formation, which is preferable. In epitaxial growth by MOCVD, the temperature may exceed 1000°C. In contrast, it is known that the low-temperature sputtering method can epitaxially grow GaN crystals including a light-emitting layer on the graphene layer 1140 at a low temperature of about 400°C to about 700°C (see Non-Patent Documents 1 and 2, etc.). Such a low-temperature sputtering method is suitable for forming the semiconductor layer 1150 on a circuit board having TFTs and the like formed by the LTPS process. A semiconductor layer 1150 of GaN is grown on the graphene layer 1140 using an appropriate deposition technique, thereby forming a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 on the graphene layer 1140. The graphene layer 1140 is cut to an appropriate size and shape and attached, so that a non-single-crystallized deposit 1160 including GaN is formed in the areas where the graphene layer 1140 is not present, as shown by the dashed line in FIG. 6A.

[0105] In this embodiment, the graphene layer 1140 is used as a seed to promote the crystal growth of GaN. A conductive buffer layer may be provided on the graphene layer 1140, and a semiconductor layer may be grown on the buffer layer by the above-mentioned sputtering method or the like. The buffer layer may be of any type as long as it is made of a material that promotes the crystal growth of GaN. For example, a metal layer containing a single crystal of Hf, Cu, or the like may be used as the buffer layer.

[0106] As shown in Fig. 6B, the semiconductor layer 1150 is formed into a desired shape by RIE (Reactive Ion Etching) or the like, to form the light emitting elements 150-1 and 150-2. At this time, the graphene layer 1140 shown in Fig. 6A is over-etched to form the graphene sheets 140-1 and 140-2 having peripheral shapes corresponding to the peripheral shapes of the light emitting elements 150-1 and 150-2. In this example, the area of ​​the light emitting element 150-1 in the XY plane view is set to be smaller than the area of ​​the light emitting element 150-2 in the XY plane view.

[0107] Thereafter, a second interlayer insulating film (second insulating film) 156 is formed to cover the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light emitting elements 150-1 and 150-2.

[0108] As shown in FIG. 7A, the via holes 162k-1 and 162k-2 are formed penetrating the second interlayer insulating film 156. The via holes 162d and 162k are formed penetrating the interlayer insulating films 112 and 156. At the same time as the via holes 162k, 162k-1, 162k-2 and 162d are formed, the openings 158-1 and 158-2 are formed in the interlayer insulating film 156, and the light emitting surfaces 153S1 and 153S2 are exposed. The openings 158-1 and 158-2 may be formed before the via holes 162k, 162k-1, 162k-2 and 162d are formed, or may be formed after the via holes 162k, 162k-1, 162k-2 and 162d are formed. The exposed light emitting surfaces 153S1 and 153S2 are roughened.

[0109] As shown in FIG. 7B, the via holes 162d, 162k, 162k-1, and 162k-2 shown in FIG. 7A are filled with a conductive material. Thereafter, or simultaneously with filling the via holes, the second wiring layer 160 is formed. A transparent electrode 159a1 is formed over the light-emitting surface 153S1 and the wiring 160a-1, and the p-type semiconductor layer 153-1 and the wiring 160a-1 are electrically connected. At the same time, a transparent electrode 159a2 is formed over the light-emitting surface 153S2, and the transparent electrode 159a2 is electrically connected to an electrode for a driving transistor other than the transistor 103. A transparent electrode 159k is also formed on the wiring 160k.

[0110] As described above, the interlayer insulating film 156 only needs to cover the light emitting elements 150-1, 150-2, etc., for insulation. The flatness of the interlayer insulating film 156 is sufficient to allow the second wiring layer 160 to be formed on the interlayer insulating film 156, and the interlayer insulating film 156 does not need to be flattened during formation. If the interlayer insulating film 156 is not flattened, the step for flattening can be eliminated, and the thickness of the interlayer insulating film 156 can be thinned in areas other than where the light emitting elements 150-1, 150-2 are formed. In areas where the thickness of the interlayer insulating film 156 is thin, the depth of the via holes 162k, 162k-1, 162k-2, 162d can be shallowed. By forming the via holes shallow, a sufficient opening diameter can be ensured throughout the depth of the via holes, making it easier to ensure electrical connection by the vias. Therefore, a decrease in yield due to poor electrical characteristics can be suppressed.

[0111] 8A and 8B are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of this embodiment.

[0112] 8A and 8B show a manufacturing process for forming the subpixel shown in FIG. 2A. In this modification, the process is the same as that of the other embodiments described above until the openings 158-1 and 158-2 are formed. Therefore, in the following, the manufacturing process of this modification will be described assuming that the steps of FIG. 8A and FIG. 8B are performed after FIG. 7A.

[0113] As shown in Fig. 8A, openings 158-1 and 158-2 are formed to expose light emitting surfaces 153S1 and 153S2 of p-type semiconductor layers 153-1 and 153-2, and then the light emitting surfaces 153S1 and 153S2 are roughened. The via holes 162k-1 and 162k-2 shown in Fig. 7A are filled with a conductive material to form vias 161k-1 and 161k-2, respectively. The via holes 162d and 162k shown in Fig. 7A are filled with a conductive material to form vias 161d and 161k, respectively.

[0114] 8B, a wiring layer 160 including wirings 160a1-1, 160a1-2, and 160k is formed on the interlayer insulating film 156. The wiring 160a1-1 is connected to a surface including the exposed light emitting surface 153S1. The wiring 160a1-2 is connected to a surface including the exposed light emitting surface 153S2.

[0115] In this manner, the sub-pixels 20a-1 and 20a-2 of the modified example are formed.

[0116] 9A and 9B are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of this embodiment. 9A and 9B show a manufacturing process for forming the subpixel shown in FIG. 2B. This modification has the same processes as the other embodiments described above up to the formation of the light-emitting element. Therefore, in the following, the manufacturing process of this modification will be described assuming that the processes of FIG. 6A and FIG. 9A and FIG. 9B are executed after FIG. 6A. In the other embodiments, the interlayer insulating film 156 is formed of an opaque insulating material such as white resin, whereas in this modification, the interlayer insulating film 256 is formed of an insulating material having light transparency, as described above.

[0117] As shown in FIG. 9A, the semiconductor layer 1150 shown in FIG. 6A is formed into a desired shape by RIE or the like, and the light emitting elements 150a-1 and 150a-2 are formed. At this time, the graphene layer 1140 shown in FIG. 6A is formed into the graphene sheets 140-1 and 140-2 having an outer periphery corresponding to the outer periphery shape of the light emitting elements 150a-1 and 150a-2 by over-etching the semiconductor layer 1150. Thereafter, the second interlayer insulating film 256 is formed to cover the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light emitting elements 150a-1 and 150a-2. The interlayer insulating film 256 is an insulating resin having light transmitting properties, and is preferably a transparent resin.

[0118] Contact holes 162a-1 and 162a-2 are formed in the second interlayer insulating film 256. Via holes 162k-1 and 162k-2 are formed penetrating the interlayer insulating film 256. Via holes 162d and 162k are formed penetrating the interlayer insulating films 112 and 156. The contact holes and via holes are formed by, for example, RIE or the like.

[0119] As shown in FIG. 9B, the contact holes 162a-1 and 162a-2 and the via holes 162d, 162k, 162k-1 and 162k-2 shown in FIG. 9A are filled with a conductive material. Then, the second wiring layer 160 is formed, and the wirings 160a2-1, 160a2-2 and 160k are formed. The wiring 160a2-1 is connected to the p-type semiconductor layer 153a-1 at one end and connected to the wiring 110d through the via 161d at the other end. The wiring 160a2-2 is connected to the p-type semiconductor layer 153a-2 at one end and connected to a wiring for another driving transistor through a via at the other end. The second wiring layer 160 may be formed at the same time that the conductive material is filled in the via holes 162d and 162k.

[0120] In this manner, the sub-pixels 20b-1 and 20b-2 of the modified example are formed.

[0121] A part of the circuit other than the subpixels 20-1 and 20-2 is formed in the circuit board 1100. For example, the row selection circuit 5 shown in FIG. 3 is formed in the circuit board 1100 together with the driving transistors, the selection transistors, and the like. That is, the row selection circuit 5 may be simultaneously incorporated in the above-mentioned manufacturing process. On the other hand, the signal voltage output circuit 7 is preferably incorporated in a semiconductor device manufactured by a manufacturing process capable of high integration by microfabrication. The signal voltage output circuit 7 is mounted on a separate board together with a CPU and other circuit elements, and is mutually connected to the wiring of the circuit board 1100, for example, before or after the incorporation of a color filter described later.

[0122] For example, the circuit board 1100 includes a light-transmitting substrate 102 made of a glass substrate including a circuit 101, and the substrate 102 is substantially rectangular. The circuit 101 for one or a plurality of image display devices is formed on the circuit board 1100. In the case of a larger screen size or the like, the circuit 101 for constituting one image display device may be divided and formed on a plurality of circuit boards 1100, and the divided circuits may be combined to form one image display device.

[0123] The circuit board 1100 includes one substrate 102, and a plurality of circuits 101 are arranged on the substrate 102, for example in a grid pattern. The circuits 101 include all the sub-pixels 20 and the like required for one image display device 1. A gap of approximately the width of a scribe line is provided between adjacently arranged circuits 101. No circuit elements or the like are arranged at or near the ends of the circuits 101.

[0124] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In FIG. 10, in order to avoid complication, the structure in the circuit board 1100, the interlayer insulating film 112, the vias 161d, 161k, 161k-1, 161k-2, the wiring layer 160, and the like shown in FIG. 1 and the like are omitted. Also, FIG. 10 shows a part of the color conversion member such as the color filter 180. In FIG. 10, a structure including the graphene sheets 140-1, 140-2, the light emitting elements 150-1, 150-2, the interlayer insulating film 156, the surface resin layer 170, and the vias, the illustration of which is omitted, is called a light emitting circuit section 172. Also, a structure in which the light emitting circuit section 172 is provided on the circuit board 1100 is called a structure 1192.

[0125] 10, one surface of color filter (wavelength conversion member) 180 is bonded to a structure 1192. The other surface of color filter 180 is bonded to a glass substrate 186. A transparent thin film adhesive layer 188 is provided on one surface of color filter 180, and color filter 180 is bonded to the surface of structure 1192 on the light emitting circuit section 172 side via transparent thin film adhesive layer 188.

[0126] In this example, color filter 180 has color conversion parts arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, red color conversion layer 183R is provided in the first layer. For green, green color conversion layer 183G is provided in the first layer. For blue, blue color conversion layer 183B is provided in the first layer. In each case, filter layer 184 is provided in the second layer, but it goes without saying that the frequency characteristics of filter layer 184 can be changed for each color of color conversion part. For blue, a single layer color conversion layer 183B may be provided. Light shielding parts 181 are provided between each color conversion part.

[0127] The color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183 R, 183 G, and 183 B of each color with the position of the light emitting element 150 .

[0128] 11A to 11D are schematic cross-sectional views showing a modified example of the manufacturing method for the image display device of this embodiment. 11A to 11D show a method for forming a color filter by inkjet printing.

[0129] As shown in FIG. 11A, a structure 1192 is prepared in which a light emitting circuit section 172 is attached to a circuit board 1100.

[0130] 11B, light shielding portion 181 is formed on structure 1192. Light shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.

[0131] As shown in FIG. 11C, phosphors corresponding to the luminescent color are ejected from the inkjet nozzle to form the color conversion layer 183. The phosphors color the areas where the light-shielding portion 181 is not formed. For example, fluorescent paint using a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material is used as the phosphor. When a perovskite phosphor material or a quantum dot phosphor material is used, each luminescent color can be realized, and monochromaticity and color reproducibility are high, which is preferable. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0132] As already explained, for blue-emitting subpixels, if no color conversion section is formed, no phosphor is ejected. Also, for blue-emitting subpixels, if only one color conversion section is required when forming a blue color conversion layer, the thickness of the coating of the blue phosphor is preferably approximately the same as the thickness of the light-shielding section 181.

[0133] 11D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coatings is approximately the same as the thickness of the light-shielding portion 181.

[0134] The effects of the image display device 1 of this embodiment will be described. In the manufacturing method of the image display device 1 of this embodiment, circuit elements such as the transistor 103 for driving the light emitting elements 150-1 and 150-2 are formed in advance on the circuit board 1100, and the graphene layer 1140 is formed on the interlayer insulating film 112 of the circuit board 1100. Furthermore, the semiconductor layer 1150 is grown on the graphene layer 1140. The crystal-grown semiconductor layer 1150 is shaped into a desired shape together with the graphene layer 1140, so that the light emitting elements 150-1 and 150-2 can be formed on the graphene sheets 140-1 and 140-2, respectively. Therefore, the process of transferring the light emitting elements 150-1 and 150-2 can be shortened compared to the case of individually transferring the individual light emitting elements to the circuit board 1100.

[0135] For example, in an image display device with 4K resolution, the number of subpixels exceeds 24 million, and in the case of an image display device with 8K resolution, the number of subpixels exceeds 99 million. If such a large number of light-emitting elements are individually mounted on a circuit board, it will take a huge amount of time, making it difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, if a large number of light-emitting elements are individually mounted, the yield will decrease due to poor connections during mounting, and further cost increases will be unavoidable.

[0136] In contrast, in the manufacturing method of the image display device 1 of this embodiment, the entire semiconductor layer 1150 is grown on the graphene layer 1140 formed on the circuit substrate 1100, and then the light-emitting elements 150-1 and 150-2 are formed, thereby eliminating the transfer process of the light-emitting elements.

[0137] Since the semiconductor layer 1150 grows with a uniform crystal structure on the graphene layer 1140, the light-emitting elements can be arranged in a self-aligned manner by making the graphene layer 1140 an appropriate size and shape. Therefore, there is no need to align the light-emitting elements on the circuit board 1100, and the light-emitting elements 150-1 and 150-2 can be easily miniaturized, which is suitable for a high-definition display.

[0138] After the light-emitting element is formed directly on the circuit board by etching or the like, the light-emitting element is electrically connected to the circuit element in the circuit board 1100 by forming a via, thereby realizing a uniform connection structure and suppressing a decrease in yield.

[0139] In this embodiment, for example, a TFT formed on a glass substrate can be used as the circuit substrate 1100, so that existing flat panel manufacturing processes and plants can be used.

[0140] In the image display device 1 of this embodiment, the first wiring layer 110 includes a wiring 110k. The wiring 110k is formed in advance at a location of the circuit board 1100 where the light emitting elements 150-1 and 150-2 are formed. Therefore, the light scattered downward from the light emitting elements 150-1 and 150-2 is reflected by the wiring 110k and distributed to the light emitting surfaces 153S1 and 153S2 side. Therefore, the light emitting efficiency of the light emitting elements 150-1 and 150-2 is substantially improved.

[0141] The wiring 110k can block light scattered downward from the light emitting elements 150-1 and 150-2, thereby suppressing irradiation of light onto circuit elements located below and in the vicinity of the light emitting elements 150-1 and 150-2, and preventing malfunction of the circuit elements.

[0142] Second Embodiment FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. FIG. 12 shows a cross section taken along line AA′ in FIG. This embodiment differs from the other embodiments described above in that one light emitting element 250 is provided on one wiring 210a. In addition, this embodiment differs from the other embodiments described above in the configuration of the light emitting element 250 and the configuration of the transistor 203 that drives the light emitting element. The same components as those in the other embodiments described above are given the same reference numerals and detailed description will be omitted as appropriate.

[0143] 12, in a subpixel 220 of the image display device of this embodiment, the first wiring layer 110 includes a wiring 210a. The wiring (second portion) 210a is provided below the light-emitting element 250 via an interlayer insulating film 112. The periphery of the wiring 210a is set so as to include the periphery of the light-emitting element 250 when the light-emitting element 250 is projected onto the wiring 210a.

[0144] A graphene sheet 140 is provided above the wiring 210a. The light emitting element 250 is provided on the graphene sheet 140.

[0145] In this embodiment, the light emitting element 250 has a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251 laminated in this order from the first interlayer insulating film 112 side toward the light emitting surface 251S side. In this embodiment, the n-type semiconductor layer 251 is the light emitting surface 251S.

[0146] The light emitting surface 251S is a surface of the n-type semiconductor layer 251 that faces a surface that is in contact with the light emitting layer 252. All of the light emitting surfaces 251S are roughened.

[0147] The light emitting element 250 may be made of the same materials as in the other embodiments described above. The light emitting element 250 emits, for example, blue light with a wavelength of about 467 nm±20 nm or blue-violet light with a wavelength of 410 nm±20 nm.

[0148] The second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112, the graphene sheet 140, and the light emitting element 250. The second interlayer insulating film 156 has an opening 258. The opening 258 is formed on the light emitting element 250, and the interlayer insulating film 156 is not provided on the light emitting surface 251S.

[0149] In this example, the transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. The TFT channel 204 is a region of polycrystalline Si formed on the first surface 102a of the substrate 102, and is polycrystallized and activated by annealing the region formed as amorphous Si with laser irradiation. The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are all provided on the TFT lower layer film 106. The region 204i is provided between the regions 204s and 204d. The regions 204s and 204d are doped with n-type impurities such as phosphorus (P), and are ohmic-connected to the vias 111s and 111d.

[0150] The gate 107 is provided on the TFT channel 204 via the insulating layer 105. When a potential higher than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i, thereby controlling the current flowing between the regions 204s and 204d.

[0151] The structure of the upper part of the transistor 203 and the structure of the wiring layer 110 are the same as those in the other embodiments described above.

[0152] The via 261a1 is provided so as to penetrate the interlayer insulating film 156. One end of the via 261a1 is connected to the step portion 253a.

[0153] The via 261a is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the via 261a is connected to the wiring 210a.

[0154] The second wiring layer 160 includes wirings 260a and 260k. The other ends of the vias 261a1 and 261a are connected to the wiring 260a. The wiring 260a is electrically connected to, for example, a power supply line 3 in FIG. 13, which will be described later. The wiring 210a is electrically connected to the power supply line 3 through the via 261a and the wiring 260a.

[0155] One end of the via 161d is connected to the wiring 110d, and the other end of the via 161d is connected to the wiring 260k. One end of the wiring 260k is connected to the surface of the n-type semiconductor layer 251 having the light emitting surface 251S. Therefore, the n-type semiconductor layer 251 is electrically connected to the region 204d corresponding to the drain electrode of the transistor 203 through the wiring 260k, the via 161d, and the wiring 110d.

[0156] A region 204s which is the source electrode of the transistor 203 is connected to a wiring 110s through a via 111s. The wiring 110s is connected to, for example, a ground line 4 in FIG.

[0157] FIG. 13 is a schematic block diagram illustrating an image display device according to this embodiment. 13, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, sub-pixels 220 are arranged in a lattice pattern on the XY plane.

[0158] As in the other embodiments described above, pixel 10 includes multiple sub-pixels 220 that emit different colored light. Sub-pixel 220R emits red light. Sub-pixel 220G emits green light. Sub-pixel 220B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 220R, 220G, and 220B emitting light at a desired brightness.

[0159] One pixel 10 is composed of three sub-pixels 220R, 220G, and 220B, which are arranged linearly on the X-axis, as in this example. Each pixel 10 may have sub-pixels of the same color arranged in the same column, or, as in this example, sub-pixels of different colors arranged in each column.

[0160] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 13, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0161] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the ground line 4 side. In other words, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0162] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0163] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity from that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

[0164] In this embodiment, the polarity of the driving transistor 226 is n-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the sub-pixel 220 of the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light with a luminance corresponding to the current that has passed.

[0165] A method for manufacturing the image display device of this embodiment will be described. 14A to 15B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In this embodiment, the process is the same as the other embodiments described above up to the formation of the graphene layer 1140 on the circuit board 1100. The following describes the manufacturing process of this embodiment from the process shown in FIG.

[0166] 14A, the semiconductor layer 1150 is formed over the graphene layer 1140. In this embodiment, the semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151 formed in this order from the graphene layer 1140 side toward the positive direction of the Z axis.

[0167] As in the other embodiments, the semiconductor layer 1150 is formed by a physical vapor deposition method such as evaporation, ion beam deposition, MBE, or sputtering, and preferably by low-temperature sputtering. By growing the GaN semiconductor layer 1150 on the graphene layer 1140, the single-crystallized semiconductor layer 1150 including the light-emitting layer 1152 is stably formed on the graphene layer 1140 even from the p-type semiconductor layer 1153 (see Non-Patent Documents 1 and 2, etc.).

[0168] 14B, the semiconductor layer 1150 is shaped into a necessary shape by RIE or the like to form the light emitting element 250. Thereafter, a second interlayer insulating film 156 is formed to cover the first interlayer insulating film 112, the graphene sheet 140, and the light emitting element 250.

[0169] As shown in FIG. 15A, the via hole 262a1 is formed penetrating the second interlayer insulating film 156. The via holes 262a, 162d are formed penetrating the interlayer insulating films 112, 256. At the same time as the via holes 262a1, 262a, 162d are formed, an opening 258 is formed in the interlayer insulating film 156 to expose the light emitting surface 251S. The exposed light emitting surface 251S is roughened. The opening 258 may be formed before the via holes 262a1, 262a, 162d are formed, or may be formed after the via holes 262a1, 262a, 162d are formed.

[0170] As shown in Fig. 15B, the via holes 262a1, 262a, and 162d shown in Fig. 15A are filled with a conductive material to form vias 261a1, 261a, and 161d. After that, or at the same time as filling the via holes 262a1, 262a, and 162d with the conductive material, the second wiring layer 160 is formed. In this example, one end of the wiring 260k is connected to the surface including the light emitting surface 251S.

[0171] Thereafter, color filters are formed in the same manner as in the other embodiments.

[0172] In this manner, the image display device 201 of this embodiment can be manufactured.

[0173] The effects of the image display device 201 of this embodiment will be described. In addition to the effects of the other embodiments described above, the present embodiment has the following further effects. That is, in the present embodiment, the semiconductor layer 1150 is grown on the graphene layer 1140, so that even a p-type semiconductor layer can be stably grown. Therefore, the yield of the image display device can be improved.

[0174] (Third embodiment) In the image display device of this embodiment, circuit elements such as transistors are formed on a flexible substrate instead of a glass substrate. In other respects, the image display device is similar to the other embodiments described above, and the same components are denoted by the same reference numerals and detailed descriptions thereof are omitted as appropriate. FIG. 16 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. FIG. 16 shows a cross section taken along line AA′ in FIG.

[0175] As shown in Fig. 16, the image display device of this embodiment includes subpixels 320-1 and 320-2. The subpixels 320-1 and 320-2 include a common substrate 402. The substrate 402 includes a first surface 402a. Circuit elements such as transistors 103 are provided on the first surface 402a. In the subpixels 320-1 and 320-2, an upper structure including the circuit elements is formed on the first surface 402a.

[0176] The substrate 402 is flexible. The substrate 402 is formed of, for example, polyimide resin. The interlayer insulating films 112, 156 and the wiring layers 110, 160 are preferably formed of materials having a certain degree of flexibility according to the flexibility of the substrate 402. The wiring layer 110, which has the longest wiring length, is at the highest risk of being broken when bent. Therefore, it is desirable to adjust the thickness, material, and quality of each film so that the neutral plane, including multiple protective films added to the front and back surfaces as necessary, is located at the position of the wiring layer 110.

[0177] In this example, the transistor 103 and the light emitting elements 150-1 and 150-2 formed on the substrate 402 are similar to those in the first embodiment, and for example, the circuit configuration in Fig. 3 is applied. The configurations of the other embodiments can also be easily applied.

[0178] A method for manufacturing the image display device of this embodiment will be described. 17A and 17B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in Fig. 17A, in this embodiment, a circuit board 3100 different from those in the other embodiments described above is prepared. The circuit board 3100 includes two layers of substrates 102 and 402. The substrate 402 is provided on the first surface 102a of the substrate 102, and is formed by, for example, applying and baking a polyimide material. Between the two layers of substrates 102 and 402, a SiN XAn inorganic film such as a TFT lower film 106, a circuit 101, and an interlayer insulating film 112 are provided on a first surface 402a of a substrate 402. The first surface 402a of the substrate 402 is a surface opposite to the surface on which the substrate 102 is provided.

[0179] On such a circuit board 3100, the upper structure of the sub-pixels 320-1 and 320-2 is formed by applying the steps described with reference to FIGS. 5A to 11D, for example.

[0180] As shown in FIG. 17B, the substrate 102 is removed from the structure on which the upper structure including the color filter and the like is formed, and a new circuit substrate 3100a is formed. For example, laser lift-off or the like is used to remove the substrate 102. The substrate 102 can be removed not only at the above-mentioned time point, but also at other appropriate time points. For example, the substrate 102 may be removed after wafer bonding or before the formation of the color filter. By removing the substrate 102 at an earlier time point, defects such as cracks and chips during the manufacturing process can be reduced.

[0181] The effects of the image display device of this embodiment will be described. Since the substrate 402 is flexible, it can be bent to form an image display device, and can be attached to a curved surface or used in a wearable device or the like without any sense of incongruity.

[0182] (Fourth embodiment) In this embodiment, a single semiconductor layer including a light emitting layer is provided with a plurality of light emitting surfaces corresponding to a plurality of light emitting elements, thereby realizing an image display device with higher light emission efficiency. In the following description, the same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. FIG. 18 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. 18, the image display device includes a subpixel group 420. The subpixel group 420 includes transistors (multiple transistors) 103-1 and 103-2, a first wiring layer (first wiring layer) 410, an interlayer insulating film (first insulating film) 112, a plug 416k, a graphene sheet (portion including graphene) 440, a semiconductor layer 450, an interlayer insulating film (second insulating film) 456, and vias (multiple vias) 461d1 and 461d2.

[0183] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected into the semiconductor layer 450 via the wiring layer 460, and electrons are injected into the semiconductor layer 450 via the plug 416k, causing the light-emitting layer 452 to emit light. For example, the circuit configuration shown in FIG. 3 is applied to the drive circuit. Using the other embodiments described above, the n-type semiconductor layer and the p-type semiconductor layer can be switched up and down to drive the semiconductor layer with n-channel transistors. In that case, for example, the circuit configuration shown in FIG. 13 is applied to the drive circuit.

[0184] The semiconductor layer 450 includes two light emitting surfaces 453S1 and 453S2, and the subpixel group 420 includes substantially two subpixels. In this embodiment, as in the other embodiments described above, the subpixel group 420 including substantially two subpixels is arranged in a lattice pattern to form a display area.

[0185] Transistors 103-1 and 103-2 are formed in TFT channels 104-1 and 104-2, respectively, which in this example include p-type doped regions with a channel region therebetween.

[0186] An insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gates 107-1 and 107-2 are formed on the insulating layer 105. The gates 107-1 and 107-2 are the gates of the transistors 103-1 and 103-2. In this example, the transistors 103-1 and 103-2 are p-channel TFTs.

[0187] The two transistors 103-1 and 103-2 are covered with an insulating film 108. On the insulating film 108, a wiring layer 410 is formed.

[0188] Vias 111s1 and 111d1 are provided between the p-type doped region of the transistor 103-1 and the wiring layer 410. Vias 111s2 and 111d2 are provided between the p-type doped region of the transistor 103-2 and the wiring layer 410.

[0189] The wiring layer 410 includes wirings 410k, 410s1, 410s2, 410d1, and 410d2. The wiring 410k is connected to a plug 416k via a connection portion 415k. The wiring 410k is connected to the ground line 4 shown in FIG.

[0190] The wiring 410s1 is electrically connected to a region corresponding to the source electrode of the transistor 103-1 through a via 111s1. The wiring 410s2 is electrically connected to a region corresponding to the source electrode of the transistor 103-2 through a via 111s2. The wirings 410s1 and 410s2 are connected to, for example, the power line 3 shown in FIG.

[0191] The wiring 410d1 is connected to a region corresponding to the drain electrode of the transistor 103-1 through a via 111d1, and the wiring 410d2 is connected to a region corresponding to the drain electrode of the transistor 103-2 through a via 111d2.

[0192] The interlayer insulating film 112 covers the transistors 103-1 and 103-2 and the wiring layer 410. The plug 416k is formed on the interlayer insulating film 112.

[0193] The planarization film 414 is formed on the interlayer insulating film 112. The planarization film 414 is also provided on the side of the plug 416k. The plug 416k is embedded in the planarization film 414, and the planarization film 414 and the plug 416k have surfaces that are in the same plane when viewed in the XY plane. These surfaces are surfaces on the sides opposite to the surface on the interlayer insulating film 112 side.

[0194] The graphene sheet 440 is provided on the plug 416k. The outer periphery of the graphene sheet 440 approximately coincides with the outer periphery of the semiconductor layer 450. The outer periphery of the plug 416k is set to include the outer periphery of the plug 416k and the graphene sheet 440 when the graphene sheet 440 and the semiconductor layer 450 are projected onto the plug 416k. Therefore, the plug 416k functions as a light reflecting plate that reflects scattered light emitted downward from the semiconductor layer 450 toward the light emitting surfaces 453S1 and 453S2.

[0195] The semiconductor layer 450 is provided on the graphene sheet 440. The semiconductor layer 450 includes an n-type semiconductor layer (first semiconductor layer) 451, a light emitting layer 452, and a p-type semiconductor layer (second semiconductor layer) 453. In the semiconductor layer 450, the n-type semiconductor layer 451, the light emitting layer 452, and the p-type semiconductor layer 453 are laminated in this order from the graphene sheet 440 side toward the light emitting surfaces 453S1 and 453S2 side. The n-type semiconductor layer 451 is provided on the graphene sheet 440. The graphene sheet 440 is sufficiently thin, so that the resistance in the thickness direction is sufficiently low. Therefore, the n-type semiconductor layer 451 is electrically connected to the plug 416k via the graphene sheet 440.

[0196] The interlayer insulating film 456 covers the planarizing film 414 and the plug 416k. The interlayer insulating film 456 covers a part of the semiconductor layer 450. Preferably, the interlayer insulating film 456 covers the surface of the p-type semiconductor layer 453 except for the light emitting surfaces (exposed surfaces) 453S1 and 453S2 of the semiconductor layer 450. The interlayer insulating film 456 covers the side surfaces of the semiconductor layer 450. The interlayer insulating film 456 is, for example, a white resin or the like, and may be a black resin.

[0197] Openings 458-1 and 458-2 are formed in the portions of the semiconductor layer 450 that are not covered with the interlayer insulating film 456. The openings 458-1 and 458-2 are formed at positions corresponding to the light emitting surfaces 453S1 and 453S2. The light emitting surfaces 453S1 and 453S2 are formed at positions spaced apart on the p-type semiconductor layer 453. The light emitting surface 453S1 is provided at a position closer to the transistor 103-1 on the p-type semiconductor layer 453. The light emitting surface 453S2 is provided at a position closer to the transistor 103-2 on the p-type semiconductor layer 453.

[0198] The openings 458-1 and 458-2 are, for example, square or rectangular in the XY plane view. They are not limited to a rectangular shape, and may be circular, elliptical, or polygonal, such as a hexagon. The light-emitting surfaces 453S1 and 453S2 are also square, rectangular, or other polygonal or circular in the XY plane view. The shapes of the light-emitting surfaces 453S1 and 453S2 may be similar to or different from the shapes of the openings 458-1 and 458-2.

[0199] The wiring layer 460 is provided on the interlayer insulating film 456. The wiring layer 460 includes wirings 460a1 and 460a2.

[0200] The vias 461d1 and 461d2 are provided penetrating the interlayer insulating films 112 and 456 and the planarizing film 414. The via 461d1 is provided between the wiring 410d1 and the wiring 460a1. One end of the via 461d1 is connected to the wiring 410d1, and the other end of the via 461d1 is connected to the wiring 460a1. The via 461d2 is provided between the wiring 410d2 and the wiring 460a2. One end of the via 461d2 is connected to the wiring 410d2, and the other end of the via 461d2 is connected to the wiring 460a2.

[0201] The transparent electrode 459a1 is provided over the wiring 460a1, and the wiring 460a1 and the transparent electrode 459a1 are electrically connected. The transparent electrode 459a1 extends to the opening 458-1. The transparent electrode 459a1 is provided over the entire light emitting surface 453S1 exposed from the opening 458-1, and is electrically connected to the p-type semiconductor layer 453 via the light emitting surface 453S1.

[0202] The transparent electrode 459a2 is provided over the wiring 460a2, and the wiring 460a2 and the transparent electrode 459a2 are electrically connected. The transparent electrode 459a2 extends to the opening 458-2. The transparent electrode 459a2 is provided over the entire light-emitting surface 453S2 exposed from the opening 458-2, and is electrically connected to the p-type semiconductor layer 453 via the light-emitting surface 453S2.

[0203] As described above, the light-emitting surfaces 453S1 and 453S2 exposed from the openings 458-1 and 458-2 are connected to the transparent electrodes 459a1 and 459a2, respectively. When the transistor 103-1 is turned on, holes are injected into the transparent electrode 459a1 through the wiring 460a1, the via 461d1, and the wiring 410d1. When the transistor 103-2 is turned on, holes are injected into the transparent electrode 459a2 through the wiring 460a2, the via 461d2, and the wiring 410d2. Meanwhile, electrons are injected into the n-type semiconductor layer 451 through the wiring 410k connected to the ground line 4, the connection portion 415k, the plug 416k, and the graphene sheet 440.

[0204] The transistors 103-1 and 103-2 are driving transistors of adjacent subpixels, and are driven sequentially. Therefore, holes injected from one of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 452, and electrons injected from the plug 416k are injected into the light-emitting layer 452, so that the light-emitting layer 452 emits light. When the transistor 103-1 is turned on, the light-emitting surface 453S1 emits light, and when the transistor 103-2 is turned on, the light-emitting surface 453S2 emits light. Thus, the light emission in the light-emitting layer 452 is localized because the resistance of the p-type semiconductor layer 453 suppresses the drift current flowing in the p-type semiconductor layer 453 in a direction parallel to the XY plane.

[0205] A method for manufacturing the image display device of this embodiment will be described. 19A to 22B are schematic cross-sectional views illustrating a method for manufacturing an image display device according to an embodiment. 19A to 20B show a step of forming a plug 416k in a circuit board 4100. 21A to 22B show a process of forming a sub-pixel group 420 by forming a semiconductor layer 450 and the like on a circuit board 4100 on which plugs 416k have been formed.

[0206] As shown in FIG. 19A, a circuit board 4100 is prepared. The circuit board 4100 includes a circuit 101, a substrate 102, a TFT lower layer film 106, and a first interlayer insulating film 112 similar to those described in FIG. 1 and the like. The circuit 101 includes transistors 103-1, 103-2, etc., and is formed on a TFT lower layer film 106 formed on a substrate 102. The circuit 101 is covered with a first interlayer insulating film 112. A contact hole h is formed in the interlayer insulating film 112. The position where the contact hole h is formed is the position where the wiring 410k is provided. The contact hole h is formed to a depth at which the surface of the wiring 410k is exposed.

[0207] 19B, a metal layer 4416 is formed over the entire surface of the interlayer insulating film 112. The contact holes h are filled with the same conductive material as the metal layer 4416 at the same time as the formation of the metal layer 4416. A connection portion 415k is formed in the contact holes h filled with the material of the metal layer 4416. Therefore, the connection portion 415k electrically connects the wiring 410k and the metal layer 4416.

[0208] 19C, a plug 416k is formed on the connection portion 415k by photolithography and dry etching. A plug may be formed directly on the wiring 410k without forming the connection portion 415k.

[0209] 20A, a planarization film 4414 is applied so as to cover the interlayer insulating film 112 and the plug 416k, and then baked. The planarization film 4414 is formed so as to be thicker than the plug 416k. Therefore, the planarization film 4414 also covers the side surface of the plug 416k. Thereafter, the surface of the planarization film 4414 is polished. For example, CMP (Chemical Mechanical Polishing) is used to polish the planarization film 4414.

[0210] 20B, the surfaces of the plugs 416k are exposed by polishing, and the planarizing film 414 is formed. In this manner, the plugs 416k and the connecting portions 415k are formed.

[0211] Further, as shown in FIG. 21A, a graphene layer 4440 is formed on the plug 416k and the planarization film 414 of the circuit board 4100. The graphene layer 4440 is cut and shaped in advance to have an appropriate periphery. The periphery of the graphene layer 4440 is set so that the semiconductor layer 4450 shown in FIG. 21B will be grown later with a sufficient area in the XY plane view. In this example, the periphery of the graphene layer 4440 is set to include the periphery of the plug 416k.

[0212] 21B, the semiconductor layer 4450 is formed on the graphene layer 4440. Preferably, pulse sputtering is used to form the semiconductor layer 4450. The semiconductor layer 4450 is grown from an n-type semiconductor layer 4451, followed by growing a light emitting layer 4452 and a p-type semiconductor layer 4453 in this order. The semiconductor layer 4450 is formed on the graphene layer 4440, and a deposit 4160 that is not single-crystallized is formed on areas other than the graphene layer 4440.

[0213] 22A, the semiconductor layer 4450 shown in FIG. 21B is shaped into a semiconductor layer 450 having a desired shape by RIE or the like. At this time, the semiconductor layer 450 is formed so that the outer periphery of the semiconductor layer 450 when projected onto the plug 416k in the XY plan view is included in the outer periphery of the plug 416k.

[0214] The graphene layer 4440 shown in FIG. 21B is shaped to have approximately the same perimeter as the perimeter of the semiconductor layer 450 by overetching the semiconductor layer 450 to form the graphene sheet 440.

[0215] 22B, a second interlayer insulating film 456 is formed to cover the planarization film 414, the plugs 416k, the side surfaces of the graphene sheet 440, and the semiconductor layer 450. Vias 461d1 and 461d2 are formed penetrating the interlayer insulating films 112 and 456 and the planarization film 414. Furthermore, a wiring layer 460 is formed, and wirings 460a1, 460a2, etc. are formed.

[0216] Thereafter, openings 458-1 and 458-2 are formed between the wirings 460a1 and 460a2. The light emitting surfaces 453S1 and 453S2 of the p-type semiconductor layers exposed by the openings 458-1 and 458-2 are roughened. Thereafter, the translucent electrodes 459a1 and 459a2 are formed.

[0217] In this manner, a sub-pixel group 420 having a semiconductor layer 450 sharing two light emitting surfaces 453S1 and 453S2 is formed.

[0218] In this embodiment, two light-emitting surfaces 453S1 and 453S2 are provided in one semiconductor layer 450, but the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces can be provided in one semiconductor layer 450. As an example, one or two columns of subpixels may be realized in a single semiconductor layer 450. This can reduce the recombination current that does not contribute to light emission per light-emitting surface, and can increase the effect of realizing finer light-emitting elements, as described later.

[0219] (Modification) FIG. 23 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the present embodiment. This modification differs from the fourth embodiment in that two p-type semiconductor layers 4453a1 and 4453a2 are provided on the light emitting layer 452. In other respects, this modification is the same as the fourth embodiment, and the same components are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0220] As shown in Fig. 23, the image display device of this modified example includes a subpixel group 420a. The subpixel group 420a includes a semiconductor layer 450a. The semiconductor layer 450a includes an n-type semiconductor layer 451, a light emitting layer 452, and p-type semiconductor layers 4453a1 and 4453a2. In the semiconductor layer 450a, the n-type semiconductor layer 451 is provided on the plug 416k via a graphene sheet 440. The light emitting layer 452 is laminated on the n-type semiconductor layer 451. Two different p-type semiconductor layers 4453a1 and 4453a2 are laminated on the light emitting layer 452.

[0221] In this example, the p-type semiconductor layers 4453a1 and 4453a2 are disposed to be spaced apart in the X-axis direction on the light emitting layer 452. An interlayer insulating film 456 is provided between the p-type semiconductor layers 4453a1 and 4453a2, and the p-type semiconductor layers 4453a1 and 4453a2 are separated by the interlayer insulating film 456.

[0222] The p-type semiconductor layers 4453a1 and 4453a2 have approximately the same shape in the XY plan view, and the shape is approximately square or rectangular, but may be another polygonal shape, a circle, or the like.

[0223] The p-type semiconductor layers 4453a1 and 4453a2 have light emitting surfaces 4453S1 and 4453S2, respectively. The light emitting surfaces 4453S1 and 4453S2 are surfaces of the p-type semiconductor layers 4453a1 and 4453a2 exposed by the openings 458-1 and 458-2, respectively.

[0224] The shapes of the light emitting surfaces 4453S1 and 4453S2 in the XY plane view are almost the same as the shapes of the light emitting surfaces in the fourth embodiment, and are almost square or the like. The shapes of the light emitting surfaces 4453S1 and 4453S2 are not limited to a square as in this embodiment, but may be a circle, an ellipse, or a polygon such as a hexagon. The shapes of the light emitting surfaces 4453S1 and 4453S2 may be similar to the shapes of the openings 458-1 and 458-2, or may be different shapes.

[0225] The light-transmitting electrodes 459a1 and 459a2 are provided on the light-emitting surfaces 4453S1 and 4453S2, respectively. The light-transmitting electrodes 459a1 and 459a2 are also provided on the wirings 460a1 and 460a2, respectively. The light-transmitting electrode 459a1 is provided between the wiring 460a1 and the light-emitting surface 4453S1, and electrically connects the wiring 460a1 and the light-emitting surface 4453S1. The light-transmitting electrode 459a2 is provided between the wiring 460a2 and the light-emitting surface 4453S2, and electrically connects the wiring 460a2 and the light-emitting surface 4453S2.

[0226] A manufacturing method for this modified example will be described. 24A and 24B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this modified example. In this modification, the same steps as those described in Fig. 19A to Fig. 21B in the fourth embodiment are applied to the circuit board 4100 in which the plug 416k is formed until the graphene layer 4440 is formed. In the following, the steps subsequent to the step shown in Fig. 21B will be described as the manufacturing process of this modification.

[0227] 24A, in this modification, the semiconductor layer 4450 grown on the graphene layer 4440 in FIG. 21B is etched to form the semiconductor layer 450a. In the process of forming the semiconductor layer 450a, after the n-type semiconductor layer 451 and the light emitting layer 452 are formed, etching is further performed to form two p-type semiconductor layers 4453a1 and 4453a2.

[0228] The p-type semiconductor layers 4453a1 and 4453a2 may be formed by deeper etching. For example, the etching for forming the p-type semiconductor layers 4453a1 and 4453a2 may be performed to a depth that reaches the inside of the light emitting layer 452 or the inside of the n-type semiconductor layer 451. In this way, when etching the p-type semiconductor layer deeply, it is desirable to set the etching position of the p-type semiconductor layer 4453 at a distance of 1 μm or more from the outer periphery of the light emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer. By setting the etching position away from the outer periphery of the light emitting surfaces 4453S1 and 4453S2, the recombination current can be suppressed.

[0229] The graphene layer 4440 shown in FIG. 21B is shaped to a periphery corresponding to the periphery of the semiconductor layer 450a by overetching the semiconductor layer 450a.

[0230] 24B, an interlayer insulating film 456 is formed to cover the planarizing film 414 and the semiconductor layer 450a, and then vias 461d1 and 461d2 are formed. Furthermore, a wiring layer 460 is formed, and wirings 460a1, 460a2, etc. are formed.

[0231] Openings 458-1 and 458-2 are formed in the interlayer insulating film 456. Light emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer exposed by the openings 458-1 and 458-2 are roughened. Then, transparent electrodes 459a1 and 459a2 are formed.

[0232] In this manner, a sub-pixel group 420a having two light emitting surfaces 4453S1 and 4453S2 is formed.

[0233] In this modified example, similarly to the fourth embodiment, the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 450a.

[0234] The effects of the image display device of this embodiment will be described. FIG. 25 is a graph illustrating the characteristics of a pixel LED element. The vertical axis of Figure 25 represents the luminous efficiency [%], and the horizontal axis represents the relative value of the current density of the current flowing through the pixel LED element. As shown in Figure 25, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is almost constant or increases monotonically. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. In other words, there exists an appropriate current density for the pixel LED element that maximizes the luminous efficiency.

[0235] It is expected that a highly efficient image display device can be realized by suppressing the current density to a level where sufficient brightness can be obtained from the light-emitting element. However, as shown in Figure 25, at low current densities, the luminous efficiency tends to decrease as the current density decreases.

[0236] For example, as described in the first embodiment, the light emitting elements 150-1 and 150-2 are formed by individually separating the entire semiconductor layer 1150 including the light emitting layers 152-1 and 152-2 by etching or the like. At this time, the junction surfaces between the light emitting layers 152-1 and 152-2 and the p-type semiconductor layers 153-1 and 153-2 are exposed at the ends. Similarly, the junction surfaces between the light emitting layers 152-1 and 152-2 and the n-type semiconductor layers 151-1 and 151-2 are exposed at the ends.

[0237] When such an edge exists, electrons and holes recombine at the edge. However, such recombination does not contribute to light emission. Recombination at the edge occurs almost independently of the current flowing through the light-emitting device. It is considered that recombination occurs according to the length of the junction surface that contributes to the light emission of the edge.

[0238] When two cubic light emitting elements of the same size are caused to emit light, ends are formed on all four sides of each light emitting element, so recombination can occur at a total of eight ends.

[0239] In contrast, in this embodiment, the number of ends of the semiconductor layers 450 and 450a having two light emitting surfaces is four. Since the region between the openings 458-1 and 458-2 has few injections of electrons and holes and hardly contributes to light emission, the number of ends that contribute to light emission can be considered to be six. Thus, in this embodiment, the number of ends of the semiconductor layer is substantially reduced, thereby reducing the recombination current that does not contribute to light emission, and the reduction in recombination current makes it possible to lower the drive current.

[0240] In the case where the distance between the subpixels is shortened for higher definition or the current density is relatively high, the distance between the light emitting surfaces 453S1 and 453S2 is shortened in the subpixel group 420 of the fourth embodiment. In this case, if the p-type semiconductor layer 453 is shared, some of the electrons injected to the adjacent light emitting surface may be diverted, causing the light emitting surface on the non-driven side to emit weak light. In the modified example, the p-type semiconductor layers 4453a1 and 4453a2 are separated for each of the light emitting surfaces 4453S1 and 4453S2, so that it is possible to reduce the occurrence of weak light emission on the light emitting surface on the non-driven side.

[0241] In this embodiment, the semiconductor layer including the light emitting layer is laminated in the order of an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer from the side of the interlayer insulating film 112, which is preferable from the viewpoint of roughening the exposed surface of the p-type semiconductor layer to improve the light emitting efficiency. As in the other embodiments described above, the lamination order of the n-type semiconductor layer and the p-type semiconductor layer may be reversed and the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer may be laminated in this order.

[0242] In all the above-mentioned embodiments and modifications, the order of stacking the light-emitting elements can be changed and applied by the above-mentioned appropriate manufacturing procedure. For example, in the light-emitting element of the first embodiment, a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer can be stacked in this order from the first interlayer insulating film 112 side toward the light-emitting surface side. Similarly, in the light-emitting element of the second embodiment, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer can be stacked in this order from the first interlayer insulating film 112 side toward the light-emitting surface side.

[0243] In addition, in the above-mentioned embodiments and modifications, the above-mentioned configurations can be applied in appropriate combination. For example, in the first to third embodiments, the plug used in the fourth embodiment can be applied to connect the lower semiconductor layer to an external circuit. Similarly, in the fourth embodiment, instead of connecting by a plug, the lower semiconductor layer can be connected to an external circuit using a via.

[0244] Fifth embodiment The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0245] FIG. 26 is a block diagram illustrating an image display device according to this embodiment. FIG. 26 shows the main components of a computer display. As shown in Fig. 26, an image display device 501 includes an image display module 502. The image display module 502 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 502 includes a display region 2 in which subpixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7. The image display device 501 may have the configuration of any of the second to fourth embodiments or modified examples.

[0246] The image display device 501 further includes a controller 570. The controller 570 receives a control signal that is separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each sub-pixel and to control the drive order.

[0247] (Modification) FIG. 27 is a block diagram illustrating an image display device according to this modified example. FIG. 27 shows the configuration of a high-definition thin television. As shown in Fig. 27, an image display device 601 includes an image display module 602. The image display module 602 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 601 includes a controller 670 and a frame memory 680. The controller 670 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied by a bus 640. The frame memory 680 stores one frame's worth of display data and is used for processing such as smooth video playback.

[0248] The image display device 601 has an I / O circuit 610. The I / O circuit 610 provides an interface circuit for connecting to an external terminal, device, etc. The I / O circuit 610 includes, for example, a USB interface for connecting an external hard disk device, etc., and an audio interface.

[0249] The image display device 601 has a receiving unit 620 and a signal processing unit 630. An antenna 622 is connected to the receiving unit 620, and separates and generates necessary signals from radio waves received by the antenna 622. The signal processing unit 630 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by the receiving unit 620 are separated by the signal processing unit 630 into image data, audio data, etc., and generated.

[0250] By configuring the receiving unit 620 and the signal processing unit 630 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for WiFi, a GPS receiver, etc., the image display device can be configured as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be configured as a mobile information terminal such as a smartphone or a car navigation system.

[0251] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be any of its modified examples or other embodiments.

[0252] FIG. 28 is a perspective view that illustrates a schematic example of the image display devices according to the first to fourth embodiments and their modified examples. 28, in the image display devices according to the first to fourth embodiments, as described above, a light-emitting circuit section 172 having a large number of sub-pixels is provided on a circuit board 100. A color filter 180 is provided on the light-emitting circuit section 172. In the fifth embodiment, a structure including the circuit board 100, the light-emitting circuit section 172, and the color filter 180 is formed as an image display module 502, 602, and is incorporated into an image display device 501, 601.

[0253] According to the embodiment described above, it is possible to realize a manufacturing method for an image display device and an image display device that shortens the transfer process of light emitting elements and improves the yield.

[0254] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0255] 1,201,501,601 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20-1,20-2,20a-1,20a-2,20b-1,20b-2 Subpixel, 22,222 Light emitting element, 24,224 Selection transistor, 26,226 Drive transistor, 28,228 Capacitor, 100 Circuit board, 101 Circuit, 102,402 Substrate, 103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulating layer, 107,107-1,107-2 Gate, 108 Insulating film, 110 First wiring layer, 110k, 210a Wiring, 112 First interlayer insulating film, 114, 414 Planarization film, 140, 140-1, 140-2, 440 Graphene sheet, 150-1, 150-2, 150a-1, 250 Light-emitting element, 156, 256, 456 Second interlayer insulating film, 159a1, 159a2, 159k, 459a1, 459a2 Transparent electrode, 160 Second wiring layer, 160a-1, 160k, 260a, 260k Wiring, 161d, 161k, 161k-1, 161k-2, 261a, 261a1, 461d1, 461d2 Via, 180 Color filter, 416k Plug, 420, 420a Subpixel group, 450, 450a Semiconductor layer, 410 First wiring layer, 410k Wiring, 1100, 3100, 3100a, 4100 Circuit board, 1140, 4440 Graphene layer, 1150 Semiconductor layer, 1192 Structure

Claims

1. A step of preparing a first substrate including a circuit including a circuit element formed on a light-transmitting substrate and a first insulating film covering the circuit; forming a layer including graphene on the first insulating film; forming a semiconductor layer including a light emitting layer on the graphene-containing layer; Etching the semiconductor layer to form a light emitting device; forming a second insulating film covering the graphene-containing layer, the light-emitting element, and the first insulating film; forming a via penetrating the first insulating film and the second insulating film; a step of electrically connecting the light emitting element and the circuit element through the via and the first wiring layer on a light emitting surface of the light emitting element that faces the surface on the first insulating film side; Equipped with the first wiring layer includes a second portion having light reflectivity; The light emitting element is provided on the second portion, A method for manufacturing an image display device, wherein the outer periphery of the second portion includes an outer periphery of the light-emitting element projected onto the second portion in a plan view.

2. 2. The method of claim 1, wherein in the step of forming the semiconductor layer, the semiconductor layer is grown by sputtering.

3. a second substrate having flexibility and provided between the light-transmitting substrate and the circuit element; The method for manufacturing an image display device according to claim 1 , further comprising the step of removing the light-transmitting substrate after the step of forming the semiconductor layer.

4. 4. The method for manufacturing an image display device according to claim 1, wherein the light-transmitting substrate includes a glass substrate.

5. 5. The method for manufacturing an image display device according to claim 1, further comprising a step of exposing the light emitting surface.

6. The method for manufacturing an image display device according to claim 5, further comprising the step of forming a translucent electrode on the exposed light-emitting surface.

7. 7. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer contains a gallium nitride compound semiconductor.

8. The method for manufacturing an image display device according to any one of claims 1 to 7, further comprising the step of forming a wavelength conversion member on the light emitting element.

9. a light-transmitting substrate having a first surface; A circuit element provided on the first surface; a first wiring layer provided on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit elements and the first wiring layer on the first surface; a first portion including graphene provided on the first insulating film; A light emitting element provided on the first portion; a second insulating film covering at least a portion of the light emitting element, the first portion, and the first insulating film; a second wiring layer provided on the second insulating film and electrically connected to a light emitting surface of the light emitting element that faces the surface of the light emitting element on the first insulating film side; a first via that penetrates the first insulating film and the second insulating film and electrically connects the first wiring layer and the second wiring layer; Equipped with the first wiring layer includes a second portion having light reflectivity; The light emitting element is provided on the second portion, The outer periphery of the second portion includes an outer periphery of the light-emitting element projected onto the second portion in a plan view.

10. The image display device according to claim 9 , wherein the light-transmitting substrate includes a glass substrate.

11. a flexible substrate having a first surface; A circuit element provided on the first surface; a first wiring layer provided on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit elements and the first wiring layer on the first surface; a first portion including graphene provided on the first insulating film; A light emitting element provided on the first portion; a second insulating film covering at least a portion of the light emitting element, the first portion, and the first insulating film; a second wiring layer provided on the second insulating film and electrically connected to a light emitting surface of the light emitting element that faces the surface of the light emitting element on the first insulating film side; a first via that penetrates the first insulating film and the second insulating film and electrically connects the first wiring layer and the second wiring layer; Equipped with the first wiring layer includes a second portion having light reflectivity; The light emitting element is provided on the second portion, The outer periphery of the second portion includes an outer periphery of the light-emitting element projected onto the second portion in a plan view.

12. A second via provided through the first insulating film and the second insulating film. Further equipped with The image display device according to claim 11 , wherein the second via electrically connects the second portion and the second wiring layer.

13. A plug provided between the first portion and the first wiring layer Further equipped with The light emitting element is provided on the plug, 12. The image display device according to claim 9, wherein an outer periphery of the plug includes an outer periphery of the light-emitting element projected onto the plug in a plan view.

14. the second insulating film has an opening exposing the light emitting surface, A light-transmitting electrode provided on the light-emitting surface. The image display device according to any one of claims 9 to 13, further comprising:

15. The image display device according to claim 14 , wherein the light emitting surface exposed through the opening includes a rough surface.

16. the light-emitting element includes a first semiconductor layer of a first conductivity type, a first light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the first light-emitting layer, the first semiconductor layer, the first light-emitting layer, and the second semiconductor layer being stacked in this order from the first insulating film side toward the light-emitting surface side; 16. The image display device according to claim 9, wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.

17. 16. The image display device according to claim 9, wherein the light emitting element includes a gallium nitride compound semiconductor.

18. 18. The image display device according to claim 9, further comprising a wavelength conversion member on the light emitting element.

19. a light-transmitting substrate having a first surface; A plurality of transistors disposed on the first surface; a first wiring layer provided on the plurality of transistors and electrically connected to the plurality of transistors; a first insulating film covering the plurality of transistors and the first wiring layer on the first surface; a portion including graphene provided on the first insulating film; a plug provided between the portion and the first wiring layer; a first semiconductor layer of a first conductivity type provided on the portion; a light emitting layer provided on the first semiconductor layer; a second semiconductor layer provided on the light emitting layer and having a second conductivity type different from the first conductivity type; a second insulating film covering the portion, the first insulating film, the light emitting layer, and the first semiconductor layer and covering at least a portion of the second semiconductor layer; a second wiring layer connected to a transparent electrode disposed on a plurality of light emitting surfaces of the second semiconductor layer, the light emitting surfaces being exposed from the second insulating film in accordance with the plurality of transistors; a plurality of vias penetrating the first insulating film and the second insulating film and electrically connecting the wiring of the first wiring layer and the wiring of the second wiring layer, respectively; Equipped with the first semiconductor layer and the light emitting layer are provided on the plug; The image display device, wherein the outer periphery of the plug includes the outer peripheries of the first semiconductor layer and the light emitting layer projected onto the plug in a plan view.

20. The image display device according to claim 19 , wherein the second semiconductor layer is separated by the second insulating film.

Images