Imaging device, photoelectric conversion system

Abstract

To solve the problem in which: the electric potential of a signal line before a signal for image formation is output to the signal line is different according to whether a signal for focus detection is output; therefore, when the signal for image formation is output to the signal line, the degree of stabilization of the electric potential of the signal line becomes easily different according to whether the signal for focus detection is output; thus a reduction in the accuracy of the signal for image formation occurs.SOLUTION: An imaging apparatus has a plurality of pixels, a signal line connected with the plurality of pixels, and a limiting circuit that limits the amplitude of the signal line. A noise signal, a focus detection signal, and an imaging signal are sequentially output to the signal line from a first pixel of the plurality of pixels. A noise signal and an imaging signal are sequentially output to the signal line from a second pixel of the plurality of pixels. In a period from when the second pixel outputs the noise signal until when the pixel outputs the imaging signal, the electric potential of the signal line is set to an electric potential determined by the limiting circuit.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an imaging device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes an imaging device that outputs a signal for focus detection and a signal for image generation. Some of the pixels output a signal for focus detection to a signal line, and then output a signal for image generation to the signal line. Another part of the pixels does not output a signal for focus detection, but outputs a signal for image generation to the signal line. Therefore, there are pixels to which a signal for focus detection is output before a signal for image generation is output, and pixels to which a signal for focus detection is not output. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-211833 A Summary of the Invention [Problem to be solved by the invention]

[0004] The potential of the signal line before the image generation signal is output to the signal line differs depending on whether the focus detection signal has been output. As a result, when the image generation signal is output to the signal line, the degree of stabilization of the potential of the signal line tends to differ depending on whether the focus detection signal has been output. This causes a decrease in the accuracy of the image generation signal. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, there is provided an image pickup apparatus including a plurality of pixels, a signal line connected to the plurality of pixels, and a limiting circuit that limits an amplitude of the signal line, wherein a noise signal, a focus detection signal, and an image pickup signal are sequentially output from a first pixel of the plurality of pixels to the signal line, and a noise signal and an image pickup signal are sequentially output from a second pixel of the plurality of pixels to the signal line;the limiting circuit is in an active state during a period from when the first pixel outputs the focus detection signal to when the first pixel outputs the imaging signal, During a period from when the second pixel outputs the noise signal to when the second pixel outputs the imaging signal, before The above limiting circuit becomes operational The imaging device is characterized in that

[0006] Another aspect of the present disclosure is a digital signal processing device including a plurality of pixels each including a plurality of photoelectric conversion units, a signal line to which the plurality of pixels are connected, and a limiting circuit that limits the amplitude of the signal line, wherein a noise signal, a first signal based on charges of only a portion of the plurality of photoelectric conversion units, and a second signal based on charges of the plurality of photoelectric conversion units are output from a first pixel of the plurality of pixels to the signal line in sequence, and a noise signal and a third signal based on charges of the plurality of photoelectric conversion units are output from a second pixel of the plurality of pixels to the signal line, the limiting circuit is in an active state during a period from when the first pixel outputs the first signal to when the first pixel outputs the second signal; During a period from when the second pixel outputs the noise signal to when the second pixel outputs the third signal, before The above limiting circuit becomes operational The imaging device is characterized in that Effect of the Invention

[0007] According to the present disclosure, it is possible to make it difficult for the accuracy of signals used for generating images to decrease. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of an imaging device; [Diagram 2] A diagram showing the configuration of a pixel [Diagram 3] A diagram showing the configuration of the readout circuit and AD conversion circuit. [Figure 4] FIG. 1 is a diagram showing the operation of an imaging device. [Diagram 5] A diagram showing the configuration of the readout circuit and AD conversion circuit. [Figure 6] FIG. 1 is a diagram showing the operation of an imaging device. [Figure 7] A diagram showing the configuration of the readout circuit and AD conversion circuit. [Figure 8] FIG. 1 is a diagram showing the operation of an imaging device. [Figure 9] A diagram showing the configuration of a photoelectric conversion system. [Figure 10] Diagram showing the configuration and operation of a moving object DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment will be described below with reference to the drawings.

[0010] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors are changed as appropriate.

[0011] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type, as compared to the description in the embodiment. The conductivity type of the semiconductor region described in the embodiment described below is also merely an example, and is not limited to the conductivity type described in the embodiment. The conductivity type may be changed as appropriate from the conductivity type described in the embodiment, and the potential of the semiconductor region may be changed as appropriate in accordance with this change.

[0012] (First embodiment) 1 is a configuration diagram of an imaging device in this embodiment. The imaging device has a pixel array 100. In the pixel array 100, a plurality of pixels 101 (sometimes called unit pixels) are arranged across a plurality of rows and a plurality of columns. A plurality of signal lines 120 are arranged corresponding to each of the plurality of columns of pixels 101. Note that, although a configuration in which one signal line 120 is provided for each column of pixels 101 is shown here, more signal lines may be provided for each column of pixels 101.

[0013] The imaging device includes a readout circuit 102. The readout circuit 102 includes a plurality of unit circuits corresponding to the plurality of signal lines 120. The imaging device also includes a first bias circuit 103 that controls the driving of the readout circuit 102 and supplies a reference bias.

[0014] The imaging device has an AD conversion circuit 104 that converts a signal output from the readout circuit 102 into a digital signal. The AD conversion circuit 104 is provided with a plurality of AD converters corresponding to the plurality of unit circuits provided in the readout circuit 102. The imaging device has a second bias circuit 105 that controls the drive of the AD conversion circuit 104 and supplies a reference bias. The imaging device includes a reference signal supply circuit that supplies a reference signal (ramp signal) used in AD conversion by the AD conversion circuit 104.

[0015] The imaging device has a memory group 106 that holds digital signals generated by the AD conversion circuit 104. The memory group 106 has a plurality of memory elements arranged corresponding to the plurality of AD converters included in the AD conversion circuit 104. A count signal indicating the passage of time is input from a counter 109 to the memory group 106. The counter 109 generates a count signal indicating the passage of time using a clock pulse output from a PLL (Phased Locked Loop) circuit 113.

[0016] The imaging device has a horizontal scanning circuit 107. The horizontal scanning circuit 107 sequentially selects memory elements in each column of the memory group 106, and sequentially outputs digital signals held by the memory elements to a DFE (Digital Front End) 115. The DFE 115 performs various arithmetic processing on the digital signals output from the horizontal scanning circuit 107, such as correction to reduce noise and errors, and arithmetic processing (addition, subtraction, etc.) between digital signals. The DFE 115 outputs the processed digital signals to the signal output circuit 112.

[0017] The imaging device includes a vertical scanning circuit 110. The vertical scanning circuit 110 selects, on a row-by-row basis, a plurality of pixels 101 arranged in a pixel array 100. The pixels 101 in the row selected by the vertical scanning circuit 110 output signals to corresponding signal lines 120.

[0018] The imaging device includes a timing generator (TG) 111. The TG 111 controls the driving of a vertical scanning circuit 110, a first bias circuit 103, a second bias circuit 105, a reference signal supply circuit 108, a counter 109, and a PLL circuit 113.

[0019] FIG. 2 is a circuit diagram of the pixel 101.

[0020] The pixel 101 has photoelectric conversion units 201 and 202. The photoelectric conversion units 201 and 202 are typically photodiodes. The pixel 101 has transfer transistors 203 and 204. The transfer transistor 203 is connected to the photoelectric conversion unit 201 and a floating diffusion (FD) 208. A signal pTXA is input to the gate of the transfer transistor 203 from the vertical scanning circuit 110 shown in FIG. 1. The transfer transistor 204 is connected to the photoelectric conversion unit 202 and the FD 208. A signal pTXB is input to the gate of the transfer transistor 204 from the vertical scanning circuit 110 shown in FIG. The photoelectric conversion units 201 and 202 are provided corresponding to one microlens ML.

[0021] The pixel 101 has a reset transistor 205. The reset transistor 205 is connected to a power supply and an FD 208. A signal pFDRES is input from the vertical scanning circuit 110 to the gate of the reset transistor 205.

[0022] The pixel 101 has an amplification transistor 206. The gate of the amplification transistor 206 is connected to an FD 208. The amplification transistor 206 is also connected to a power source and a selection transistor 207.

[0023] A signal pSEL is input to the gate of the selection transistor 207 from the vertical scanning circuit 110. The selection transistor 207 is connected to a signal line 120.

[0024] The transfer transistors 203 and 204, the reset transistor 205, the amplification transistor 206, and the selection transistor 207 included in the pixel 101 are all N-type MOS transistors. The transfer transistors 203 and 204, the reset transistor 205, and the selection transistor 207 are in an on state when the signal input from the vertical scanning circuit 110 is at a high level (Hi), and are in an off state when the signal is at a low level (Lo).

[0025] Fig. 3 is a circuit diagram of a unit circuit 1020 included in the readout circuit 102 and an AD converter 1040 included in the AD conversion circuit 104 shown in Fig. 1. The readout circuit 102 is provided with a plurality of unit circuits 1020 as described with reference to Fig. 1. Moreover, the AD conversion circuit 104 is provided with a plurality of AD converters 1040 as described with reference to Fig. 1.

[0026] The unit circuit 1020 includes a current source load 301. The current source load 301 controls the amount of current flowing through the signal line 120. The unit circuit 1020 includes a sample-and-hold circuit (SH circuit) 310. The SH circuit 310 includes a switch 311 and a capacitance element 312. The switch 311 is controlled by a signal pSH output from the TG 111 shown in FIG. 1. The signal output from the pixel 101 to the signal line 120 is represented as a signal PIXSIG.

[0027] The unit circuit 1020 has a limiting circuit 320. The limiting circuit 320 has a clipping transistor 321 and a switch 322. The switch 322 is controlled by a signal pCLIP output from the TG 111. A voltage VCLIP is input from the first bias circuit 103 to the gate of the clipping transistor 321. The limiting circuit 320 is a circuit that limits the range in which the potential of the signal line 120 can change. Specifically, the clipping transistor 321 clips the potential of the signal line 120 at a potential (called a clipping potential) that is lowered from the voltage VCLIP by the sum of a threshold voltage Vth and an overdrive voltage for causing a current value determined by the current source 301 to flow. In other words, the potential of the signal line 120 is limited so as not to change beyond this clipping potential.

[0028] The AD converter 1040 includes a comparator 300. A reference signal RAMP is input to the comparator 300 from the reference signal supply circuit 108 in FIG. 1. The reference signal RAMP is a signal whose potential changes over time, and is also called a ramp signal. This change in potential may be in the form of a slope or a step. Also, the amount of change in potential may change while the potential is changing.

[0029] 4(a) is a diagram showing the operation of the reference example. In this reference example, the imaging device does not have the limiting circuit 320 shown in FIG.

[0030] In this reference example, a noise signal and a signal for image generation (imaging signal) are output from the pixel 101 in the Nth row, and a noise signal, a signal for focus detection (focus detection signal), and an imaging signal are output from the pixel 101 in the N+1th row.

[0031] The T1 period is a signal readout period for image generation on the Nth row, the T2 period is a signal readout period for focus detection on the N+1th row, and the T3 period is a signal readout period for image generation on the N+1th row.

[0032] At time t410, the vertical scanning circuit 110 sets the signal pSEL to Hi. This turns on the selection transistor 207 of the pixel 101 in the Nth row, and connects the amplification transistor (SF) 206 to the signal line 120.

[0033] In addition, since the vertical scanning circuit 110 sets the signal pFDRES to Hi, the reset transistor 205 is on. As a result, the FD 208 is reset to a voltage based on the power supply voltage (typically, a voltage obtained by subtracting the threshold voltage of the reset transistor from the power supply voltage).

[0034] At time t411, the vertical scanning circuit 110 sets the signal pFDRES to Lo. This turns off the reset transistor 205, and the FD 208 becomes floating. Noise occurs in the FD 208 when the state of the reset transistor 205 changes from on to off. Charge injection by the reset transistor 205 mainly appears as noise. At this time, the signal Vn1, which is the signal PIXSIG on the signal line, is a noise signal.

[0035] During the period from the start of period T1 to time t412, TG111 sets signal pSH to Hi. This turns on switch 311 and inputs signal Vn1 to capacitive element 312 (sampling). Then, TG111 sets signal pSH to Lo. This turns off switch 311 and capacitive element 312 holds signal Vn1.

[0036] During the period from time t412 to time t413 when the signal pSH is Lo, the reference signal RAMP changes and the signal held in the signal holding unit 310 is AD converted. A count signal corresponding to the timing when the magnitude relationship between the potentials of the signal Vn1 and the reference signal RAMP is reversed is obtained as a digital signal corresponding to the signal Vn1. This period during which the reference signal RAMP changes and the signal Vn1 is converted into a digital signal is called an NAD period.

[0037] During the period from time t413 to time t415 after the NAD conversion period, the TG111 sets the signal pSH to Hi again.

[0038] At time t414, the vertical scanning circuit 110 sets the signals pTXA and pTXB to Hi. This turns on the transfer transistors 203 and 204. As a result, the charges generated in the photoelectric conversion units 201 and 202 are transferred to the FD 208.

[0039] The voltage of the FD 208 drops due to the charges transferred from the photoelectric conversion units 201 and 202. In conjunction with this, the signal PIXSIG also drops from the potential of the signal Vn1. At this time, the signal PIXSIG drops to the potential of the signal Vpix1.

[0040] In this reference example, at time t415, the TG 111 sets the signal pSH to Lo. This time t415 is before the potential of the signal line 120 finishes decreasing to the signal Vpix1 (before it becomes statically settled). As a result, the signal held by the capacitive element 312 is the signal Vs1, which has a higher potential than the potential of the signal Vpix1.

[0041] After time t415, the potential of the reference signal RAMP starts to change, and the signal Vs1 held by the capacitive element 312 is AD converted.

[0042] At time t416, the magnitude relationship between the potentials of the signal Vs1 and the reference signal RAMP is reversed. At this timing, the comparator 300 outputs the signal LATCH to the corresponding memory element of the memory group 106. The count signal corresponding to this timing is written to the corresponding memory element of the memory group 106. The period during which the potential of this reference signal VRAMP changes is defined as an S1 period.

[0043] If the difference between the true image signal ΔVpix1 of the Nth row and the image signal ΔVs1 to be AD converted is dV1, dV1=Vpix1-Vs1...Equation (1) It becomes.

[0044] As can be seen from equation (1), when signal pSH becomes Lo at time t415, signal PIXSIG has not yet fallen completely to signal Vpix1, so a signal that is smaller than the original imaging signal by dV1 is AD converted as the imaging signal.

[0045] After that, at time t417, the vertical scanning circuit 110 sets the signal pSEL to Lo, which turns off the selection transistors 207 of the pixels 101 in the Nth row.

[0046] Next, at time t417, the vertical scanning circuit 110 sets the signal pSEL to be output to the pixels 101 in the (N+1)th row to Hi. This turns on the selection transistors 207 in the (N+1)th row and connects them to the signal lines 120.

[0047] From time t417 to time t423, the noise signals of the pixels 101 in the Nth row are read out, and an operation similar to the AD conversion operation of the noise signals is also performed on the pixels 101 in the (N+1)th row.

[0048] At time t424, the vertical scanning circuit 110 sets the signal pTXA to Hi. This turns on the transfer transistor 203 of the pixel 101 on the (N+1)th row, and transfers the charge generated in the photoelectric conversion unit 201 to the FD 208. At this time, since the signal pTXB remains Lo, the charge generated in the photoelectric conversion unit 202 is not transferred to the FD 208 at this point. The signal PIXSIG drops toward the signal Vpix2, which is a signal potential corresponding to the charge of the photoelectric conversion unit 201.

[0049] At time t424-2, the vertical scanning circuit 110 sets the signal pTXA to Lo.

[0050] At time t425, the TG 111 sets the signal pSH to Lo. The time t425 is before the potential of the signal line 120 becomes statically determinative. This causes the capacitive element 312 to hold the signal Vs2, which has a higher potential than the signal Vpix2.

[0051] Thereafter, the potential of the reference signal RAMP changes, and the AD conversion circuit 140 converts the signal Vs2 into a digital signal. The period during which the potential of the reference signal RAMP changes and the signal based on the charge generated by the photoelectric conversion unit 201 is AD converted is defined as an S2 period.

[0052] After the AD conversion period, TG111 makes the signal pSH Hi again.

[0053] At time t434, the vertical scanning circuit 110 sets both the signals pTXA and pTXB to Hi. This turns on the transfer transistors 203 and 204 in the (N+1)th row. As a result, the charges generated in the photoelectric conversion unit 201 after time t424-2 and the charges generated in the photoelectric conversion unit 202 are transferred to the FD 208.

[0054] As a result, the signal VSIGPIX decreases from the signal Vpix2 as a starting point toward the signal Vpix3, which is a signal potential corresponding to the charges of the photoelectric conversion units 201 and 202.

[0055] After that, the vertical scanning circuit 110 sets both the signals pTXA and pTXB to Lo.

[0056] For ease of explanation, it is assumed that the signal Vpix3 has the same potential as the signal Vpix1 of the Nth row pixel 101. Also, it is assumed that the signal Vpix2 (a signal corresponding to the charge of the photoelectric conversion unit 201) has an amplitude that is half that of the signal Vpix3 (a signal corresponding to the charge of the photoelectric conversion units 201, 201).

[0057] The amount of change in the potential of the signal line 120 during the T3 period is Vpix3-Vpix2=Vpix1-(1 / 2 Vpix1)=1 / 2 Vpix1...Equation (2) It is expressed as:

[0058] At time t435, the TG 111 sets the signal pSH to Lo. Time t435 is before the potential of the signal line 120 becomes statically deterministic. At this time, the signal Vs3 of the signal line 120 is held in the capacitor 312. The signal Vs3 has a higher potential than the signal Vpix3.

[0059] The period from time t435 to time t436 corresponds to the above-mentioned S1 period, during which the signal Vs3 is AD converted.

[0060] As shown in formula (2), the amplitude of the signal line 120 in the T3 period is approximately half that in the T1 period, and therefore is closer to the signal Vpix at time t435. That is, the signal Vs3 written to the capacitive element 312 has a lower potential than the signal Vs1 in the T1 period. Therefore, although the signals Vpix1 and Vpix3 are the same, the imaging signal that is AD converted in the T3 period is larger than the imaging signal obtained in the T1 period.

[0061] As a result, when a captured image is generated, horizontal lines are generated due to the difference between the image signals that are AD converted in the T1 period and the T3 period.

[0062] FIG. 4(b) is a diagram showing the operation of the imaging device of this embodiment.

[0063] The operations at the times indicated by the same numbers as those in FIG. 4(a) are the same as those in FIG. 4(a), and therefore will not be described.

[0064] During the period T1 from time t418 to time t419, the TG111 sets the signal pCLIP to Hi. This turns on the switch 322 of the limiting circuit 320. Therefore, the clip transistor 321 of the limiting circuit 320 is connected to the signal line 120. The gate voltage of the clip transistor 321 at this time is set near the reset level of the FD208 of the pixel 101.

[0065] At time t414, the transfer transistors 203 and 204 are turned on, and the charges photoelectrically converted by the photoelectric conversion units 201 and 202 are transferred to the FD 208. Accordingly, the potential of the signal line 120 starts to decrease.

[0066] Before time t419, the signal line 120 reaches the signal VCLIP_VL. Here, the signal VCLIP_VL is a potential that is fixed when the clip transistor 321 operates. The signal pCLIP is Hi until time t419. Therefore, the clip transistor 321 prevents the potential of the signal line 120 from falling below the signal VCLIP_VL.

[0067] At time t419, the signal pCLIP becomes Lo, and the clip clip transistor 321 is disconnected from the signal line 120. This releases the signal line 120 from being fixed to the signal VCLIP_VL, and the potential of the signal line 120 starts to decrease due to the amount of charge obtained by photoelectric conversion. The operations from time t415 to time t417 are the same as those described in FIG. 4(a), and therefore will not be described.

[0068] The potential of the signal line 120 is set to the signal VCLIP_VL during the period from time t418 to time t419.

[0069] From time t428 to time t429 in the T2 period, the clip transistor 321 and the switch 322 perform the same operations as those from time t418 to time t419 in the T1 period. This limits the change range of the potential of the signal line 120 to the signal VCLIP_VL.

[0070] Next, in the T3 period, from time t438 to time t439, the clip transistor 321 and the switch 322 perform the same operations as those performed from time t418 to time t419 in the T1 period and from time t428 to time t429 in the T2 period. As a result, in the T3 period, the signal is set to VCLIP_VL from time t434 to time t435.

[0071] In this embodiment, during periods T1, T2, and T3 when the charges of the photoelectric conversion units 201 and 202 are transferred to the FD 208, the potential of the signal line 120 is once set to the same potential of the signal VCLIP_VL.

[0072] Therefore, the potential change toward the signals Vpix1 and Vpix3 can start from the signal VCLIP_VL, which has the same potential.

[0073] In this embodiment, the potential of the signal line 120 is set to the signal VCLIP_VL during a predetermined period before the image pickup signal is output. This predetermined period is from time t418 to time t419, from time t428 to time t429, and from time t438 to time t439.

[0074] In this way, the start points of the potential change to the image pickup signal can be aligned regardless of whether or not the focus detection signal is output before the image pickup signal. This reduces the inconsistency in the static state of the image pickup signal depending on whether or not the focus detection signal is output. Therefore, it is possible to suppress the deterioration of the signal accuracy of the image pickup signal.

[0075] In this embodiment, the signal pCLIP is set to Lo during a period in which the signal pTXA or the signal pTXB is Hi, but the timing at which the signal pCLIP is set to Lo may be after the signal pTXA or the signal pTXB has become Lo. Also, the timing at which the signal pCLIP is set to Lo may be the same as the signal pTXA or the signal pTXB becomes Hi.

[0076] To further enhance the effect of this embodiment, it is preferable that the length of the period from the timing when the signal pCLIP goes to Lo to the timing when the signal pSH goes to Lo be at least the same for the T1 period and the T3 period.

[0077] In this embodiment, the SH circuit 310 is provided and the capacitive element 312 holds the signal PIXSIG, but the SH circuit 310 may not be provided. Even if the SH circuit 310 is provided, the switch 311 may be kept on and the signal may not be held. In that case, the same effect as in this embodiment can be obtained by matching the time from when the signal pCLIP becomes Lo to when the AD conversion starts with at least the T1 period and the T3 period.

[0078] In this embodiment, the pixels 101 in the Nth row output noise signals and signals for image generation (imaging signals). The pixels 101 in the N+1th row output noise signals, signals for focus detection, and imaging signals. The positions of the rows are not limited to these, and it is possible to appropriately change which row of the pixel rows outputs noise signals and signals for image generation (imaging signals), and which row outputs noise signals, signals for focus detection, and imaging signals. The selection of the row may be changed for each frame.

[0079] Second embodiment The present embodiment will be described focusing on the differences from the first embodiment.

[0080] Fig. 5 shows a circuit diagram of the readout circuit 102 of this embodiment. Fig. 6 shows the operation timing of the imaging device of this embodiment, signal lines, and voltage transitions of AMP_OUT, which will be described later.

[0081] First, we will explain Figure 5. In Figure 5, the same numbers as in Figure 3 are the same circuits as in Figure 3, so their explanation will be omitted.

[0082] 1 has a unit circuit 1021 instead of the unit circuit 1020. The unit circuit 1021 has an inverting amplifier 501. The inverting amplifier 501 outputs a signal obtained by amplifying a voltage change on the signal line 120 by a capacitance ratio between a capacitance element 503 (input capacitance) and a capacitance element 502 (feedback capacitance).

[0083] The switch 504 is a switch for initializing the inverting amplifier 501, the feedback capacitance 502, and the input capacitance 503 by shorting the signal AMP_OUT, which is the output of the inverting amplifier 501, to the inverting input terminal. The power supply voltage VREF is input to the non-inverting input terminal of the inverting amplifier circuit 501. The inverting input terminal and the non-inverting input terminal of the inverting amplifier 501 are virtually shorted. Therefore, when the switch 504 is turned on, the signal AMP_OUT and the inverting input terminal are reset to the potential of the power supply voltage VREF.

[0084] A switch 505 and a switch 506 are switches for switching the voltage applied to the gate of a clip transistor 507 in order to fix the signal AMP_OUT to a predetermined voltage.

[0085] When TG111 sets the signal p2 to Hi, the switch 505 turns on. As a result, the voltage VCAN is applied to the gate of the clip transistor 507. Also, when TG111 sets the signal p2B to Hi, the switch 506 turns on and the voltage VCAS is applied to the gate of the clip transistor 507.

[0086] The block consisting of the switches 505 and 506 and the clip transistor 507 is referred to as a control circuit 520 .

[0087] Next, the operation will be described with reference to FIG.

[0088] As in the first embodiment, the T1 period is a signal readout period for image generation on the Nth row, the T2 period is a signal readout period for focus detection on the N+1th row, and the T3 period is a signal readout period for image generation on the N+1th row.

[0089] Regarding the signals pSEL, pTXA, pTXB, and pSH in each period, descriptions of parts that overlap with those in the first embodiment will be partially omitted.

[0090] During the period from time t610 to time t612, signal p1 becomes Hi. This turns on switch 504, and the output of inverting amplifier 501 and the inverting input terminal are shorted. This causes signal AMP_OUT, which is the output of inverting amplifier 501, to be initialized to the potential of power supply voltage VREF connected to the non-inverting input terminal. Then, when switch 504 is turned off, the potential of signal line 120 at this time (signal PIXSIG) is clamped by capacitive element 503. Inverting amplifier 502 calculates the amount of change in PIXSIG since the clamped PIXSIG at time 612. AMP_OUT=−ΔPIXSIG×(capacitance value of capacitive element 503 / capacitance value of capacitive element 502) Equation (3) Amplify it at and output.

[0091] Here, ΔPIXSIG is the change amount of PIXSIG from time t612.

[0092] At time t613, the signal pHS becomes Lo and the writing of the signal AMP_OUT to the capacitive element 312 ends. This voltage is used as the signal of the reference level of the inverting amplifier 501 and the pixel 102, and is called Vn. By comparing this Vn with the reference voltage RAMP, the AD conversion of the noise signal of the Nth row is performed. This AD conversion ends within the period until the time t614 when the signal pSH becomes Lo.

[0093] At time t615, the signals pTXA and pTXB become Hi. Therefore, the charges generated in the photoelectric conversion unit 201 and the photoelectric conversion unit 202 are transferred to the FD208. From time t615, the signal PIXSIG starts to decrease due to the charge transferred to the FD208, and the inverting amplifier 502 amplifies the change of the signal PIXSIG and outputs it to the signal AMP_OUT.

[0094] From time t611 to time t616, the signal p2 becomes Hi and the switch 505 is turned on. As a result, the gate voltage VCA1 of the clip transistor 507 is VCAN.

[0095] The signal p2B is a pulse of the inverted phase of the signal p2. Therefore, when the signal p2 is Hi, the switch 505 is turned on and the switch 506 is turned off, and VCA1 = VCAN. Also, when the signal p2 is Lo, the switch 505 is turned off and the switch 507 is turned on, and VCA1 = VCAN. At this time, VCAN < VCAS ··· Equation (4) is.

[0096] Therefore, although the signal AMP_OUT starts to change from time t615, it is clipped to the voltage corresponding to the voltage VCAN by the clip transistor 507.

[0097] The potential of the clipped signal AMP_OUT is taken as the signal VCLIP_AMP.

[0098] After that, at time t616, the signal p2 goes to Lo and the voltage VCA1 switches from the voltage VCAN to the voltage VCAS, which releases the clipping of the signal AMP_OUT by the clipping transistor 507. This causes the signal AMP_OUT to start changing again.

[0099] At time t617, the signal pSH goes to Lo. The signal Vs1, which is the potential of the signal AMP_OUT at that time, is held by the capacitive element 312. After that, the signal AMP_OUT changes to the signal Vamp_out1 corresponding to the signal PIXSIG.

[0100] During the period from time t617 to time t619, the reference signal RAMP changes, and AD conversion of the imaging signal is performed. At time t618, the magnitude relationship between the signal Vs1 and the reference signal RAMP is reversed. A count signal based on this timing is generated as a digital signal corresponding to the signal Vs1.

[0101] At time t619, the signal pFDRES becomes Hi, resetting the FD 208. As a result, the signal PIXSIG, which is the potential of the signal line 120, starts to rise toward the reset level.

[0102] Next, the T2 period will be explained.

[0103] The operation from time t620 to time t625 can be the same as the operation from time t610 to time t615 in the T1 period.

[0104] At time t625, the signal pTXA goes Hi, and the charge of the photoelectric conversion unit 201 is transferred to the FD 208. In response to this, the signal PIXSIG starts to change from the reset level, and the inverting amplifier 502 amplifies the change and outputs it as the signal AMP_OUT.

[0105] Since the signal p2 is Hi from time t621 to time t626, the signal AMP_OUT is clipped to the signal VCLIP_AMP corresponding to the voltage VCAN by the clip transistor 507, as in the T1 period. At time t626, the signal p2 becomes Lo, and the voltage VCA1 switches to the voltage VCAS. This releases the clipping of the signal AMP_OUT to the signal VCLIP_AMP. This causes the change of the signal AMP_OUT to resume from time t626.

[0106] At time t627, the signal pSH goes to Lo, and the voltage Vs2 of the signal AMP_OUT at that time is held in the capacitive element 312. Thereafter, the signal AMP_OUT changes to the signal Vamp_out2 corresponding to the signal PIXSIG.

[0107] Between time t627 and time t629, the reference signal RAMP is changed and AD conversion of the signal Vs2 is performed. At time t628, the magnitude relationship between the reference signal RAMP and the signal Vs2 is reversed. A count signal based on this timing is generated as a digital signal corresponding to the signal Vs2.

[0108] Next, the T3 period will be explained.

[0109] At time t631, the TG 111 changes the signal p2 to Hi. As a result, the signal AMP_OUT drops from the signal Vamp_out2 to the signal VCLIP_AMP. The signal PIXSIG maintains the final potential of the T2 period because the FD 208 is not reset in the T3 period.

[0110] At time t635, the signals pTXA and pTXB go to Hi, and the charges in the photoelectric conversion units 201 and 202 are transferred to the FD 208. This causes the signal PIXSIG to start changing.

[0111] At this time, the signal AMP_OUT is clipped by the signal VCLIP_AMP until the signal p2 becomes Lo at time t636 and the voltage VCA1 switches from the voltage VCAN to the voltage VCAS. After the clipping is released at time t636, the signal AMP_OUT changes in accordance with the change in the signal PIXSIG.

[0112] At time t637, the signal pSH goes to Lo. At this time, the signal Vs3 of the signal AMP_OUT is held by the capacitive element 312. The signal AMP_OUT changes to the signal Vamp_out3 corresponding to the signal PIXSIG.

[0113] Between time t637 and time t639, the reference signal RAMP is changed and AD conversion of the signal Vs3 is performed. At time t638, the magnitude relationship between the reference signal RAMP and the signal Vs3 is reversed. A count signal based on this timing is generated as a digital signal corresponding to the signal Vs3.

[0114] Throughout the periods T1, T2, and T3, the signal AMP_OUT is clipped to the signal VCLIP_AMP before AD conversion. That is, the level at which the signal AMP_OUT starts to change can be made the same in the periods T1, T2, and T3.

[0115] Therefore, the time from when the signal p2 is changed to Lo to release the clip to when the signal pSH is changed to Lo to hold the signal AMP_OUT by the capacitive element 312 is made the same. Vs1≒Vs3...Equation (5) It is possible to do so.

[0116] This makes it possible to suppress a decrease in the accuracy of the image pickup signal, which occurs depending on whether or not a signal for focus detection is output.

[0117] In this embodiment, clipping of the signal AMP_OUT by the signal VCLIP_AMP is released while the signal pTXA is Hi, but it may be released after the signal pTXA changes from Hi to Lo.

[0118] In addition, in this embodiment, the signal is held by the capacitive element 312, but as described in the first embodiment, the SH circuit 310 does not have to be provided, and even if the SH circuit 310 is provided, the hold operation may not be performed.

[0119] Third embodiment The present embodiment will be described focusing on the differences from the first embodiment.

[0120] Fig. 7 is a circuit diagram of the readout circuit 102 of this embodiment. Fig. 8 shows the operation of the imaging device of this embodiment.

[0121] In the imaging device of this embodiment, the readout circuit 102 in FIG. 1 has a unit circuit 1022 shown in FIG.

[0122] In FIG. 7, the elements having the same reference numerals as those shown in FIG. 3 and FIG. 5 will not be described.

[0123] The unit circuit 1022 in Fig. 7 has a limiting circuit 321. The limiting circuit 321 has a clipping transistor 701. The clipping transistor 701 is a clipping transistor for clipping the signal AMP_OUT of the inverting amplifier 501 so that it does not fall below a predetermined level. A voltage VCA2 is applied to the gate of the clipping transistor 701. When the signal AMP_OUT falls to a voltage obtained by subtracting from the voltage VCA2 the threshold voltage of the clipping transistor 701 and the overdrive voltage when the clipping transistor 701 operates, the signal AMP_OUT is clipped to that level.

[0124] The voltage VCA2 is set so that the AMP_OUT that is clipped by the operation of the clipping transistor 701 is a voltage that does not cause the transistors that constitute the inverting amplifier 501 to go out of the saturation region.

[0125] Next, the operation will be described with reference to FIG.

[0126] The operations of the signals pSEL, pTXA, pTXB, pFDRES, and p1 are similar to those of the first and second embodiments, and therefore detailed description thereof will be omitted.

[0127] First, the T1 period will be explained.

[0128] At time t8101, the signal pFDRES becomes Lo, and the reset of the FD 208 is released. The potential of the signal PIXSIG at this time is defined as the signal VPIX_RES.

[0129] After that, during the period from time t8105 to time t8107, the signal pCLIP goes Hi, and the clip transistor 321 is connected to the signal line 120 via the switch 322.

[0130] At this time, the gate voltage VCLIP of the clip transistor 321 is VCLIP-Vth1-ΔVov=VCLIP_PIX, VCLIP_PIX>VPIX_RES...Formula (6) Set the voltage to satisfy.

[0131] Here, Vth1 is the threshold voltage of the clipping transistor 321, and ΔVov is the overdrive voltage when the clipping transistor 321 operates. The signal VCLIP_PIX is the voltage at which the signal PIXSIG is clipped when the clipping transistor 321 operates.

[0132] At time t8102, the signal p1 becomes Lo. The signal VPIX_RES, which is the signal PIXSIG at that time, is clamped by the capacitive element 503. Therefore, the signal AMP_OUT at that time is the signal Vn, which is the potential when the inverting amplifier 501 is initialized.

[0133] After that, by the operation from time t8105 to time t8107 described above, the signal PIXSIG becomes as shown in equation (6). ΔVclippix=VCLIP_PIX-VPIX_RES>0...Equation (7) It changes like this.

[0134] This causes the inverting input terminal of the inverting amplifier 501 to fluctuate to the positive side, resulting in the signal AMP_OUT decreasing from the signal Vn.

[0135] At this time, the clip transistor 701 on the output side of the inverting amplifier 501 is turned on to prevent the signal AMP_OUT from dropping too much. AMP_OUT=VCLIP_AMP=VCA2-Vth2-ΔVov2...Equation (8) The target value of the voltage VCLIP_AMP is set so that the components of the inverting amplifier 501 do not fall out of the saturation region. It is advisable to adjust the voltage VCA2 so as to satisfy this target value.

[0136] At time t8107, the signal pCLIP becomes Lo. Therefore, the clip transistor 321 is disconnected from the signal line 120. As a result of the clip being released, the signal PIXSIG starts to change in response to the charges transferred from the photoelectric conversion unit 201 and the photoelectric conversion unit 202 to the FD 208 when the signals pTXA and pTXB become Hi at time t8106.

[0137] In conjunction with this, the signal AMP_OUT also starts to change from the signal VCLIP_AMP to the signal Vamp_out1. Here, the signal Vamp_out1 is the potential of the signal AMP_OUT when the change in the signal PIXSIG corresponding to the charge read out to the FD 208 is amplified by the inverting amplifier 501.

[0138] At time t8108, the signal pSH becomes Lo. At that time, the signal AMP_OUT has not yet reached the signal Vamp_out1, and the signal Vs1, which is AMP_OUT at that time, is held in the capacitive element 312.

[0139] Between time t8108 and time t8110, the reference signal RAMP is changed to perform SAD conversion on the Nth row. At time t8109, the magnitude relationship between the reference signal RAMP and the signal Vs1 is reversed. The comparator 300 outputs the LATCH signal to end the AD conversion of the signal Vs1.

[0140] Next, the T2 period will be explained.

[0141] The period from time t8200 to time t8204 is the same as the period from time t8100 to time t8104 in the T1 period, and therefore the description will be omitted.

[0142] From time t8205 to time t8207, the signal pCLIP goes Hi, and the clip transistor 321 is connected to the signal line 120. The signal PIXSIG is clipped to the signal VCLIP_PIX. Accordingly, the signal AMP_OUT is clipped to the signal VCLIP_AMP, similar to the period T1.

[0143] At time t8207, the signal pCLIP goes low, the clipping transistor 321 is disconnected from the signal line 120, and the clipping of the signal PIXSIG is released.

[0144] As a result, the signal PIXSIG starts to change in response to the charge transferred from the photoelectric conversion unit 201 to the FD 208 when the signal pTXA becomes Hi at time t8206.

[0145] In conjunction with this, the signal AMP_OUT also starts to change from the signal VCLIP_AMP to the signal Vamp_out2. Here, the signal Vamp_out2 is the signal AMP_OUT when the change in the signal PIXSIG corresponding to the charge read out to the FD 208 is amplified by the inverting amplifier 501.

[0146] At time t8208, the signal pSH becomes Lo. At that time, the signal AMP_OUT has not yet reached the signal Vamp_out2, and the signal Vs2, which is the signal AMP_OUT at that time, is held in the capacitive element 312.

[0147] Between time t8208 and time t8210, the reference signal RAMP is changed to perform AD conversion of the focus detection signal on the (N+1)th row. At time t8209, the magnitude relationship between the reference signal RAMP and the signal Vs2 is reversed, and the comparator 300 outputs the LATCH signal. The AD conversion of the signal Vs2 is completed.

[0148] Next, the T3 period will be explained.

[0149] From time t8305 to time t8307, the signal pCLIP goes Hi, and the clip transistor 321 is connected to the signal line 120.

[0150] In the T3 period, the signal pFDRES is not input, and the FD 208 maintains the state in which, in the T2 period, the charge is transferred from the photoelectric conversion unit 201. Therefore, in the period from time t8305 to time t8307, the signal PIXSIG is changed by the clip transistor 321 from the level at the time of pixel signal readout in the T2 period to the signal VCLIP_PIX.

[0151] Accordingly, the output AMP_OUT of the inverting amplifier 501 changes from the signal Vamp_out2 to the signal VCLIP_AMP.

[0152] At time t8306, the signals pTXA and pTXB become Hi, and the charges generated in the photoelectric conversion units 201 and 202 are transferred to the FD 208. The signal line 120 does not change because it is clipped to the signal VCLIP_PIX by the clip transistor 321.

[0153] At time t8307, the signal pCLIP becomes Lo, and the clip transistor 321 is disconnected from the signal line 120. Therefore, the signal PIXSIG changes in response to the charge transferred to the FD 208 at time t8306.

[0154] Along with this, the signal AMP_OUT which is the output of the inverting amplifier 501 also starts to change towards the signal Vamp_out3.

[0155] The signal Vamp_out 3 is the signal AMP_OUT obtained when the change in the signal PIXSIG corresponding to the charge read out to the FD 208 is amplified by the inverting amplifier 501 .

[0156] At time t8308, the signal pSH becomes Lo. At that time, the signal AMP_OUT has not yet reached the signal Vamp_out3, and the signal Vs3, which is the signal AMP_OUT at that time, is held in the capacitive element 312.

[0157] Between time t8308 and time t8310, the reference signal RAMP is changed to perform AD conversion of the imaging signal in the (N+1)th row. At time t8309, the reference signal RAMP and the signal Vs3 intersect, and the comparator 300 outputs the LATCH signal, completing the AD conversion of the imaging signal.

[0158] where

[0159] (VCLIP_PIX-VPIX_RES)×(capacitance value of capacitive element 503 / capacitance value of capacitive element 502)>Vn-VCLIP_AMP Equation (9) The gate voltage VCLIP of the clip transistor 321 and the gate voltage VCA2 of the clip transistor 701 are set so that: This makes it possible to clip the signal AMP_OUT to the signal VCLIP_AMP.

[0160] As described above, before the start of SAD in the T1, T2, and T3 periods, PIXSIG is clipped to a predetermined voltage called VCLIP_PIX, and AMP_OUT is also clipped to a predetermined voltage called VCLIP_AMP.

[0161] Therefore, the settling times of the signal line 120 (PIXSIG) and the output AMP_OUT of the inverting amplifier 501 can be made substantially the same during the periods T1 and T3. Vs1≒Vs3...Equation (10) It is possible to do so.

[0162] This makes it possible to roughly match the levels of the imaging signals to be AD converted in the T1 and T3 periods, thereby making it possible to suppress image degradation due to differences in characteristics between the T1 and T3 periods and provide good images.

[0163] In this embodiment, clipping of the signal AMP_OUT at VCLIP_AMP is released while the signal pTXA is Hi, but it may be released after the signal pTXA transitions from Hi to Lo.

[0164] In this embodiment, the signal is sampled and held in the capacitive element 312, but as described in the first and second embodiments, this function does not have to be used. In that case, the same effect as that described in this embodiment can be obtained by matching the time from when clipping of the signal AMP_OUT at VCLIP_AMP is released to when AD conversion starts with at least the T1 period and the T3 period.

[0165] 7, the control circuit 520 may be omitted in this embodiment, but as described in the second embodiment, the control circuit 520 may be used in conjunction with this embodiment.

[0166] (Fourth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0167] The imaging devices described in the first to third embodiments are applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion systems. FIG. 9 illustrates a block diagram of a digital still camera as an example of these.

[0168] 9 includes an image capture device 1004, a lens 1002 that forms an optical image of a subject on the image capture device 1004, an aperture 1003 that varies the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image capture device 1004. The image capture device 1004 is a photoelectric conversion device (image capture device) according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0169] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on a semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Moreover, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0170] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0171] The photoelectric conversion system further includes an overall control / calculation unit 1009 which is a control unit that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 which processes the output signal output from the image capture device 1004.

[0172] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0173] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0174] Fifth embodiment The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0175] FIG. 10(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0176] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0177] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 10(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0178] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0179] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0180] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also included in the embodiments of the present invention.

[0181] Furthermore, the photoelectric conversion systems shown in the above fourth and fifth embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 9 and 10.

[0182] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0183] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when it states that "A is B," it is assumed that the case that "A is not B" is taken into consideration. [Explanation of symbols]

[0184] 100 pixel array 101 pixels 102 Readout circuit 104 AD conversion circuit 120 Signal Line 320 Limiting Circuit 321 Limiting Circuit 1020 Unit Circuit 1021 Unit Circuit 1022 Unit Circuit 1040 A / D converter

Claims

1. A plurality of pixels; A signal line connected to the plurality of pixels; a limiting circuit for limiting the amplitude of the signal line; a noise signal, a focus detection signal, and an image pickup signal are output in this order from a first pixel of the plurality of pixels to the signal line, and a noise signal and an image pickup signal are output in this order from a second pixel of the plurality of pixels to the signal line; the limiting circuit is in an active state during a period from when the first pixel outputs the focus detection signal to when the first pixel outputs the imaging signal, the limiting circuit is in an operative state during a period from when the second pixel outputs the noise signal to when the second pixel outputs the imaging signal.

2. 2. The image pickup apparatus according to claim 1, wherein the limiting circuit narrows a range within which the potential of the signal line can change during a period in which the focus detection signal is output to the signal line.

3. 3. The imaging device according to claim 1, wherein the limiting circuit narrows a range within which the potential of the signal line can change during a period during which the imaging signals of the first pixel and the second pixel are output to the signal line.

4. The imaging device according to any one of claims 1 to 3, characterized in that the limiting circuit narrows a range within which the potential of the signal line can change during a period in which the noise signals of each of the first pixel and the second pixel are output to the signal line.

5. A plurality of pixels each including a plurality of photoelectric conversion units; A signal line to which the plurality of pixels are connected; a limiting circuit for limiting the amplitude of the signal line; a noise signal, a first signal based on charges of only a portion of the photoelectric conversion units, and a second signal based on charges of the photoelectric conversion units are sequentially output to the signal line from a first pixel of the plurality of pixels; a noise signal and a third signal based on charges of the plurality of photoelectric conversion units are output to the signal line from a second pixel of the plurality of pixels; the limiting circuit is in an active state during a period from when the first pixel outputs the first signal to when the first pixel outputs the second signal; the limiting circuit is in an operative state during a period from when the second pixel outputs the noise signal to when the second pixel outputs the third signal.

6. 6. The imaging device according to claim 5, wherein one microlens is provided corresponding to each of the plurality of photoelectric conversion portions.

7. 7. The imaging device according to claim 5, wherein the limiting circuit narrows a range within which the potential of the signal line can change during a period in which the first signal is output to the signal line.

8. The imaging device according to any one of claims 5 to 7, characterized in that the limiting circuit narrows the range within which the potential of the signal line can change during the period in which the second signal and the third signal are output to the signal line.

9. The imaging device according to any one of claims 5 to 8, characterized in that the limiting circuit narrows a range within which the potential of the signal line can change during a period in which the noise signals of each of the first pixel and the second pixel are output to the signal line.

10. An imaging device according to any one of claims 1 to 9, and a signal processing unit that generates an image using a signal output from the imaging device.

11. A moving object including the imaging device according to any one of claims 1 to 9, A moving object comprising: a control unit that controls the movement of the moving object using a signal output from the imaging device.

Images