Semiconductor memory device and control method thereof

Abstract

To provide a semiconductor storage device with a long life and a control method thereof.SOLUTION: A semiconductor storage device includes: a memory transistor; a transistor electrically connected to a gate electrode of the memory transistor; a voltage supply line electrically connected to the gate electrode of the memory transistor via the transistor; a signal supply line connected to a gate electrode of the transistor; a capacitor electrically connected to the gate electrode of the memory transistor without passing through the transistor; and wiring connected to a current path between the gate electrode of the memory transistor and the transistor via the capacitor. At a first timing of a write operation to the memory transistor, the voltage of the voltage supply line is a first voltage, the voltage of the signal supply line is a second voltage, and the voltage of the wiring is a third voltage. At a second timing, the voltage of the signal supply line rises to a fourth voltage. At a third timing, the voltage of the wiring rises to a fifth voltage.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] 2. Description of the Related Art Semiconductor memory devices including a plurality of memory transistors are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-157260 A Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a semiconductor memory device having a long life. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first memory transistor, a first transistor, a first voltage supply line, a first signal supply line, a first capacitor, and a first wiring. The first transistor is electrically connected to a gate electrode of the first memory transistor. The first voltage supply line is electrically connected to the gate electrode of the first memory transistor via the first transistor. The first signal supply line is electrically connected to the gate electrode of the first transistor. The first capacitor is electrically connected to the gate electrode of the first memory transistor without the first transistor. The first wiring is connected to a current path between the gate electrode of the first memory transistor and the first transistor via the first capacitor. At a first timing of a write operation to the first memory transistor, the voltage of the first voltage supply line is a first voltage, the voltage of the first signal supply line is a second voltage, and the voltage of the first wiring is a third voltage. At a second timing after the first timing, the voltage of the first signal supply line falls from the second voltage to a fourth voltage smaller than the second voltage. At a third timing that is later than the second timing, the voltage of the first wiring rises from the third voltage to a fifth voltage that is higher than the third voltage. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic block diagram showing a configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Diagram 3] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Diagram 5] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 6] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Figure 7] FIG. 6 is a schematic enlarged view of a portion indicated by A in FIG. 5. [Figure 8]FIG. 7 is a schematic enlarged view of a portion indicated by B in FIG. 6. [Figure 9] FIG. 11 is a schematic cross-sectional view for explaining a read operation. [Figure 10] FIG. 11 is a schematic cross-sectional view for explaining a write operation. [Figure 11] FIG. 11 is a schematic cross-sectional view for explaining an erase operation. [Figure 12] 1 is a schematic circuit diagram for explaining a write operation of the semiconductor memory device according to the embodiment. FIG. [Figure 13] FIG. 11 is a schematic waveform diagram for explaining the write operation. [Figure 14] 13 is a schematic waveform diagram for explaining a write operation of the semiconductor memory device according to the second embodiment. FIG. [Figure 15] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 16] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 17] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 18] 13 is a schematic cross-sectional view for explaining a write operation of the semiconductor memory device according to the fifth embodiment. FIG. [Figure 19] 1 is a schematic cross-sectional view showing a configuration of a transistor TBL0 according to a first comparative example. [Figure 20] 11 is a schematic cross-sectional view showing the configuration of a transistor TBL1 according to a second comparative example. FIG. [Figure 21] 13 is a schematic cross-sectional view showing the configuration of a transistor TBL2 according to a fifth embodiment. FIG. [Figure 22] 13 is a schematic cross-sectional view showing the configuration of a transistor TBL3 according to a sixth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0010] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0011] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0014] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0015] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0016] [First embodiment] [Circuit configuration] Fig. 1 is a schematic block diagram showing the configuration of a semiconductor memory device according to the first embodiment. Figs. 2 to 4 are schematic circuit diagrams showing the configuration of a portion of the semiconductor memory device.

[0017] FIG. 1 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to high active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high active signals and low active signals. In FIG. 1, the reference numerals of the control terminals corresponding to low active signals include an overline. In this specification, the reference numerals of the control terminals corresponding to low active signals include a slash (" / "). The description in FIG. 1 is an example, and the specific embodiment can be appropriately adjusted. For example, it is also possible to make some or all of the high active signals low active signals, and to make some or all of the low active signals high active signals.

[0018] 1, the semiconductor memory device includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0019] [Circuit configuration of memory cell array MCA] 2, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0020] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), a source side select transistor STS, and a source side select transistor STSb. The drain side select transistor STD, the plurality of memory cells MC, the source side select transistor STS, and the source side select transistor STSb are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD, the source side select transistor STS, and the source side select transistor STSb may be simply referred to as select transistors (STD, STS, STSb).

[0021] The memory cells MC are field-effect transistors. The memory cells MC include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC changes depending on the amount of charge in the charge storage film. The memory cells MC store one bit or multiple bits of data. The gate electrodes of the memory cells MC corresponding to one memory string MS are each realized by a part of a word line WL. These word lines WL each function as the gate electrodes of the memory cells MC included in all the memory strings MS in one memory block BLK.

[0022] The selection transistors (STD, STS, STSb) are field-effect transistors. The selection transistors (STD, STS, STSb) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are realized by parts of the selection gate lines (SGD, SGS, SGSb). One drain side selection gate line SGD functions as the gate electrodes of the drain side selection transistors STD included in all the memory strings MS in one string unit SU. One source side selection gate line SGS functions as the gate electrodes of the source side selection transistors STS included in all the memory strings MS in one memory block BLK. One source side selection gate line SGSb functions as the gate electrodes of the source side selection transistors STSb included in all the memory strings MS in one memory block BLK.

[0023] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 1) includes a plurality of voltage generating units vg1 to vg3, as shown in FIG. 3. The voltage generating units vg1 to vg3 generate voltages of a predetermined magnitude in a read operation, a write operation, and an erase operation, and supply the voltage to the voltage supply line L. VG1 ,L VG2 ,L VG3 The operating voltages output from the voltage generating units vg1 to vg3 are appropriately adjusted in accordance with control signals from the sequencer SQC and the like.

[0024] The voltage generating unit vg1 is a boosting circuit such as a charge pump circuit. CC is boosted to the voltage supplied to the selected word line (voltage V PGM -α (FIG. 13)). In addition, the voltage generating unit vg1 outputs the power supply voltage V CC is boosted to the erase voltage V ERA The output terminal of the voltage generating unit vg1 may be connected to the voltage supply line L VG1 The voltage supply line LVG1 is electrically connected to the voltage generating unit vg2.

[0025] The voltage generating unit vg2 is, for example, a step-down circuit such as a regulator. In a read operation, the voltage generating unit vg2 generates a read pass voltage V READ In addition, in the write operation, the voltage generating unit vg2 outputs a write pass voltage V PASS Output.

[0026] The voltage generation unit vg3 is, for example, a step-down circuit such as a regulator. In a read operation, the voltage generation unit vg3 outputs a read voltage, which will be described later. In a write operation, the voltage generation unit vg3 outputs a verify voltage, which will be described later.

[0027] [Circuit configuration of row decoder RD] As shown in FIG. 3, the row decoder RD includes a block decoder BLKD, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0028] The block decoder BLKD includes a plurality of block decode units blkd. The plurality of block decode units blkd correspond to a plurality of memory blocks BLK in the memory cell array MCA. The block decode unit blkd includes a plurality of transistors T BLK A plurality of transistors T BLK The transistors T BLK is, for example, a field effect NMOS transistor. BLK The drain electrode of the transistor T is connected to the word line WL. BLK The source electrode of the transistor T is connected to a voltage supply line CG. The voltage supply line CG is connected to all the block decode units blkd in the block decoder BLKD. BLKThe gate electrodes of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T20, T21, T32, T42, T19, T22, T23, T34, T44, T56, T68, T18, T25, T19, T26, T36, T48, T19, T27, T18, T28, T39, T49, T56, T68, T19, T29, T30, T41, T42, T56, T68, T10, T21, T12, T22, T13, T23, T14, T24, T15, T25, T36, T42, T16, T26, T BLK is connected to.

[0029] In a read operation, a write operation, etc., for example, the address data D in the address register ADR (FIG. 1) ADD The voltage of one signal supply line BLKSEL corresponding to the block address included in the block address BLKSEL is set to the “H” state, and the voltage of the other signal supply lines BLKSEL is set to the “L” state. For example, a predetermined driving voltage having a positive magnitude is supplied to one signal supply line BLKSEL, and a ground voltage V SS As a result, all word lines WL in one memory block BLK corresponding to this block address are electrically connected to all voltage supply lines CG. Also, all word lines WL in the other memory blocks BLK are in a floating state.

[0030] The word line decoder WLD includes a plurality of word line decode units wld. The plurality of word line decode units wld correspond to a plurality of memory cells MC in the memory string MS. In the illustrated example, the word line decode unit wld includes two transistors T WLS ,T WLU The transistor T WLS ,T WLU is, for example, a field effect NMOS transistor. WLS ,T WLU The drain electrode of the transistor T is connected to the voltage supply line CG. WLS The source electrode of the voltage supply line CG S Transistor T WLU The source electrode of the voltage supply line CG U Transistor T WLS The gate electrode of the signal supply line WLSEL S Transistor T WLUThe gate electrode of the signal supply line WLSEL U Signal supply line WLSEL S is one of the transistors T included in each word line decode unit wld. WLS A plurality of signal supply lines WLSEL are provided corresponding to the signal supply lines WLSEL. U The other transistor T included in each word line decode unit wld is WLU A plurality of such sensors are provided corresponding to the number of sensors.

[0031] In a read operation, a write operation, etc., for example, the address data D in the address register ADR (FIG. 1) ADD A signal supply line WLSEL corresponding to one word line decode unit wld corresponding to the page address included in S The voltage of the WLSEL U The voltage of the signal supply line WLSEL corresponding to the other word line decode units wld is in the “L” state. S The voltage of the WLSEL U The voltage of the voltage supply line CG S The selected word line WL S A voltage corresponding to the voltage supply line CG U The unselected word lines WL U As a result, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. S In addition, a voltage corresponding to the unselected word line WL is supplied to the other word lines WL. U A voltage corresponding to

[0032] The driver circuit DRV is, for example, a transistor T DRV1 ~T DRV4 The transistor T DRV1 ~T DRV4 is, for example, a field effect NMOS transistor. DRV1 ~T DRV3 The drain electrode of S Transistor TDRV4 The drain electrode of U Transistor T DRV1 The source electrode of the voltage supply line L VG1 , and is connected to the output terminal of the voltage generating unit vg1 via the transistor T DRV2 ,T DRV4 The source electrode of the voltage supply line L VG2 , and is connected to the output terminal of the voltage generating unit vg2 via the transistor T DRV3 The source electrode of the voltage supply line L VG3 , and is connected to the output terminal of the voltage generating unit vg3 via the transistor T DRV1 ~T DRV4 The gate electrodes of these transistors are connected to signal supply lines VSEL1 to VSEL4, respectively.

[0033] In a read operation, a write operation, etc., for example, the voltage supply line CG S The voltage of one of the multiple signal supply lines VSEL1 to VSEL3 corresponding to the voltage supply line CG U The voltage of the signal supply line VSEL4 corresponding to this signal becomes "H".

[0034] An address decoder (not shown) sequentially reads address data D from the address register ADR (FIG. 1) in accordance with a control signal from the sequencer SQC (FIG. 1). ADD The address decoder refers to the row address RA included in the signal supply lines BLKSEL and WLSEL. The row address RA includes the above-mentioned block address and page address. S ,WLSEL U The voltage is controlled to be in the “H” or “L” state.

[0035] In the example of Fig. 3, the row decoder RD is provided with one block decode unit blkd for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block decode unit blkd may be provided for two or more memory blocks BLK.

[0036] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM includes a plurality of sense amplifiers SA, as shown in FIG. 4. The plurality of sense amplifiers SA are electrically connected to a plurality of bit lines BL. In addition, a plurality of transistors T BL The plurality of transistors T BL The gate electrodes of the transistors T BL The drain electrode of the bit line BL is connected to the erase voltage V ERA (for example, the voltage generating unit vg1 in FIG. 3).

[0037] [Circuit configuration of cache memory CM] The cache memory CM (FIG. 1) includes a plurality of latch circuits. The plurality of latch circuits are connected to the sense amplifier module SAM via wiring DBUS. Data DAT contained in the plurality of latch circuits is transferred sequentially to the sense amplifier module SAM or the input / output control circuit I / O.

[0038] A decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the address data D in the address register ADR. ADD The switch circuit connects the latch circuit corresponding to the column address CA to the bus DB (FIG. 1) in response to the output signal of the decode circuit.

[0039] [Circuit configuration of sequencer SQC] The sequencer SQC (Figure 1) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D STis output to the status register STR.

[0040] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / / BY. While the voltage of the terminal RY / / BY is in the "L" state, access to the semiconductor memory device is basically prohibited. Meanwhile, while the voltage of the terminal RY / / BY is in the "H" state, access to the semiconductor memory device is permitted.

[0041] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are each connected to a power supply voltage V CCQ and ground voltage V SS is connected to the terminal supplied with

[0042] The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to the internal control signal from the logic circuit CTR. Also, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to the internal control signal from the logic circuit CTR.

[0043] The input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the toggle signal input / output terminals DQS, / DQS. The output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the toggle signal input / output terminals DQS, / DQS.

[0044] [Circuit configuration of logic circuit CTR] The logic circuit CTR (FIG. 1) receives external control signals via external control terminals / CEn, CLE, ALE, / WE, / RE, and RE, and outputs internal control signals to the input / output control circuit I / O in response to the external control signals.

[0045] [Structure of semiconductor memory device] FIG. 5 is a schematic plan view showing a configuration of a portion of a semiconductor memory device. FIG. 6 is a schematic perspective view showing a configuration of a portion of a semiconductor memory device. Note that FIG. 6 is a diagram for explaining the schematic configuration of the semiconductor memory device, and does not show the number, shape, arrangement, etc. of specific components. FIG. 7 is a schematic enlarged view of a portion indicated by A in FIG. 5. FIG. 8 is a schematic enlarged view of a portion indicated by B in FIG. 6.

[0046] 5, the semiconductor memory device includes a semiconductor substrate 100. In the illustrated example, the semiconductor substrate 100 includes four memory cell array regions R aligned in the X and Y directions. MCA will be established.

[0047] The semiconductor memory device includes, for example, a semiconductor substrate 100 and a transistor layer L provided on the semiconductor substrate 100, as shown in FIG. TR and the transistor layer L TR A memory cell array layer L MCA and the memory cell array layer L MCA and a wiring layer M0 provided above the wiring layer M1.

[0048] [Structure of semiconductor substrate 100] The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region in which the N-type well region and the P-type well region are not provided, and an insulating region 100I are provided.

[0049] [Transistor Layer L TR Structure of For example, as shown in FIG. 6, a wiring layer GC is provided on the upper surface of the semiconductor substrate 100 via an insulating layer. The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. The plurality of electrodes gc function as gate electrodes of a plurality of transistors Tr constituting the peripheral circuit PC, electrodes of a plurality of capacitors, and the like. The plurality of electrodes gc are each connected to a contact electrode CS. The contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The plurality of contact electrodes CS are connected to a plurality of wirings included in the wiring layers D0, D1, and D2. The plurality of wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0050] [Memory cell array layer L MCA Structure of For example, as shown in FIG. MCA The memory cell array region R MCA In the memory block BLK, a plurality of memory blocks BLK arranged in the Y direction are provided. The memory block BLK includes a plurality of string units SU arranged in the Y direction, as shown in FIG. 7, for example. An inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction. An inter-string unit insulating layer SHE made of silicon oxide (SiO2) or the like is provided between two string units SU adjacent to each other in the Y direction, as shown in FIG. 7, for example.

[0051] As shown in FIG. 6, the memory block BLK includes a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0052] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction. A contact electrode CC extending in the Z direction is provided at one end of the conductive layer 110 in the X direction.

[0053] 6, a conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 is provided between the conductive layer 111 and the conductive layer 110.

[0054] A conductive layer 112 is provided below the conductive layer 111. The conductive layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 112 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. An insulating layer 101 is provided between the conductive layer 112 and the conductive layer 111.

[0055] The conductive layer 112 functions as a source line SL (FIG. 2). The conductive layer 112 is, for example, MCA This is provided commonly to all memory blocks BLK included in FIG.

[0056] The conductive layer 111 functions as a gate electrode of a source side select gate line SGSb (FIG. 2) and a plurality of source side select transistors STSb connected thereto. The conductive layer 111 is electrically independent for each memory block BLK.

[0057] Among the multiple conductive layers 110, one or more conductive layers 110 located in the lowest layer function as a source side select gate line SGS (FIG. 2) and the gate electrodes of multiple source side select transistors STS connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0058] Moreover, the multiple conductive layers 110 located above the word lines WL function as gate electrodes of the multiple memory cells MC connected thereto (FIG. 2). The multiple conductive layers 110 are electrically independent for each memory block BLK.

[0059] In addition, one or more conductive layers 110 located above the drain side select gate line SGD function as gate electrodes of the drain side select transistors STD (FIG. 2) connected thereto. For example, as shown in FIG. 7, the width Y SGD is the width Y of the other conductive layer 110 in the Y direction WL 7, the above-mentioned inter-string unit insulating layer SHE is provided between two conductive layers 110 adjacent to each other in the Y direction. Each of the multiple conductive layers 110 is electrically independent for each string unit SU.

[0060] The semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 7. The semiconductor pillars 120 function as channel regions of a plurality of memory cells MC and select transistors (STD, STS, STSb) included in one memory string MS (FIG. 2). The semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially cylindrical shape, for example, as shown in FIG. 6, and an insulating layer 125 such as silicon oxide is provided in the center portion.

[0061] The outer periphery of the semiconductor pillar 120 is surrounded by a plurality of conductive layers 110 and 111, respectively, and faces these plurality of conductive layers 110 and 111. The lower end of the semiconductor pillar 120 is connected to the conductive layer 112. The upper end of the semiconductor pillar 120 is connected to the bit line BL via an impurity region 121 containing N-type impurities such as phosphorus (P) and contact electrodes Ch and Vy. The bit line BL extends in the Y direction and is aligned in the X direction.

[0062] The gate insulating film 130 has a substantially cylindrical shape covering the outer circumferential surface of the semiconductor pillar 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110, as shown in FIG. 8, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the conductive layer 112.

[0063] 8 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0064] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to FIG 9, which is a schematic cross-sectional view for explaining the read operation.

[0065] In the following description, the word line WL that is the object of the operation is referred to as the selected word line WL S and the other word lines WL are called unselected word lines WL U In the following description, the selected word line WLS An example will be described in which a read operation is performed on a memory cell connected to the selected page PG (hereinafter, sometimes referred to as a "selected memory cell MC"). In the following description, a configuration including such a plurality of selected memory cells MC may be referred to as a selected page PG.

[0066] In a read operation, for example, a voltage V DD Also, a voltage V SRC Supply voltage V SRC is the ground voltage V SS It can be larger than the ground voltage V SS It can be equal to the voltage V DD is the voltage V SRC Greater than.

[0067] In addition, in the read operation, the drain side select gate line SGD is applied with a voltage V SG Supply voltage V SG is the voltage V DD Also, the voltage V SG and voltage V DD The voltage difference between the drain side select transistor STD and the drain side select transistor STD is greater than the threshold voltage when the drain side select transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain side select transistor STD, and a voltage V DD will be transferred.

[0068] In addition, in the read operation, a voltage V SG Supply voltage V SG is the voltage V SRC Also, the voltage V SG and voltage V SRC The voltage difference between the source side select transistors STS and STSb and the threshold voltage when the source side select transistors STS and STSb function as NMOS transistors is larger than the threshold voltage. Therefore, an electron channel is formed in the channel region of the source side select transistors STS and STSb, and a voltage V SRC will be transferred.

[0069] In a read operation, the unselected word lines WLU Read pass voltage V READ The read pass voltage V READ is the voltage V DD ,V SRC Also, the read pass voltage V READ and voltage V DD ,V SRC The voltage difference between the selected memory cell MC and the unselected memory cell MC is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and a voltage V DD ,V SRC will be transferred.

[0070] In a read operation, the selected word line WL S Read voltage V CGR Supply the read voltage V CGR is the read pass voltage V READ The read voltage V CGR and V SRC The voltage difference between the read voltage V and the bit line BL is larger than the threshold voltage of the memory cell MC in which some data is stored. Therefore, the memory cell MC in which some data is stored is in the ON state. Therefore, a current flows through the bit line BL connected to such a memory cell MC. On the other hand, the read voltage V CGR and V SRC The voltage difference between the bit line BL and the threshold voltage of the memory cell MC in which some data is stored is smaller than the threshold voltage of the memory cell MC in which some data is stored. Therefore, the memory cell MC in which some data is stored is in the OFF state. Therefore, no current flows through the bit line BL connected to such a memory cell MC.

[0071] In addition, in a read operation, the sense amplifier module SAM (Figure 1) detects whether or not a current flows through the bit line BL, thereby detecting the ON / OFF state of the memory cell MC, and thereby obtaining data indicating the state of the memory cell MC.

[0072] Furthermore, in a read operation, arithmetic operations such as AND and OR are performed on the data indicating the state of the memory cells MC as necessary, thereby calculating the data recorded in the memory cells MC.

[0073] [Write operation] Next, a write operation of the semiconductor memory device according to this embodiment will be described with reference to FIG 10, which is a schematic cross-sectional view for explaining the write operation.

[0074] In the following description, an example will be described in which a write operation is performed on a plurality of selected memory cells MC corresponding to a selected page PG.

[0075] In a write operation, for example, a bit line BL connected to one of the selected memory cells MC for which the threshold voltage is to be adjusted is W Voltage V SRC Also, the bit line BL connected to the selected memory cells MC whose threshold voltages are not adjusted is supplied. P Voltage V DD Hereinafter, among the multiple selected memory cells MC, those whose threshold voltages are adjusted are sometimes called "write memory cells MC," and those whose threshold voltages are not adjusted are sometimes called "prohibited memory cells MC."

[0076] In addition, in the write operation, the drain side select gate line SGD is applied with a voltage V SGD is supplied.

[0077] Voltage V SGD is the voltage V SRC Also, the voltage V SGD and voltage V SRC The voltage difference between the drain side select transistor STD and the bit line BL W An electron channel is formed in the channel region of the drain side select transistor STD connected to SRC will be transferred.

[0078] On the other hand, voltage VSGD and voltage V DD The voltage difference between the drain side select transistor STD and the bit line BL P The drain side select transistor STD connected to is turned off.

[0079] In the write operation, the source line SL is supplied with a voltage V SRC is supplied to the source side select gate lines SGS and SGSb, and the ground voltage V SS As a result, the source side selection transistors STS and STSb are turned off.

[0080] In addition, in a write operation, the unselected word lines WL U Write pass voltage V PASS The write pass voltage V PASS is the read pass voltage V READ Also, the write pass voltage V PASS and voltage V SRC The voltage difference between the non-selected memory cell MC and the write memory cell MC is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and a voltage V SRC will be transferred.

[0081] In a write operation, the selected word line WL S Program voltage V PGM Supply the program voltage V PGM is the write pass voltage V PASS Greater than.

[0082] Here, for example, as shown in FIG. W The channel of the semiconductor pillar 120 connected to SRC Such a semiconductor pillar 120 and the selected word line WL SA relatively large electric field is generated between the charge storage film 132 (FIG. 8) and the write memory cell MC. This causes electrons in the channel of the semiconductor pillar 120 to tunnel into the charge storage film 132 (FIG. 8) through the tunnel insulating film 131 (FIG. 8). This increases the threshold voltage of the write memory cell MC.

[0083] Also, the bit line BL P The channel of the semiconductor pillar 120 connected to the selected word line WL is electrically floating, and the potential of this channel is U The write pass voltage V PASS The semiconductor pillar 120 and the selected word line WL S An electric field smaller than the electric field described above is generated between the semiconductor pillar 120 and the charge storage film 132. Therefore, the electrons in the channel of the semiconductor pillar 120 do not tunnel into the charge storage film 132 (FIG. 8). Therefore, the threshold voltage of the inhibit memory cell MC does not increase.

[0084] [Erase operation] Next, the erase operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 11, which is a schematic cross-sectional view for explaining the erase operation.

[0085] In the following description, an example will be described in which an erase operation is performed on a memory block BLK that is the target of the operation.

[0086] In the erase operation, an erase voltage V ERA The erase voltage V ERA For example, the program voltage V PGM It can be larger than the program voltage V PGM It may be equal to.

[0087] In addition, in the erase operation, the drain side select gate line SGD is applied with a voltage V SG ´ is supplied. Voltage V SG ´ is the erase voltage V ERAThis causes gate induced drain leakage (GIDL) in the drain side select transistor STD, generating electron-hole pairs. The electrons move to the bit line BL, and the holes move to the memory cell MC.

[0088] In addition, in the erase operation, the source side select gate lines SGS and SGSb are supplied with a voltage V SG ´´ is supplied. Voltage V SG ´´ is the erase voltage V ERA This causes GIDL in the source side select transistors STS and STSb, generating electron-hole pairs. The electrons move to the source line SL, and the holes move to the memory cell MC.

[0089] In the erase operation, the word line WL is applied with the ground voltage V SS is supplied. As a result, holes in the channel of the semiconductor pillar 120 tunnel into the charge storage film 132 (FIG. 8) via the tunnel insulating film 131 (FIG. 8). This reduces the threshold voltage of the memory cell MC.

[0090] In the erase operation, the transistor T BL is turned off. Therefore, in the erase operation, the sense amplifier module SAM is electrically disconnected from the bit line BL.

[0091] [Program voltage V PGM How to generate As described with reference to FIG. 10, in the semiconductor memory device according to the first embodiment, the selected word line WL S Program voltage V PGM where the program voltage V PGM is a relatively large voltage among the voltages used in semiconductor memory devices. Therefore, the program voltage V PGM In some cases, concerns may arise regarding the withstand voltage, reliability, life, etc. of the configuration for controlling the above.

[0092] Therefore, in the semiconductor memory device according to the first embodiment, the program voltage V PGM This prevents the occurrence of concerns regarding the breakdown voltage, reliability, and lifespan.

[0093] Fig. 12 is a schematic circuit diagram for explaining the write operation of the semiconductor memory device according to this embodiment, and Fig. 13 is a schematic waveform diagram for explaining the same write operation.

[0094] FIG. 12 illustrates one memory cell MC. FIG. 12 also illustrates a word line WLa connected to this memory cell MC and another word line WLb. These two word lines WLa, WLb are connected to other components in the peripheral circuit PC via transistors Ta, Tb and voltage supply lines Lwla, Lwlb, respectively. A common signal supply line Lg1 is connected to the gate electrodes of the transistors Ta, Tb. The memory cell MC also includes a bit line BL and a transistor T BL The peripheral circuit PC is connected via the transistor T BL A signal supply line Lg2 is connected to the gate electrode of this transistor.

[0095] The transistors Ta and Tb are, for example, the transistor T BLK 4. Moreover, the signal supply line Lg1 may be the signal supply line BLKSEL described with reference to Fig. 3. Moreover, the voltage supply lines Lwla, Lwlb may be, for example, the voltage supply line CG described with reference to Fig. 3. Moreover, the signal supply line Lg2 may be the signal supply line BLS described with reference to Fig. 4.

[0096] As shown in FIG. 12, the semiconductor memory device according to this embodiment includes capacitors Cba and Cbb connected to word lines WLa and WLb, and a wiring Lb commonly connected to these capacitors Cba and Cbb.

[0097] As shown in FIG. 13, at timing t101 of the write operation according to this embodiment, a write pass voltage V PASS and the signal supply line Lg1 is supplied with a voltage V PGMH and the ground voltage V SS and supplies the bit line BL W Voltage V SRC and the signal supply line Lg2 is supplied with a voltage V DD Supply voltage V PGMH For example, the voltage V PGM At timing t101, the word lines WLa and WLb are applied with a write pass voltage V PASS will be transferred.

[0098] At timing t102, the voltage supply line Lwla is supplied with the voltage V PGM Supply voltage V PGM -α is the program voltage V PGM This causes the word line WLa to have a voltage V PGM -α is transferred.

[0099] At timing t103, the signal supply lines Lg1 and Lg2 are supplied with the ground voltage V SS This causes the word lines WLa, WLb and the bit line BL to be in a floating state. Note that the voltage of the signal supply line Lg1 is set to a voltage at which the transistors Ta, Tb are in an OFF state, and is set to a ground voltage V SS It doesn't have to be.

[0100] At timing t104, the voltage of the wiring Lb is set to the ground voltage V SS Then, the voltage is raised to α.

[0101] As described with reference to FIG. 12, the capacitors Cba and Cbb are provided between the wiring Lb and the word lines WLa and WLb. Therefore, the voltage of the wiring Lb is set to the ground voltage V SS When the program voltage VPGM In the illustrated example, the voltage of the word line WLb rises to the write pass voltage V PASS Voltage greater than V PASS It has increased to +α.

[0102] Furthermore, when the voltages of the word lines WLa and WLb increase by voltage α, the potential of the electron channel formed on the outer circumferential surface of the semiconductor pillar 120 also increases by about voltage α due to capacitive coupling between the word line WL and the semiconductor pillar 120. This causes the voltage of the bit line BL to also increase by about voltage α. In the illustrated example, the voltage of the bit line BL is increased by voltage V SRC It has increased to +α.

[0103] In the illustrated example, at timing t104, the voltage supply lines Lwla and Lwlb are supplied with a ground voltage V SS is being supplied.

[0104] At timing t105, the signal supply line Lg2 is supplied with a voltage V DD This causes the bit line BL to be supplied with a voltage V SRC This causes the voltages described with reference to FIG.

[0105] At timing t106, the voltage of the wiring Lb is changed from the voltage α to the ground voltage V SS In addition, the signal supply line Lg1 is turned on. PGMH This causes the charges in the word lines WLa and WLb to be discharged, and the ground voltage V SS Stand down until

[0106] At timing t107, the voltages of the signal supply lines Lg1 and Lg2 are set to the ground voltage V SS Stand down until

[0107] Here, for example, the transistors Ta and Tb are the transistors T BLK When the voltage supply lines Lwla and Lwlb are the voltage supply lines CG described with reference to FIG. 3, a voltage is generated from the output terminal of the voltage generating unit vg1 to the transistor TBLK The maximum voltage in the current path up to the source terminal of the PGM Voltage V PGM -α.

[0108] According to this method, the voltage to be transferred is reduced, so that the transistor T WLS ,T WLU ,T DRV1 ,T DRV3 It is possible to suppress concerns about the withstand voltage, reliability, and life of the voltage generating unit vg1. It is also possible to adopt a transistor having a smaller circuit area. BLK The maximum voltage V supplied to the gate electrodes of PGMH It is possible to reduce the BLK Therefore, it is possible to suppress the occurrence of leakage current between the first and second electrodes.

[0109] [Second embodiment] Next, the semiconductor memory device according to the second embodiment will be described with reference to Fig. 14. Fig. 14 is a schematic waveform diagram for explaining the write operation of the semiconductor memory device according to the present embodiment.

[0110] The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, part of the write operation in the semiconductor memory device according to the second embodiment is different from part of the write operation in the semiconductor memory device according to the first embodiment.

[0111] As shown in FIG. 14, the operations at timings t201 and t202 of the write operation according to this embodiment are similar to the operations at timings t101 and t102 of the write operation according to the first embodiment.

[0112] At timing t203, the voltage V1 is supplied to the signal supply line Lg1, and the ground voltage V SS Here, voltage V1 is the write pass voltage V PASS Also, the voltage V1 and the write pass voltage VPASS The voltage difference between V1 and V2 is greater than the threshold voltage of the transistor Tb. Therefore, the transistor Tb is maintained in the ON state. On the other hand, PGM The voltage difference between -α is smaller than the threshold voltage of the transistor Ta, so the transistor Ta is turned off, and the word line WLa is selectively brought into a floating state.

[0113] At timing t204, the voltage of the wiring Lb is set to the ground voltage V SS The voltage of the word line WLa is increased from the program voltage V PGM Meanwhile, the voltage of the word line WLb rises to the write pass voltage V PASS In the illustrated example, at timing t204, the voltage of the voltage supply line Lwla is maintained at voltage V PGM -α. This is to keep the transistor Ta in the OFF state. Also, the voltage of the voltage supply line Lwlb is kept at the write pass voltage V PASS This is because the transistor Tb is in the ON state.

[0114] The operation from timing t205 to t207 is basically the same as the operation from timing t105 to t107 of the write operation according to the first embodiment. However, at timing t206, the ground voltage V SS is being supplied.

[0115] According to this method, the unselected word lines WL U The voltage of the write pass voltage V PASS It is possible to maintain

[0116] [Third embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to Fig. 15. Fig. 15 is a schematic cross-sectional view for explaining a write operation of the semiconductor memory device according to this embodiment.

[0117] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first or second embodiment. However, in the semiconductor memory device according to the third embodiment, the source lines SL are electrically independent for each string unit SU. FIG. 15 illustrates a conductive layer 312 that functions as a source line SL. The conductive layer 312 is basically configured in the same manner as the conductive layer 112. However, the conductive layer 312 is electrically independent for each string unit SU.

[0118] In the semiconductor memory device according to the third embodiment, in a write operation, the configuration in the string unit SU that does not include the selected page PG is used as the capacitors Cba and Cbb (FIG. 12). For example, when the string unit SUa includes the selected page PG, the semiconductor pillars 120 corresponding to the string units SUb-SUe function as one electrode of the capacitors Cba and Cbb. Also, the multiple conductive layers 110 function as the other electrode of the capacitors Cba and Cbb. Also, the conductive layers 312 (source lines SL) corresponding to the string units SUb-SUe function as the wiring Lb.

[0119] The write operation according to the third embodiment is basically performed in the same manner as the write operation according to the first or second embodiment. However, in the write operation of the semiconductor memory device according to the third embodiment, for example, the voltage of the conductive layer 312 corresponding to the string unit SUa is set to a voltage higher than the voltage of the conductive layer 312 corresponding to the string units SUb to SUe. Also, the voltages of the source side select gate lines SGS, SGSb are adjusted to a magnitude such that the source side select transistors STS, STSb corresponding to the string unit SUa are in the OFF state and the source side select transistors STS, STSb corresponding to the string units SUb to SUe are in the ON state. Also, at timing t104 in FIG. 13 or timing t204 in FIG. 14, the voltage of the conductive layer 312 corresponding to the string units SUb to SUe is increased by a voltage α. Accordingly, the potential of the channel formed on the outer circumferential surface of the semiconductor pillar 120 in the string units SUb to SUe increases by α. Furthermore, due to capacitive coupling between semiconductor pillar 120 and conductive layer 110, the voltage of conductive layer 110 increases by α.

[0120] When such a method is adopted, the voltage of the conductive layer 312 corresponding to the string units SUb to SUe is V SRC If the voltage V s is about 10 V, the threshold voltage of the memory cells MC in the string units SUb to SUe may vary. Therefore, the voltage of the conductive layer 312 corresponding to the string units SUb to SUe is set to at least the voltage V SRC Larger is preferable.

[0121] In addition, when such a method is adopted, the voltage of the conductive layer 312 corresponding to the string units SUb to SUe is set to the write pass voltage V PASS If the voltage is about 10 V, there is a risk that an electron channel will not be formed on the outer circumferential surface of the semiconductor pillar 120. Therefore, the voltage of the conductive layer 312 corresponding to the string units SUb to SUe is, for example, a write pass voltage V PASS and the read pass voltage V READ Voltage difference with the voltage V PASS -V READ Smaller is preferable.

[0122] [Fourth embodiment] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Fig. 16 and Fig. 17. Fig. 16 and Fig. 17 are schematic cross-sectional views showing a configuration of a part of the semiconductor memory device according to this embodiment. Note that the Y-direction position corresponding to the XZ cross section in Fig. 16 is different from the Y-direction position corresponding to the XZ cross section in Fig. 17.

[0123] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the first or second embodiment. However, as shown in Fig. 17, the semiconductor memory device according to the fourth embodiment includes an insulating layer 401 and a conductive layer 410 that cover the ends in the X direction of the multiple conductive layers 110. The conductive layer 410 functions as one electrode of the capacitors Cba and Cbb and the wiring Lb described with reference to Fig. 12.

[0124] 16 and 17 show the ends in the X direction of the multiple conductive layers 110 aligned in the Z direction. FIG. 16 also shows multiple contact electrodes CC aligned in the X direction. FIG. 17 shows a conductive layer 410 and an insulating layer 401. The conductive layer 410 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 410 includes multiple facing regions 411 and multiple connection regions 412. Each of the multiple facing regions 411 extends in the X direction and faces the upper surfaces of the multiple conductive layers 110 aligned in the Z direction. Each of the connection regions 412 extends in the Z direction and is connected to two facing regions at different heights. The insulating layer 401 includes, for example, silicon oxide (SiO2).

[0125] [Fifth embodiment] Next, a semiconductor memory device according to a fifth embodiment will be described.

[0126] In the first to fourth embodiments, the word line WL is electrically separated from the peripheral circuit PC, and the program voltage V PGMThis suppresses concerns about the withstand voltage, reliability, and lifespan of the components in the peripheral circuit PC.

[0127] However, this method is merely an example. For example, if a negative voltage is supplied to the bit line BL in a write operation, the selected word line WL S It is possible to reduce the voltage supplied to the

[0128] Fig. 18 is a schematic cross-sectional view for explaining a write operation of the semiconductor memory device according to the fifth embodiment. The write operation according to the fifth embodiment is basically performed similarly to the write operation described with reference to Fig. 10. However, in the write operation according to the fifth embodiment, as shown in Fig. 18, the voltages supplied to the bit lines BL, word lines WL, and drain side select gate lines SGD are lower by a voltage β than the respective voltages described with reference to Fig. 10.

[0129] When the write operation is performed in this manner, for example, the bit line BL W The negative voltage V SRC In such a case, the transistor T BL It is desirable to adopt a configuration capable of supplying a negative voltage as the power supply voltage, as will be described below.

[0130] FIG. 19 shows a transistor T BL FIG. 19 is a schematic cross-sectional view showing the configuration of a transistor T BL As an example of the configuration of the transistor T BL0 The transistor T BL0 is provided on a P-type semiconductor substrate 100. S The contact area with the junction is an impurity region R containing N-type impurities. n+ The drain electrode CS of the semiconductor substrate 100 is provided. D The contact area with the junction is an impurity region R containing N-type impurities. n+ A part of the semiconductor substrate 100 is provided with a transistor TBL0 This channel region and the drain electrode CS D Between them is a diffusion region R containing N-type impurities. n- The semiconductor substrate 100 is also provided with an electrode CS for supplying a substrate voltage to the semiconductor substrate 100. Sub This electrode CS Sub The ground voltage V SS is being supplied.

[0131] In such a configuration, for example, transistor T BL0 Source electrode CS S When a negative voltage is applied to the electrode CS Sub and the source electrode CS S This may result in a forward bias relationship between the first and second electrodes, causing a large current to flow through the semiconductor substrate 100. This may also result in the entire device being destroyed.

[0132] FIG. 20 shows a transistor T BL FIG. 20 is a schematic cross-sectional view showing the configuration of a transistor T BL As an example of the configuration of the transistor T BL1 In the example of FIG. 20, an N-type well W containing N-type impurities is formed in a P-type semiconductor substrate 100. n In addition, the N-type well W n P-type well W containing P-type impurities p A transistor T BL1 is basically a transistor T BL0 The transistor T BL1 is P-type well W p In the example of FIG. 20, the N-type well W n 2, electrode CS Wn In addition, a P-type well W p 2, electrode CS Wp Also, the electrode CS Wn is the voltage V DD is supplied, and the electrode CS Wp is the voltage V SS´ is being supplied.

[0133] In such a configuration, for example, transistor T BL1 Source electrode CS S When a negative voltage is applied to the electrode CS Wp Voltage V SS By making the polarity of the voltages of the polarities of the terminals ' and ' also negative, the voltages of the negative polarity can be suitably transferred.

[0134] However, in such a configuration, the semiconductor substrate 100 has an N-type well W n and P-type well W p This may result in an increase in the circuit area.

[0135] Therefore, in this embodiment, the transistor T BL As the negative polarity voltage, a transistor capable of suitably transferring a negative polarity voltage while suppressing an increase in the circuit area is adopted.

[0136] FIG. 21 shows a transistor T BL FIG. 21 is a schematic cross-sectional view showing the configuration of a transistor T BL As an example of the configuration of the transistor T BL2 21 illustrates a semiconductor substrate 100, a semiconductor layer 510 facing the upper surface of the semiconductor substrate 100, and a gate insulating film 501 such as silicon oxide (SiO2) provided between the semiconductor substrate 100 and the semiconductor layer 510.

[0137] In the illustrated example, an impurity region R containing N-type impurities is formed on the upper surface of the semiconductor substrate 100. n+ This impurity region R n+ is the transistor T BL2 This impurity region R n+ The impurity region R is connected to a contact electrode (not shown). n+ is connected to the signal supply line BLS (FIG. 4) via this contact electrode.

[0138] The semiconductor layer 510 is, for example, a semiconductor layer made of polycrystalline silicon (Si), etc. The semiconductor layer 510 includes a source region 511, a drain region 512, and a gate region 513 provided between them.

[0139] The source region 511 is provided on the upper surface of the insulating region 100I. The upper surface of the source region 511 is connected to the source electrode CS S The source region 511 is connected to an impurity region R n+ is provided.

[0140] The drain region 512 is provided on the upper surface of the insulating region 100I. The upper surface of the drain region 512 is connected to the drain electrode CS D The drain electrode CS of the drain region 512 is connected to D The contact area with the junction is an impurity region R containing N-type impurities. n+ In addition, a diffusion region R containing an N-type impurity is provided in the other region of the drain region 512. n- The diffusion region R n- The impurity concentration of the N-type impurity in the impurity region R n+ The impurity concentration of the N-type impurity in the

[0141] The gate region 513 is provided on the upper surface of the gate insulating film 501. The gate region 513 includes an impurity region R p The lower surface of the gate region 513 is in contact with the impurity region R n+ and is opposed to.

[0142] In such a configuration, for example, transistor T BL2 Source electrode CS S Therefore, even if a negative voltage is supplied to the MOSFET, the above-mentioned current problem does not occur, and the negative voltage can be suitably transferred.

[0143] In addition, in this configuration, an N-type well W is formed in the semiconductor substrate 100. n and P-type well Wp Therefore, it is not necessary to provide the transistor T BL1 This can be realized with a smaller circuit area as compared to the above.

[0144] [Sixth embodiment] Next, a semiconductor memory device according to a sixth embodiment will be described with reference to Fig. 22. Fig. 22 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to this embodiment.

[0145] The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the fifth embodiment. However, in the sixth embodiment, an N-type well W containing N-type impurities is formed in the semiconductor substrate 100. n In addition, the semiconductor memory device according to the sixth embodiment includes a transistor T BL2 Instead of transistor T BL3 It is equipped with:

[0146] Transistor T BL3 Basically, the transistor T BL2 However, in the sixth embodiment, the N-type well W n The upper surface of the impurity region R p+ is provided, and this impurity region R p+ is the transistor T BL3 It functions as a gate electrode.

[0147] Transistor T BL3 In the case of transistor T BL3 As the gate voltage, it is possible to use both a positive voltage and a negative voltage.

[0148] [Other embodiments] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, the above description is merely an example, and the specific configurations, operation methods, and the like can be appropriately adjusted.

[0149] For example, the operation methods described with reference to Figures 13 and 14 are merely examples. In Figures 13 and 14, the magnitude of the voltage supplied to each wiring, the timing of supplying the voltage, etc. can be adjusted as appropriate. For example, the voltage transferred to the voltage supply lines Lwla and Lwlb at timing t101 in Figure 13 is the write pass voltage V PASS Voltage V is smaller than the voltage α PASS -α is also fine.

[0150] Moreover, the capacitors Cba and Cbb in FIG. 12 can be realized by any configuration. For example, the capacitors Cba and Cbb may be realized by the semiconductor substrate 100 (FIG. 6) and the electrode gc (FIG. 6). Alternatively, they may be realized by a capacitor using a configuration such as a contact electrode CC. Alternatively, they may be realized by the conductive layer 110 and the semiconductor pillar 120, as described with reference to FIG. 15. Alternatively, they may be realized by the conductive layer 110 and the conductive layer 410, as described with reference to FIG. 17. Alternatively, they may be realized by other configurations.

[0151] In addition, the semiconductor memory devices according to the first to fourth embodiments include a transistor T BL (Figure 4) As the transistor T BL0 (Fig. 19), transistor T BL1 (Fig. 20), transistor T BL2 (FIG. 21), and transistor T BL3 In the semiconductor memory device according to the first to fourth embodiments, the transistor T BL (Figure 4) may be omitted.

[0152] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0153] MC... memory cell (memory transistor), BL... bit line, WLa, WLb... word line, Ta, Tb, T BL ...transistor, Lwla, Lwlb...voltage supply lines, Lg1, Lg2...signal supply lines, Cba, Cbb...capacitors, Lb...wiring.

Claims

1. A semiconductor substrate, a plurality of first conductive layers arranged in a first direction intersecting a surface of the semiconductor substrate; a first semiconductor pillar extending in the first direction and facing the first conductive layers; a first charge storage film provided between the plurality of first conductive layers and the first semiconductor pillar; a first memory transistor having one of the plurality of first conductive layers as a gate electrode and the first semiconductor pillar as a channel region; a first transistor electrically connected to a gate electrode of the first memory transistor; a first voltage supply line electrically connected to a gate electrode of the first memory transistor via the first transistor; a first signal supply line electrically connected to a gate electrode of the first transistor; a first capacitor electrically connected to the gate electrode of the first memory transistor without passing through the first transistor; a first wiring connected to a current path between a gate electrode of the first memory transistor and the first transistor via the first capacitor; Equipped with the plurality of first conductive layers include a portion that functions as one electrode of the first capacitor; A write operation to the first memory transistor, At a first timing, a voltage of the first voltage supply line is a first voltage, a voltage of the first signal supply line is a second voltage, and a voltage of the first wiring is a third voltage; at a second timing that is later than the first timing, the voltage of the first signal supply line falls from the second voltage to a fourth voltage that is smaller than the second voltage; At a third timing that is later than the second timing, the voltage of the first wiring rises from the third voltage to a fifth voltage that is higher than the third voltage. Semiconductor memory device.

2. a memory string including the first memory transistor and a second memory transistor; a second transistor electrically connected to a gate electrode of the second memory transistor; a second voltage supply line electrically connected to a gate electrode of the second memory transistor via the second transistor; a second capacitor electrically connected to the gate electrode of the second memory transistor without passing through the second transistor; 2. The semiconductor memory device according to claim 1, comprising:

3. During a write operation on the first memory transistor, the voltage of the second voltage supply line is maintained at a sixth voltage lower than the first voltage from the first timing to the third timing.

3. The semiconductor memory device according to claim 2.

4. a second semiconductor pillar extending in the first direction and facing the first conductive layers; a second charge storage film provided between the plurality of first conductive layers and the second semiconductor pillar; Equipped with The second semiconductor pillar includes a portion that functions as the other electrode of the first capacitor.

2. The semiconductor memory device according to claim 1.

5. a first region and a second region aligned in a second direction intersecting the first direction, The first region is the first semiconductor pillar; The first charge storage film; Including, The second region is a plurality of contact electrodes extending in the first direction and connected to the plurality of first conductive layers, respectively; a second conductive layer facing the plurality of first conductive layers; Including, The second conductive layer includes a portion that functions as the other electrode of the first capacitor.

2. The semiconductor memory device according to claim 1.

6. A semiconductor substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the semiconductor substrate; a first semiconductor pillar extending in the first direction and facing the first conductive layers; a first charge storage film provided between the plurality of first conductive layers and the first semiconductor pillar; a first memory transistor having one of the plurality of first conductive layers as a gate electrode and the first semiconductor pillar as a channel region; a first transistor electrically connected to a gate electrode of the first memory transistor; a first voltage supply line electrically connected to a gate electrode of the first memory transistor via the first transistor; a first signal supply line electrically connected to a gate electrode of the first transistor; a first capacitor electrically connected to the gate electrode of the first memory transistor without passing through the first transistor; a first wiring connected to a current path between a gate electrode of the first memory transistor and the first transistor via the first capacitor; Equipped with The plurality of first conductive layers include a portion that functions as one electrode of the first capacitor. A method for controlling a semiconductor memory device, comprising: A write operation to the first memory transistor, At a first timing, a voltage of the first voltage supply line is a first voltage, a voltage of the first signal supply line is a second voltage, and a voltage of the first wiring is a third voltage; at a second timing that is later than the first timing, the voltage of the first signal supply line falls from the second voltage to a fourth voltage that is smaller than the second voltage; At a third timing that is later than the second timing, the voltage of the first wiring rises from the third voltage to a fifth voltage that is higher than the third voltage. A method for controlling a semiconductor memory device.

7. The semiconductor memory device includes: a memory string including the first memory transistor and a second memory transistor; a second transistor electrically connected to a gate electrode of the second memory transistor; a second voltage supply line electrically connected to a gate electrode of the second memory transistor via the second transistor; a second capacitor electrically connected to the gate electrode of the second memory transistor without passing through the second transistor; 7. The method for controlling a semiconductor memory device according to claim 6, further comprising:

8. During a write operation on the first memory transistor, the voltage of the second voltage supply line is maintained at a sixth voltage lower than the first voltage from the first timing to the third timing.

8. The method for controlling a semiconductor memory device according to claim 7.

9. a second semiconductor pillar extending in the first direction and facing the first conductive layers; a second charge storage film provided between the plurality of first conductive layers and the second semiconductor pillar; Equipped with The second semiconductor pillar includes a portion that functions as the other electrode of the first capacitor.

7. The method for controlling a semiconductor memory device according to claim 6.

10. a first region and a second region aligned in a second direction intersecting the first direction, The first region is the first semiconductor pillar; The first charge storage film; Including, The second region is a plurality of contact electrodes extending in the first direction and connected to the plurality of first conductive layers, respectively; a second conductive layer facing the plurality of first conductive layers; Including, The second conductive layer includes a portion that functions as the other electrode of the first capacitor.

7. The method for controlling a semiconductor memory device according to claim 6.

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