Memory Access Control Device

Abstract

To provide a memory access controller that reads out data from memories in one cycle independent of the parallelism of the data and stride.SOLUTION: A system 100 includes an FPGA 400 as a memory access controller. The FPGA comprises: access control units (writing control unit 52, reading control unit 54) that are sequentially assigned with addresses and control accesses to a plurality of memories in and from which data is written and read; a determination unit 62 that determines a read-out path between the access control units and memories through which the data can be read-out from a predetermined number of memories in one cycle, according to parameters including the number of memories used for the accesses, the parallelism of the data indicating the number of memories reading out the data in one access, and stride indicating the interval between read-out addresses corresponding to a data read-out interval; and a reconstruction unit 64 that reconstructs a connection path between the access control units and the memories according to the read-out path determined by the determination unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory access control device. [Background technology]

[0002] Recently, data processing such as image processing can be performed at high speed and with high accuracy by utilizing AI (Artificial Intelligence) technology such as deep learning. Accordingly, there is a demand for hardware accelerators and the like that perform calculations in parallel and at high speed. For example, by storing data of adjacent pixel blocks to which addresses are assigned sequentially in separate external memories, it becomes possible to access multiple parallel pixel data in the same cycle (see, for example, Patent Document 1). In addition, in an image processing memory, by providing independent Y decoders for multiple memory blocks and making it possible to control the memory blocks independently, it becomes possible to read out pixel data thinned out in the horizontal or vertical direction at high speed (see, for example, Patent Document 2). Summary of the Invention [Problem to be solved by the invention]

[0003] However, when data used for image processing or the like is read from memory, the data parallelism, which indicates the number of data read in one access, and the stride, which indicates the data read interval, may change depending on the image processing. Even if data can be read from memory in one cycle with a certain data parallelism or a certain stride, data may not be read from memory in one cycle with another parallelism or another stride.

[0004] The disclosed technology has an object to read data from memory in one cycle, regardless of the parallelism and stride of the data. [Means for solving the problem]

[0005] In order to solve the above technical problem, a memory access control device according to one aspect of the present invention includes an access control unit that controls access to a plurality of memories to which addresses are assigned in sequence and from which data is read and written, and a data parallelism indicating the number of the memories used for access, the number of the memories from which data is read in one access, and a stride indicating an interval between read addresses corresponding to an interval between data reads, according to parameters including: The number of memories satisfying the judgment formula A or the number of memories satisfying all of the judgment formulas B-1, B-2, and B-3 a determination unit that determines a read path between the access control unit and the memory, the read path being capable of reading data from the memory in one cycle; Judgment formula A: (degree of parallelism × (stride + 1)) ≦ number of memories, Judgment formula B-1: (stride + 1) ≠ multiple of number of memories, Judgment formula B-2: number of memories ≠ multiple of (stride + 1), Judgment formula B-3: degree of parallelism ≦ number of memories, The memory device further comprises a reconfiguration unit that reconfigures a connection path between the access control unit and the memory in accordance with the read path determined by the determination unit. Effect of the Invention

[0006] Data can be read from memory in one cycle, regardless of the parallelism and stride of the data. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an example of a system including a memory access control device according to a first embodiment of the present invention. [Diagram 2] FIG. 11 is an explanatory diagram showing an example of reading pixel data according to a change in stride; [Diagram 3] FIG. 11 is an explanatory diagram showing an example of differences in read data depending on combinations of data parallelism and stride. [Figure 4] FIG. 13 is an explanatory diagram showing the relationship between the number of SRAMs and the stride and the number of cycles required for access when the degree of parallelism is 2. [Diagram 5] FIG. 13 is an explanatory diagram showing the relationship between the number of SRAMs and the stride and the number of cycles required for access when the degree of parallelism is 3. [Figure 6] FIG. 11 is an explanatory diagram showing the relationship between the degree of parallelism of data, the number of SRAMs, and the stride and the number of access cycles. [Figure 7]FIG. 11 is a block diagram showing an example of a system including a memory access control device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for signal lines through which information such as signals is transmitted. In addition, in each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted.

[0009] (First embodiment) Fig. 1 is a block diagram showing an example of a system including a memory access control device according to a first embodiment of the present invention. The system 100 shown in Fig. 1 has a control board 200 and an option board 300. For example, the control board 200 has a CPU 20 that controls the overall operation of the system 100. The option board 300 has an FPGA (Field-Programmable Gate Array) 400 that functions as a memory access control device and a plurality of SRAMs (Static Random Access Memories) 30 that are an example of memory.

[0010] For example, the system 100 is a multi-function peripheral (MFP) having a copy function, a printer function, a scanner function, and a fax function, and the option board 300 is used for image processing. Alternatively, the system 100 may be an image processing device that performs image processing, or a server that performs deep learning.

[0011] The FPGA 400 has a memory controller 500 and a reconfiguration control unit 600. The memory controller 500 has a memory interface (I / F) unit 50, a write control unit 52, a read control unit 54, and a connection interface (I / F) unit 56. The reconfiguration control unit 600 has a parameter register 60, a determination unit 62, and a reconfiguration unit 64. The write control unit 52 and the read control unit 54 are an example of an access control unit that controls access to the multiple SRAMs 30.

[0012] The memory controller 500 can reconfigure the circuitry by the reconfiguration unit 64. The memory interface unit 50 accepts an access request to the SRAM 30 from the CPU 20. The access request is either a write access request including write data or a read access request. The write access request and the read access request include an address to be accessed and an access type (write or read). The access request may be supplied from the CPU 20 to the memory interface unit 50 as a packet including multiple addresses.

[0013] When the memory interface unit 50 receives a write access request, it outputs the write access request including a write address and write data to the write control unit 52. Based on the write access request, the write control unit 52 generates a write command for causing the SRAM 30 to execute a write operation, and outputs the generated write command to the connection interface unit 56. For example, the write command includes a write enable signal at an active level, a write address, and write data.

[0014] The connection interface unit 56 is programmed (reconfigured) in advance so that the CPU 20 reads data in the minimum number of cycles according to the stride indicating the degree of thinning of the read data and the parallelism of the read data. The stride and parallelism of the read data will be described in FIG. 2 and subsequent figures.

[0015] The connection interface unit 56 generates a chip select signal that selects the SRAM 30 to be accessed in response to the write address. The connection interface unit 56 outputs an active-level write enable signal, a write address, and write data to the SRAM 30 at a predetermined timing together with the generated chip select signal. The write data is then written to a predetermined address in the SRAM 30 selected by the chip select signal.

[0016] On the other hand, when the memory interface unit 50 receives a read access request, it outputs the read access request including a read address to the read control unit 54. Based on the read access request, the read control unit 54 generates a read command for causing the SRAM 30 to execute a read operation, and outputs the generated read command to the connection interface unit 56. For example, the read command includes a write enable signal at an inactive level and a read address.

[0017] The connection interface unit 56 generates a chip select signal for selecting the SRAM 30 to be accessed in response to the read address. The connection interface unit 56 outputs a write enable signal of an inactive level and a read address to the SRAM 30 at a predetermined timing together with the generated chip select signal. Then, data held at a predetermined address of the SRAM 30 selected by the chip select signal is output from the SRAM 30 as read data.

[0018] The connection interface unit 56 outputs the read data output from the SRAM 30 to the read control unit 54. The read control unit 54 outputs the read data received from the read control unit 54 to the memory interface unit 50. Then, the memory interface unit 50 outputs the read data to the CPU 20 as a response to the read access request.

[0019] In the reconfiguration control unit 600, the parameter register 60 holds parameters related to access to the SRAM 30 received from the CPU 20. For example, the parameters related to access to the SRAM 30 are the number of SRAMs 30 used for access, the stride, and the degree of parallelism. Alternatively, the parameters related to access to the SRAM 30 may be operation mode information indicating the number of SRAMs 30 used for access, the stride, and the degree of parallelism. Note that the parameters stored in the parameter register 60 may not include the number of SRAMs 30 used. Hereinafter, the number of SRAMs 30 used or the number of SRAMs 30 accessed in parallel (simultaneously) is also referred to as the number of SRAMs.

[0020] The determination unit 62 determines the circuit configuration of the connection interface unit 56 that can read data from the SRAM 30 in one cycle based on the parameters held in the parameter register 60. Note that the determination unit 62 may determine the circuit configurations of the write control unit 52 and the read control unit 54 in addition to the circuit configuration of the connection interface unit 56.

[0021] The reconfiguration unit 64 reconfigures the circuit of the connection interface unit 56, or reconfigures the circuits of the connection interface unit 56, the write control unit 52, and the read control unit 54, based on the circuit configuration determined by the determination unit 62. For example, the reconfiguration unit 64 writes circuit information into a lookup table arranged in an area that constitutes the connection interface unit 56 in the FPGA 400.

[0022] When the CPU 20 changes the combination of the parallelism and the stride, the CPU 20 may rewrite the parameter register 60 according to the changed combination. In this case, the determination unit 62A determines the circuit configuration of the connection interface unit 56 and the like based on the newly set parameters.

[0023] Furthermore, when option board 300 is equipped with a non-volatile storage unit that holds circuit information, reconfiguration unit 64 may store in the non-volatile storage unit circuit information that realizes the circuit configuration determined by determination unit 62. Then, for example, when option board 300 is powered on again, the circuit information stored in the storage unit may be transferred to FPGA 400, thereby reconfiguring connection interface unit 56 and the like.

[0024] FIG. 2 is an explanatory diagram showing an example of pixel data readout by changing the stride. For ease of understanding, FIG. 2 shows an example of 64 pixel data items, 8 pixels vertically and 8 pixels horizontally. Assume that the pixel data is accessed in parallel in units of 3 pixels (degree of parallelism=3). The numbers shown in the pixel matrix indicate the pixel number and the memory address of the SRAM 30 where the pixel data is stored. Assume that the number of SRAMs used for one read access is equal to or greater than the degree of parallelism. For example, the method of reading pixel data shown in FIG. 2 is used when performing a convolution operation on pixel data in image processing.

[0025] The stride indicates the interval at which pixel data is read out, and indicates the number of pixel data skipped. When the stride is 0, no pixel data is skipped. Therefore, pixel data 1, 2, 3, pixel data 9, 10, 11, and pixel data 17, 18, 19 are read out in parallel from the three SRAMs 30 in order by three access cycles.

[0026] When the stride is 1, every other pixel data is read out. Therefore, three access cycles are used to read pixel data 1, 3, 5, pixel data 17, 19, 21, and pixel data 33, 35, 37 in parallel from the three SRAMs 30 in sequence. When the stride is 2, every third pixel data is read out. Therefore, three access cycles are used to read pixel data 1, 4, 7, pixel data 25, 28, 31, and pixel data 49, 52, 55 in parallel from the three SRAMs 30 in sequence.

[0027] Fig. 3 is an explanatory diagram showing an example of the difference in read data depending on the combination of data parallelism and stride. Fig. 3 shows the cases of 2-parallel and 3-parallel with strides of 1 to 3. Also, Fig. 3 shows an example in which the address is regularly increased according to the stride, unlike Fig. 2.

[0028] In order to read out a plurality of data corresponding to the degree of parallelism in one cycle of the clock CLK, the data to be read out in parallel must be stored in different SRAMs 30. For example, in the case of 2-parallel and stride 1, data 1 and 3 must be stored in different SRAMs 30. If data 1 and 3 are stored in the same SRAM 30, two cycles are required to read data 1 and 3. In the case of 3-parallel and stride 2, data 1, 4 and 7 must be stored in different SRAMs 30. If at least two of data 1, 4 and 7 are stored in the same SRAM 30, two or more cycles are required to read data 1, 4 and 7.

[0029] Fig. 4 is an explanatory diagram showing the relationship between the number of SRAMs, the stride, and the number of cycles required for access when the parallelism level is 2. In Fig. 4, symbols (circle, triangle, square, diamond, and pentagon) attached to data numbers (i.e., access addresses) indicate data that is read in parallel (simultaneously). For example, addresses are assigned in sequence to the multiple SRAMs 30 used for access so that data is stored in sequence.

[0030] Each row (horizontal square) shown in the access pattern for each stride and number of SRAMs corresponds to one SRAM 30. In each SRAM 30, if there is only one identical symbol, it indicates that the parallel data can be read in one cycle. In each SRAM 30, if the same symbol appears in multiple squares, it indicates that the parallel data cannot be read in one cycle.

[0031] When the number of SRAMs is 2, reading can be done in one cycle with stride 2, but two cycles are required with strides 1 and 3. When the number of SRAMs is 3, reading can be done in one cycle with strides 1 and 3, but two cycles are required with stride 2.

[0032] When the number of SRAMs is 4, readout can be performed in one cycle with strides 1 and 2, but two cycles are required with stride 3. When the number of SRAMs is 5, readout can be performed in one cycle with strides 1, 2, and 3.

[0033] Fig. 5 is an explanatory diagram showing the relationship between the number of SRAMs and stride and the number of cycles required for access when the parallelism level is 3. Detailed explanations of the same elements as in Fig. 4 will be omitted. When the number of SRAMs is 2, 2 cycles are required for stride 2, and 3 cycles are required for strides 1 and 3. When the number of SRAMs is 3, reading can be done in 1 cycle for strides 1 and 3, but 3 cycles are required for stride 2.

[0034] When the number of SRAMs is 4, a read can be performed in one cycle with a stride of 2, but two cycles are required with a stride of 1, and three cycles are required with a stride of 3. When the number of SRAMs is 5, a read can be performed in one cycle with strides of 1, 2, and 3. As shown in Figures 4 and 5, there are various combinations of the number of SRAMs, parallelism, and stride that can read parallel data in one cycle.

[0035] Fig. 6 is an explanatory diagram showing the relationship between the degree of parallelism of data, the number of SRAMs, and the stride and the number of access cycles. In Fig. 6, combinations that allow multiple data to be read in parallel in one cycle are marked with a circle, and combinations that do not allow multiple data to be read in parallel in one cycle are marked with an X. Fig. 6 includes the information shown in Fig. 4 and Fig. 5. Note that Fig. 6 omits the display of parameter combinations with a degree of parallelism of 6 or more, a number of SRAMs of 8 or more, and a stride of 5 or more.

[0036] 6, the determination unit 62 shown in Fig. 1 determines the number of SRAMs capable of reading data in parallel in one cycle based on the parallelism and stride set in the parameter register 60. Note that the parameter register 60 may be set with operation mode information (such as a first operation mode or a second operation mode) indicating the parallelism and stride.

[0037] For example, the determination unit 62 can determine the number of SRAMs using the following criteria A, B-1, B-2, and B-3 as a condition for satisfying the relationship shown in Fig. 6. When the number of SRAMs satisfies the criteria A, or when the number of SRAMs satisfies all of the criteria B-1, B-2, and B-3, data can be read in parallel from the SRAMs 30 in one cycle ("A" or ("B-1" and "B-2" and "B-3")).

[0038] Judgment formula A: (Parallelism × (Stride + 1)) ≦ Number of SRAMs Judgment formula B-1: (Stride + 1) ≠ Multiple of number of SRAMs Judgment formula B-2: Number of SRAMs ≠ Multiple of (Stride + 1) Judgment formula B-3: Degree of parallelism ≦ Number of SRAMs

[0039] Then, the determination unit 62 determines the number of SRAMs that satisfy the judgment formula A or the number of SRAMs that satisfy all of the judgment formulas B-1, B-2, and B-3 as the number of SRAMs 30 to be used for access. The determination unit 62 also determines the circuit specifications (connection path and read path) of the connection interface unit 56 for making the number of SRAMs 30 determined to be used accessible by the write control unit 52 and the read control unit 54. As a result, the determination unit 62 can determine one of the SRAMs 30 corresponding to the circled areas as the SRAM 30 to be used for access, according to the parallelism and stride specified by the CPU 20.

[0040] Note that, due to the degree of parallelism (data bus width), there are cases where a memory controller cannot be constructed by reconfiguring the circuit of only the connection interface unit 56. In this case, the determination unit 62 determines the circuit specifications (connection path and read path) of the connection interface unit 56, the write control unit 52, and the read control unit 54. The reconfiguration unit 64 reconfigures the connection path and read path of the connection interface unit 56 based on the circuit configuration determined by the determination unit 62. Alternatively, the reconfiguration unit 64 reconfigures the connection path and read path of the connection interface unit 56, the write control unit 52, and the read control unit 54.

[0041] The CPU 20 may preliminarily determine the degree of parallelism, stride, and number of SRAMs that allow data to be read in one cycle based on the judgment formula A, and the judgment formulas B-1, B-2, and B-3. In this case, the CPU 20 stores information indicating the determined degree of parallelism, stride, and number of SRAMs in the parameter register 60. The determination unit 62 determines the circuit specifications of the connection interface unit 56, or the circuit specifications of the connection interface unit 56, the write control unit 52, and the read control unit 54 based on the information stored in the parameter register 60.

[0042] As described above, in the first embodiment, the reconfiguration control unit 600 can determine the number of SRAMs capable of reading parallel data in one cycle according to a combination of the parallelism and stride instructed by the CPU 20. Then, the reconfiguration control unit 600 can construct, on the FPGA 400, a memory controller 500 capable of reading parallel data in one cycle.

[0043] Alternatively, the reconfiguration control unit 600 can construct, on the FPGA 400, a memory controller 500 capable of reading parallel data in one cycle according to a combination of the number of SRAMs, the parallelism, and the stride instructed by the CPU 20. This allows the CPU 20 to read data from the SRAM 30 in one cycle, regardless of the parallelism and stride of the data.

[0044] As a result, for example, the CPU 20 can improve the efficiency of data processing or image processing compared to when parallel data is read in multiple cycles. Furthermore, since the number of cycles required for reading does not change depending on the parallelism or stride, the CPU 20 can always execute the read process of the SRAM 30 in one cycle without considering the parallelism or stride. Second Embodiment Fig. 7 is a block diagram showing an example of a system including a memory access control device according to a second embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The system 100A shown in Fig. 7 has a control board 200 and an option board 300. The option board 300 has an FPGA 400 and a plurality of SRAMs 30. The FPGA 400 shown in Fig. 7 is similar to the FPGA 400 in Fig. 1, except that the circuit reconfigured in the FPGA 400 is different from that in Fig. 1.

[0045] The FPGA 400 has multiple types of memory controllers 500 (501, 502, 503) that are selectively used, path switching units 40 and 42, and a reconfiguration control unit 600A. Note that the number of types of memory controllers 501, 502, and 503 is not limited to three. The reconfiguration control unit 600A is similar to the reconfiguration control unit 600 in FIG. 1, except that it has a determination unit 62A and a reconfiguration unit 64A instead of the determination unit 62 and the reconfiguration unit 64 in FIG. 1.

[0046] In this embodiment, one of the memory controllers 500 (501, 502, or 503) capable of reading parallel data in one cycle is selected according to a combination of the number of SRAMs, the parallelism, and the stride. The selected memory controller 500 is then connected to the CPU 20 and the SRAM 30 corresponding to the number of SRAMs via the path switching units 40 and 42. The selected memory controller 500 and the path switching units 40 and 42 are an example of a memory access control device.

[0047] The determination unit 62A determines a memory controller 500 capable of reading data in parallel from the SRAM 30 in one cycle based on the parameters held in the parameter register 60. The determination unit 62A also determines the circuit configurations of the path switching units 40 and 42 for connecting the determined memory controller 500 to the CPU and the SRAM 30, respectively.

[0048] The reconfiguration unit 64A reconfigures the circuits of the path switching units 40 and 42 based on the circuit configuration determined by the determination unit 62, and connects the path switching units 40 and 42 to the determined memory controller 500. As a result, similar to the above-described embodiment, it is possible to construct on the FPGA 400 a memory controller 500 capable of reading parallel data in one cycle according to a combination of the number of SRAMs, the parallelism, and the stride.

[0049] As a result, similarly to the above-described embodiment, for example, the CPU 20 can improve the efficiency of data processing or image processing. Furthermore, the CPU 20 can always execute the read process of the SRAM 30 in one cycle without considering the degree of parallelism or stride.

[0050] As in the above embodiment, when the CPU 20 changes the combination of the parallelism and the stride, the CPU 20 may rewrite the parameter register 60 according to the changed combination. In this case, the determination unit 62A determines the circuit configuration of the memory controller 500 and the path switching units 40 and 42 to be used based on the newly set parameters.

[0051] As described above, the second embodiment can achieve the same effects as the first embodiment. Furthermore, in this embodiment, the determination unit 62A determines, from among a plurality of memory controllers 500 (501, 502, 503), a memory controller capable of reading data in parallel from the SRAM 30 in one cycle. Then, the reconfiguration unit 64A reconfigures the circuit configurations of the path switching units 40 and 42 in accordance with the memory controller 500 determined by the determination unit 62A. This makes it possible to construct a memory controller 500 capable of reading data in parallel from the SRAM 30 in one cycle.

[0052] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0053] 20 CPU 40, 42 Path switching section 50 Memory interface section 52 Write control section 54 Readout control section 56 Connection interface section 60 Parameter Register 62, 62A Decision Section 64, 64A reconstruction part 100, 100A Systems 200 Control Board 300 Option Board 500, 501, 502, 503 Memory Controllers 600, 600A Reconfiguration control section [Prior art documents] [Patent documents]

[0054] [Patent Document 1] JP 2008-52522 A [Patent Document 2] JP 2009-123306 A

Claims

1. an access control unit that controls access to a plurality of memories to which addresses are assigned in sequence and to which data is read and written; a determination unit that determines a read path between the access control unit and the memory, which is capable of reading data in one cycle from the number of the memories that satisfies the judgment formula A or the number of the memories that satisfies all of the judgment formulas B-1, B-2, and B-3, according to parameters including the number of the memories used for access, a data parallelism indicating the number of the memories corresponding to the number of data to be read in one access, and a stride indicating an interval between read addresses corresponding to the data read interval; Judgment formula A: (parallelism degree × (stride + 1))≦number of memories Decision formula B-1: (stride + 1) ≠ multiple of number of memories Judgment formula B-2: Number of memories ≠ multiple of (stride + 1) Judgment formula B-3: Parallelism≦Number of memories a reconfiguration unit that reconfigures a connection path between the access control unit and the memory according to the read path determined by the determination unit; A memory access control device comprising:

2. a plurality of access control units capable of controlling access to the memories in response to parameters including a number of memories to which addresses are sequentially assigned and data is read and written, a data parallelism indicating the number of the memories corresponding to the number of data to be read in one access, and a stride indicating an interval between read addresses corresponding to an interval at which data is read; a determination unit that determines, according to the parameters, one of the access control units that satisfies a judgment formula A or one of the access control units that satisfies all of the judgment formulas B-1, B-2, and B-3 as the access control unit capable of reading data from the memory to be used for access in one cycle; Judgment formula A: (parallelism degree × (stride + 1))≦number of memories Decision formula B-1: (stride + 1) ≠ multiple of number of memories Judgment formula B-2: Number of memories ≠ multiple of (stride + 1) Judgment formula B-3: Parallelism≦Number of memories a reconfiguration unit that reconfigures a connection path that connects the access control unit determined by the determination unit and the memory used for access; A memory access control device comprising:

3. an access control unit that controls access to a plurality of memories to which addresses are assigned in sequence and to which data is read and written; a determination unit that determines the number of the memories to be used for access, the access control unit capable of reading data from the memory to be used for access in one cycle, and a read path between the access control unit and the memory to be used for access, which satisfy a judgment formula A, according to parameters including a degree of data parallelism indicating the number of the memories corresponding to the number of data to be read in one access, and a stride indicating an interval between read addresses corresponding to the data read interval; or the number of the memories to be used for access, the access control unit capable of reading data from the memory to be used for access in one cycle, and a read path between the access control unit and the memory to be used for access, which satisfy all of judgment formulas B-1, B-2, and B-3; Judgment formula A: (parallelism degree × (stride + 1))≦number of memories Decision formula B-1: (stride + 1) ≠ multiple of number of memories Judgment formula B-2: Number of memories ≠ multiple of (stride + 1) Judgment formula B-3: Parallelism≦Number of memories a reconfiguration unit that reconfigures a connection path between the access control unit and the memory according to the access control unit and the read path determined by the determination unit; A memory access control device comprising:

4. a plurality of access control units capable of controlling access to a plurality of memories to which addresses are sequentially assigned and from which data is read and written, in response to parameters including a degree of parallelism of data indicating the number of memories corresponding to the number of data to be read in one access and a stride indicating an interval between read addresses corresponding to an interval between data reads; a determination unit that determines, according to the parameters, the number of memories to be used for access and one of the access control units capable of reading data from the memory to be used for access in one cycle, which satisfy a judgment formula A, or determines the number of memories to be used for access and one of the access control units capable of reading data from the memory to be used for access in one cycle, which satisfy all of the judgment formulas B-1, B-2, and B-3; Judgment formula A: (parallelism degree × (stride + 1))≦number of memories Decision formula B-1: (stride + 1) ≠ multiple of number of memories Judgment formula B-2: Number of memories ≠ multiple of (stride + 1) Judgment formula B-3: Parallelism≦Number of memories a reconfiguration unit that reconfigures a connection path that connects the access control unit determined by the determination unit and the memory used for access; A memory access control device comprising:

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