Machine learning control of object handover

Abstract

To provide reliable handover techniques that allow robots to receive objects from human operators.SOLUTION: A robotic control system directs a robot to take an object 102 from human grasp by obtaining an image of a human hand 104 holding an object 102, estimating poses of the human hand 104 and the object 102, and determining a grasp pose for the robot that will not interfere with the human hand 104. In at least one example, a depth camera is used to obtain a point cloud of the human hand 104 holding the object 102. The point cloud is provided to a deep network that is trained to generate grasp pose for a robotic gripper 106 that can take the object 102 from the human hand 104 without pinching or touching the human's fingers.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Robotic automation of tasks is an important area of ​​development. However, some tasks require collaboration with a human operator. Tasks such as personal care tasks, object handover, or interfacing between robotic and manual tasks often require interaction between a robot and a human. One problem in the collaborative task space is exchanging objects between a human operator and a robot. As part of task execution, the exchange may occur from the robot to the human and / or from the human to the robot. When taking an object from a human's hand, the exchange can be difficult if the robot selects a grasp that can securely grasp the object but interferes with the human's hand. Failure can result in the object being dropped, potentially injuring the human operator. Therefore, developing reliable handover techniques that allow a robot to receive an object from a human operator is a key problem in the collaborative task space. Summary of the Invention [Means for solving the problem]

[0002] Various techniques will be described with reference to the drawings. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 illustrates an example of a human-robot interaction pose in which the human performs a palm-down pinching grasp on an object, according to one embodiment. [Figure 2] 1A-1C illustrate examples of human-robot interaction poses in which the human performs a grasp to lower an object, according to one embodiment. [Figure 3] FIG. 1 illustrates an example of a human-robot interaction pose in which the human performs a palm-up pinch grasp on an object, according to one embodiment. [Figure 4]1A-1C illustrate examples of human-robot interaction poses in which the human performs a horizontal pinch grasp on an object, according to one embodiment. [Figure 5] FIG. 1 illustrates an example framework for performing handover between a robot and a human hand, according to one embodiment. [Figure 6] 1A-1C illustrate examples of human hand poses that can be used to prompt object movement from a robot, according to one embodiment. [Figure 7] FIG. 1 illustrates example hand postures that may be used to grasp an object, according to one embodiment. [Figure 8A] FIG. 1 illustrates an example of a robot gripper, according to one embodiment. [Figure 8B] FIG. 1 illustrates an example of a robotic gripper with four fingers, according to one embodiment. [Figure 9] FIG. 1 illustrates an example of robot-human interaction, according to one embodiment. [Figure 10] FIG. 1 illustrates data representing the performance of a human-robot interaction system, according to one embodiment. [Figure 11] FIG. 10 illustrates example hand postures that may be used to present an object to a robot, according to one embodiment. [Figure 12] FIG. 1 illustrates an example process performed by a computer system to perform object transfer between a robot and a human hand, according to one embodiment. [Figure 13A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 13B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 14] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 15] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 16A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 16B] 16B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 16A, according to at least one embodiment. [Figure 16C] FIG. 16B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 16A, according to at least one embodiment. [Figure 16D] FIG. 16B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 16A, according to at least one embodiment. [Figure 17] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 18] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 19] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 20] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 21F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 22] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 23A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 23B]FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 24A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 24B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 25] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 26A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 26B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 26C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 26D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 27] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 28] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 29] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 30] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 31] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 32] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 33] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 34]FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 35] FIG. 35 is a block diagram of a graphics processing engine 3510 of a graphics processor, according to at least one embodiment. [Figure 36] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 37A] FIG. 37 illustrates thread execution logic 3700 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 37B] FIG. 37 illustrates thread execution logic 3700 including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 38] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 39] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 40] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 41] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0004] This specification describes a vision-based system that enables a robot to receive an object presented to a human hand. In one example, a human grasps an object and presents it within a visual field monitored by a depth camera. The depth camera captures a 3D image of the hand grasping the object and provides it to the system. The system generates a point cloud from the image and separates the portion of the point cloud associated with the human hand from the portion of the point cloud associated with the object. Using this information, the system can determine the pose of the human hand and the pose of the object. The system generates a set of grasps that can be performed by the robot to grasp the object and then selects a grasp from the set of grasps that does not interfere with the human hand. In one implementation, the human grasps are classified into different types of hand poses to assist the system in selecting an appropriate grasp for the robot to acquire the object. In another implementation, given a dataset of human object handovers annotated with ground truth hand and object poses, a deep network is trained that takes as input the colored point cloud observed by a depth camera to segment the human hand from the object and propose appropriate grasping and control for the robot so that it can receive the object from the human hand without pinching the human's fingers. The techniques described herein may, in various examples, be applied to systems where an object is passed from one robot to another, or from an animal to a robot, or in some instances when an object is taken from an appendage other than a human hand (e.g., when taking a hat).

[0005] Transferring objects between humans and robots is an important function for robots collaborating with humans. Both robot-to-human and human-to-robot handovers can be challenging. Some techniques described herein describe a human-to-robot handover approach in which the robot responds to the human midway by classifying the human's grasp of an object and rapidly planning a trajectory accordingly to remove the object from the human's hand according to the human's intent. At least one embodiment collects a dataset of human grasps covering typical ways of holding objects with various hand shapes and postures, and trains a deep model on this dataset to classify hand grasps into one of these categories. At least one embodiment provides a planning and execution approach to remove an object from the human's hand according to the detected grasp and hand position, and replans as necessary when the handover is interrupted. Through systematic evaluation, the present specification demonstrates that various embodiments achieve improved handovers over two baselines.

[0006] Giving objects to and taking objects from humans is a fundamental function for collaborative robots across applications ranging from manufacturing to physical assistance in the home. Some techniques focus on transferring objects from the robot to the human and assume that the reverse transfer requires the human to simply place the object in the robot's gripper. This approach is sometimes impractical in situations where the human needs to pay attention to the task at hand, such as during surgery, or where an impairment limits the human's mobility or arm movement. Therefore, at least one embodiment provides a more reactive handover that can accommodate a human presenting an object to the robot and interacting with the robot along the way to retrieve the object.

[0007] In at least one embodiment, one challenge in making a human-to-robot handover reactive is reliably and continuously perceiving the object and the human. At least one embodiment utilizes computer vision methods to estimate the pose of the human hand as well as the 6D object pose. Various techniques may be used, including techniques that estimate the hand pose and the object pose separately. At least some embodiments estimate the pose of the hand and the object while the hand is interacting with the object.

[0008] In at least one embodiment, the technique described herein addresses the problem of human-to-robot handover perception by formulating it as a hand grasp classification problem. In one example, the technique discretizes the ways in which humans can hold small objects into several categories, and a dataset is collected to train a deep model that classifies a given human hand holding an object into one of these grasp categories. The handover task is modeled as a robust logical-dynamical system, which, given the human grasp classification, generates a motion plan that avoids contact between the gripper and the human hand. At least one embodiment is compared with two baseline methods: one that does not infer human hand pose, and the other that relies on independent hand and object pose estimation. At least one embodiment demonstrates that our approach is more successful and time-efficient than the two baselines. A user study (N=9) is presented, demonstrating its effectiveness with unbiased users, both when they are paying attention to the robot and when they are focused on a secondary task.

[0009] At least one embodiment provides a reliable vision-based algorithm that can generate a collision-avoiding grasp for a human-to-robot or robot-to-robot handoff task, e.g., how a robot can pick up an object from a human or another robot. At least one embodiment adjusts how the robot grasps an object based on how the object is being held by a human hand. As a result, at least one embodiment is more reliable in avoiding contact with the human hand.

[0010] Human-robot handovers are an important topic in human-robot collaboration across numerous application domains, from collaborative manufacturing to household assistance. At least one embodiment focuses on robot-to-human handovers, in which a robot starts with an object in its hand and hands it to a human. One challenge is selecting parameters of the robot's behavior to optimize to achieve a smooth handover. This includes selecting an object pose and the robot's grasp of the object, taking into account user comfort, preferences based on subjective feedback, the object's affordances and intended use after the handover, human motion constraints, the human's social role, and the object's configuration as grasped before the handover. At least one embodiment focuses on parameters of the trajectory to reach the handover pose, exploring the approach angle, the starting pose of the trajectory as opposed to the handover pose, smoothness of the movement, object release time, estimated human wrist pose, relative timing of the handover phase, and human ergonomic preferences. While some embodiments focus on offline calculation of handover parameters, at least one embodiment requires human perception to enable a reactive handover.

[0011] The techniques described herein focus on human perception to enable responsive handover and utilize human hand pose estimation techniques. Human hand pose estimation can be achieved using both 2D RGB monocular images or 3D depth camera information. In general, 3D depth cameras provide additional information that allows for more accurate hand pose estimation than techniques that rely solely on 2D RGB images.

[0012] The techniques described herein implement a system for executing tasks based on Robust Logical Dynamical Systems, a method for automatically generating reactive task plans for robots. In at least one embodiment, this concept continuously identifies the current logical state and reactively re-plans to address uncertainty and changes in the logical state, a method useful for dealing with partially observable environments. In some instances, task models can be thought of in a manner similar to Behavior Trees, a method for representing complex tasks useful for human-robot collaboration.

[0013] At least one embodiment partially solves this problem by classifying human grasp poses, which in at least one embodiment are discretized into seven categories, and these categories may not cover all the ways a human hand can grasp an object.

[0014] In at least one embodiment, a dataset of human object handovers annotated with ground truth hand and object poses is generated, and a deep network is trained using this dataset, which takes as input a colored point cloud acquired by an RGB depth camera, segments the human hand from the object, and proposes a robotic grasp and control such that the robot can accept the object from the human hand without pinching or touching the human fingers.

[0015] One advantage of the techniques described herein is that by learning from hand and object manipulation datasets, models may be generated for robotic graspers that can receive objects from a human hand (or another robot's gripper) without pinching the human hand (or another robot's gripper). Some examples provide low-cost solutions based on RGB-D cameras, which are cheaper and lighter than many wearable sensors. Various embodiments enable reliable handovers, which are important when building more complex robotic systems. For example, the techniques described herein may be applicable to elderly care robots or cooking robots that can work closely with humans.

[0016] The techniques described herein provide, in various embodiments, (1) inference of hand-object interactions with a dataset covering a wide variety of hand shapes and poses for handover posed as a classification problem; (2) a system that adaptively plans a robot's grasp to take an object from a human, allowing the robot to respond smoothly and naturally to the human; and (3) experimental results demonstrating improvements over baseline methods and a user study validating our approach with unbiased users.

[0017] Human hands handle objects differently. They can present objects in their palms, or they can use a pinch grasp and present the object in different orientations. The techniques described herein can determine which grasp the human is using and adapt accordingly, enabling reactive handoffs between humans and robots.

[0018] 1 illustrates an example human-robot interaction pose in which a human performs a palm-down pinch grasp on an object, according to one embodiment. The robot 100 is positioned to pick up the object 102 from the human's hand 104. In at least one embodiment, a depth camera captures images of the human's hand 104 grasping the object 102, generates a point cloud from the images, and provides the point cloud to a trained neural network. The neural network generates an appropriate grasp for a robotic gripper 106 coupled to the robot 100, enabling the robotic gripper 106 to grasp the object 102 without interfering with the human's hand 104.

[0019] 2 illustrates an example human-robot interaction pose in which a human performs a grasp to set down an object, according to one embodiment. The robot 200 is positioned to take the object 202 from the human's hand 204. In at least one embodiment, a depth camera captures images of the human's hand 204 grasping the object 202, generates a point cloud from the images, and provides the point cloud to a trained neural network. The neural network generates an appropriate grasp for a robot gripper 206 coupled to the robot 200, enabling the robot gripper 206 to grasp the object 202 without interfering with the human's hand 204.

[0020] 3 illustrates an example human-robot interaction pose in which a human performs a palm-up pinch grasp on an object, according to one embodiment. The robot 300 is positioned to pick up the object 302 from the human's hand 304. In at least one embodiment, a depth camera captures images of the human's hand 304 grasping the object 302, generates a point cloud from the images, and provides the point cloud to a trained neural network. The neural network generates an appropriate grasp for a robotic gripper 306 coupled to the robot 300, enabling the robotic gripper 306 to grasp the object 302 without interfering with the human's hand 304.

[0021] 4 illustrates an example human-robot interaction pose in which a human performs a horizontal pinch grasp on an object, according to one embodiment. The robot 400 is positioned to take the object 402 from the human's hand 404. In at least one embodiment, a depth camera captures images of the human's hand 404 grasping the object 402, generates a point cloud from the images, and provides the point cloud to a trained neural network. The neural network generates an appropriate grasp for a robotic gripper 406 coupled to the robot 400, enabling the robotic gripper 406 to grasp the object 402 without interfering with the human's hand 404.

[0022] In at least one embodiment, when a robot takes an object from a human hand, the robot's behavior is adjusted depending on how the object is grasped by the human hand. Generally, this prevents the robot from behaving in a non-intuitive manner or in a manner that interferes with or even makes dangerous contact with the human finger. In at least one embodiment, the handover framework addresses this issue by taking a point cloud centered on the human hand detected by the Azure Body Tracking Software Development Kit ("SDK") and then inferring a class of hand grasp based on how the object is grasped by the human hand. At least one embodiment then adaptively plans the robot's grasp.

[0023] FIG. 5 shows an example framework for performing a handoff between a robot and a human hand, according to one embodiment. In one example, the framework acquires an RGBD image 502 showing a hand holding an object. Using the RGBD image, a point cloud 504 of the hand and object is generated. In at least one embodiment, the framework takes the point cloud centered around the hand detection and then uses a model 506 to classify the point cloud as one of seven grasp types that cover the various ways in which objects tend to be grasped by human users. The task model then adaptively plans the robot's grasp 508.

[0024] 6 shows example human hand postures that can be used to prompt the transfer of an object from a robot, according to one embodiment. For example, a first hand posture 602 may be designed as a posture that signals that the human is ready to receive the object, and a second hand posture 604 may be designed as a posture that indicates that the human is not ready to receive the object from the robot.

[0025] At least one embodiment defines a discrete set of human grasps that indicate how an object is grasped by a human hand for a handover task. At least one embodiment discretizes common human grasps for handover tasks between humans and robots into seven categories, such as those shown in FIG. 7. For example, if a hand is grasping a block, the hand pose can be classified as open palm up, bottom pinch, top pinch, side pinch, or lifting. In another example, if the hand is not holding anything, the hand can either be waiting for the robot to hand over the object or doing nothing in particular (other).

[0026] FIG. 7 illustrates example hand postures that may be used to grasp an object, according to one embodiment. A first hand posture 704 illustrates an object being held in an open palm. A second hand posture 704 illustrates an object being held in a bottom-pinch position. A third hand posture 706 illustrates an object being held in a lifting position. A fourth hand posture 708 illustrates an object being held in a top-pinch position. A fifth hand posture 710 illustrates an object being held when pinched from the side. These and other hand postures may be used by a human when presenting an object to a robot. In some implementations, a classification of hand postures may be used, such as the hand posture categories illustrated in FIG. 7 . In other implementations, the hand postures may be free-form, which may include various types of hand postures not illustrated in FIG. 7 . In such an example, the system may use the hand point cloud or skeletal pose to construct a pose suitable for the robot to pick up the object from the human's hand.

[0027] 8A shows an example of a robotic gripper, according to one embodiment. In one example, the robotic gripper 802 includes a set of jaws 804 that can close and open. Some examples may include tactile sensors on the surface of the jaws 804 so that the degree of force can be captured by the system. In some examples, the gripper 802 includes a wrist joint that can articulate and position the set of jaws 804 under the control of the system.

[0028] FIG. 8B illustrates an example of a four-fingered robotic gripper 806 that can be used in one embodiment. The robotic gripper 806 includes a first finger 808, a second finger 810, a third finger 812, and an opposable finger 814 that closely mimic a human hand. The robotic gripper 806 can be used with various embodiments described and illustrated herein. For example, the robotic gripper 806 can be used to pick up an object held by a human hand in a manner that does not interfere with the human hand. Additionally, other types of robotic grippers with more or fewer fingers can also be used. In one example, the robotic gripper can have two, three, four, five, or more fingers, and each finger can have a friction surface to assist in grasping the object. In one example, the fingers of the robotic gripper can have tactile sensors that assist the system by indicating contact with the object. In one example, the gripper can include a magnetic element to assist in picking up a ferrous object from a human hand. In another example, the gripper may include a vacuum pick-up element for capturing the object.

[0029] In one example, to train a model for classifying human grasps, an embodiment uses an Azure Kinect RGBD camera to generate a dataset covering eight subjects with various hand shapes and hand postures. For example, in one implementation, exemplary images of hand grasps are shown to a subject, and similar postures performed by the subject are recorded over a period of 20 to 60 seconds. The series of images is labeled as the corresponding category of human grasp. During recording, the subject can move their body and hands into different positions to diversify the camera's viewpoint. Both left and right hands are recorded for each subject. In one example, the dataset consists of 151,551 images.

[0030] Instead of learning deep features using ConvNets on depth images, at least one embodiment employs PointNet++ on point clouds to classify human grasps. In at least one embodiment, the backbone network consists of four set abstraction layers for learning point features and a three-layer perceptron with batch normalization, ReLu, and dropout to learn global features and classify human grasps. Given a point cloud cropped around the hand, the network classifies it into one of the defined grasp categories, which may be used for further planning of the robotic grasp.

[0031] At least one embodiment associates each human grasp type with a canonical robot grasp orientation to minimize human effort during human-to-robot handover. As shown in Figure 3, the coordinates indicate the canonical robot grasp frame within the camera frame. The motivation is to keep the robot's motion and trajectory as natural and smooth as possible while reducing the chance of the robot grabbing the human's hand.

[0032] At least one embodiment of the task model is based on Robust Logical Dynamical Systems, which represents a task as a list of operators o that have specific properties and are executed reactively. Each operator is a tuple o={L P ,LR ,L E ,π}, where L P is the set of logical preconditions for entering o, and L R is the set of execution conditions that must apply while the execution of o is in progress, and L E is the set of logical effects that will be true. Operators are also associated with policies π, which are the set of logical effects L E In at least one embodiment, the policies and predicates are learned from data, while in other embodiments, they are manually specified. Given a plan, at least one embodiment selects the operator with the highest priority whose preconditions are met, checking the conditions at 10hz to allow for rapid response to changes.

[0033] Figure 9 shows an example of robot-human interaction according to one embodiment. Figure 9 provides an overview of the various steps of the final task planning. In at least one embodiment, the system must adapt to various possible grasps, reactively selecting the correct way to approach and take an object from a human user. In one example, the system stays in a "home" position and waits until it has a stable estimate of how the human wants to present the block.

[0034] In various embodiments, the handover from human to robot is accomplished in four stages: the robot waits for the human to present the object in an appropriate pose 902, then creates a plan to position the robot gripper to grasp the object 904, grasps the object 906, and then in some instances drops the object 908.

[0035] In addition to using reactive local planning, some implementations plan based on multiple feasible grasps and make intelligent decisions to find a grasp that is natural for a human user. The following table shows an example of task planning, ordered by priority: The following table lists the operators and corresponding prerequisites L for task execution. P, as well as reactive execution. Operators are listed in order of precedence, and if all preconditions are true, the techniques described herein execute the associated operator regardless of what operator was previously executed. [Table 1]

[0036] Waiting for a human. At least one embodiment computes several predicates that determine how the robot should interact with the hand: stable, hand_over_table, and hand_has_obj, and too_close_to_hand. The predicate hand_over_table corresponds to whether or not these observations are within a particular volume on the table shown above, and stable() is true if the hand is not moving and has been observed for at least five timestamps (0.5 seconds). This is at least in part due to speed: stable()=||x t-1 -x t ||2<λ where position x and time t for a threshold λ. If these conditions are not true, the robot waits at its home position.

[0037] Avoid humans. In at least one embodiment, if too_close_to_hand() is true for any hand and the robot is not in the approach region corresponding to a particular grasp, the robot will attempt to avoid the hand and return to the home position. At least one embodiment defines too_close_to_hand() to be true if the Euclidean distance between the end effector and the hand is less than 20 cm.

[0038] Find a feasible goal. To ensure the robot's movement is safe, rather than a purely reactive policy, the techniques described here plan a global trajectory to execute. In the cases of stable(), hand_over_table(), and hand_has_obj(), the robot attempts to remove the object from the hand using the canonical grasping pose described above.

[0039] In at least one embodiment, to find a valid trajectory ξ, the robot first finds a valid grasp pose, whereby the system populates has_goal and is_goal_valid. If either of these is false, the system searches for a valid goal pose.

[0040] In at least one embodiment, a planner generates a list of candidate goal poses and associated standoff positions. In one example, there are 10 choices for rotation around the y-axis, θ_y∈{-π / 4,-π / 8,0,π / 8,π / 4}, and around the z-axis, θ_z∈{0,π}, in FIG. 3. In at least one embodiment, to be considered a feasible goal option, both the grasp position and the standoff position must be collision-free and have a valid IK solution. In various examples, an additional constraint is added that the robot must never occlude its view of an object when determining whether a state is valid.

[0041] Find a plan. In at least one embodiment, if the planner has a list of goal options, it then sorts the goal options according to their distance from the current joint configuration and attempts to find a motion plan to the standoff position using RRT-Connect

[58] . If the system can find both a grasp pose and a motion plan, the robot executes a sub-policy to follow this motion plan.

[0042] However, the human may move the hand or change the way the object is held in the hand. A goal is considered valid (per the predicate is_goal_valid) if it has an associated motion plan and the object has not moved within some threshold of where it was first observed. If the object moves too much, the robot stops and the task model goes back to finding a new grasp.

[0043] Grasp an object. In at least one embodiment, once motion planning is complete, the robot should be in a standoff pose and have an associated goal pose, i.e., the expected location of the object in a human hand. These two poses define an approach region, i.e., a conical volume within which the robot can move to approach the object. When the gripper closes, the predicate has_obj is set to true if the robot is in that goal pose. The grasp operator may occlude the object, so it is implemented as a simple blocking open-loop behavior.

[0044] Releases the gripper. In at least one embodiment, if has_obj is true, indicating that the robot thinks it is holding an object, this perception may be incorrect if the object has moved or the pose estimation is incorrect. In some instances, a predicate gripper_fully_closed is added to state that the gripper is fully closed. If both conditions are true, has_obj is set to false and the robot returns to a different state.

[0045] Move to the drop position and drop the object. In at least one embodiment, the drop position is a single joint space position, and the robot will find a safe, collision-free motion plan. When the robot is in the drop position, the system will instruct the robot to release the gripper and place the object on the table.

[0046] Systematic testing of an example of the entire system, including the classification and task models described above, was performed for various hand positions and grasps, as shown in Figure 7. The example uses two different Franka Panda robots mounted in different locations on the same table. A human user handed the robot four colored blocks, one at a time. During the systematic evaluation, three approaches were tested to determine which grasp posture to use to take an object from the human.

[0047] Simple baseline: Wait until you see a block in a human hand and then take the object from the hand using a fixed grasp orientation. The human hand is detected by a Microsoft Azure body tracker.

[0048] Hand Pose Estimation: A version of the state estimation based system in which the grasp direction is inferred using the human hand pose from the Azure body tracker.

[0049] Example of the proposed system: The proposed system classifies human grasps based on the depth information described above.

[0050] The variants performed the same task model described above. The order in which these three test cases were presented was randomized. The user presented the block to the robot using their right hand.

[0051] System performance was evaluated using a set of metrics calculated during testing, which were automatically calculated and logged while the user was performing the task.

[0052] Plan Success Rate: The number of times the follow_plan operator was successfully executed, putting the robot into its standoff posture and measuring both human and system certainty.

[0053] Grasp success rate: How often the robot was able to successfully take an object from a human's hand compared to the total number of grasps the robot attempted.

[0054] Behavior Execution Time: Tracks the amount of time it takes to execute a single planned trajectory, grab the block, and place it on the table. This will be higher if the robot has to take a longer path to grab the block from the human.

[0055] Total execution time: The amount of time it took to execute all planned paths, including re-planning due to human movement or changes in gripping style.

[0056] Trial duration: The time from when a human hand is first detected to when the trial is completed.

[0057] Figure 10 shows the results for various metrics during the systematic evaluation. The technique described herein consistently improves the success rate and reduces the total execution time and test duration compared to two other baseline methods, demonstrating the effectiveness and reliability of the method. The first chart 1002 shows the accuracy of human hand grasp classification. The second chart 1004 shows the object miss detection rate comparison between our hand state classification and PoseCNN. In many cases, the hand occludes the object, meaning that obtaining an accurate pose estimate is very challenging.

[0058] One exception is Action Execution Time, where the naive baseline method may be faster because it does not plan adaptively as much as the other methods and does not attempt exceptional grasps. This means that the time from successful approach to dropping the object can, on average, be significantly shorter.

[0059] Evaluation of human grasp classification: One example evaluates the hand grasp classification model on a validation set collected with subjects not seen during the training procedure. The classification accuracy is reported in the first chart 1002, which demonstrates the good generalization ability of our model for unseen subjects.

[0060] Further experiments are performed to evaluate the detection rate, i.e., whether an object is present in the hand, to provide insight into how robust the handover system is against occlusion. The detection rate (object present / not present) of our hand grasp classification model is compared to that of alternative object detection methods. The results are reported in a second chart 1004. One embodiment of the human grasp model described herein achieves a higher detection rate and is more robust than alternative methods, especially when high occlusion occurs (e.g., 87.5% vs. 6.8% for side pinch, 94.4% vs. 11.9% for lift).

[0061] A user survey was conducted to verify that the system enabled smooth human-robot collaboration. Nine users aged 20 to 36 were recruited, two of whom were female and seven were male. The average age was 30.44 ± 4.74 years. The survey consisted of three sessions.

[0062] Free-form: Users were given four blocks and instructed to stand in front of a table and hand the blocks to the robot one at a time. Users were instructed that the robot would only take the blocks if the user's hands remained still, but that they could hold the blocks in any way they wanted.

[0063] Attention condition: A set of five human grasps, shown in Figure 3, was demonstrated: top pinch, bottom pinch, side pinch, lift, and open palm. Participants were again asked to hand over the four blocks. Participants were encouraged to try the given grasps, but could use any other grasp.

[0064] Distracted condition: User performance was tested in the presence of distractions.

[0065] The results of the delivery performance based on our quantitative metrics are shown in the table below. The planning success rate indicates how often the system had to re-plan its approach, while the grasping success rate indicates how many times the system successfully picked up the object. [Table 2]

[0066] In addition to the metrics mentioned above, the following statistics were also counted during the user study: (a) the number of times the robotic grasper contacted a human finger, (b) the number of times the user changed the grasp used, and (c) the number of times the user changed their hand position. After each trial, participants were asked to describe any problems they experienced while passing the block to the robot. After all three trials had been performed, participants were asked to fill out a Likert-scale questionnaire and explain their answers.

[0067] While reactions were mixed, users mentioned some common issues when asked for feedback, although they said they worked smoothly with the robot and believed it behaved appropriately. Users also believed the robot was aware of their actions.

[0068] Quantitative metrics for the user data are shown in the table above. When users' attention was distracted, approaches and grasps were less successful, but for similar periods of time. Users counted an average of 12:88 ± 3:48 faces in the music video, with a correct count of 13. This suggests that many users felt a certain level of confidence in the delivery system and paid a sufficient amount of attention to the video.

[0069] In one embodiment, the human grasp categorization described herein covers 77% of typical user grasps. At least one embodiment can handle most first-time human grasps, which tend to have higher uncertainty and may cause the robot to back off and replan. Some of these first-time grasps are shown in Figure 11. Figure 11 shows examples of outlier grasps not present in our training dataset, as well as examples of grasp types for which our system exhibited higher uncertainty and slightly worsened handoff performance.

[0070] During the final distracted test, users had to reposition or change their grip more frequently compared to the first two trials. Some users complained of pinched fingers or witnessed the robot fail to grasp the object. One user specifically "selected and used a palm-up hand posture" to minimize the risk of failure, while another "had to look at the robot every 10 seconds or so."

[0071] The following table provides quantitative results from user research: Users were able to complete tasks quickly, even when their attention was distracted and they had to focus on a different situation. [Table 3]

[0072] In at least one example, the system will clearly show which block the robot is trying to move and how it is trying to get there.

[0073] Overall, during testing, users quickly noticed when the robot was conservatively trying to grasp the block. They also noticed slight errors in the robot's grasp and approach, but typically adjusted accordingly. After the second round of experiments, once users were shown how to hold the object, the system became more reliable and easier to work with.

[0074] This specification describes an embodiment of a system that enables handoffs between humans and robots by classifying different types of grasps. Another embodiment trains a neural network to generate grasps from a point cloud of a human hand holding an object, making the planning system more flexible and supporting a wide range of grasp types. Variations of these techniques can be applied to many other types of human-robot collaboration, such as medical surgery, manufacturing, and personal care tasks.

[0075] 12 illustrates an example process that, when executed by a computer system, performs the transfer of an object between a robot and a human hand, according to one embodiment. At least one embodiment may be implemented using a computer system, processor, GPU, or machine learning network, such as those shown in FIGS. 13-41 and described in the associated description. At least one embodiment is implemented using a processor that reads executable instructions from a computer-readable memory that stores instructions that, when executed by one or more processors of the computer system, cause the computer system to perform the operations described below.

[0076] In at least one embodiment, in block 1202, an image of a hand holding an object is acquired using a depth camera. In various instances, the depth camera can be a binocular RGB camera, a medical imaging device, such as a 3D x-ray, ultrasound, CAT scan, or magnetic resonance imaging ("MRI"). In some instances, such as those involving autonomous vehicles, the image may be an image generated by a radar imager or a laser imager ("LIDAR"). In at least one embodiment, in block 1204, the system generates a point cloud from the image. The point cloud provides a three-dimensional set of points representing the object and the hand. In one instance, the point cloud is a colored point cloud from an RGB depth camera.

[0077] In at least one example, in block 1206, the system processes the point cloud and identifies a first portion of the point cloud that represents a hand holding an object. In block 1208, the system identifies a second portion of the point cloud that represents the object. Using the appropriate portion of the point cloud, in at least one example, in block 1210, the system determines a pose of the object from the second portion of the point cloud and a pose of the hand from the first portion of the point cloud 1212. In one example, the pose of the hand includes identifying the skeletal structure of the hand, including joint and segment lengths for the fingers of the hand.

[0078] In at least one embodiment, in block 1214, the system generates a set of gripping poses for the robot gripper that will allow the gripper to grasp the object. This may be accomplished using the portions of the point cloud that represent the object and / or object poses determined in block 1210. In at least one embodiment, the object pose information includes the size, shape, and orientation of the object in space. The object orientation may include vertical and horizontal rotation and tilt. The set of gripping poses may include many poses that would interfere with a human hand but are still preferable if the hand is not present.

[0079] Thus, in block 1216, the system identifies a particular grasp from the set of grasp poses that does not interfere with the hand. Interfering with the hand means contacting the hand or pinching the hand or part of the hand with the robotic gripper. In at least one embodiment, the system selects a grasp that meets sufficient safety criteria for the object while maximizing distance from the fingers of the hand. After identifying a suitable grasp that does not interfere with the hand, in block 1218, the system instructs the robot to perform the identified grasp to take the object from the human's hand.

[0080] Logic of inference and training Figure 13A illustrates inference and / or training logic 1315 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 1315 are provided below in conjunction with Figures 13A and / or 13B.

[0081] In at least one embodiment, the inference and / or training logic 1315 may include, without limitation, code and / or data storage 1301 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 1315 may include or be coupled to code and / or data storage 1301 for storing graph code or other software for controlling the timing and / or order in which the weights and / or other parameter information are loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads the weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1301 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1301 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0082] In at least one embodiment, any portion of code and / or data storage 1301 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1301 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1301 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0083] In at least one embodiment, the inference and / or training logic 1315 may include, without limitation, code and / or data storage 1305 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiments. In at least one embodiment, the code and / or data storage 1305 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiments. In at least one embodiment, training logic 1315 may include or be coupled to code and / or data storage 1305 for storing graph code or other software for timing and / or sequencing control, and code and / or data storage 1305 may be loaded with weights and / or other parameter information to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 1305 may be included with other on-chip or off-chip data storage, including processor L1, L2, or L3 caches or system memory. In at least one embodiment, any portion of code and / or data storage 1305 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1305 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage.In at least one embodiment, the choice of whether code and / or data storage 1305 is internal or external to the processor, for example, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inferencing and / or training of the neural network, or any combination of these factors.

[0084] In at least one embodiment, code and / or data storage 1301 and code and / or data storage 1305 may be separate storage structures. In at least one embodiment, code and / or data storage 1301 and code and / or data storage 1305 may be the same storage structure. In at least one embodiment, code and / or data storage 1301 and code and / or data storage 1305 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 1301 and code and / or data storage 1305 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0085] In at least one embodiment, inference and / or training logic 1315 may include one or more arithmetic logic units (“ALUs”) 1310, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 1320, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1301 and / or code and / or data storage 1305. In at least one embodiment, the activations stored in activation storage 1320 are generated according to linear algebra and / or matrix-based calculations performed by ALU 1310 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 1305 and / or data 1301 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1305, or code and / or data storage 1301, or in separate storage, on-chip or off-chip.

[0086] In at least one embodiment, ALU 1310 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 1310 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 1310 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, data storage 1301, code and / or data storage 1305, and activation storage 1320 may be in the same processor or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1320 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0087] In at least one embodiment, active storage 1320 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, active storage 1320 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether active storage 1320 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, for example, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in neural network inference and / or training, or any combination of these factors. In at least one embodiment, the inference and / or training logic 1315 shown in Figure 13A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 1315 shown in Figure 13A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0088] FIG. 13B illustrates inference and / or training logic 1315 according to at least one various embodiment. In at least one embodiment, the inference and / or training logic 1315 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 1315 illustrated in FIG. 13B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 1315 illustrated in FIG. 13B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (“GPU”) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 1315 includes, without limitation, code and / or data storage 1301 and code and / or data storage 1305, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 13B , code and / or data storage 1301 and code and / or data storage 1305 are each associated with dedicated computational resources, such as compute hardware 1302 and compute hardware 1306, respectively. In at least one embodiment, compute hardware 1302 and compute hardware 1306 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 1301 and code and / or data storage 1305, respectively, with the results stored in activation storage 1320.

[0089] In at least one embodiment, each of code and / or data storage 1301 and 1305 and corresponding computational hardware 1302 and 1306 corresponds to a different layer of a neural network, whereby activations resulting from one "storage / computation pair 1301 / 1302" of code and / or data storage 1301 and computational hardware 1302 are provided as input to the next "storage / computation pair 1305 / 1306" of code and / or data storage 1305 and computational hardware 1306 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 1301 / 1302 and 1305 / 1306 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 1315 after or in parallel with storage / computation pairs 1301 / 1302 and 1305 / 1306.

[0090] Neural network training and deployment FIG. 14 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 91406 is trained using a training data set 1402. In at least one embodiment, the training framework 1404 is the PyTorch framework, while in other embodiments, the training framework 1404 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 1404 trains the untrained neural network 1406 and enables it to be trained using processing resources described herein to generate a trained neural network 1408. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0091] In at least one embodiment, the untrained neural network 1406 is trained using supervised learning, where the training data set 1402 includes inputs paired with desired outputs for those inputs, or the training data set 1402 includes inputs with known outputs, and the outputs of the neural network 1406 are manually scored. In at least one embodiment, the untrained neural network 1406 is trained in a supervised manner, processing inputs from the training data set 1402 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 1406. In at least one embodiment, the training framework 1404 adjusts the weights that control the untrained neural network 1406. In at least one embodiment, training framework 1404 includes tools to monitor how well untrained neural network 1406 is converging toward a model, such as trained neural network 1408, that is suitable for generating correct answers, such as results 1414, based on known input data, such as new data 1412. In at least one embodiment, training framework 1404 iteratively trains untrained neural network 1406 while adjusting weights to refine the output of untrained neural network 1406 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 1404 trains untrained neural network 1406 until untrained neural network 1406 reaches a desired accuracy. In at least one embodiment, trained neural network 1408 can then be deployed to implement any number of machine learning operations.

[0092] In at least one embodiment, the untrained neural network 1406 is trained using unsupervised learning, where the untrained neural network 1406 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1402 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1406 can learn groupings within the training data set 1402 and determine how individual inputs relate to the untrained data set 1402. In at least one embodiment, unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1408 that can perform operations useful for reducing the dimensionality of the new data 1412. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new data set 1412 that deviate from the normal patterns of the new data set 1412.

[0093] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1402. In at least one embodiment, the training framework 1404 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1408 to adapt to new data 1412 without forgetting the knowledge instilled in the network during initial training.

[0094] Data Center 15 illustrates an exemplary data center 1500 in which at least one embodiment may be used. In at least one embodiment, data center 1500 includes a data center infrastructure layer 1510, a framework layer 1520, a software layer 1530, and an application layer 1540.

[0095] 15, data center infrastructure layer 1510 may include a resource orchestrator 1512, grouped computing resources 1514, and node computing resources (“node CRs”) 1516(1) through 1516(N), where “N” represents any positive integer. In at least one embodiment, node CRs 1516(1) through 1516(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 1516(1)-1516(N) may be a server having one or more of the computing resources described above.

[0096] In at least one embodiment, grouped computing resources 1514 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). Separate groups of node CRs within grouped computing resources 1514 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0097] In at least one embodiment, resource orchestrator 1512 may configure or otherwise control one or more nodes CR 1516(1)-1516(N) and / or grouped computing resources 1514. In at least one embodiment, resource orchestrator 1512 may include a software design infrastructure (“SDI”) management entity for data center 1500. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0098] In at least one embodiment shown in FIG. 15 , framework layer 1520 includes job scheduler 1532, configuration manager 1534, resource manager 1536, and distributed file system 1538. In at least one embodiment, framework layer 1520 may include frameworks to support software 1532 in software layer 1530 and / or one or more applications 1542 in application layer 1540. In at least one embodiment, software 1532 or applications 1542 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1520 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 1538 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1532 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1500. In at least one embodiment, configuration manager 1534 may be capable of configuring different tiers, such as software tier 1530 and framework tier 1520, which includes Spark and distributed file system 1538 to support large-scale data processing. In at least one embodiment, resource manager 1536 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1538 and job scheduler 1532. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1514 in data center infrastructure tier 1510.In at least one embodiment, resource manager 1536 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 1512.

[0099] In at least one embodiment, software 1532 included in software layer 1530 may include software used by nodes CR 1516(1)-1516(N), grouped computing resources 1514, and / or at least a portion of distributed file system 1538 of framework layer 1520. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0100] In at least one embodiment, applications 1542 included in application layer 1540 may include one or more types of applications used by nodes CR 1516(1)-1516(N), grouped computing resources 1514, and / or at least a portion of distributed file system 1538 of framework layer 1520. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0101] In at least one embodiment, any of configuration manager 1534, resource manager 1536, and resource orchestrator 1512 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable data center operators of data center 1500 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0102] In at least one embodiment, data center 1500 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1500. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1500 by using weight parameters calculated by one or more techniques described herein.

[0103] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0104] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 15 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0105] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0106] Autonomous Vehicles 16A illustrates an example of an autonomous vehicle 1600 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1600 (alternatively referred to herein as “vehicle 1600”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1600 may be a semi-tractor trailer truck for transporting cargo. In at least one embodiment, the vehicle 1600 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0107] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1600 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1600 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0108] Various embodiments of the human-robot interaction system may be integrated into vehicles to assist with tasks such as package delivery and warehouse automation. For example, embodiments may be used to receive and deliver packages from humans or to accept physical cash payments on behalf of customers.

[0109] In at least one embodiment, vehicle 1600 may include components such as, without limitation, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1600 may include a propulsion system 1650 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1650 may be coupled to a drive train of vehicle 1600, which may include, without limitation, a transmission to enable propulsion of vehicle 1600. In at least one embodiment, propulsion system 1650 may be controlled in response to receiving a signal from throttle / accelerator 1652.

[0110] In at least one embodiment, a steering system 1654, which may include without limitation a steering wheel, is used to steer the vehicle 1600 (e.g., along a desired path or route) when the propulsion system 1650 is operating (e.g., when the vehicle is moving). In at least one embodiment, the steering system 1654 may receive signals from a steering actuator 1656. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 1646 may be used to operate the vehicle brakes in response to receiving signals from a brake actuator 1648 and / or brake sensor.

[0111] In at least one embodiment, controller 1636, which may include, without limitation, one or more systems on chip (“SoC”) (not shown in FIG. 16A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1600. For example, in at least one embodiment, controller 1636 may send signals to operate vehicle brakes via brake actuators 1648, steering system 1654 via steering actuators 1656, and propulsion system 1650 via throttle / accelerator 1652. Controller 1636 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1600. In at least one embodiment, the controllers 1636 may include a first controller 1636 for autonomous driving functions, a second controller 1636 for functional safety functions, a third controller 1636 for artificial intelligence functions (e.g., computer vision), a fourth controller 1636 for infotainment functions, a fifth controller 1636 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1636 may handle two or more of the above functionalities, two or more controllers 1636 may handle a single functionality, and / or some combination thereof.

[0112] In at least one embodiment, controller 1636 provides signals to control one or more components and / or systems of vehicle 1600 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1658 (e.g., global positioning system sensors), RADAR sensors 1660, ultrasonic sensors 1662, LIDAR sensors 1664, inertial measurement units (“IMUs”), and the like. The vehicle 1600 vehicle information may be received from sensors 1666 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphones 1696, stereo cameras 1668, wide-angle cameras 1670 (e.g., fisheye cameras), infrared cameras 1672, ambient cameras 1674 (e.g., 360-degree cameras), long-range cameras (not shown in FIG. 16A ), mid-range cameras (not shown in FIG. 16A ), speed sensors 1644 (e.g., for measuring the speed of the vehicle 1600), vibration sensors 1642, steering sensors 1640, brake sensors (e.g., as part of a brake sensor system 1646), and / or other types of sensors.

[0113] In at least one embodiment, one or more of the controllers 1636 may receive input (e.g., represented by input data) from the instrument cluster 1632 of the vehicle 1600 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1634, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1600. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 16A )), location data (e.g., the location of the vehicle 1600 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 1636, etc. For example, in at least one embodiment, the HMI display 1634 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0114] In at least one embodiment, vehicle 1600 further includes network interface 1624, which may use a wireless antenna 1626 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1624 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. Additionally, in at least one embodiment, wireless antenna 1626 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0115] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 16A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0116] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0117] 16B illustrates example camera locations and fields of view for the autonomous vehicle 1600 of FIG. 16A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are exemplary examples and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on the vehicle 1600.

[0118] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1600. The camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0119] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0120] In at least one embodiment, one or more of the cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0121] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of the vehicle 1600 may be used for a surroundings view to facilitate identification of the path and obstacles ahead and, in conjunction with the controller 1636 and / or one or more of the control SoCs, may assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0122] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1670 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 16B shows only one wide-angle camera 1670, in other embodiments, there may be any number (including zero) of wide-angle cameras 1670 on the vehicle 1600. In at least one embodiment, any number of long-range cameras 1698 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1698 may also be used for object detection and classification, as well as basic object tracking.

[0123] In at least one embodiment, any number of stereo cameras 1668 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1668 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1600 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1668 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1600 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1668 may be used in addition to or instead of those described herein.

[0124] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of the vehicle 1600 (e.g., side view cameras) may be used for the surrounding view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1674 (e.g., four surrounding cameras 1674 as shown in FIG. 16B ) may be disposed on the vehicle 1600. The surrounding cameras 1674 may include, without limitation, any number and combination of wide-angle cameras 1670, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1600. In at least one embodiment, the vehicle 1600 may use three surrounding cameras 1674 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0125] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1600 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 1698, and / or mid-range camera 1676, stereo camera 1668, infrared camera 1672, etc.).

[0126] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 16B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0127] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0128] FIG. 16C is a block diagram illustrating an example system architecture for the autonomous vehicle 1600 of FIG. 16A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1600 of FIG. 16C is shown as connected via a bus 1602. In at least one embodiment, the bus 1602 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1600 used to assist in controlling various features and functions of the vehicle 1600, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1602 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1602 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1602 may be an ASIL B compliant CAN bus.

[0129] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 1602 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1602 may be used to perform different functions and / or to provide redundancy. For example, a first bus 1602 may be used for collision avoidance functions and a second bus 1602 may be used for actuation control. In at least one embodiment, each bus 1602 may communicate with any of the components of the vehicle 1600, or two or more buses 1602 may communicate with the same component. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1604, each of controllers 1636, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1600) and may be connected to a common bus, such as a CAN bus.

[0130] In at least one embodiment, vehicle 1600 may include one or more controllers 1636, such as those described herein with respect to FIG. 16A. Controller 1636 may be used for a variety of functions. In at least one embodiment, controller 1636 may be coupled to any of a variety of other components and systems of vehicle 1600 and may be used to control vehicle 1600, artificial intelligence of vehicle 1600, and / or infotainment of vehicle 1600, etc.

[0131] In at least one embodiment, vehicle 1600 may include any number of SoCs 1604. Each of SoCs 1604 may include, without limitation, a central processing unit ("CPU") 1606, a graphics processing unit ("GPU") 1608, a processor 1610, a cache 1612, an accelerator 1614, a data store 1616, and / or other components and features not shown. In at least one embodiment, SoCs 1604 may be used to control vehicle 1600 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1604 may be incorporated into a system (e.g., that of vehicle 1600) having a high definition ("HD") map 1622 that can obtain map refreshes and / or updates via a network interface 1624 from one or more servers (not shown in FIG. 16C ).

[0132] In at least one embodiment, CPU 1606 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1606 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1606 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1606 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 1606 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1606 to be active at any given time.

[0133] In at least one embodiment, one or more of the CPUs 1606 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPUs 1606 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0134] In at least one embodiment, GPU 1608 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1608 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1608 may use an extended tensor instruction set. In one embodiment, GPU 1608 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1608 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1608 may use a compute application programming interface (API). In at least one embodiment, the GPU 1608 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0135] In at least one embodiment, one or more of the GPUs 1608 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 1608 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0136] In at least one embodiment, one or more of the GPUs 1608 may include high bandwidth memory (“HBW”) and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0137] In at least one embodiment, the GPU 1608 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow the GPU 1608 to directly access the CPU 1606 page tables. In at least one embodiment, when the GPU 1608 memory management unit (“MMU”) encounters a miss, an address translation request may be sent to the CPU 1606. In at least one embodiment, in response, the CPU 1606 may look up the virtual-to-physical address mapping in its page table and send the translation back to the GPU 1608. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1606 and the GPU 1608 memory, thereby simplifying programming the GPU 1608 and porting applications to the GPU 1608.

[0138] In at least one embodiment, GPU 1608 may include any number of access counters that can record the frequency of GPU 1608's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0139] In at least one embodiment, one or more of the SoCs 1604 may include any number of caches 1612, including those described herein. For example, in at least one embodiment, the caches 1612 may include a level 3 (“L3”) cache available to both the CPU 1606 and the GPU 1608 (e.g., connected to both the CPU 1606 and the GPU 1608). In at least one embodiment, the caches 1612 may include a write-back cache that can record line state using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0140] In at least one embodiment, one or more of the SoCs 1604 may include one or more accelerators 1614 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1604 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1608 and offload some of the GPU 1608's tasks (e.g., freeing up more cycles for the GPU 1608 to perform other tasks). In at least one embodiment, accelerator 1614 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0141] In at least one embodiment, the accelerator 1614 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPU”), which may be further configured to provide tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design allows for improved performance per millimeter over typical general-purpose GPUs, typically far exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 1696, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0142] In at least one embodiment, the DLA may perform any function of the GPU 1608, and a designer may target either the DLA or the GPU 1608 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1608 and / or other accelerators 1614.

[0143] In at least one embodiment, the accelerator 1614 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1638, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0144] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0145] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1606. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0146] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0147] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0148] In at least one embodiment, the accelerator 1614 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1614. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0149] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0150] In at least one embodiment, one or more of the SoCs 1604 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0151] In at least one embodiment, accelerator 1614 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run-times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 1600, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0152] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0153] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0154] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence may further enable the system to make decisions regarding which detections should be considered positive detections rather than false detections. For example, in at least one embodiment, the system may set a threshold for confidence and consider only detections that exceed the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1666 that correlates with the orientation of the vehicle 1600, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1664 or a RADAR sensor 1660), among others.

[0155] In at least one embodiment, one or more of the SoCs 1604 may include a data store 1616 (e.g., memory). In at least one embodiment, the data store 1616 may be on-chip memory of the SoC 1604, which may store neural networks running on the GPU 1608 and / or DLA. In at least one embodiment, the capacity of the data store 1616 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1616 may comprise an L2 or L3 cache.

[0156] In at least one embodiment, one or more of the SoCs 1604 may include any number of processors 1610 (e.g., embedded processors). The processors 1610 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1604 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to low power states, manage the thermal and temperature sensors of the SoC 1604, and / or manage the power state of the SoC 1604. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1604 may use the ring oscillator to detect the temperature of the CPU 1606, GPU 1608, and / or accelerator 1614. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1604 in a low power state, and / or place the vehicle 1600 in a driver-safety shutdown mode (e.g., bring the vehicle 1600 to a safety shutdown).

[0157] In at least one embodiment, processor 1610 may further include a set of embedded processors capable of acting as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0158] In at least one embodiment, processor 1610 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0159] In at least one embodiment, the processor 1610 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1610 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1610 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0160] In at least one embodiment, processor 1610 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1670, surrounding camera 1674, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1604 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0161] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0162] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to compose a user interface when the operating system desktop is in use, eliminating the need for the GPU 1608 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload the GPU 1608 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0163] In at least one embodiment, one or more of the SoCs 1604 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1604 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0164] In at least one embodiment, one or more of the SoCs 1604 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. The SoCs 1604 may be used to process data from cameras (e.g., connected via gigabit multimedia serial links and Ethernet), data from sensors (e.g., LIDAR sensors 1664, RADAR sensors 1660, etc., which may be connected via Ethernet), data from bus 1602 (e.g., vehicle 1600 speed, steering wheel position, etc.), data from GNSS sensors 1658 (e.g., connected via Ethernet or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1604 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1606.

[0165] In at least one embodiment, the SoC 1604 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1604 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1614, when combined with the CPU 1606, GPU 1608, and data store 1616, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0166] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0167] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU1620) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0168] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1608.

[0169] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1600. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1604 provides security against theft and / or carjacking.

[0170] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1696 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1604 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1658. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1662 until the emergency vehicle has passed.

[0171] In at least one embodiment, vehicle 1600 may include a CPU 1618 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1604 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1618 may include, for example, an X86 processor. CPU 1618 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1604 and / or monitoring the status and health of controller 1636 and / or infotainment system on a chip (“infotainment SoC”) 1630.

[0172] In at least one embodiment, vehicle 1600 may include a GPU 1620 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1604 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 1620 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1600.

[0173] In at least one embodiment, vehicle 1600 may further include a network interface 1624, which may include, without limitation, a wireless antenna 1626 (e.g., one or more wireless antennas 1626 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1624 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1600 and the other vehicles, and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide vehicle 1600 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1600). In at least one embodiment, the above-described functionality may be part of a cooperative adaptive cruise control function of the vehicle 1600.

[0174] In at least one embodiment, network interface 1624 may include an SoC that provides modulation and demodulation functionality and enables controller 1636 to communicate over a wireless network. In at least one embodiment, network interface 1624 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0175] In at least one embodiment, vehicle 1600 may further include a data store 1628, which may include, without limitation, off-chip (e.g., not on SoC 1604) storage. In at least one embodiment, data store 1628 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0176] In at least one embodiment, vehicle 1600 may further include GNSS sensors 1658 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1658 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0177] In at least one embodiment, vehicle 1600 may further include RADAR sensor 1660. RADAR sensor 1660 may be used by vehicle 1600 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. RADAR sensor 1660 may use CAN and / or bus 1602 for control (e.g., to transmit data generated by RADAR sensor 1660) and to access object tracking data, and in some examples, may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1660 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1660 are pulse-Doppler RADAR sensors.

[0178] In at least one embodiment, the RADAR sensor 1660 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250-meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1660 may help distinguish between static and moving objects and may be used by the ADAS system 1638 to provide emergency braking assistance and forward collision warning. The sensors 1660 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1600 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting vehicle 1600's lane.

[0179] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1660 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1638 to provide blind spot detection and / or lane change assistance.

[0180] In at least one embodiment, vehicle 1600 may further include ultrasonic sensors 1662. The ultrasonic sensors 1662 may be located at the front, rear, and / or sides of vehicle 1600 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1662 may be used, and different ultrasonic sensors 1662 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1662 may operate at functional safety level ASIL B.

[0181] In at least one embodiment, vehicle 1600 may include a LIDAR sensor 1664. The LIDAR sensor 1664 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 1664 may be functional safety level ASIL B. In at least one embodiment, vehicle 1600 may include multiple LIDAR sensors 1664 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0182] In at least one embodiment, the LIDAR sensor 1664 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1664 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1664 may be used. In such an embodiment, the LIDAR sensor 1664 may be implemented as a small device that can be integrated into the front, rear, sides, and / or corners of the vehicle 1600. In at least one embodiment, the LIDAR sensor 1664 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1664 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0183] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1600 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1600 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1600. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0184] In at least one embodiment, the vehicle may further include an IMU sensor 1666. In at least one embodiment, the IMU sensor 1666 may be positioned at the center of the rear axle of the vehicle 1600. In at least one embodiment, the IMU sensor 1666 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1666 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1666 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0185] In at least one embodiment, the IMU sensor 1666 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1666 enables the vehicle 1600 to estimate its orientation by directly observing changes in velocity and correlating them from the GPS to the IMU sensor 1666 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1666 and the GNSS sensor 1658 may be combined into a single integrated unit.

[0186] In at least one embodiment, vehicle 1600 may include microphones 1696 located in and / or around vehicle 1600. In at least one embodiment, microphones 1696 may be used for, among other things, emergency vehicle detection and identification.

[0187] In at least one embodiment, vehicle 1600 may further include any number of camera types, including stereo cameras 1668, wide-angle cameras 1670, infrared cameras 1672, perimeter cameras 1674, long-range cameras 1698, mid-range cameras 1676, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1600. In at least one embodiment, the types of cameras used vary depending on vehicle 1600. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1600. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1600 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 16A and 16B.

[0188] In at least one embodiment, vehicle 1600 may further include a vibration sensor 1642. Vibration sensor 1642 may measure vibrations of components of vehicle 1600, such as an axle. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, if two or more vibration sensors 1642 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0189] In at least one embodiment, vehicle 1600 may include an ADAS system 1638. ADAS system 1638 may include, without limitation, an SoC in some examples. In at least one embodiment, the ADAS systems 1638 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0190] In at least one embodiment, the ACC system may use a RADAR sensor 1660, a LIDAR sensor 1664, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 1600 and automatically adjusts the speed of the vehicle 1600 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1600 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0191] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by the network interface 1624 and / or wireless antenna 1626 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of the vehicle 1600 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of the vehicle 1600 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0192] In at least one embodiment, the FCW system is designed to alert the driver to hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0193] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0194] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1600 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or brake control to correct the vehicle 1600 if the vehicle 1600 begins to drift out of its lane.

[0195] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1660 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0196] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1600. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0197] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major issue because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1600 itself determines whether to follow the results from the primary computer (e.g., first controller 1636) or the secondary computer (e.g., second controller 1636). For example, in at least one embodiment, the ADAS system 1638 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1638 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0198] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0199] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC1604.

[0200] In at least one embodiment, the ADAS system 1638 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0201] In at least one embodiment, the output of the ADAS system 1638 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1638 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0202] In at least one embodiment, vehicle 1600 may further include an infotainment SoC 1630 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1630 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1630 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1600. For example, infotainment SoC 1630 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1634, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1630 may also be used to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from an ADAS system 1638, autonomous driving information such as a vehicle maneuver plan, a trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0203] In at least one embodiment, infotainment SoC 1630 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1630 may communicate with other devices, systems, and / or components of vehicle 1600 via bus 1602 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 1630 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1636 (e.g., vehicle 1600's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1630 may place vehicle 1600 in a driver-safety shutdown mode, as described herein.

[0204] In at least one embodiment, vehicle 1600 may further include an instrument cluster 1632 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 1632 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1632 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1630 and instrument cluster 1632. In at least one embodiment, instrument cluster 1632 may be included as part of infotainment SoC 1630, or vice versa.

[0205] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 16C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0206] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0207] 16D is a diagram of a system 1676 for communicating between a cloud-based server and the autonomous vehicle 1600 of FIG. 16A , according to at least one embodiment. In at least one embodiment, the system 1676 may include any number and type of vehicles, including, without limitation, a server 1678, a network 1690, and the vehicle 1600. The server 1678 may include, without limitation, multiple GPUs 1684(A)-1684(H) (collectively referred to herein as GPUs 1684), PCIe switches 1682(A)-1682(H) (collectively referred to herein as PCIe switches 1682), and / or CPUs 1680(A)-1680(B) (collectively referred to herein as CPUs 1680). The GPUs 1684, CPUs 1680, and PCIe switches 1682 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1688 developed by NVIDIA, and / or a PCIe connection 1686. In at least one embodiment, the GPUs 1684 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1684 and PCIe switches 1682 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 1684, two CPUs 1680, and four PCIe switches 1682 are illustrated, but this is not intended to be limiting. In at least one embodiment, each of the servers 1678 may include any number of GPUs 1684, CPUs 1680, and / or PCIe switches 1682 in any combination, without limitation. For example, in at least one embodiment, the servers 1678 may each include 8, 16, 32, and / or more GPUs 1684.

[0208] In at least one embodiment, server 1678 may receive image data from the vehicle over network 1690 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1678 may transmit neural network 1692, updated neural network 1692, and / or map information 1694, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 1690. In at least one embodiment, updates to map information 1694 may include, without limitation, updates to HD map 1622, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1692, updated neural network 1692, and / or map information 1694 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1678 and / or other servers).

[0209] In at least one embodiment, server 1678 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. The training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1690) and / or used by server 1678 to remotely monitor the vehicle.

[0210] In at least one embodiment, server 1678 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1678 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1684, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1678 may also include a deep learning infrastructure using a CPU-powered data center.

[0211] In at least one embodiment, the deep learning infrastructure of server 1678 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1600. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1600, such as a series of images and / or objects that vehicle 1600 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1600; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1600 has failed, server 1678 may send a signal to vehicle 1600 instructing the vehicle's 1600 fail-safe computer to take control, notify the occupants, and complete a safe stop maneuver.

[0212] In at least one embodiment, server 1678 may include a GPU 1684 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 1315 is used to execute one or more embodiments. Details regarding hardware structure 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B.

[0213] Computer Systems 17 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof 1700 formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1700 may include components such as, without limitation, a processor 1702 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1700 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1700 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux), embedded software, and / or graphical user interfaces may also be used.

[0214] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0215] In at least one embodiment, computer system 1700 may include, without limitation, a processor 1702, which may include one or more execution units 1708 for performing training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, system 17 is a single-processor desktop or server system, while in other embodiments, system 17 may be a multiprocessor system. In at least one embodiment, processor 1702 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1702 may be coupled to a processor bus 1710, which may transmit digital signals between processor 1702 and other components within computer system 1700.

[0216] In at least one embodiment, processor 1702 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1704. In at least one embodiment, processor 1702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1702. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1706 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0217] In at least one embodiment, processor 1702 also includes an execution unit 1708, including, without limitation, logic for performing integer and floating-point operations. Processor 1702 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1708 may include logic for a packed instruction set 1709. In at least one embodiment, including packed instruction set 1709, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 1702 allows operations used by many multimedia applications to be performed using packed data in general-purpose processor 1702. In one or more embodiments, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0218] In at least one embodiment, execution unit 1708 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1700 may include, without limitation, memory 1720. In at least one embodiment, memory 1720 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 1720 may store instructions 1719 and / or data 1721 represented by data signals that may be executed by processor 1702.

[0219] In at least one embodiment, a system logic chip may be coupled to the processor bus 1710 and the memory 1720. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1716, and the processor 1702 may communicate with the MCH 1716 via the processor bus 1710. In at least one embodiment, the MCH 1716 may provide a high-bandwidth memory path 1718 to the memory 1720 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1716 may route data signals between the processor 1702, the memory 1720, and other components of the computer system 1700, and may bridge data signals between the processor bus 1710, the memory 1720, and the system I / O 1722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1716 may be coupled to memory 1720 via a high-bandwidth memory path 1718, and the graphics / video card 1712 may be coupled to the MCH 1716 via an Accelerated Graphics Port (“AGP”) interconnect 1714.

[0220] In at least one embodiment, computer system 1700 may use system I / O 1722, a proprietary hub interface bus, to couple MCH 1716 to I / O controller hub (“ICH”) 1730. In at least one embodiment, ICH 1730 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1720, a chipset, and processor 1702. Examples may include, without limitation, an audio controller 1729, a firmware hub ("flash BIOS") 1728, a wireless transceiver 1726, data storage 1724, a legacy I / O controller 1723 including a user input and keyboard interface, a serial expansion port 1727 such as a Universal Serial Bus ("USB"), and a network controller 1734. Data storage 1724 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0221] In at least one embodiment, FIG. 17 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 17 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 17 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1700 may be interconnected using a compute express link (CXL) interconnect.

[0222] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 17 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0223] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0224] 18 is a block diagram illustrating an electronic device 1800 for utilizing a processor 1810, according to at least one embodiment. In at least one embodiment, electronic device 1800 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0225] In at least one embodiment, system 1800 may include a processor 1810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, including, without limitation, processor 1810 coupled using a bus or interface, such as an I / C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 18 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 18 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 18 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 18 may be interconnected using a Compute Express Link (CXL) interconnect.

[0226] In at least one embodiment, FIG. 18 illustrates a display 1824, a touch screen 1825, a touch pad 1830, a Near Field Communications unit ("NFC") 1845, a sensor hub 1840, a thermal sensor 1846, an Express Chipset ("EC") 1835, a Trusted Platform Module ("TPM") 1838, a BIOS / firmware / flash memory ("BIOS,FW flash") 1822, a DSP 1860, a drive ("SSD or HDD") 1820, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN"), and a wireless local area network ("WLAN") 1840. The memory may include a Bluetooth unit 1850, a Bluetooth unit 1852, a Wireless Wide Area Network unit (“WWAN”) 1856, a Global Positioning System (GPS) 1855, a camera such as a USB 3.0 camera (“USB 3.0 camera”) 1854, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1815, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0227] In at least one embodiment, other components may be communicatively coupled to the processor 1810 via the components described above. In at least one embodiment, an accelerometer 1841, an ambient light sensor (“ALS”) 1842, a compass 1843, and a gyroscope 1844 may be communicatively coupled to the sensor hub 1840. In at least one embodiment, a thermal sensor 1839, a fan 1837, a keyboard 1846, and a touchpad 1830 may be communicatively coupled to the EC 1835. In at least one embodiment, a speaker 1863, headphones 1864, and a microphone (“mic”) 1865 may be communicatively coupled to an audio unit (audio codec and class D amplifier) ​​1864, which may be communicatively coupled to the DSP 1860. In at least one embodiment, the audio unit 1864 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1857 may be communicatively coupled to the WWAN unit 1856. In at least one embodiment, components such as the WLAN unit 1850 and the Bluetooth unit 1852, and the WWAN 1856 may be implemented in a Next Generation Form Factor (“NGFF”).

[0228] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 18 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0229] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0230] 19 illustrates a computer system 1900, according to at least one embodiment. In at least one embodiment, the computer system 1900 is configured to implement the various processes and methods described throughout this disclosure.

[0231] In at least one embodiment, computer system 1900 includes at least one central processing unit ("CPU") 1902 connected to a communication bus 1910 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1900 includes main memory 1904 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1904, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1922 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 1900 to other systems.

[0232] In at least one embodiment, computer system 1900 includes, without limitation, input device(s) 1908, a parallel processing system 1912, and a display device 1906, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1908, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0233] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, training logic 1315 may be used in the system of Figure 19 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0234] The computer system described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0235] 20 illustrates a computer system 2000 according to at least one embodiment. In at least one embodiment, the computer system 2000 may include, without limitation, a computer 2010 and a USB stick 2020. In at least one embodiment, the computer system 2010 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, the computer 2010 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0236] In at least one embodiment, USB stick 2020 includes, without limitation, a processing unit 2030, a USB interface 2040, and USB interface logic 2050. In at least one embodiment, processing unit 2030 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 2030 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 2030 comprises an application specific integrated circuit ("ASIC") optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing core 2030 is a tensor processing unit ("TPC") optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing core 2030 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0237] In at least one embodiment, USB interface 2040 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 2040 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 2040 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 2050 may include any amount and type of logic that enables processing unit 2030 to interface with a device (e.g., computer 2010) via USB connector 2040.

[0238] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in the system of Figure 20 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0239] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0240] 21A illustrates an exemplary architecture in which multiple GPUs 2110-2113 are communicatively coupled to multiple multi-core processors 2105-2106 via high-speed links 2140-2143 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 2140-2143 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0241] Additionally, in one embodiment, two or more of GPUs 2110-2113 may be interconnected via high-speed links 2129-2130, which may be implemented using the same or different protocol / links as used for high-speed links 2140-2143. Similarly, two or more of multi-core processors 2105-2106 may be connected via high-speed link 2128, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 21A may be achieved using the same protocol / links (e.g., via a common interconnect fabric).

[0242] In one embodiment, each multi-core processor 2105-2106 is communicatively coupled to processor memory 2101-2102 via a memory interconnect 2126-2127, respectively, and each GPU 2110-2113 is communicatively coupled to GPU memory 2120-2123 via a GPU memory interconnect 2150-2153, respectively. The memory interconnects 2126-2127 and 2150-2153 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memory 2101-2102 and the GPU memory 2120-2123 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memory 2101-2102 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0243] As described herein, the various processors 2105-2106 and GPUs 2110-2113 may each be physically coupled to a particular memory 2101-2102, 2120-2123, but a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, the processor memories 2101-2102 may each have 64 GB of system memory address space, and the GPU memories 2120-2123 may each have 32 GB of system memory address space (resulting in this example in a total of 256 GB of addressable memory).

[0244] 21B shows further details of the interconnection between the multi-core processor 2107 and the graphics acceleration module 2146 according to one example embodiment. The graphics acceleration module 2146 may include one or more GPU chips integrated on a line card that is coupled to the processor 2107 via a high-speed link 2140. Alternatively, the graphics acceleration module 2146 may be integrated in the same package or chip as the processor 2107.

[0245] In at least one embodiment, the illustrated processor 2107 includes multiple cores 2160A-2160D, each having a translation lookaside buffer 2161A-2161D and one or more caches 2162A-2162D. In at least one embodiment, the cores 2160A-2160D may include various other components, not shown, for executing instructions and processing data. The caches 2162A-2162D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 2156 may be included in the caches 2162A-2162D and shared by the set of cores 2160A-2160D. For example, one embodiment of the processor 2107 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 2107 and graphics acceleration module 2146 are connected to system memory 2114, which may include processor memory 2101-2102 of FIG. 21A.

[0246] Coherence is maintained for data and instructions stored in the various caches 2162A-2162D, 2156, and system memory 2114 through inter-core communication via a coherence bus 2164. For example, each cache may have associated cache coherence logic / circuitry for communicating via the coherence bus 2164 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 2164 to monitor cache accesses.

[0247] In one embodiment, proxy circuit 2125 communicatively couples graphics acceleration module 2146 to coherence bus 2164 to enable graphics acceleration module 2146 to participate in cache coherence protocols as a peer of cores 2160A-2160D. In particular, interface 2135 provides a connection to proxy circuit 2125 over high-speed link 2140 (e.g., PCIe bus, NVLink, etc.), and interface 2137 connects graphics acceleration module 2146 to link 2140.

[0248] In one implementation, the accelerator integrated circuit 2136 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 2131, 2132, N of the graphics acceleration module 2146. The graphics processing engines 2131, 2132, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 2131, 2132, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 2146 may be a GPU having multiple graphics processing engines 2131-2132, N, or the graphics processing engines 2131-2132, N may be individual GPUs integrated into a common package, line card, or chip.

[0249] In one embodiment, the accelerator integrated circuitry 2136 includes a memory management unit (MMU) 2139 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing the system memory 2114. The MMU 2139 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 2138 stores commands and data for efficient access by the graphics processing engines 2131-2132, N. In one embodiment, data stored in the cache 2138 and the graphics memory 2133-2134, M is kept coherent with the core caches 2162A-2162D, 2156, and the system memory 2114. As noted above, this may be accomplished via the proxy circuit 2125 on behalf of the cache 2138 and memories 2133-2134, M (e.g., sending updates regarding modifications / accesses of cache lines in the processor caches 2162A-2162D, 2156 to the cache 2138 and receiving updates from the cache 2138).

[0250] A set of registers 2145 stores context data for threads executed by the graphics processing engines 2131-2132, and a context management circuit 2148 manages thread contexts. For example, the context management circuit 2148 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 2148 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 2148 may restore the register values. In one embodiment, the interrupt management circuit 2147 receives and processes interrupts received from system devices.

[0251] In one implementation, virtual / effective addresses from the graphics processing engine 2131 are translated to real / physical addresses in the system memory 2114 by the MMU 2139. One embodiment of the accelerator integration circuit 2136 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 2146 and / or other accelerator devices. The graphics accelerator modules 2146 may be dedicated to a single application running on the processor 2107 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 2131-2132, N, are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0252] In at least one embodiment, the accelerator integration circuitry 2136 acts as a bridge to the system for the graphics acceleration module 2146, providing address translation and system memory caching services. Additionally, the accelerator integration circuitry 2136 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 2131-2132.

[0253] The hardware resources of the graphics processing engines 2131-2132, N are explicitly mapped into the real address space seen by the host processor 2107, so that any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 2136 is to physically separate the graphics processing engines 2131-2132, N so that they appear as independent units to the system.

[0254] In at least one embodiment, one or more graphics memories 2133-2134, M are coupled to each of the graphics processing engines 2131-2132, N, respectively. The graphics memories 2133-2134, M store instructions and data that are processed by the respective graphics processing engines 2131-2132, N. The graphics memories 2133-2134, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0255] In one embodiment, to reduce data traffic over link 2140, a biasing technique is used to ensure that the data stored in graphics memory 2133-2134, M is data that will be most frequently used by graphics processing engines 2131-2132, N, and preferably is data that is not used (or at least not frequently used) by cores 2160A-2160D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 2131-2132, N) in the cores' caches 2162A-2162D, 2156 and system memory 2114.

[0256] FIG. 21C illustrates another exemplary embodiment in which the accelerator integration circuitry 2136 is integrated within the processor 2107. In at least this embodiment, the graphics processing engines 2131-2132, N communicate directly with the accelerator integration circuitry 2136 via high-speed link 2140 via interface 2137 and interface 2135 (again, any form of bus or interface protocol can be utilized). The accelerator integration circuitry 2136 may perform the same operations as described with respect to FIG. 21B, but may potentially operate at a higher throughput given its proximity to the coherence bus 2164 and caches 2162A-2162D, 2156. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integration circuitry 2136 and a programming model controlled by the graphics acceleration module 2146.

[0257] In at least one embodiment, graphics processing engines 2131-2132, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 2131-2132, N, achieving virtualization within a VM / partition.

[0258] In at least one embodiment, the graphics processing engines 2131-2132,N may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize the graphics processing engines 2131-2132,N and allow access by each operating system. In a single-partition system without a hypervisor, the graphics processing engines 2131-2132,N are owned by the operating system. In at least one embodiment, the operating system may virtualize the graphics processing engines 2131-2132,N and provide access to each process or application.

[0259] In at least one embodiment, the graphics acceleration module 2146 or an individual graphics processing engine 2131-2132,N selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 2114 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 2131-2132,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0260] FIG. 21D illustrates an exemplary accelerator integration slice 2190. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuitry 2136. An application effective address space 2182 in the system memory 2114 stores a process element 2183. In one embodiment, the process element 2183 is stored in response to a GPU call 2181 from an application 2180 running on the processor 2107. The process element 2183 contains the process state of the corresponding application 2180. A work descriptor (WD) 2184 contained in the process element 2183 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 2184 is a pointer to a job request queue in the application's address space 2182.

[0261] The graphics acceleration module 2146 and / or the individual graphics processing engines 2131-2132, N may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD2184 to the graphics acceleration module 2146 to start a job in a virtualized environment.

[0262] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 2146 or an individual graphics processing engine 2131. Because the graphics acceleration module 2146 is owned by a single process, when the graphics acceleration module 2146 is allocated, the hypervisor initializes the accelerator integration circuitry 2136 for the owning partition, and the operating system initializes the accelerator integration circuitry 2136 for the owning process.

[0263] In operation, the WD fetch unit 2191 in the accelerator integrated slice 2190 fetches the next WD 2184, which contains an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 2146. As shown, data from the WD 2184 is stored in registers 2145 and may be used by the MMU 2139, the interrupt management circuit 2147, and / or the context management circuit 2148. For example, one embodiment of the MMU 2139 includes segment / page walk circuitry for accessing a segment / page table 2186 in the OS virtual address space 2185. The interrupt management circuit 2147 may process interrupt events 2192 received from the graphics acceleration module 2146. When performing graphics operations, the effective addresses 2193 generated by the graphics processing engines 2131-2132, N are translated into real addresses by the MMU 2139.

[0264] In one embodiment, the same set of registers 2145 may be replicated for each graphics processing engine 2131-2132, N, and / or graphics acceleration module 2146 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 2190. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 4]

[0265] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 5]

[0266] In one embodiment, each WD 2184 is specific to a particular graphics acceleration module 2146 and / or graphics processing engine 2131-2132, N. The WD 2184 contains all the information the graphics processing engine 2131-2132, N needs to do its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0267] 21E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 2198 in which a process element list 2199 is stored. The hypervisor real address space 2198 is accessible through a hypervisor 2196 that virtualizes the graphics acceleration module engine of the operating system 2195.

[0268] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 2146. There are two programming models in which the graphics acceleration module 2146 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0269] In this model, the system hypervisor 2196 owns the graphics acceleration module 2146 and makes its functions available to all operating systems 2195. In order for the graphics acceleration module 2146 to support virtualization by the system hypervisor 2196, the graphics acceleration module 2146 may comply with the following: 1) an application's job request must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 2146 must provide a mechanism for saving and restoring context. 2) the application's job request must be guaranteed by the graphics acceleration module 2146 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 2146 must provide the ability to preempt job processing. 3) the graphics acceleration module 2146 must ensure fairness between processes when operating in a specified shared programming model.

[0270] In at least one embodiment, the application 2180 must make a system call to the operating system 2195 with the graphics acceleration module 2146 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 2146 type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module 2146 type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 2146 and may be in the form of a graphics acceleration module 2146 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 2146. In one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. If the implementation of the accelerator integrated circuit 2136 and the graphics acceleration module 2146 does not support a User Permission Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. The hypervisor 2196 may optionally apply the current Permission Mask Override Register (AMOR) value before placing the AMR in the process element 2183. In at least one embodiment, the CSRP is one of the registers 2145 that contains the effective address of an area in the application's address space 2182 for the graphics acceleration module 2146 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0271] Upon receiving the system call, the operating system 2195 may verify that the application 2180 is registered and authorized to use the graphics acceleration module 2146. The operating system 2195 then calls the hypervisor 2196 with the information shown in Table 3. [Table 6]

[0272] Upon receiving the hypervisor call, the hypervisor 2196 verifies that the operating system 2195 is registered and authorized to use the graphics acceleration module 2146. The hypervisor 2196 then places the process element 2183 into the process element linked list of the corresponding graphics acceleration module 2146 type. The process element may include the information shown in Table 4. [Table 7]

[0273] In at least one embodiment, the hypervisor initializes registers 2145 of multiple accelerator integrated slices 2190.

[0274] As shown in Figure 21F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 2101-2102 and GPU memories 2120-2123. In this implementation, operations performed on GPUs 2110-2113 utilize the same virtual / effective memory address space as those used to access processor memories 2101-2102, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 2101, a second portion is allocated to second processor memory 2102, a third portion is allocated to GPU memory 2120, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 2101-2102 and GPU memories 2120-2123, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0275] In one embodiment, bias / coherence management circuits 2194A-2194E in one or more of the MMUs 2139A-2139E ensure cache coherence between the caches of one or more host processors (e.g., 2105) and the caches of the GPUs 2110-2113 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. While multiple instances of bias / coherence management circuits 2194A-2194E are shown in FIG. 21F, the bias / coherence circuits may also be implemented within the MMUs of one or more host processors 2105 and / or within the accelerator integration circuit 2136.

[0276] One embodiment allows the GPU-associated memory 2120-2123 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU-associated memory 2120-2123 can be accessed as system memory without cumbersome cache coherence overhead, providing a beneficial operating environment for GPU offload. This configuration allows the host processor 2105 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access the GPU-associated memory 2120-2123 without cache coherence overhead can be critical to the execution time of the offloaded computation. For example, in cases where there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 2110-2113. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0277] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (i.e., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU-attached memories 2120-2123, with or without a bias cache in the GPUs 2110-2113 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the bias table may be maintained entirely within the GPU.

[0278] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 2120-2123 is accessed prior to the actual access to the GPU memory, resulting in the following actions: First, a local request from a GPU 2110-2113 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 2120-2123. A local request from a GPU that finds its page in the host bias is forwarded to the processor 2105 (e.g., via the high-speed link described above). In one embodiment, a request from the processor 2105 that finds the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 2110-2113. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0279] One mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 2105 bias to GPU bias, but not for transitions in the opposite direction.

[0280] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 2105. To access these pages, the processor 2105 may request access from the GPU 2110, which may or may not immediately grant the access. Therefore, to reduce communication between the processor 2105 and the GPU 2110, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 2105, or vice versa.

[0281] To implement one or more embodiments, a hardware structure 1315 is used. Details regarding the hardware structure (x) 1315 are provided herein in conjunction with Figures 13A and / or 13B.

[0282] 22 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0283] 22 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2200 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2200 includes one or more application processors 2205 (e.g., CPUs), at least one graphics processor 2210, and may further include an image processor 2215 and / or a video processor 2220, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2200 includes peripheral or bus logic including a USB controller 2225, a UART controller 2230, an SPI / SDIO controller 2235, and an I.sup.2S / I.sup.2C controller 2240. In at least one embodiment, integrated circuit 2200 may include a display device 2245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2250 and a mobile industry processor interface (MIPI) display interface 2255. In at least one embodiment, storage may be provided by a flash memory subsystem 2260 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 2265 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 2270.

[0284] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in integrated circuit 2200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0285] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0286] 23A-23B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0287] 23A-23B are block diagrams illustrating exemplary graphics processors for use within an SoC according to embodiments described herein. FIG. 23A illustrates an exemplary graphics processor 2310 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 23B illustrates a further exemplary graphics processor 2340 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 2310 of FIG. 23A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2340 of FIG. 23B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 2310, 2340 can be a variation of the graphics processor 2210 of FIG. 22.

[0288] In at least one embodiment, the graphics processor 2310 includes a vertex processor 2305 and one or more fragment processors 2315A-2315N (e.g., 2315A, 2315B, 2315C, 2315D-2315N-1, and 2315N). In at least one embodiment, the graphics processor 2310 can execute different shader programs through separate logic, such that the vertex processor 2305 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2315A-2315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2305 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processors 2315A-2315N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by the vertex processor 2305. In at least one embodiment, the fragment processors 2315A-2315N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0289] In at least one embodiment, the graphics processor 2310 further includes one or more memory management units (MMUs) 2320A-2320B, caches 2325A-2325B, and circuit interconnects 2330A-2330B. In at least one embodiment, the one or more MMUs 2320A-2320B provide virtual-to-physical address mapping for the graphics processor 2310, including the vertex processor 2305 and / or fragment processors 2315A-2315N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 2325A-2325B. In at least one embodiment, one or more MMUs 2320A-2320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 2205, image processor 2215, and / or video processor 2220 of Figure 22, allowing each processor 2205-2220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2330A-2330B enable graphics processor 2310 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0290] In at least one embodiment, graphics processor 2340 includes one or more MMUs 2320A-2320B, caches 2325A-2325B, and circuit interconnects 2330A-2330B of graphics processor 2310 of FIG. 23A. In at least one embodiment, graphics processor 2340 includes one or more shader cores 2355A-2355N (e.g., 2355A, 2355B, 2355C, 2355D, 2355E, 2355F-2355N-1, and 2355N), providing a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 2340 includes an inter-core task manager 2345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2355A-2355N, and a tiling unit 2358 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0291] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in integrated circuits 23A and / or 23B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0292] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0293] 24A-24B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 24A illustrates a graphics core 2400, which, in at least one embodiment, may be included in graphics processor 2210 of Figure 22, or, in at least one embodiment, may be integrated shader cores 2355A-2355N, as in Figure 23B. Figure 24B illustrates a highly parallel, general-purpose graphics processing unit 2430 suitable for incorporation into a multi-chip module in at least one embodiment.

[0294] In at least one embodiment, graphics core 2400 includes a shared instruction cache 2402, a texture unit 2418, and a cache / shared memory 2420, which are common to execution resources within graphics core 2400. In at least one embodiment, graphics core 2400 may include multiple slices 2401A-2401N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2400. Slices 2401A-2401N may include supporting logic, including local instruction caches 2404A-2404N, thread schedulers 2406A-2406N, thread dispatchers 2408A-2408N, and sets of registers 2410A-2410N. In at least one embodiment, slices 2401A-2401N may include a set of additional functional units (AFUs 2412A-2412N), floating point units (FPUs 2414A-2414N), integer arithmetic logic units (ALUs 2416-2416N), address calculation units (ACUs 2413A-2413N), double precision floating point units (DPFPUs 2415A-2415N), and matrix processing units (MPUs 2417A-2417N).

[0295] In at least one embodiment, the FPUs 2414A-2414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2415A-2415N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2416A-2416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2417A-2417N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2417A-2417N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, the AFUs 2412A-2412N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0296] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B. In at least one embodiment, inference and / or training logic 1315 may be used in graphics core 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0297] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0298] FIG. 24B illustrates a general-purpose processing unit (GPGPU) 2430, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2430 can be directly linked to other instances of the GPGPU 2430 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2430 includes a host interface 2432 for enabling connection to a host processor. In at least one embodiment, the host interface 2432 is a PCI Express interface. In at least one embodiment, the host interface 2432 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2430 receives commands from the host processor and, using a global scheduler 2434, distributes execution threads associated with these commands to a set of compute clusters 2436A-2436H. In at least one embodiment, compute clusters 2436A-2436H share cache memory 2438. In at least one embodiment, cache memory 2438 can act as a higher level cache for cache memories within compute clusters 2436A-2436H.

[0299] In at least one embodiment, GPGPU 2430 includes memory 2444A-2444B coupled to compute clusters 2436A-2436H via a set of memory controllers 2442A-2442B. In at least one embodiment, memory 2444A-2444B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0300] In at least one embodiment, compute clusters 2436A-2436H each include a set of graphics cores, such as graphics core 2400 of FIG. 24A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2436A-2436H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0301] In at least one embodiment, multiple instances of GPGPU 2430 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2436A-2436H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2430 communicate through host interface 2432. In at least one embodiment, GPGPU 2430 includes I / O hub 2439, which couples GPGPU 2430 to GPU link 2440, which enables direct connection to other instances of GPGPU 2430. In at least one embodiment, GPU link 2440 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2430. In at least one embodiment, GPU link 2440 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2430 are located in separate data processing systems and communicate via a network device accessible via host interface 2432. In at least one embodiment, GPU link 2440 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2432.

[0302] In at least one embodiment, the GPGPU 2430 can be configured to train a neural network. In at least one embodiment, the GPGPU 2430 can be used within an inference platform. In at least one embodiment, when the GPGPU 2430 is used for inference, the GPGPU may include fewer compute clusters 2436A-2436H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2444A-2444B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2430 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0303] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, the inference and / or training logic 1315 may be used in the GPGPU 2430 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0304] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0305] 25 is a block diagram illustrating a computing system 2500 according to at least one embodiment. In at least one embodiment, computing system 2500 includes a processing subsystem 2501 having one or more processors 2502 and system memory 2504 that communicate via an interconnection path that may include a memory hub 2505. In at least one embodiment, memory hub 2505 may be a separate component within a chipset component or may be integrated within one or more processors 2502. In at least one embodiment, memory hub 2505 is coupled to an I / O subsystem 2511 via communication link 2506. In at least one embodiment, I / O subsystem 2511 includes an I / O hub 2507 that can enable computing system 2500 to receive input from one or more input devices 2508. In at least one embodiment, the I / O hub 2507 can enable a display controller, which may be included in one or more processors 2502 and provide output to one or more display devices 2510A. In at least one embodiment, the one or more display devices 2510A coupled to the I / O hub 2507 can include local, internal, or embedded display devices.

[0306] In at least one embodiment, processing subsystem 2501 includes one or more parallel processors 2512 coupled to memory hub 2505 via a bus or other communication link 2513. In at least one embodiment, communication link 2513 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 2512 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 2512 form a graphics processing subsystem that can output pixels to one of one or more display devices 2510A coupled via I / O hub 2507. In at least one embodiment, the one or more parallel processors 2512 may also include a display controller and display interface (not shown) that allows for direct connection to one or more display devices 2510B.

[0307] In at least one embodiment, a system storage unit 2514 may be connected to an I / O hub 2507 to provide a storage mechanism for the computing system 2500. In at least one embodiment, an I / O switch 2516 may be used to provide an interface mechanism to enable communication between the I / O hub 2507 and other components, such as a network adapter 2518 and / or a wireless network adapter 2519, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2520. In at least one embodiment, the network adapter 2518 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2519 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0308] In at least one embodiment, computing system 2500 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2507. In at least one embodiment, the communication paths interconnecting the various components of FIG. 25 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0309] In at least one embodiment, one or more parallel processors 2512 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2512 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2500 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2512, memory hub 2505, processor 2502, and I / O hub 2507 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2500 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2500 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0310] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, the inference and / or training logic 1315 may be used in the system of Figure 2500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0311] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0312] Processor 26A illustrates a parallel processor 2600 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2600 is a variation of one or more parallel processors 2512 shown in FIG. 25 according to an example embodiment.

[0313] In at least one embodiment, parallel processor 2600 includes parallel processing units 2602. In at least one embodiment, parallel processing units 2602 include I / O units 2604 that enable communication with other devices, including other instances of parallel processing units 2602. In at least one embodiment, I / O units 2604 may be directly connected to other devices. In at least one embodiment, I / O units 2604 are connected to other devices through the use of a hub or switch interface, such as memory hub 2505. In at least one embodiment, the connection between memory hub 2505 and I / O units 2604 forms communication link 2513. In at least one embodiment, I / O units 2604 are connected to host interface 2606 and memory crossbar 2616, where host interface 2606 receives commands directed to the execution of processing operations and memory crossbar 2616 receives commands directed to the execution of memory operations.

[0314] In at least one embodiment, when host interface 2606 receives command buffers via I / O unit 2604, host interface 2606 can direct work operations to execute these commands to front end 2608. In at least one embodiment, front end 2608 is coupled to scheduler 2610, which is configured to distribute commands or other work items to processing cluster array 2612. In at least one embodiment, scheduler 2610 ensures that processing cluster array 2612 is properly configured and in a valid state before tasks are distributed to processing cluster array 2612 of processing cluster array 2612. In at least one embodiment, scheduler 2610 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2610 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, allowing rapid preemption and context switching of threads executing in the processing array 2612. In at least one embodiment, host software can signal the scheduling workload in the processing array 2612 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 2612 by scheduler 2610 logic in the microcontroller that includes the scheduler 2610.

[0315] In at least one embodiment, processing cluster array 2612 can include up to “N” processing clusters (e.g., cluster 2614A, cluster 2614B through cluster 2614N). In at least one embodiment, each cluster 2614A through 2614N of processing cluster array 2612 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 2610 can allocate work to clusters 2614A through 2614N of processing cluster array 2612 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2610 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2612. In at least one embodiment, different clusters 2614A through 2614N of processing cluster array 2612 can be allocated to process different types of programs or perform different types of computations.

[0316] In at least one embodiment, processing cluster array 2612 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2612 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2612 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0317] In at least one embodiment, the processing cluster array 2612 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2612 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2612 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2602 may transfer data from system memory via the I / O unit 2604 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2622) during processing and then written back to system memory.

[0318] In at least one embodiment, when graphics processing is performed using parallel processing unit 2602, scheduler 2610 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2614A-2614N of processing cluster array 2612. In at least one embodiment, portions of processing cluster array 2612 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2614A-2614N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2614A-2614N for further processing.

[0319] In at least one embodiment, the processing cluster array 2612 can receive processing tasks to be performed via a scheduler 2610, which receives commands defining the processing tasks from the front end 2608. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2610 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2608. In at least one embodiment, the front end 2608 can be configured to ensure that the processing cluster array 2612 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0320] In at least one embodiment, each of one or more instances of parallel processing unit 2602 can be coupled to parallel processor memory 2622. In at least one embodiment, parallel processor memory 2622 can be accessed via memory crossbar 2616, which can receive memory requests from processing cluster array 2612 as well as I / O unit 2604. In at least one embodiment, memory crossbar 2616 can access parallel processor memory 2622 via memory interface 2618. In at least one embodiment, memory interface 2618 can include multiple partition units (e.g., partition unit 2620A, partition unit 2620B through partition unit 2620N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2622. In at least one embodiment, the number of partition units 2620A-2620N is configured to be equal to the number of memory units, such that a first partition unit 2620A has a corresponding first memory unit 2624A, a second partition unit 2620B has a corresponding memory unit 2624B, and an Nth partition unit 2620N has a corresponding Nth memory unit 2624N. In at least one embodiment, the number of partition units 2620A-2620N does not have to be equal to the number of memory devices.

[0321] In at least one embodiment, the memory units 2624A-2624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2624A-2624N may also include 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2622, render targets, such as frame buffers or texture maps, may be stored across the memory units 2624A-2624N, allowing the partition units 2620A-2620N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2622 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0322] In at least one embodiment, any one of the clusters 2614A-2614N in the processing cluster array 2612 can process data that is to be written to any one of the memory units 2624A-2624N in the parallel processor memory 2622. In at least one embodiment, the memory crossbar 2616 can be configured to forward the output of each cluster 2614A-2614N to any partition unit 2620A-2620N or to another cluster 2614A-2614N that can perform further processing operations on the output. In at least one embodiment, each cluster 2614A-2614N can communicate with a memory interface 2618 through the memory crossbar 2616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2616 has connections to memory interface 2618 for communicating with I / O units 2604, as well as connections to local instances of parallel processor memory 2622, allowing processing units in different processing clusters 2614A-2614N to communicate with system memory or other memory not local to parallel processing units 2602. In at least one embodiment, memory crossbar 2616 can use virtual channels to separate traffic streams between clusters 2614A-2614N and partition units 2620A-2620N.

[0323] In at least one embodiment, multiple instances of parallel processing unit 2602 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2602 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2602 or parallel processor 2600 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0324] FIG. 26B is a block diagram of a partition unit 2620 according to at least one embodiment. In at least one embodiment, partition unit 2620 is an instance of one of partition units 2620A-2620N of FIG. 26A. In at least one embodiment, partition unit 2620 includes an L2 cache 2621, a frame buffer interface 2625, and a raster operations unit (ROP) 2626. L2 cache 2621 is a read / write cache configured to execute load and store operations received from memory crossbar 2616 and ROP 2626. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 2621 to frame buffer interface 2625 for processing. In at least one embodiment, updates are also sent to frames via frame buffer interface 2625 for processing. In at least one embodiment, frame buffer interface 2625 interfaces with one of the memory units of a parallel processor memory, such as memory units 2624A-2624N (eg, in parallel processor memory 2622) of FIG.

[0325] In at least one embodiment, ROP2626 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2626 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2626 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. The type of compression performed by ROP2626 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0326] In at least one embodiment, ROP 2626 is included within each processing cluster (e.g., clusters 2614A-2614N of FIG. 26 ) rather than within partition unit 2620. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2616. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2510 of FIG. 25 , may be routed for further processing by processor 2502, or may be routed for further processing by one of the processing entities in parallel processor 2600 of FIG. 26A.

[0327] FIG. 26C is a block diagram of a processing cluster 2614 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 2614A-2614N of FIG. 26. In at least one embodiment, processing cluster 2614 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0328] In at least one embodiment, operation of the processing clusters 2614 may be controlled via a pipeline manager 2632, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2632 receives instructions from the scheduler 2610 of FIG. 26 and manages the execution of those instructions via the graphics multiprocessor 2634 and / or the texture unit 2636. In at least one embodiment, the graphics multiprocessor 2634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing clusters 2614. In at least one embodiment, one or more instances of the graphics multiprocessor 2634 may be included within the processing clusters 2614. In at least one embodiment, the graphics multiprocessor 2634 may process data, and a data crossbar 2640 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2632 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 2640.

[0329] In at least one embodiment, each graphics multiprocessor 2634 in a processing cluster 2614 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0330] In at least one embodiment, instructions sent to processing cluster 2614 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2634. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2634. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2634. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2634, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 2634.

[0331] In at least one embodiment, the graphics multiprocessor 2634 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2634 can forgo the internal cache and use cache memory (e.g., L1 cache 2648) within the processing cluster 2614. In at least one embodiment, each graphics multiprocessor 2634 can also access an L2 cache within a partition unit (e.g., partition units 2620A-2620N in FIG. 26), which may be shared among all processing clusters 2614 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2634 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2602 may be used as global memory. In at least one embodiment, processing cluster 2614 includes multiple instances of graphics multiprocessor 2634 that can share common instructions and data, which may be stored in L1 cache 2648.

[0332] In at least one embodiment, each processing cluster 2614 may include an MMU 2645 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2645 may reside within memory interface 2618 of FIG. 26. In at least one embodiment, MMU 2645 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail) and optionally cache line indices. In at least one embodiment, MMU 2645 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2634 or an L1 cache, or processing cluster 2614. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0333] In at least one embodiment, processing cluster 2614 may be configured such that each graphics multiprocessor 2634 is coupled to a texture unit 2636 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2634 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2634 outputs processed tasks to data crossbar 2640 to provide the processed tasks to another processing cluster 2614 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2616. In at least one embodiment, a pre-ROP 2642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2634 and direct the data to a ROP unit, which may be located within a partition unit (e.g., partition units 2620A-2620N of FIG. 26 ), as described herein. In at least one embodiment, the pre-ROP 2642 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0334] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in graphics processing cluster 2614 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0335] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0336] 26D illustrates a graphics multiprocessor 2634 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2634 couples with a pipeline manager 2632 of a processing cluster 2614. In at least one embodiment, the graphics multiprocessor 2634 has an execution pipeline including, but not limited to, an instruction cache 2652, an instruction unit 2654, an address mapping unit 2656, a register file 2658, one or more general-purpose graphics processing unit (GPGPU) cores 2662, and one or more load / store units 2666. The GPGPU cores 2662 and the load / store units 2666 are coupled to a cache memory 2672 and a shared memory 2670 via a memory and cache interconnect 2668.

[0337] In at least one embodiment, instruction cache 2652 receives a stream of instructions to execute from pipeline manager 2632. In at least one embodiment, instructions are cached in instruction cache 2652 and dispatched for execution by instruction unit 2654. In at least one embodiment, instruction unit 2654 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2662. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2656 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2666.

[0338] In at least one embodiment, register file 2658 provides a set of registers to the functional units of graphics multiprocessor 2634. In at least one embodiment, register file 2658 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2662, load / store unit 2666) of graphics multiprocessor 2634. In at least one embodiment, register file 2658 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2658. In one embodiment, register file 2658 is partitioned among the different warps being executed by graphics multiprocessor 2634.

[0339] In at least one embodiment, the GPGPU cores 2662 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2634. The GPGPU cores 2662 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2662 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 2634 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangular copy or pixel-blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0340] In at least one embodiment, GPGPU core 2662 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may execute in parallel via a single SIMD8 logical unit.

[0341] In at least one embodiment, memory and cache interconnect 2668 is an interconnect network connecting each functional unit of graphics multiprocessor 2634 to register file 2658 and shared memory 2670. In at least one embodiment, memory and cache interconnect 2668 is a crossbar interconnect that allows load / store unit 2666 to implement load and store operations between shared memory 2670 and register file 2658. In at least one embodiment, register file 2658 can operate at the same frequency as GPGPU cores 2662, and therefore data transfers between GPGPU cores 2662 and register file 2658 have very low latency. In at least one embodiment, shared memory 2670 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2634. In at least one embodiment, cache memory 2672 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2636. In at least one embodiment, shared memory 2670 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2662 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2672.

[0342] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0343] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in graphics multiprocessor 2634 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0344] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0345] FIG. 27 illustrates a multi-GPU computing system 2700, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2700 may include a processor 2702 coupled to multiple general-purpose graphics processing units (GPGPUs) 2706A-D via a host interface switch 2704. In at least one embodiment, the host interface switch 2704 is a PCI Express switch device that couples the processor 2702 to a PCI Express bus, via which the processor 2702 can communicate with the GPGPUs 2706A-D. The GPGPUs 2706A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2716. In at least one embodiment, the GPU-to-GPU links 2716 are connected to each of the GPGPUs 2706A-D via dedicated GPU links. In at least one embodiment, P2P GPU link 2716 allows direct communication between each of GPGPUs 2706A-D without requiring communication via host interface bus 2704 to which processor 2702 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 2716, host interface bus 2704 remains available for access to system memory or for communication with other instances of multi-GPU computing system 2700, for example, via one or more network devices. In at least one embodiment, GPGPUs 2706A-D are connected to processor 2702 via host interface switch 2704, and in at least one embodiment, processor 2702 includes direct support for P2P GPU link 2716 and can be directly connected to GPGPUs 2706A-D.

[0346] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, the inference and / or training logic 1315 may be used in the multi-GPU computing system 2700 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0347] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0348] 28 is a block diagram of a graphics processor 2800 according to at least one embodiment. In at least one embodiment, graphics processor 2800 includes a ring interconnect 2802, a pipeline front end 2804, a media engine 2837, and graphics cores 2880A-2880N. In at least one embodiment, ring interconnect 2802 couples graphics processor 2800 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2800 is one of multiple processors integrated within a multi-core processing system.

[0349] In at least one embodiment, graphics processor 2800 receives batches of commands via ring interconnect 2802. In at least one embodiment, the incoming commands are interpreted by command streamer 2803 of pipeline front end 2804. In at least one embodiment, graphics processor 2800 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2880A-2880N. In at least one embodiment, for 3D geometry processing commands, command streamer 2803 supplies the commands to geometry pipeline 2836. In at least one embodiment, for at least some media processing commands, command streamer 2803 supplies the commands to video front end 2834, which is coupled to media engine 2837. In at least one embodiment, the media engine 2837 includes a Video Quality Engine (VQE) 2830 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2833 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2836 and the media engine 2837 each spawn execution threads for thread execution resources provided by at least one graphics core 2880A.

[0350] In at least one embodiment, graphics processor 2800 includes scalable thread execution resources characterized by modular cores 2880A-2880N (sometimes referred to as core slices), each having multiple sub-cores 2850A-2850N, 2860A-2860N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2800 can have any number of graphics cores 2880A-2880N. In at least one embodiment, graphics processor 2800 includes graphics core 2880A having at least a first sub-core 2850A and a second sub-core 2860A. In at least one embodiment, graphics processor 2800 is a low-power processor having a single sub-core (e.g., 2850A). In at least one embodiment, graphics processor 2800 includes multiple graphics cores 2880A-2880N, each including a set of first sub-cores 2850A-2850N and a set of second sub-cores 2860A-2860N. In at least one embodiment, each of first sub-cores 2850A-2850N includes at least a first set of execution units 2852A-2852N and media / texture samplers 2854A-2854N. In at least one embodiment, each of second sub-cores 2860A-2860N includes at least a second set of execution units 2862A-2862N and samplers 2864A-2864N. In at least one embodiment, each sub-core 2850A-2850N, 2860A-2860N shares a set of shared resources 2870A-2870N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0351] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with Figures 13A and / or 13B. In at least one embodiment, inference and / or training logic 1315 may be used in graphics processor 2800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0352] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0353] FIG. 29 is a block diagram illustrating the micro-architecture of a processor 2900 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2900 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2910 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2910 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0354] In at least one embodiment, processor 2900 includes an in-order front end (“front end”) 2901 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2901 may include several units. In at least one embodiment, an instruction prefetcher 2926 fetches instructions from memory and provides the instructions to an instruction decoder 2928, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2928 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2928 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2930 may assemble the decoded uops into program-order sequences, or traces, in uop queue 2934 for execution. In at least one embodiment, when trace cache 2930 encounters a complex instruction, microcode ROM 2932 provides the uops necessary to complete the operation.

[0355] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2928 may access the microcode ROM 2932 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2928. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 2932. In at least one embodiment, the trace cache 2930 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2932, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2932 has finished sequencing micro-ops for an instruction, the machine front end 2901 may resume fetching micro-ops from the trace cache 2930.

[0356] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2903 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 2903 includes, without limitation, allocator / register renamer 2940, memory uop queue 2942, integer / floating point uop queue 2944, memory scheduler 2946, fast scheduler 2902, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2904, and simple floating point scheduler ("simple FP scheduler") 2906. In at least one embodiment, fast scheduler 2902, slow / general purpose floating point scheduler 2904, and simple floating point scheduler 2906 are also collectively referred to herein as "uop schedulers 2902, 2904, 2906." Allocator / register renamer 2940 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2940 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2940 also allocates each uop's entry to one of two uop queues—memory uop queue 2942 for memory operations and integer / floating point uop queue 2944 for non-memory operations—before memory scheduler 2946 and uop schedulers 2902, 2904, 2906. In at least one embodiment, uop schedulers 2902, 2904, 2906 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2902 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2904 and simple floating point scheduler 2906 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2902, 2904, 2906 arbitrate for dispatch ports to schedule uops for execution.

[0357] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 2908, floating point register file / bypass network (“FP register file / bypass network”) 2910, address generation units (“AGUs”) 2912 and 2914, fast arithmetic logic units (ALUs) (“fast ALUs”) 2916 and 2918, slower arithmetic logic unit (“slower ALU”) 2920, floating point ALU (“FP”) 2922, and floating point move unit (“FP move”) 2924. In at least one embodiment, integer register file / bypass network 2908 and floating point register file / bypass network 2910 are also referred to herein as “register files 2908, 2910.” In at least one embodiment, AGUs 2912 and 2914, fast ALUs 2916 and 2918, slow ALU 2920, floating-point ALU 2922, and floating-point move unit 2924 are also referred to herein as "execution units 2912, 2914, 2916, 2918, 2920, 2922, and 2924." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0358] In at least one embodiment, register files 2908, 2910 may be located between uop schedulers 2902, 2904, 2906 and execution units 2912, 2914, 2916, 2918, 2920, 2922, and 2924. In at least one embodiment, integer register file / bypass network 2908 performs integer operations. In at least one embodiment, floating point register file / bypass network 2910 performs floating point operations. In at least one embodiment, each of register files 2908, 2910 may include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 2908, 2910 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2908 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2910 may include, without limitation, 128-bit wide entries.

[0359] In at least one embodiment, execution units 2912, 2914, 2916, 2918, 2920, 2922, and 2924 may execute instructions. In at least one embodiment, register files 2908 and 2910 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2900 may include any number and combination of execution units 2912, 2914, 2916, 2918, 2920, 2922, and 2924, without limitation. In at least one embodiment, floating-point ALU 2922 and floating-point move unit 2924 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2922 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 2916, 2918. In at least one embodiment, the fast ALUs 2916, 2918 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the slow ALU 2920 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, so most complex integer operations proceed to the slow ALU 2920. In at least one embodiment, memory load / store operations may be performed by the ALUs 2912, 2914. In at least one embodiment, fast ALU 2916, fast ALU 2918, and slow ALU 2920 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2916, fast ALU 2918, and slow ALU 2920 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2922 and floating-point move unit 2924 may be implemented to support wide operands having various bit widths.In at least one embodiment, floating-point ALU 2922 and floating-point move unit 2924 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0360] In at least one embodiment, the uop schedulers 2902, 2904, 2906 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2900, the processor 2900 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0361] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0362] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B . In at least one embodiment, some or all of the inference and / or training logic 1315 may be incorporated into the EXE block 2911 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the EXE block 2911. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 2911 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0363] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0364] 30 illustrates a deep learning application processor 3000 according to at least one embodiment. In at least one embodiment, the deep learning application processor 3000 uses instructions that, when executed by the deep learning application processor 3000, cause the deep learning application processor 3000 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 3000 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 3000 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 3000 includes, without limitation, processing clusters 3010(1)-3010(12), inter-chip links (“ICLs”) 3020(1)-3020(12), inter-chip controllers (“ICCs”) 3030(1)-3030(2), high-bandwidth memory second generation (“HBM2”) 3040(1)-3040(4), memory controllers (“Mem Ctrlrs”) 3042(1)-3042(4), high-bandwidth memory physical layers (“HBM The PCI Express 16-lane peripheral component interconnect express port ("PCI Express x16") 3080 includes a management-controller central processing unit ("Management-Controller CPU") 3050, a serial peripheral interface, inter-integrated circuit, and general-purpose input / output block ("SPI, I2C, GPIO") 3060, a peripheral component interconnect express controller and direct memory access block ("PCIe Controller and DMA") 3070, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 3080.

[0365] In at least one embodiment, the processing clusters 3010 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 3010 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 3000 may include any number and types of processing clusters 3000. In at least one embodiment, the inter-chip link 3020 is bidirectional. In at least one embodiment, the inter-chip link 3020 and the inter-chip controller 3030 enable multiple deep learning application processors 3000 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 3000 may include any number and types (including zero) of ICLs 3020 and ICCs 3030.

[0366] In at least one embodiment, the HBM2 3040 provides a total of 32 Gigabytes (GB) of memory. Each HBM2 3040(i) is associated with both a memory controller 3042(i) and an HBM PHY 3044(i). In at least one embodiment, any number of HBM2 3040s may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 3042 and HBM PHYs 3044 (including zero). In at least one embodiment, the SPI, I2C, GPIO 3060, PCIe controller and DMA 3070, and / or PCIe 3080 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0367] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B. In at least one embodiment, the deep learning application processor 3000 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 3000. In at least one embodiment, the deep learning application processor 3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 3000. In at least one embodiment, the processor 3000 may be used to perform one or more neural network use cases described herein.

[0368] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0369] FIG. 31 is a block diagram of a neuromorphic processor 3100, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 3100 receives one or more inputs from sources external to the neuromorphic processor 3100. In at least one embodiment, these inputs may be sent to one or more neurons 3102 within the neuromorphic processor 3100. In at least one embodiment, the neurons 3102 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 3100 may include, without limitation, thousands or millions of instances of neurons 3102, although any suitable number of neurons 3102 may be used. In at least one embodiment, each instance of a neuron 3102 may include a neuron input 3104 and a neuron output 3106. In at least one embodiment, the neuron 3102 may generate an output, which may be sent to an input of another instance of the neuron 3102. For example, in at least one embodiment, neuron input 3104 and neuron output 3106 may be interconnected via synapse 3108 .

[0370] In at least one embodiment, neurons 3102 and synapses 3108 may be interconnected such that neuromorphic processor 3100 operates to process or analyze information received by neuromorphic processor 3100. In at least one embodiment, neuron 3102 may send an output pulse (or "fire" or "spike") when input received via neuron input 3104 exceeds a threshold. In at least one embodiment, neuron 3102 may sum or integrate signals received at neuron input 3104. For example, in at least one embodiment, neuron 3102 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 3102 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 3104 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 3104 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 3102 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 3102 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron 3106 when the result of applying the transfer function to neuron 3104 exceeds a threshold. In at least one embodiment, neuron 3102 may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value, once it fires.In at least one embodiment, once the membrane potential is reset to zero, neuron 3102 may resume normal operation after a suitable period (or refractory period).

[0371] In at least one embodiment, neurons 3102 may be interconnected through synapses 3108. In at least one embodiment, synapses 3108 may operate to transmit a signal from an output of a first neuron 3102 to an input of a second neuron 3102. In at least one embodiment, neurons 3102 may transmit information through two or more instances of synapses 3108. In at least one embodiment, one or more instances of neuron outputs 3106 may be connected to instances of neuron inputs 3104 of the same neuron 3102 through instances of synapses 3108. In at least one embodiment, an instance of neuron 3102 that generates an output to be transmitted through an instance of synapse 3108 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 3108. In at least one embodiment, an instance of neuron 3102 that receives an input to be transmitted through an instance of synapse 3108 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 3108. In at least one embodiment, an instance of neuron 3102 may receive input from one or more instances of synapse 3108 and may send output through one or more instances of synapse 3108, so a single instance of neuron 3102 may therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 3108.

[0372] In at least one embodiment, neurons 3102 may be organized into one or more layers. Each instance of a neuron 3102 may have one neuron output 3106 that can fan out to one or more neuron inputs 3104 through one or more synapses 3108. In at least one embodiment, a neuron output 3106 of a neuron 3102 in a first layer 3110 may be connected to a neuron input 3104 of a neuron 3102 in a second layer 3112. In at least one embodiment, layer 3110 may be referred to as a "feed-forward" layer. In at least one embodiment, each instance of a neuron 3102 in an instance of a first layer 3110 may fan out to each instance of a neuron 3102 in a second layer 3112. In at least one embodiment, first layer 3110 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 3102 in the second layer 3112 may fan out to fewer than all instances of a neuron 3102 in the third layer 3114. In at least one embodiment, the second layer 3112 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, the neurons 3102 in the second layer 3112 may fan out to neurons 3102 in multiple other layers, including neurons 3102 in the same second layer 3112. In at least one embodiment, the second layer 3112 may be referred to as a "recurrent layer." The neuromorphic processor 3100 may include any suitable combination of recurrent and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0373] In at least one embodiment, neuromorphic processor 3100 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting synapses 3108 to neurons 3102. In at least one embodiment, neuromorphic processor 3100 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 3102 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, synapses 3108 may be connected to neurons 3102 using an interconnect fabric such as a network-on-chip or using dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0374] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0375] 32 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 3200 includes one or more processors 3202 and one or more graphics processors 3208 and may be a single-processor desktop system, a multi-processor workstation system, or a server system with multiple processors 3202 or processor cores 3207. In at least one embodiment, system 3200 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0376] In at least one embodiment, system 3200 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 3200 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 3200 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 3200 is a television or set-top box device having one or more processors 3202 and a graphical interface generated by one or more graphics processors 3208.

[0377] In at least one embodiment, the one or more processors 3202 each include one or more processor cores 3207 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 3207 is configured to process a particular instruction set 3209. In at least one embodiment, the instruction set 3209 may facilitate computing via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, each processor core 3207 may process a different instruction set 3209, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 3207 may also include other processing devices, such as a digital signal processor (DSP).

[0378] In at least one embodiment, processor 3202 includes cache memory 3204. In at least one embodiment, processor 3202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 3202. In at least one embodiment, processor 3202 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown), which may be shared among processor cores 3207 using known cache coherence techniques. In at least one embodiment, processor 3202 further includes a register file 3206, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 3206 may include general-purpose registers or other registers.

[0379] In at least one embodiment, the one or more processors 3202 are coupled to one or more interface buses 3210 to transmit communication signals, such as address, data, or control signals, between the processor 3202 and other components in the system 3200. In at least one embodiment, the interface bus 3210 may be a processor bus, such as, in one embodiment, a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 3210 is not limited to a DMI bus, but may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 3202 includes an integrated memory controller 3216 and a platform controller hub 3230. In at least one embodiment, the memory controller 3216 facilitates communication between memory devices and other components of the system 3200, while the platform controller hub (PCH) 3230 provides connectivity to I / O devices via a local I / O bus.

[0380] In at least one embodiment, memory device 3220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, memory device 3220 may operate as system memory for system 3200, storing data 3222 and instructions 3221 for use by one or more processors 3202 when executing applications or processes. In at least one embodiment, memory controller 3216 also couples to an optional external graphics processor 3212, which may communicate with one or more graphics processors 3208 within processor 3202 to perform graphics and media operations. In at least one embodiment, a display device 3211 may be connected to processor 3202. In at least one embodiment, display device 3211 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., display port, etc.). In at least one embodiment, display device 3211 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0381] In at least one embodiment, platform controller hub 3230 allows peripheral devices to connect to memory device 3220 and processor 3202 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 3246, a network controller 3234, a firmware interface 3228, a wireless transceiver 3226, a touch sensor 3225, and a data storage device 3224 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 3224 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensor 3225 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 3226 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 3228 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 3234 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 3210. In at least one embodiment, audio controller 3246 is a multi-channel high-definition audio controller. In at least one embodiment, system 3200 includes an optional legacy I / O controller 3240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.In at least one embodiment, platform controller hub 3230 can also connect to one or more universal serial bus (USB) controller 3242 connected input devices, such as a keyboard and mouse 3243 combination, a camera 3244, or other USB input devices.

[0382] In at least one embodiment, instances of memory controller 3216 and platform controller hub 3230 may be integrated into a separate external graphics processor, such as external graphics processor 3212. In at least one embodiment, platform controller hub 3230 and / or memory controller 3216 may be external to one or more processors 3202. For example, in at least one embodiment, system 3200 may include an external memory controller 3216 and platform controller hub 3230, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with processor 3202.

[0383] Inference and / or training logic 1315 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1315 are provided herein in conjunction with FIG. 13A and / or FIG. 13B . In at least one embodiment, some or all of inference and / or training logic 1315 may be incorporated into graphics processor 3200. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in pipeline 3212. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 13A or FIG. 13B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 3200 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0384] The techniques described above may be used, for example, to implement a system for performing object exchange between a human and a robot. Some examples use inference and / or training logic to create a neural network trained to generate a grasp of an object held by a human hand, as described above.

[0385] 33 is a block diagram of a processor 3300 having one or more processor cores 3302A-3302N, an integrated memory controller 3314, and an integrated graphics processor 3308, according to at least one embodiment. In at least one embodiment, processor 3300 may include a smaller number of additional cores, including additional core 3302N, represented by a dashed box. In at least one embodiment, each of processor cores 3302A-3302N includes one or more internal cache units 3304A-3304N. In at least one embodiment, each processor core also has access to one or more shared cache units 3306.

[0386] In at least one embodiment, the internal cache units 3304A-3304N and the shared cache unit 3306 represent a cache memory hierarchy within the processor 3300. In at least one embodiment, the cache memory units 3304A-3304N may include at least one level of instruction and data cache within...

Claims

1. Generate a point cloud from images of a hand holding an object, identifying a first portion of the point cloud that represents the object; determining a pose of the object from a first portion of the point cloud; identifying a second portion of the cloud of points representing the hand; classifying a second portion of the point cloud as one of a plurality of discretized hand pose categories; determining a pose of the hand from a second portion of the classified points; generating a set of grasping poses that enable the robot to grasp the object; selecting a target grasp posture from the set of grasp postures that does not interfere with the hand based at least in part on the posture of the hand; causing the robot to perform the target grasping posture. A processor comprising one or more computers comprising one or more processors for

2. The processor of claim 1 , wherein the pose of the hand identifies a number of segments and joint angles.

3. the image is a three-dimensional image acquired from a depth camera; The processor of claim 1 , wherein the one or more processors generate the point cloud from the three-dimensional image.

4. the set of gripping poses are poses for a robot gripper of the robot; The processor of claim 1 , wherein the robotic gripper has two opposing fingers that perform the gripping.

5. The processor of claim 1 , wherein the pose of the object includes three angles that indicate an orientation of the object and information identifying a position of the object.

6. The processor of claim 1 , wherein the robot picks up the object from the hand.

7. 1. A system comprising one or more processors coupled to a computer readable medium, comprising: The computer-readable medium, when executed by the one or more processors, provides the system with: identifying an object from a three-dimensional image of an appendage holding the object and determining a pose of the identified object; identifying the appendage from the three-dimensional image, classifying the identified appendage as one of a plurality of discretized appendage pose categories, and determining a pose of the appendage from the classified appendage; determining a set of gripping poses that enable a robotic gripper to grip the object; selecting a gripping posture from the set of gripping postures that does not interfere with the appendage; and Executing the gripping position. A system storing executable instructions to cause a

8. The system of claim 7 , wherein the three-dimensional image is generated from a depth camera, a radar image, a LIDAR image, or a three-dimensional medical imaging device.

9. The executable instructions, as a result of being executed by the one or more processors, further provide the system with: generating a point cloud from the three-dimensional image; Let them do so, Identifying the appendage from the three-dimensional image comprises identifying a first portion of the point cloud that represents the appendage; The system of claim 7 , wherein identifying the object from the three-dimensional image comprises identifying a second portion of the point cloud that represents the object.

10. The executable instructions, as a result of being executed by the one or more processors, further provide the system with: providing the determined object pose and the determined appendage pose to a trained model that outputs the grasp pose. The system of claim 7 .

11. The system of claim 10 , wherein the trained model is trained by providing ground truth data including point cloud information and corresponding grasp poses.

12. The system of claim 7 , wherein the gripping pose is determined to interfere with the appendage if the robotic gripper is predicted to contact the appendage while performing the gripping pose.

13. When executed by one or more processors, the one or more processors are caused to at least: Obtaining a three-dimensional image of the appendage holding the object; generating a 3D model from the three-dimensional image; identifying a first portion of the 3D model representing the object; determining a pose of the object from a first portion of the 3D model; identifying a second portion of the 3D model representing the appendage; classifying a second portion of the 3D model as one of a plurality of discretized appendage pose categories; determining a pose of the appendage from a second portion of the classified 3D model; providing the determined object pose and the determined appendage pose to a trained network that generates a gripping pose for a robotic gripper that can grip the object without contacting the appendages; and causing the robot gripper to perform the gripping posture. A machine-readable medium having stored thereon a set of instructions that cause a

14. 14. The machine-readable medium of claim 13, wherein the trained network is trained at least in part by providing the trained network with training data including a colored 3D model of an appendage holding an object and a proposed grasp for the robotic gripper such that the robotic gripper can receive the object from the appendage without contacting the appendage.

15. The training data includes at least Generating a dataset of human object handovers; and Annotating the dataset with ground truth hand poses and ground truth object poses.

15. The machine-readable storage medium of claim 14, generated by:

16. the grasp pose is based, at least in part, on the determined object pose and the determined appendage pose; The machine-readable storage medium of claim 13 , wherein the grasp pose is determined as a grasp that results in successful grasping of the object without contacting the appendage.

17. 14. The machine-readable storage medium of claim 13, wherein the trained network is trained using images of the appendages bearing different object types.

18. 1. A processor comprising one or more arithmetic logic units (ALUs) for training one or more neural networks to generate gripping poses for a robotic gripper that can receive an object from an appendage without interfering with the appendage holding the object, the processor comprising: generating a 3D model from the three-dimensional image of the appendage holding the object; identifying a first portion of the 3D model representing the object; determining a pose of the object from a first portion of the 3D model; identifying a second portion of the 3D model representing the appendage; classifying a second portion of the 3D model as one of a plurality of discretized appendage pose categories; determining a pose of the appendage from a second portion of the classified 3D model; providing the determined object pose and the determined appendage pose to the one or more neural networks to generate a gripping pose for the robotic gripper; causing the robot gripper to perform the gripping posture Processor for.

19. The training data is at least Generating a dataset of human object handovers; and Annotating the dataset with ground truth hand poses and ground truth object poses.

20. The processor of claim 18, wherein the processor is generated by:

20. 20. The processor of claim 18, wherein the one or more neural networks are trained at least in part by providing the one or more neural networks with training data including a colored 3D model of an appendage holding an object and a proposed grasp for the robotic gripper such that the robotic gripper can receive the object from the appendage without interfering with the appendage.

21. The processor of claim 18 , wherein the 3D model is a point cloud.

22. 20. The processor of claim 18, wherein the appendage is a human hand, a robotic gripper or hand, a part of an animal, or a human leg or arm.

Images