Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory in Deep Learning Artificial Neural Networks

Abstract

To provide a tandem row decoder for controlling word lines and control gate lines coupled to rows of nonvolatile memory cells in an array.SOLUTION: A tandem row decoder includes a word line decoder 5201 and a control gate decoder 5202. The tandem row decoder shows reduced leakage current on a word line WL0 and a control gate line CG0 when the tandem row decoder is not enabled.SELECTED DRAWING: Figure 52

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 033,953, filed June 3, 2020, entitled "Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory in Deep Learning Artificial Neural Network," and U.S. Patent Application No. 17 / 104,385, filed November 25, 2020, entitled "Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory in Deep Learning Artificial Neural Network."

[0002] FIELD OF THEINVENTION Various embodiments of a tandem row decoder are disclosed. Each embodiment of the tandem row decoder comprises a word line decoder and a control gate decoder cross-coupled to the word line decoder. The tandem row decoder exhibits little or no leakage current on the word lines or control gate lines when the tandem row decoder is not enabled. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the output of the neural network. At each level, the neurons make decisions individually or collectively based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. <Non-volatile memory cells>

[0007] Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline terminal 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electronic current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0011] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0012] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to those of Figure 2.

[0013] FIG. 4 shows a four-gate memory cell 410 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0014] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0015] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0016] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (where erasure occurs through the use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0017] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0018] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a wordline) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as previously described for memory cell 210.

[0019] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. [Table 4]

[0020] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0021] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0022] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be very precisely and individually tunable, making the memory array ideal for storage and fine tuning adjustments to the synaptic weights of neural networks.

[0023] The methods and means described herein can be applied to other non-volatile memory technologies such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable) and CeRAM (correlated electron ram). The methods and means described herein can be applied to, but not limited to, SRAM, DRAM, and volatile memory technologies used in neural networks such as volatile synapse cells. <Neural network using non-volatile memory cell array>

[0024] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiment. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0025] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0026] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify square edges, or the aspect ratio of a particular feature, etc.

[0027] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0028] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0029] 9 is a block diagram of a system that can be used for that purpose. A vector-by-matrix multiplication (VMM) system 32 includes non-volatile memory cells and is used as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes a VMM array 33 including non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37 that decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0030] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, it effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with on-the-fly memory computation.

[0031] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0032] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (which receive input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and the activation function circuit 39 constitute a number of neurons.

[0033] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0034] FIG. 10 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, an input, labeled Inputx, is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog to analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulses (D / P) converter to convert an external digital input to a mapped digital pulse to the input VMM system 32a.

[0035] The output generated by the input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to the next input VMM system (hidden level 2) 32c, and so on. The various layers of the VMM systems 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or the multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or the multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory system. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed to various portions of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. <VMMアレイ>

[0036] 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array could be located at the bottom.

[0037] In the VMM array 1100, control gate lines such as control gate line 1103 run vertically (so that row-wise reference array 1102 is orthogonal to control gate line 1103) and erase gate lines such as erase gate line 1104 run horizontally. Here, inputs to the VMM array 1100 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0038] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0039] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L). * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0040] If an IV log converter is used to convert the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor, then Vg is: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0041] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w for each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth = Vth0 + gamma (SQRT | Vsb - 2 * ΦF)-SQRT|2 * ΦF|) where Vth0 is the threshold voltage with zero substrate bias, ΦF is the surface potential, and gamma is the body effect parameter.

[0042] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0043] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta=u * Cox * Wt / L Therefore, W α (Vgs−Vth), that is, the weight W in the linear region, is proportional to (Vgs−Vth).

[0044] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0045] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0046] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 ; beta=u * Cox * Wt / L Therefore, W α (Vgs-Vth) 2 That is, the weight W in the saturation region is (Vgs-Vth) 2 is proportional to.

[0047] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0048] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation).

[0049] Other embodiments for the VMM array 32 of Figure 9 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0050] FIG. 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cells 210 shown in FIG. 2 and is used as a synapse between an input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 arranged in the columns of the array function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only a portion of which is shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0051] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. With the memory array 1203 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and is also power efficient. Here, voltage inputs are provided to the word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0-BLN during read (inference) operations. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0052] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate the operations of read, erase, and program. [Table 5]

[0053] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 run in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0054] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. [Table 6]

[0055] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1412 includes a respective multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on the bit line (e.g., BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0056] The memory array 1403 serves two purposes. First, it stores the weights used by the VMM array 1400. Second, it multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1401 and 1402 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory cell array, and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current applied to each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0057] The VMM array 1400 implements one-way tuning of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (in which case an incorrect value is stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0058] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. [Table 7]

[0059] FIG. 15 shows a neuron VMM array 1500, which is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of synapses and neurons between the input layer and the next layer. The VMM array 1500 comprises a memory array 1503 of non-volatile memory cells, a reference array 1501 or a first non-volatile reference memory cell, and a reference array 1502 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1514) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0060] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. [Table 8]

[0061] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2400, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0062] 25 illustrates a neuron VMM array 2500 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0063] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0064] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT Nare bit lines BL0, ..., BL N is generated.

[0065] 28 shows a neuron VMM array 2800 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0066] 29 shows a neuron VMM array 2900 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N , 2901-(N-1) and 2901-N, which are respectively coupled to bit line control gates 2901-1, 2901-2, ..., 2901-(N-1) and 2901-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0067] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N are generated respectively.

[0068] 31 shows a neuron VMM array 3100 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0069] 32 shows a neuron VMM array 3200 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. Long and short term memory

[0070] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0071] FIG. 16 illustrates an exemplary LSTM 1600. The LSTM 1600 in this example includes cells 1601, 1602, 1603, and 1604. Cell 1601 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1602 receives an input vector x1, an output vector (hidden state) h0 from cell 1601, and a cell state c0 from cell 1601, and generates an output vector h1 and a cell state vector c1. Cell 1603 receives an input vector x2, an output vector (hidden state) h1 from cell 1602, and a cell state c1 from cell 1602, and generates an output vector h2 and a cell state vector c2. Cell 1604 receives an input vector x3, an output vector (hidden state) h2 from cell 1603, and a cell state c2 from cell 1603, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0072] Figure 17 shows an example implementation of an LSTM cell 1700 that can be used for cells 1601, 1602, 1603, and 1604 in Figure 16. The LSTM cell 1700 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0073] LSTM cell 1700 includes sigmoid function devices 1701, 1702, and 1703, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1700 also includes tanh devices 1704 and 1705 for applying a hyperbolic tangent function to the input vector, multiplier devices 1706, 1707, and 1708 for multiplying two vectors, and adder device 1709 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0074] FIG. 18 shows an example of an implementation of the LSTM cell 1700, the LSTM cell 1800. For the convenience of the reader, the same numbering scheme from the LSTM cell 1700 is used in the LSTM cell 1800. The sigmoid function devices 1701, 1702, and 1703, and the tanh device 1704 each include a plurality of VMM arrays 1801 and activation circuit blocks 1802. Thus, the VMM array proves to be particularly useful in the LSTM cell used in certain neural network systems. The multiplier devices 1706, 1707, and 1708, and the adder device 1709 are implemented in a digital or analog manner. The activation function block 1802 can be implemented in a digital or analog manner.

[0075] An alternative example of LSTM cell 1800 (and another example of one implementation of LSTM cell 1700) is shown in Figure 19. In Figure 19, sigmoid function devices 1701, 1702, and 1703, and tanh device 1704 share the same physical hardware (VMM array 1901 and activation function block 1902) in a time-multiplexed manner. LSTM cell 1900 also includes a multiplier device 1903 for multiplying two vectors, an adder device 1908 for adding two vectors, a tanh device 1705 (which includes activation circuit block 1902), a register 1907 for storing the value i(t) as it is output from sigmoid function block 1902, and a register 1908 for storing the value f(t). * a register 1904 for storing c(t-1) as that value is output from the multiplier device 1903 via a multiplexer 1910; * A register 1905 for storing u(t) as its value is output from the multiplier device 1903 via a multiplexer 1910; and a value o(t). * It includes a register 1906 for storing {tilde over (c)}(t) as its value is output from the multiplier device 1903 via a multiplexer 1910, and a multiplexer 1909.

[0076] Whereas LSTM cell 1800 includes multiple sets of VMM arrays 1801 and respective activation function blocks 1802, LSTM cell 1900 includes only one set of VMM arrays 1901 and activation function blocks 1902, which are used to represent multiple layers in embodiments of LSTM cell 1900. LSTM cell 1900 requires less space than LSTM 1800, as it requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1800.

[0077] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. <Gated Recurrent Unit>

[0078] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0079] 20 illustrates an exemplary GRU 2000. The GRU 2000 in this example includes cells 2001, 2002, 2003, and 2004. Cell 2001 receives an input vector x0 and generates an output vector h0. Cell 2002 receives an input vector x1 and an output vector h0 from cell 2001 and generates an output vector h1. Cell 2003 receives an input vector x2 and an output vector (hidden state) h1 from cell 2002 and generates an output vector h2. Cell 2004 receives an input vector x3 and an output vector (hidden state) h2 from cell 2003 and generates an output vector h3. Additional cells can be used, and a GRU with four cells is merely an example.

[0080] FIG. 21 illustrates an exemplary implementation of a GRU cell 2100 that can be used for cells 2001, 2002, 2003, and 2004 of FIG. 20. The GRU cell 2100 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell, and generates an output vector h(t). The GRU cell 2100 includes sigmoid function devices 2101 and 2102, each of which applies a number between 0 and 1 to the output vector h(t-1) and a component from the input vector x(t). The GRU cell 2100 also includes a tanh device 2103 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 2104, 2105, and 2106 for multiplying two vectors, an adder device 2107 for adding the two vectors, and a complementary device 2108 for subtracting the input from 1 to generate an output.

[0081] FIG. 22 shows a GRU cell 2200, which is an example of one implementation of the GRU cell 2100. For the convenience of the reader, the same numbering method from the GRU cell 2100 is used in the GRU cell 2200. As can be seen from FIG. 22, the sigmoid function devices 2101 and 2102 and the tanh device 2103 each include a plurality of VMM arrays 2201 and activation function blocks 2202. Therefore, it can be seen that the VMM array is particularly used in the GRU cell used in a specific neural network system. The multiplier devices 2104, 2105, 2106, the adder device 2107, and the complementary device 2108 are implemented in a digital or analog manner. The activation function block 2202 can be implemented in a digital or analog manner.

[0082] An alternative example of GRU cell 2200 (and another example of one implementation of GRU cell 2300) is shown in FIG. 23. In FIG. 23, GRU cell 2300 utilizes a VMM array 2301 and an activation function block 2302, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In FIG. 23, sigmoid function devices 2101 and 2102, and tanh device 2103 share the same physical hardware (VMM array 2301 and activation function block 2302) in a time-multiplexed manner. GRU cell 2300 also includes a multiplier device 2303 for multiplying two vectors together, an adder device 2305 for adding two vectors together, a complement device 2309 for subtracting the input from 1 to generate the output, a multiplexer 2304, and a value h(t-1) * A register 2306 for holding r(t) as its value is output from the multiplier device 2303 via multiplexer 2304, and a value h(t-1) * A register 2307 for holding z(t) as its value is output from the multiplier device 2303 via multiplexer 2304, and a register 2308 for holding the value ĥ(t) *and a register 2308 for holding (1-z((t)) as its value is output from the multiplier device 2303 via the multiplexer 2304.

[0083] Whereas GRU cell 2200 includes multiple sets of VMM arrays 2201 and activation function blocks 2202, GRU cell 2300 includes only one set of VMM arrays 2301 and activation function blocks 2302, which are used to represent multiple tiers in an embodiment of GRU cell 2300. GRU cell 2300 requires less space than GRU cell 2200, as it requires ⅓ of the space for the VMM and activation function blocks compared to GRU cell 2200.

[0084] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient.

[0085] The input to the VMM array can be analog levels, binary levels, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the output can be analog levels, binary levels, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0086] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, or by a differential cell, or by two blended memory cells (average of two cells). In the case of differential cells, two memory cells are required to implement weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement weight W as an average of two cells.

[0087] Each non-volatile memory cell used in an analog neural memory system must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] One challenge in a vector matrix multiplication (VMM) system is the ability to select specific cells or groups of cells, or possibly entire arrays of cells, for erase, programming, and read operations. A related challenge is reducing, and preferably minimizing, leakage in each cell, as leakage can adversely affect the accuracy of the system.

[0089] What is needed is an improved decoding system that reduces, and preferably minimizes, leakage during read operations of non-volatile memory cells in analog neural memory systems. Summary of the Invention

[0090] An improved decoding system is disclosed that reduces leakage during read operations for analog neural network systems that utilize non-volatile memory cells.

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[0145] [Brief description of the drawings]

[0146] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 9] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 15] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 16] 1 shows a prior art long-short-term memory system. [Figure 17] An exemplary cell for use in the long- and short-term memory system is shown. [Figure 18] 18 illustrates an embodiment of the exemplary cell of FIG. 17. [Figure 19] 18 illustrates an alternative embodiment of the exemplary cell of FIG. 17. [Figure 20] 1 shows a prior art gated recurrent unit system. [Figure 21]1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 22] 22 illustrates an embodiment of the exemplary cell of FIG. 21. [Figure 23] 22 illustrates an alternative embodiment of the exemplary cell of FIG. 21. [Figure 24] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 25] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 26] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 27] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 28] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 29] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 30] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 31] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 32] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 33] 1 illustrates an example block diagram of a vector matrix multiplication system. [Diagram 34] 1 illustrates an exemplary decoding embodiment of a vector matrix multiplication system. [Diagram 35] 4 illustrates another exemplary decoding embodiment of a vector matrix multiplication system. [Diagram 36] 1 illustrates an exemplary row decoder. [Figure 37] 4 illustrates another exemplary decoding embodiment of a vector matrix multiplication system. [Figure 38] 4 illustrates another exemplary decoding embodiment of a vector matrix multiplication system. [Figure 39] 4 illustrates another exemplary decoding embodiment of a vector matrix multiplication system. [Diagram 40] 1 illustrates one embodiment of a low voltage row decoder. [Diagram 41] 1 illustrates one embodiment of a combined low voltage row decoder and control gate decoder. [Diagram 42] 1 illustrates one embodiment of a bit line decoder. [Diagram 43] 1 shows a vector matrix multiplication system and an input block. [Diagram 44] A multiplexer is shown for receiving outputs from an array and providing inputs to one or more arrays in a multiplexed format. [Figure 45A] 1 illustrates an example layout of a vector matrix multiplication system. [Figure 45B] 1 illustrates an example layout of a vector matrix multiplication system. [Diagram 46] 1 illustrates an example layout of a vector matrix multiplication system. [Figure 47] 1 shows a word line decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix. [Figure 48] 1 shows an erasure gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix. [Figure 49] 13 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 50] 13 illustrates another embodiment of a word line driver for use with a vector multiplier matrix. [Figure 51A] 4 illustrates another exemplary decoding embodiment of a vector matrix multiplication system. [Figure 51B] 4 illustrates yet another exemplary decoding embodiment of a vector matrix multiplication system. [Figure 52] 1 illustrates an embodiment of a tandem decoder. [Figure 53] 4 illustrates another embodiment of a tandem decoder. [Figure 54] 4 illustrates another embodiment of a tandem decoder. [Figure 55] 4 illustrates another embodiment of a tandem decoder.

Best Mode for Carrying Out the Invention

[0147] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. <Embodiments of a Decoding System and Physical Layout for a VMM Array>

[0148] Figures 33 to 51 disclose various decoding systems and physical layouts for a VMM array that can be used with respect to Figures 2 to 7 or with any of the types of memory cells described above with respect to other non-volatile memory cells.

[0149] Figure 33 shows a VMM system 3300. The VMM system 3300 includes a VMM array 3301 (which can be based on any of the foregoing VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM designs), a low-voltage row decoder 3302, a high-voltage row decoder 3303, a column decoder 3304, a column driver 3305, control logic 3306, a bias circuit 3307, a neuron output circuit block 3308, an input VMM circuit block 3309, an algorithm controller 3310, a high-voltage generation device block 3311, an analog circuit block 3315, and control logic 3316.

[0150] The input circuit block 3309 serves as an interface from an external input to the input terminal of the memory array 3301. The input circuit block 3309 may include, without limitation, a digital-to-analog converter (DAC), a digital-to-pulse converter (DPC), an analog-to-pulse converter (APC), a current-to-voltage converter (IVC), an analog-to-analog converter such as voltage to voltage scaler (AAC), or a frequency-to-analog converter (FAC). The neuron output block 3308 serves as an interface from the memory array output to an external interface (not shown). The neuron output block 3308 may include, without limitation, an ADC (analog-to-digital converter), an APC (analog-to-pulse converter), a DPC (digital-to-pulse converter), an IVC (current-to-voltage converter), or an IFC (current-to-frequency converter). The neuron output block 3308 may include, without limitation, an activation function, a normalization circuit, and / or a rescaling circuit.

[0151] The low voltage row decoder 3302 provides bias voltages for read and program operations, and provides decoded signals to the high voltage row decoder 3303. The high voltage row decoder 3303 provides high voltage bias signals for program and erase operations.

[0152] Algorithm controller 3310 provides control of the bit lines during program, verify, and erase operations.

[0153] The high voltage generator block 3311 includes a charge pump 3312, a charge pump regulator 3313, and a high voltage generation circuit 3314, which provide multiple voltages required for various program, erase, program verify, and read operations.

[0154] FIG. 34 illustrates a VMM system 3400 that is particularly suitable for use with memory cells of the type shown in FIG. VMM system 3400 includes VMM arrays 3401, 3402, 3402, and 3404 (which may each be based on any of the previously described VMM array designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, and 31000, or other VMM array designs), low voltage row decoders 3405, 3406, 3407, and 3408, a shared high voltage row decoder 3409, word lines or word input lines 3411, 3412, 3413, and 3414, bit lines 3421, 3422, 3423, and 3424, control gate lines 3432, source lines 3434, and erase gate lines 3434. A shared high voltage row decoder 3409 provides the control gate lines 3432, source lines 3434, and erase gate lines 3436. In this configuration, the word lines 3411, 3412, 3413, and 3414, and the bit lines 3421, 3422, 3423, and 3424 are parallel to one another. In one embodiment, the word lines and bit lines are arranged vertically. The control gate lines 3432, source lines 3434, and erase gate lines 3436 are parallel to one another and arranged horizontally, and thus perpendicular to the word lines or word input lines 3411, 3412, 3413, and 3414, and the bit lines 3421, 3422, 3423, and 3424.

[0155] In VMM system 3400, VMM arrays 3401, 3402, 3403, and 3404 share control gate lines 3432, source line lines 3434, erase gate lines 3436, and high voltage row decoder 3409. However, each of the arrays has its own low voltage row decoder, such that low voltage row decoder 3405 is used with VMM array 3401, low voltage row decoder 3406 is used with VMM array 3402, low voltage row decoder 3407 is used with VMM array 3403, and low voltage row decoder 3408 is used with VMM array 3404. The advantage of this configuration is that word lines 3411, 3412, 3413, and 3414 are arranged vertically such that word line 3411 can be routed only to VMM array 3401, word line 3412 can be routed only to VMM array 3402, word line 3413 can be routed only to VMM array 3403, and word line 3414 can be routed only to VMM array 3404. This would be very inefficient in a conventional layout where the word lines are arranged horizontally with multiple VMM arrays sharing the same high voltage decoder and the same high voltage decode lines.

[0156] Figure 35 shows a VMM system 3500 that is particularly suitable for use with memory cells of the type shown in Figure 4 as memory cell 410. VMM system 3500 is similar to VMM system 3300 of Figure 33, except that VMM system 3500 includes separate word lines and low voltage row decoders for read and programming operations.

[0157] VMM system 3500 includes VMM arrays 3501, 3502, 3503, and 3504 (which may be based on any of the VMM designs previously described, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), low voltage read row decoders, and low voltage read row decoders. 3, the memory cell 3500 includes three memory cell arrays 3505, 3506, 3507, and 3508, a shared low voltage program row decoder 3530, a shared high voltage row decoder 3509, read word lines or word input lines 3511, 3512, 3513, and 3514, a program pre-decode row line 3515, bit lines 3521, 3522, 3523, and 3524, a control gate line 3532, a source line 3533, and an erase gate line 3535. The shared high voltage row decoder 3509 provides the control gate line 3532, the source line 3533, and the erase gate line 3535. In this layout, the read word lines or word input lines 3511, 3512, 3513, and 3514, the program pre-decode row line 3515, and the bit lines 3521, 3522, 3523, and 3524 are parallel to one another and are arranged vertically. The control gate lines 3532, source lines 3533, and erase gate lines 3535 are parallel to one another and arranged horizontally and therefore perpendicular to the read word lines or word input lines 3511, 3512, 3513, and 3514, the program pre-decode row lines 3515, and the bit lines 3521, 3522, 3523, and 3524. In this VMM system 3500, a low voltage program row decoder 3530 is shared across multiple VMM arrays.

[0158] In VMM system 3500, VMM arrays 3501, 3502, 3503, and 3504 share control gate lines 3532, source lines 3533, erase gate lines 3535, and high voltage row decoder 3509. However, each of the VMM arrays has its own low voltage read row decoder, such that low voltage read row decoder 3505 is used with VMM array 3501, low voltage read row decoder 3506 is used with VMM array 3502, low voltage read row decoder 3507 is used with VMM array 3503, and low voltage read row decoder 3508 is used with VMM array 3504. The advantage of this layout is that the read word lines or word input lines 3511, 3512, 3513, and 3514 are arranged vertically such that word line 3511 can be routed only to VMM array 3501, word line 3512 can be routed only to VMM array 3502, word line 3513 can be routed only to VMM array 3503, and word line 3514 can be routed only to VMM array 3504. This would be very inefficient in a conventional layout where the word lines are arranged horizontally for multiple arrays sharing the same high voltage decoder and the same high voltage decode lines. In particular, the program pre-decode row line 3515 can be connected to any of the VMM arrays 3501, 3502, 3503, and 3504 through the low voltage program row decoder 3530, so that the cells of one or more of those VMM arrays can be programmed at once.

[0159] 36 shows further details regarding certain aspects of VMM system 3500, particularly low voltage row decoders 3505, 3506, 3507, and 3508, illustrated as low voltage row decoder 3600. Low voltage read row decoder 3600 comprises a number of switches, such as the exemplary switches shown for selectively coupling rows and word lines of cells in VMM arrays 3601, 3602, 3603, and 3604, respectively. Low voltage program decoder 3630 includes exemplary NAND gates 3631 and 3632, PMOS transistors 3633 and 3635, and NMOS transistors 3636 and 3636, configured as shown. NAND gates 3631 and 3632 receive program pre-decoded row line XP 3615 as an input. During a program operation, the switches Sp (which may be CMOS multiplexers or another type of switch) in the low voltage read row decoders 3605, 3606, and 3608 are closed, so that the program word lines Wlp0-n are coupled to the word lines in the array to apply a voltage for programming. During a read operation, the read word lines or word input lines 3611, 3612, 3613, and 3614 are selectively coupled to apply a voltage to the word line terminals of rows in one or more of the arrays 3601, 3602, 3603, and 3604 using the Sr switches (which may be CMOS multiplexers or another type of switch) in the low voltage read row decoders 3605, 3606, 3607, and 3608 (which are closed).

[0160] FIG. 37 illustrates a VMM system 3700 that is particularly suitable for use with memory cells of the type shown in FIG. VMM system 3700 includes VMM arrays 3701, 3702, 3703, and 3704 (which may be based on any of the VMM designs previously discussed, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, and 3100, respectively, or other VMM array designs), low voltage row decoders 3705, 3706, 3707, and 3708, local high voltage row decoders 3709 and 3710 and global high voltage row decoder 3730, word lines 3711, 3712, 3713, and 3714, bit lines 3721, 3722, 3723, and 3724, high voltage and / or low voltage 37. The shared global high voltage row decoder 3730 provides the HV / LV pre-decode lines 3732, the source line lines 3733, and the erase gate lines 3734. In this layout, the word lines 3711, 3712, 3713, and 3714, and the bit lines 3721, 3722, 3723, and 3724 are parallel to each other and arranged vertically. The HV / LV pre-decode lines 3732, the source line lines 3733, and the erase gate lines 3734 are parallel to each other and arranged horizontally and therefore perpendicular to the word lines 3711, 3712, 3713, and 3714, and the bit lines 3721, 3722, 3723, and 3724. HV / LV pre-decoded lines 3732 are input to local high voltage decoders 3709 and 3710. Local high voltage decoder 3709 outputs local control gate lines for VMM arrays 3701 and 3702. Local high voltage decoder 3710 outputs local control gate lines for VMM arrays 3703 and 3704. In another embodiment, local high voltage decoders 3709 and 3710 can provide local source lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively.In another embodiment, local high voltage decoders 3709 and 3710 can provide local erase gate lines for VMM arrays 3701 / 3702 and VMM arrays 3703 / 3704, respectively.

[0161] Here, local high voltage row decoder 3709 is shared by VMM arrays 3701 and 3702, and local high voltage row decoder 3710 is shared by VMM arrays 3703 and 3704. Global high voltage decoder 3730 routes high and low voltage pre-decoded signals to local high voltage row decoders, such as local high voltage row decoders 3709 and 3710. Thus, the high voltage decode function is split between global high voltage row decoder 3730 and local high voltage decoders, such as local high voltage decoders 3709 and 3710.

[0162] In VMM system 3700, VMM arrays 3701, 3702, 3703, and 3704 share HV / LV pre-decode lines 3732, source lines 3733, erase gate lines 3734, and global high voltage row decoder 3730. However, each of the VMM arrays has its own low voltage row decoder, such that low voltage row decoder 3705 is used with VMM array 3701, low voltage row decoder 3706 is used with VMM array 3702, low voltage row decoder 3707 is used with VMM array 3703, and low voltage row decoder 3708 is used with VMM array 3704. The advantage of this layout is that word lines 3711, 3712, 3713, and 3714 are arranged vertically such that word line 3711 can be routed only to VMM array 3701, word line 3712 can be routed only to VMM array 3702, word line 3713 can be routed only to VMM array 3703, and word line 3714 can be routed only to VMM array 3704. This would be very inefficient for multiple arrays sharing a single high voltage decoder in a conventional layout where the word lines are arranged horizontally.

[0163] 38 illustrates a VMM system 3800 that is particularly suitable for use with memory cells of the type shown in FIG. 4 as memory cell 410. VMM system 3800 includes VMM arrays 3801, 3802, 3803, and 3804 (each of which may be based on any of the VMM designs discussed above, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs); The array includes low voltage row decoders 3805, 3806, 3807, and 3808, local high voltage row decoders 3809 and 3810, a global high voltage row decoder 3830, bit lines 3821, 3822, 3823, and 3824, control gate lines or control gate input lines 3811 and 3812, HV / LV pre-decode lines 3833, source lines 3834, and erase gate lines 3835. The shared global high voltage row decoder 3830 provides the HV / LV pre-decode lines 3833, source lines 3834, and erase gate lines 3835. The local high voltage decoders 3809 and 3810 couple the control gate inputs CG 3811 and 3812 to the local control gates of the VMM arrays 3801, 3802 and 3803, 3804, respectively. Low voltage row decoders 3805, 3806, 3807, and 3808 provide local (horizontal) word lines for arrays 3801, 3802, 3803, 3804, respectively. In this layout, control gate lines 3811 and 3812 and bit lines 3821, 3822, 3823, and 3824 are parallel to each other and arranged vertically. Source lines 3834 and erase gate lines 3835 are parallel to each other and arranged horizontally and are therefore perpendicular to control gate lines 3811 and 3812 and bit lines 3821, 3822, 3823, and 3824.

[0164] 37, local high voltage row decoder 3809 is shared by VMM arrays 3801 and 3802, and local high voltage row decoder 3810 is shared by VMM arrays 3803 and 3804. Global high voltage decoder 3830 routes signals to local high voltage row decoders, such as local high voltage row decoders 3809 and 3810. Thus, the high voltage decode function is split between global high voltage row decoder 3830 and local high voltage decoders, such as local high voltage decoders 3809 and 3810 (which may provide local source lines and / or local erase gate lines).

[0165] In VMM system 3800, VMM arrays 3801, 3802, 3803, and 3804 share HV / LV pre-decode lines 3833, source line lines 3834, erase gate lines 3835, and a global high voltage row decoder 3830. However, each of the VMM arrays has its own low voltage row decoder, such that low voltage row decoder 3805 is used with VMM array 3801, low voltage row decoder 3806 is used with VMM array 3802, low voltage row decoder 3807 is used with VMM array 3803, and low voltage row decoder 3808 is used with VMM array 3804. An advantage of this layout is that the control gate lines 3811 and 3812, which may be readout or input lines, are arranged vertically such that control gate line 3811 can be routed only to VMM arrays 3801 and 3802, and control gate line 3812 can be routed only to VMM arrays 3803 and 3804. This would not be possible in a conventional layout where the word lines are arranged horizontally.

[0166] FIG. 39 shows a VMM system 3900 that is particularly suitable for use with memory cells of the type shown in FIG. 3 as memory cell 310, in FIG. 4 as memory cell 410, in FIG. 5 as memory cell 510, or in FIG. VMM system 3900 includes VMM arrays 3901 and 3902 (which may be based on any of the previously discussed VMM designs, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, respectively, or other VMM array designs), low voltage row decoder 3903 (used in conjunction with arrays 3901 and 3902), local high voltage row decoder 3905, global high voltage row decoder 3904, control gate lines 3908 and 3909, and bit lines 3906 and 3907. In this layout, control gate line 3908 is used only by VMM array 3901, and control gate line 3909 is used only by VMM array 3902. The low voltage row decode line 3910 is used as a decode input to the global high voltage row decoder 3904. The global high voltage row decode line 3911 is used as a decode input to the local high voltage decoder 3905.

[0167] Local high voltage row decoder 3905 is shared by VMM arrays 3901 and 3902. Global high voltage decoder 3904 routes signals to local high voltage row decoders of multiple VMM systems, such as local high voltage row decoder 3905 of VMM system 3900. Thus, the high voltage decoding function is divided between global high voltage row decoder 3904 and local high voltage decoders, such as local high voltage decoder 3905, as described above.

[0168] In VMM system 3900, VMM arrays 3901 and 3902 share word lines (not shown), source gate lines (not shown) if present, erase gate lines (not shown) if present, and a global high voltage row decoder 3904. VMM arrays 3901 and 3902 instead share a low voltage row decoder 3903. An advantage of this layout is that VMM arrays 3901 and 3902 do not share control gate lines, thereby allowing each array to be accessed independently using control gate lines 3908 and 3909, respectively.

[0169] 51A shows a VMM system 5100 that is particularly suitable for use with memory cells of the type shown in FIG. 4 as memory cell 410. VMM system 5100 includes VMM arrays 5101, 5102, 5103, and 5104 (each of which may be based on any of the VMM array designs previously described, such as VMM arrays 1000, 1100, 1200, 1300, 1400, 1510, 2400, 2510, 2600, 2700, 2800, 2900, 3000, 3100, and 3200, or other VMM array designs), high voltage decoder 5130, routing blocks 5151 and 5152, input word lines 5111 and 5112, bit lines 5121, 5122, 5123, and 5124, control gate lines 5132, source lines 5133, and erase gate lines 5134. High voltage decoder 5130 provides signals to control gate lines 5132, source lines 5133, and erase gate lines 5134. Routing blocks 5151, 5152 are where the vertically received input word lines 5111 and 5112 are routed to the horizontally running word lines of the VMM arrays 5101-5104, respectively. Alternatively, routing blocks 5151, 5152 may route the vertically received control gate input lines 5132 to the horizontally running control gate lines 5132 of the VMM array.

[0170] FIG. 51B shows a VMM system 5150 that is identical in every respect to the VMM system 5100, except that bit lines can be routed from the top and bottom of the array, and control gates (CG) can be routed from the right side of the array and from the left side of the array. This means that both sides of the array can be used for bit line routing or control gate (or word line) routing. Local decoders or multiplexing may be required on each side of the array to which the terminals (BL, CG, WL) are routed. For example, this routing method is required for neural read mode (neural network inference mode).

[0171] FIG. 40 shows a low voltage row decoder 4000 including a NAND gate 4001, a PMOS transistor 4002, and an NMOS transistor 4003. The NAND gate 4001 receives a row address signal 4004. The PMOS transistor 4002 is coupled to a vertical word line input 4005. The output is at a horizontal word line 4006, which is one of many word lines that couple to the respective VMM array. In this example, there are a total of 16 word lines, and therefore there are 16 instances of the row decoder 4000, each outputting one of the 16 word lines. Thus, based on the received row address signal, one word line, such as word line 4006, outputs a respective signal, such as a voltage, and the other word lines are set to ground.

[0172] Figure 41 shows a combined co-select / deselect word line and control gate decoder 4100 including a low voltage row decoder as in Figure 40, now with a NAND gate 4101, a PMOS transistor 4102, an NMOS transistor 4103, a row address signal 4104, a vertical input word line 4105, and a horizontal word output line 4106 that couples to the word lines of the VMM array. The combined word line and control gate decoder 4100 further includes an inverter 4107, switches 4108 and 4112, and an isolation transistor 4109, and receives a control gate input 4110 CGIN0 and outputs a control gate line 4111 CG0. The word line output 4106 WL0 and the control gate output CG0 4111 are simultaneously selected or deselected by decode logic (not shown) that controls the NAND gate 4101.

[0173] FIG. 42 shows a bitline decoder 4200 operating with VMM arrays 4201 and 4202. Bitline decoder 4200 includes a column multiplexer 4203 (for selecting one or more bitlines for program and verify, where a verify operation is used to ensure that the cell current reaches a particular target during a tuning operation (program or erase operation)) and a sense amplifier 4204 (for performing a read operation on one or more bitlines). As shown, local bitline muxes 4201b and 4202b multiplex the local array bitlines to global bitlines 4220x, which are coupled to column multiplexer 4203. The sense amplifiers include ADCs or other devices. Thus, bitline decoder 4200 is shared across multiple arrays.

[0174] 43 shows a VMM system 4300, which includes VMM arrays 4301, 4302, 4303, and 4304, low voltage row decoders 4305 and 4307, local high voltage row decoders 4306 and 4308, global high voltage row decoder 4309, digital bus inputs QIN[7:0] 4311 and 4312 (which are now inputs to the VMM array), and bit lines 4321, 4322, 4323, and 4324. Each low voltage row decoder, such as low voltage row decoder 4305, includes an exemplary data input block 4331 (which may consist of eight latches or registers) that outputs a signal 4333 on the word line, and a circuit block row decoder 4335 for each word line, such as block 4332 (which may include a data-to-voltage conversion circuit or a data-to-pulse conversion circuit). The input to this low voltage row decoder is thus a digital bus QIN[7:0] with appropriate control logic. In each circuit block column decoder 4335, the digital inputs QIN[7:0] 4311 and 4312 are appropriately latched by synchronous clocking means and methods (eg, by a serial to parallel clocking interface, etc.).

[0175] FIG. 44 illustrates a neural network array I / O bus multiplexer 4400 that receives outputs from a VMM array (such as from an ADC) and provides those outputs in a group-multiplexed fashion to the input blocks of other VMM arrays (such as DACs or DPCs). In the example shown, the input to the I / O bus multiplexer 4400 includes 2048 bits (256 sets, NEU0,...,NEU255, each of 8 bits), which the I / O bus multiplexer 4400 provides in 64 different groups of 32 bits per group, multiplexing between the different groups (providing one group of 32 bits at any given time), such as by using time division multiplexing. Control logic 4401 generates control signals 4402 that control the I / O bus multiplexer 4400.

[0176] 45A and 45B show an example layout of a VMM array where the wordlines are laid out in a horizontal fashion (FIG. 45A) versus a vertical fashion (FIG. 45B, such as FIG. 34 or FIG. 35).

[0177] Figure 46 shows an example layout of a VMM array in which the wordlines are laid out in a vertical fashion (like Figure 34 or Figure 35). However, in this layout, two wordlines (such as wordlines 4601 and 4602) can occupy the same column but access different rows in the array (due to the gap between them).

[0178] FIG. 47 shows a VMM high voltage decode circuit including a word line decoder circuit 4701, a source line decoder circuit 4704, and a high voltage level shifter 4708 suitable for use with memory cells of the type shown in FIG.

[0179] Word line decoder circuit 4701 includes a PMOS select transistor 4702 (controlled by signal HVO_B) and an NMOS deselect transistor 4703 (controlled by signal HVO_B), configured as shown.

[0180] The source line decoder circuit 4704 includes an NMOS monitoring transistor 4705 (controlled by signal HVO), a drive transistor 4706 (controlled by signal HVO), and a deselect transistor 4707 (controlled by signal HVO_B), configured as shown.

[0181] A high voltage level shifter 4708 receives an enable signal EN and outputs a high voltage signal HV and its complement HVO_B.

[0182] FIG. 48 shows a VMM high voltage decode circuit including an erase gate decoder circuit 4801, a control gate decoder circuit 4804, a source line decoder circuit 4807, and a high voltage level shifter 4811 suitable for use with memory cells of the type shown in FIG.

[0183] The erase gate decoder circuit 4801 and the control gate decoder circuit 4804 use the same design as the word line decoder circuit 4701 of FIG.

[0184] Source line decoder circuit 4807 uses the same design as source line decoder circuit 4704 of FIG.

[0185] High voltage level shifter 4811 uses the same design as high voltage level shifter 4708 in FIG.

[0186] FIG. 49 illustrates a word line driver 4900. The word line driver 4900 selects a word line (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown herein) and provides a bias voltage to that word line. Each word line is attached to a select isolation transistor, such as select transistor 4901, which is controlled by control line 4902. The select transistors, such as select transistor 4901, isolate the high voltages (e.g., 8-12V) used during erase operations from the word line decode transistors, and the select transistors can be implemented using IO transistors that operate at low voltages (e.g., 1.8V, 3.3V). Now, during any operation, the control line 4902 is activated and all select transistors similar to select transistor 4901 are turned on. Exemplary bias transistor 4903 (part of the word line decode circuitry) selectively couples the word lines to a first bias voltage (such as 3V), and exemplary bias transistor 4904 (part of the word line decode circuitry) selectively couples the word lines to a second bias voltage (lower than the first bias voltage, including ground, a bias between ground and the first bias voltage, or a negative voltage bias to reduce leakage from unused memory rows). During an ANN (Analog Neural Network) read operation, all used word lines are selected and tied to the first bias voltage. All unused word lines are tied to the second bias voltage. During other operations, such as program operations, only one word line is selected and the other word line is tied to the second bias voltage, which may be a negative bias (e.g., -0.3 to -0.5V or higher) to reduce array leakage.

[0187] Bias transistors 4903 and 4904 are coupled to the output of a stage 4906 of a shift register 4905. The shift register 4905 allows each row to be independently controlled according to an input data pattern (loaded at the start of the ANN operation).

[0188] FIG. 50 shows a word line driver 5000. Word line driver 5000 is similar to word line driver 4900, except that each select transistor is further coupled to a capacitor, such as capacitor 5001. Capacitor 5001 can provide a precharge or bias to the word lines at the start of operation, enabled by transistor 5002 to sample the voltage on line 5003. Capacitor 5001 acts to sample and hold (S / H) the input voltage to each word line. Transistors 5004 and 5005 are off during ANN operation (array current adder and activation function) of the VMM array, meaning that the voltage on S / H capacitor 5001 acts as a (floating) voltage source for the respective word line. Alternatively, capacitor 5001 can be provided by the capacitance of the word line from the VMM array (or as a control gate capacitance if the input is on the control gate). Tandem Row Decoder

[0189] 52-55 show an embodiment of a tandem decoder. The tandem decoder reduces and preferably minimizes array leakage. During neural readout, unused rows are preferably shut off to reduce array leakage. In the prior art, a word line decoder is typically used to drive a control gate decoder, and control gate switching is used to switch off unused cells. This is not optimal for high current levels due to the number of current decade / VCG IV (e.g., 2 current decades / 1V) curve characteristics. That is, the current in the control gate line changes by approximately 100nA to 1nA when the control gate CG voltage is reduced by 1V. The tandem decoder overcomes this limitation of the prior art.

[0190] In the following example, during a verify operation, it is desired that the word line decoder overdrives the control gate decoder, meaning that the control gate state does not change until the word line state changes. During a read neural operation, the control gate decoder overdrives the word line decoder, meaning that the word line state does not change until the control gate line state changes.

[0191] Figure 52 shows a tandem row decoder 5200 that includes a word line decoder 5201 coupled to a control gate decoder 5202. In this example, the tandem row decoder 5200 is used for row 0 in the array. All of the other rows in the array have a similar tandem row decoder assigned to them.

[0192] Word line decoder 5201 includes PMOS transistor 5203 and NMOS transistor 5204 arranged as an inverter, NAND gate 5205, NAND gate 5206, and inverter 5207, configured as shown. Control gate decoder 5202 includes NAND gate 5208, inverter 5209, NAND gate 5210, inverter 5211, switch 5212, switch 5213, and isolation NMOS transistor 5214 configured as shown, which acts as a pass gate (from logic signals from inverter 5211 and switches 5212 and 5213) with its gate connected to an intermediate voltage such as Vdd to isolate high voltage levels on CG from the high voltage circuitry in non-volatile operation.

[0193] When word line WL0 enters a mode in which it is desired to overdrive (to disable or enable) control gate CG0 (such as during a verify operation), control signal CFG_ENWL provided to one input of NAND gate 5208 is set to "1" and CFG_ENCG provided to one input of NAND gate 5206 is set to "0". When control gate line CG0 enters a mode in which it is desired to overdrive (to disable or enable) word line WL0 (such as during a read neural operation), control signal CFG_ENCG is set to "1" and CFG_ENWL is set to "0". When row 0 enters a mode in which no row is used, CFG_ENWL and CFG_ENCG are both set to "0", which means that tandem decoder 5200 is not enabled. In a mode in which row 0 is not used at all, each word line WL decoder and each control gate CG decoder must be individually (separately) enabled / disabled.

[0194] First, consider the mode in which tandem decoder 5200 is not enabled (i.e., CFG_ENWL and CFG_ENCG=“0”). When CFG_ENCG and CFG_ENWL are “0”, the outputs of NAND gates 5206 and 5208 are each “1”, regardless of the value of the other inputs of each NAND gate. Since row 0 is not addressed, the output of NAND gate 5205 is “1” since pre-decoded address lines ENX0...ENXn are not asserted. Thus, PMOS transistor 5203 is turned off and NMOS transistor 5203 is turned on, thereby causing WL0 to be “0”. Since input CFG_ENWL is “0”, the output of NAND gate 5208 is “1”, and since row 0 is not addressed, the output of NAND gate 5210 is “1” since pre-decoded lines ENG0...ENGn are not asserted. Thus, switch 5213 is closed. The output of inverter 5211 is a "0" which opens switch 5212. Switch 5213, in the closed state, pulls the input to pass gate 5214 low and output CG0 is a "0". Thus, in this mode where no pre-decoded lines are asserted, WL0 and CG0 are pulled to "0", which is the desired state since tandem decoder 5200 is not being used. In particular, the memory cell does not exhibit any appreciable leakage current because terminals WL0 and CG0 are both pulled to ground through pull-down transistor 5204 and switch 5213 (typically also NMOS transistors), respectively.

[0195] Second, consider the mode in which tandem decoder 5200 is enabled and word line WL0 overdrives (to enable or disable) control gate CG0. CFG_ENCG is set to "0" and CFG_ENWL is set to "1". The output of NAND gate 5206 is "1" regardless of the value received at the other inputs. In this case, it is assumed that an address corresponding to row 0 is received, so inputs ENX0...ENXn to NAND 5205 are each "1", which means that the output of NAND 5205 is "0". PMOS transistor 5203 is turned on and NMOS transistor 5204 is turned off, and WL0 is pulled to "1", specifically towards the word line bias voltage WLBIAS. The input to inverter 5209 is "1", the output of inverter 5209 is "0", and the output of NAND gate 5208 is "1". In this case, it is assumed that an address corresponding to row 0 is being received, so inputs ENG0...ENGn to NAND 5210 are each a "1", which means that the output of NAND gate 5210 is a "0" which opens switch 5213. As above, the output of inverter 5211 is a "1", switch 5212 is closed (enabled), switch 5213 is open (disabled), pass gate 5214 is already on, and control gate CG0 is pulled to input CGIN0. CG0 will not switch from a "0" to the control gate bias voltage CGIN0 until WL0 switches from a "0" to a "1", because NAND gate 5208 outputs a "0" until that happens.

[0196] Third, consider the mode in which tandem decoder 5200 is enabled and the control gate enabling ENCGIN or control gate CG0 overdrives (to enable or disable) word line WL0. CFG_ENCG is set to "1" and CFG_ENWL is set to "0". The output of NAND gate 5208 is "1" regardless of the value received at the other inputs. In this case, it is assumed that an address corresponding to row 0 is received, so inputs ENG0...ENGn to NAND 5210 are each "1", which means that the output of NAND 5210 is "0". The output of inverter 5211 is "1", switch 5212 is closed, switch 5213 is open, and CG0 is driven to input CGIN0. The input to inverter 5207 is "1", the output of inverter 5207 is "0", and the output of NAND gate 5206 switches to "1". In this case, it is assumed that an address corresponding to row 0 is received, so inputs ENX0...ENXn to NAND 5205 are each "1", which means that the output of NAND 5205 is "0" assuming the output of NAND gate 5206 is asserted (i.e. = "1"). PMOS transistor 5203 is on and NMOS transistor 5204 is off, resulting in output WL0 being "1". In this third mode (CG decode overdrives WL decode), WL0 does not switch from "0" to "1" until CG0 switches from "0" to "1", because NAND gate 5206 outputs a "0" until that happens. Depending on the mode, WL0 (WL decode) is used to enable / disable CG0 (CG decode), and vice versa in the reversed wire style (WL0 interconnect line and CG0 interconnect line).

[0197] FIG. 53 shows a tandem row decoder 5300 including a word line decoder 5301 coupled to a control gate decoder 5302. In this example, the tandem row decoder 5300 is used for row 0 in the array. All of the other rows in the array have a similar tandem row decoder assigned to it. The word line decoder 5301 is identical to the word line decoder 5201 of FIG. 52. The control gate decoder 5302 is identical to the control gate decoder 5202 of FIG. 52, except that the coupling from the control gate decoder 5302 to the inverter 5207 has been moved from upstream of the switch 5212 (as shown in FIG. 52) to the output node CG0, thereby ensuring that WL0 does not switch from "0" to "1" until "CGIN0" switches from "0" to the control gate bias voltage "CGIN0" which is a high enough voltage level, such as a reference level, e.g., 0.5V or higher. Tandem row decoder 5300 otherwise operates in the same manner as tandem row decoder 5200. Inverter 5207 functions as a comparator whose trip point is approximately half the supply, meaning that if CG0 is < approximately 0.5Vdd, its output = "1". Another embodiment is shown in the insert with comparator 5207B whose output OUT = "1" if the input voltage level IN (i.e., CG0) < reference voltage level VREF (e.g., 0.5V). Similarly, inverter 5209 can be implemented as a comparator similar to comparator 5207B.

[0198] FIG. 54 shows a tandem row decoder 5400 including a word line decoder 5401 and a control gate decoder 5402. In this example, the tandem row decoder 5400 is used for row 0 in the array. All of the other rows in the array have a similar tandem row decoder assigned to it. The row decoder 5400 uses respective local latches to enable or disable each word line or each control gate line. Alternatively, one latch can be used to enable / disable each word line and control gate line together in tandem.

[0199] Source line decoder 5401 comprises PMOS transistor 5403, NMOS transistor 5404, NAND gate 5405, and latch 5406, configured as shown. Control gate decoder 5402 comprises NAND gate 5408, latch 5409, inverter 5410, switch 5411, switch 5412, and pass gate 5413, configured as shown.

[0200] Tandem row decoder 5400 is enabled by setting EN_LATWL / EN_LATCG and DINLAT to "1", which enables word line decoder 5401 and control gate decoder 5402. In this example, row 0 is selected, so decoded address signals ENX0...ENXn and ENG0...ENGn are all "1". When this happens, the output of latch 5406 is set to "1", the output of NAND gate 5405 is "0", PMOS transistor 5403 is turned on and NMOS transistor 5404 is turned off. WL0 is driven high to WLBIAS which is "1". When EN_LATCG and DINLAT are set to "1", the output of latch 5409 is set to "1", the output of NAND gate 5408 is "0", the output of inverter 5410 is "1", switch 5411 is closed and switch 5412 is open. CGO is driven to input CGIN0 level.

[0201] When the tandem row decoder 5400 is not enabled, EN_LATWL / EN_LATCG are set to "1" and DINLAT is set to "0", so that the word line decoder 5401 and the control gate decoder are not enabled. Regardless of the state of the received address signal and EN0, the output of latch 5406 is "0", the output of NAND gate 5405 is "1", NMOS transistor 5403 is turned off and NMOS transistor 5404 is turned on, pulling WL0 to ground at "0". The output of latch 5409 is also "0", the output of NAND gate 5408 is "1", the output of inverter 5410 is "0", switch 5411 is open, switch 5412 is closed, and CG0 is pulled to ground at "0" via switch 5412. In particular, since both terminals WL0 and CG0 are pulled to ground through pull-down transistor 5404 and switch 5412 (which are typically also NMOS transistors), there is no apparent leakage current in the memory cell due to WL0 or CG0.

[0202] FIG. 55 shows a tandem row decoder 5500 including a word line decoder 5501 and a control gate decoder 5502. In this example, the tandem row decoder 5500 is used for row 0 in the array. All of the other rows in the array have a similar tandem row decoder assigned to it. This decoder uses a level shifter on the output to extend the voltage range of the output, for example, to a high power supply Vdd (WLBIASH>Vdd) or ground level (WLBIASL<0V, a negative level such as -0.4V to -1V to reduce memory cell leakage even further).

[0203] Word line decoder 5501 includes, configured as shown, a level shifter 5503, a NAND gate 5504, a NAND gate 5505, an inverter 5506, and an inverter 5507. Control gate decoder 5502 includes a NAND gate 5508, an inverter 5509, a NAND gate 5510, a level shifter 5511, a switch 5512, a switch 5513, a pass gate 5514, and an inverter 5515.

[0204] When word line WL0 enters a mode in which it is desired to overdrive control gate CG0, control signal CFG_ENWL is set to "1" and CFG_ENCG is set to "0". When control gate line CG0 enters a mode in which it is desired to overdrive word line WL0, control signal CFG_ENCG is set to "1" and CFG_ENWL is set to "0". When row 0 is not being used in row decoder tandem mode, CFG_ENWL and CFG_ENCG are both set to "0", which means that decoder 5500 is enabled separately for WL and CG depending on its own input.

[0205] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly on" (with no intermediate material, element, or gap disposed between them) and "indirectly on" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), and "attached to" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached to" (with an intermediate material, element, or gap disposed between them), and "electrically coupled to" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate with no intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. a tandem row decoder for controlling word lines and control gate lines coupled to rows of non-volatile memory cells in the array, a word line decoder for driving the word lines; a control gate decoder for driving the control gate lines; A tandem row decoder, wherein the word line decoder overdrives the control gate decoder or the control gate decoder overdrives the word line decoder.

2. 2. The tandem row decoder of claim 1, wherein said array is a neural analog memory.

3. 2. The tandem row decoder of claim 1, wherein said non-volatile memory cells are split-gate memory cells.

4. 2. The tandem row decoder of claim 1, wherein said word line decoder includes a level shifter for generating an output of said word line decoder.

5. 5. The tandem row decoder of claim 4, wherein the output of the word line decoder comprises a high level or a low level, the high level being greater than an operating voltage Vdd of the row decoder and the low level being less than ground.

6. 2. The tandem row decoder of claim 1, wherein said control gate decoder includes a level shifter for generating an output of said word line decoder.

7. 7. The tandem row decoder of claim 6, wherein the output of the control gate decoder comprises a high level or a low level, the high level being greater than an operating voltage Vdd of the row decoder and the low level being less than ground.

8. The tandem row decoder of claim 1, further comprising a latch for enabling or disabling the word line decoder.

9. 9. The tandem row decoder of claim 8, wherein the control gate decoder enables a control gate bias voltage to be applied to the control gate lines.

10. 9. The tandem row decoder of claim 8, wherein the array is a neural analog memory.

11. 9. The tandem row decoder of claim 8, wherein said non-volatile memory cells comprise split-gate memory cells.

12. 9. The tandem row decoder of claim 8 further comprising a latch for enabling or disabling the control gate decoder.

13. 9. The tandem row decoder of claim 8, wherein control gate line terminals are located on a first side of the array and word line terminals are located on a second side of the array opposite the first side.

14. 14. The tandem row decoder of claim 13, wherein bit lines are accessed from a third side and a fourth side of the array, the third side being adjacent to the first side, and the second side and the fourth side being opposite the third side.

15. a tandem row decoder for controlling control gate lines coupled to rows of non-volatile memory cells in the array, a control gate decoder for driving the control gate lines; a latch for enabling or disabling the control gate decoder.

16. The tandem row decoder of claim 15, further comprising a word line decoder for driving a word line coupled to the row of the non-volatile memory cells in the array corresponding to a row address.

17. 16. The tandem row decoder of claim 15, wherein the array is a neural analog memory.

18. 16. The tandem row decoder of claim 15, wherein the non-volatile memory cells comprise split-gate memory cells.

19. a tandem row decoder for controlling control gate lines coupled to rows of non-volatile memory cells in the array, a word line decoder including a first level shifter for selectively driving the word lines; a control gate decoder including a second level shifter for selectively driving the control gate lines; A tandem row decoder, wherein the word line decoder overdrives the control gate decoder during a first mode and the control gate decoder overdrives the word line decoder during a second mode.

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