Antenna Package Structure

Abstract

To provide an antenna package structure.SOLUTION: An antenna package structure 10 includes a glass substrate 100, an interconnected structure 106, a plurality of semiconductor chips 102, and an antenna array structure 104. The glass substrate 100 has a first surface 100A and a second surface 100B opposite to the first surface 100A. The interconnected structure 106 is disposed on the first surface 100A of the glass substrate 100. The plurality of semiconductor chips 102 are mounted on the interconnect structure 106. The antenna array structure 104 is formed on the second surface 100B of the glass substrate 100. Additionally, the plurality of semiconductor chips 102 are coupled to the antenna array structure 104 via the interconnect structure 106 and the glass substrate 100.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] (PRIORITY CLAIM AND CROSS REFERENCE) This application claims priority to U.S. Provisional Application No. 63 / 351,881, filed June 14, 2022, and U.S. Non-Provisional Application No. 18 / 066,002, filed December 14, 2022, the disclosures of which are incorporated by reference in their entireties herein.

[0002] The present disclosure relates to an antenna packaging structure. [Background technology]

[0003] In modern wireless communication technology, phased array antenna technology has attracted much attention because of its advantages such as high gain, high reliability, and beam steering capability compared with traditional antenna technology. Phased array antenna technology employs an array of antennas organized with proper management of antenna spacing, so the board area on which the array antennas are placed is much larger than that of traditional non-array antennas. The planarity of the board is one of the key challenges for developing large-scale antenna arrays at an acceptable cost. Meanwhile, high-frequency circuits with high circuit density and low power consumption are required to improve the signal processing performance of antenna arrays. Summary of the Invention

[0004] In one exemplary aspect, an antenna package structure is provided. The antenna package structure includes a glass substrate, an interconnect structure, a plurality of semiconductor chips, and an antenna array structure. The glass substrate has a first surface and a second surface opposite to the first surface. The interconnect structure is disposed on the first surface of the glass substrate. The plurality of semiconductor chips are mounted on the interconnect structure. The antenna array structure is formed on the second surface of the glass substrate. Furthermore, the plurality of semiconductor chips are coupled to the antenna array structure via the interconnect structure and the glass substrate.

[0005] In another exemplary aspect, an antenna package structure is provided. The antenna package structure includes a substrate, a semiconductor chip, and an antenna. The substrate has a first surface and a second surface opposite to the first surface. The semiconductor chip is mounted on the first surface of the substrate. The antenna is formed on the second surface of the substrate. Furthermore, the semiconductor chip is electromagnetically coupled to the antenna through the substrate. [Brief description of the drawings]

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view of a device that is adapted to receive and transmit signals from a control device to a processor;

[0007] [Figure 1A] 1A-1D show cross-sectional views of antenna packaging structures according to some comparative embodiments of the present disclosure. [Figure 1B] 1A-1D show three-dimensional schematic diagrams of antenna packaging structures according to some comparative embodiments of the present disclosure. [Figure 1C] 1A-1D show cross-sectional views of antenna packaging structures according to some comparative embodiments of the present disclosure. [Figure 1D] 1A-1D show cross-sectional views of antenna packaging structures according to some comparative embodiments of the present disclosure. [Diagram 2] 1 illustrates a cross-sectional view of an antenna packaging structure according to some embodiments of the present disclosure. [Diagram 3] 1 illustrates a three-dimensional schematic diagram of an antenna packaging structure according to some embodiments of the present disclosure. [Figure 4] 1 illustrates a cross-sectional view of an antenna packaging structure according to some embodiments of the present disclosure. [Diagram 5] 1 illustrates a cross-sectional view of an antenna packaging structure according to some embodiments of the present disclosure. [Figure 6] 1 illustrates a cross-sectional view of an antenna packaging structure according to some embodiments of the present disclosure. [Figure 7]1 illustrates a cross-sectional view of an antenna packaging structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0009] Additionally, spatially relative terms such as "lower," "below," "bottom," "upper," "top," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings for ease of description. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0010] As used herein, terms such as "first", "second" and "third" describe various elements, components, regions, layers and / or sections, but these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first", "second" and "third" as used herein do not imply a sequence or order unless clearly indicated by the context.

[0011] In a comparative embodiment shown in FIG. 1A, an antenna package structure 90 having a package substrate 91 is provided. In such an embodiment, the antenna package structure 90 is packaged with an antenna-in-package (AiP) technology. The AiP technology is an antenna packaging solution that implements one or more antennas in an IC package that can accommodate a bare RF chip (transceiver). For example, a typical AiP can include one or more RF chips 92 attached to a package substrate 91 with solder balls for connection to a printed circuit board (PCB) 93, and an array of antennas 94 is also formed on the PCB 93. In another example, referring to FIG. 1B, the RF chips 92 can be embedded in a liquid crystal polymer (LCP) layer 95. The LCP layer 95 is attached to a side of a flexible PCB (FPCB) 96, and the array of antennas 94 is formed on another side of the FPCB 96.

[0012] In another comparative embodiment shown in FIG. 1C, the PCB used for the antenna package structure 90 can be a high density interconnect (HDI) PCB 97, which is a PCB with a higher wiring density per unit area than a conventional PCB. In general, an HDI PCB is defined as a PCB that has one or all of the following features: microvias, blind / buried vias, build-up lamination, and high signal performance considerations. Using HDI technology, designers can place many components on both sides of the raw PCB. Using multiple via processes such as via-in-pad and blind via technology, components can be placed closer together, reducing the size of the components to achieve more I / O in a smaller geometry. The HDI PCB 97 can have up to about 16 metal layers inside. Although the parasitic capacitance of the HDI PCB 97 is low, the thermal expansion coefficient of the HDI PCB 97 is high enough to induce profile defect situations such as warping.

[0013] Besides the HDI PCB 97, the PCB in FIG. 1D can be a low-temperature co-fired ceramics (LTCC) substrate 98, which is an alternative glass-ceramic multilayer substrate. LTCC is a lamination technology that can be used for high-frequency modules, semiconductor package substrates, and substrates for applications that require environmental resistance. For example, LTCC is a material that contains ceramic, so it has excellent heat resistance, moisture resistance, and no outgassing. The LTCC substrate 98 can have up to about 60 metal layers inside. In addition, the thermal expansion coefficient of the LTCC substrate 98 is relatively close to that of silicon, making it an advantageous substrate for bare chip mounting. However, the application of the LTCC substrate 98 is limited due to its high cost, low precision, inaccurate alignment between layers, and shrinkage problems during sintering.

[0014] Referring to FIG. 2, in some embodiments of the present disclosure, an antenna package structure 10 having a glass substrate is provided. The antenna package structure 10 includes a substrate 100, a plurality of semiconductor chips 102, and an antenna array structure 104. The substrate 100 includes a first surface 100A and a second surface 100B opposite to the first surface 100A. In some embodiments, the substrate 100 includes a planar profile, and therefore both the first surface 100A and the second surface 100B are substantially flat and parallel to each other. Ensuring the flatness of the two main surfaces of the substrate 100 is one of the items to be considered when selecting the material of the substrate 100.

[0015] That is, even though silicon substrates (e.g., silicon wafers, silicon-based printed circuit boards, etc.) are used as a common choice in current electrical technology, in a situation where the substrate is implemented as part of an antenna package structure requiring a large area (e.g., a substrate having an area of ​​20 cm square), the silicon substrate is not a preferred choice due to cost and flatness issues. More specifically, although the flatness of the silicon wafer may be acceptable in the manufacture of the antenna package structure, the cost of the silicon wafer is a major barrier. Furthermore, the circular shape of the silicon wafer is also not suitable for the antenna package structure. Despite the availability of the silicon wafer option, substrates such as general printed circuit boards are not applicable as well because they cannot provide a substantially flat surface over a large area.

[0016] Thus, in some embodiments of the present disclosure, the substrate 100 is a glass substrate. A substrate made of glass can have the advantages of both low cost and excellent flatness. In some embodiments, the substrate 100 has a rectangular shape or a square shape having four straight sides. In some embodiments, the length of one side of the substrate 100 (i.e., the length of the side of the substrate 100) is about 20 cm or more. In some embodiments, the length of one side of the substrate 100 is about 40 cm or more. In some embodiments, the length of one side of the substrate 100 is about 80 cm or more, so that the antenna package structure 10 can have an area of ​​about 80 cm*80 cm or more, which is much larger than the scale of a general silicon substrate. In other words, the substrate 100 implemented in the present disclosure has a panel-level size, but the size of a substrate for forming a typical semiconductor structure is a wafer-level size. In some embodiments, the substrate 100 in the present disclosure can be provided by a thin film transistor (TFT) panel technology such as a 3.5 generation facility. Also, by using TFT panel technology, the line width of the antenna package structure 10 can be significantly narrower than that of a normal PCB (e.g., HDI PCB, LTCC substrate, etc.). For example, the line width can be narrowed to about 1 / 8 of that of a normal PCB, thus reducing parasitic capacitance and signal loss. In some embodiments, the glass material for forming the substrate 100 can be a transparent material similar to glass, such as fused silica, silicon oxide, quartz, etc.

[0017] Since the substrate 100 of the present disclosure is used in the field of antenna package structure, the area of ​​the substrate 100 must correspond to the structure of the antenna. Compared with a substrate for forming a semiconductor device (e.g., a semiconductor substrate, a silicon wafer, etc.), it is desirable that the density of the semiconductor devices formed on the substrate is as high as possible in order to reduce the average cost of the semiconductor device. In other words, the semiconductor devices are densely formed on the substrate. In contrast, in the present disclosure, the antenna structures are not densely organized on the substrate 100 because the spacing or pitch between the antenna structures is related to the wavelength (e.g., 1 / 2λ) of the antenna. Furthermore, the semiconductor devices densely formed on the substrate are eventually diced along the scribe lines of the substrate, but the substrate 100 in the present disclosure is for arranging at least an antenna array thereon, and these antenna structures will be implemented as a final product without further separation.

[0018] Further, in some embodiments, the substrate 100 is characterized not only by being a large-area substrate made of glass, but also by being a glass substrate with a fairly thin thickness. In some embodiments, the thickness of the substrate 100 is about 5 mm or less. In some embodiments, the thickness of the substrate 100 is about 3 mm or less. In some embodiments, the thickness of the substrate 100 is about 2 mm or less. In some embodiments, the thickness of the substrate 100 is in the range of about 0.5 mm to about 1.5 mm. In some embodiments, the thickness of the substrate 100 is based on the consideration of the parameters of dielectric constant (Dk) and dielectric loss (Df) depending on the particular operating frequency of the antenna structure. In general, a substrate made of glass can have certain advantages such as good insulating properties and low electrical loss (especially at high operating frequencies).

[0019] In the situation where the substrate 100 is a large area made of thin glass, in some embodiments of the present disclosure, the substrate 100 is a via-free glass substrate. In other words, in this embodiment, no conductive via structures or through-glass vias are formed in the substrate 100. In the field of semiconductor manufacturing, there are glass substrates that can be drilled to have multiple through-holes, such as for semiconductor packages, for forming glass interposers, for forming three-dimensional glass integrated passive devices (IPDs), for forming MEMS or sensor devices, etc. Such through-holes in glass substrates are called through-glass vias (TGVs) and can be formed by laser drilling or etching techniques. However, the cost of forming TGVs is high and the yield and strength of the substrate may be reduced at the same time, therefore, in some embodiments of the present disclosure, the profile of the substrate 100 is as it is, without any through-holes, trenches, recesses, etc.

[0020] As shown in FIG. 2, in some embodiments, an interconnect structure 106 is formed on a first surface 100A of a glass substrate 100. In some embodiments, the interconnect structure 106 includes one or more redistribution layers (RDLs). A plurality of semiconductor chips 102 are mounted on the interconnect structure 106. In some embodiments, the interconnect structure 106 includes a plurality of dielectric layers, which in turn include a plurality of conductive layers (also called redistribution layers) and conductive vias embedded therein. In some embodiments, the redistribution layers and conductive vias are formed of a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, alloys thereof, and the like.

[0021] As shown in FIG. 2, in some embodiments, the interconnect structure 106 includes a first dielectric layer 108 disposed on the first surface 100A of the substrate 100 and a second dielectric layer 110 disposed in a stack on the first dielectric layer 108. Further, in the stack of multiple dielectric layers, a first redistribution layer 112 is formed on the first surface 100A of the substrate 100, and a second redistribution layer 114 is formed on the top surface of the first dielectric layer 108. In some embodiments, the first redistribution layer 112 is a conductive metal pattern embedded in the first dielectric layer 108, and the second redistribution layer 114 is another conductive metal pattern embedded in the second dielectric layer 110. In some embodiments, the first redistribution layer 112 and the second redistribution layer 114 are electrically connected through conductive vias of the interconnect structure 106. The number of dielectric layers in the interconnect structure 106 depends on the layout design of the antenna packaging structure. For example, in scenarios where more power lines are required, three or more dielectric layers are feasible.

[0022] In some embodiments, the first dielectric layer is formed between the glass substrate and the second dielectric layer. In some embodiments, the first dielectric layer 108 is configured to have a first redistribution layer 112 for forming a plurality of apertures for transmitting RF signals through the substrate 100 to the antenna array structure 104. In some embodiments, the first redistribution layer 112 is electrically connected to a ground voltage. In some embodiments, the second dielectric layer 110 is configured to have a second redistribution layer 114 for conducting a supply power. The second redistribution layer 114 may be configured to be a signal port for transmitting signals to / from corresponding positions of the apertures.

[0023] In some embodiments, at least some of the conductive vias include a dimple profile, and therefore the dielectric layer formed thereon can replicate such a dimple profile to some extent. That is, as shown in FIG. 2, the first conductive via 116A includes a dimple profile 116B, and therefore a portion of the second dielectric layer 110 is embedded in the dimple profile 116B of the first conductive via 116A. Meanwhile, the second dielectric layer 110 can have a dimple profile 110B replicated to some extent from the dimple profile 116B. The dimple profile 110B is formed directly on the dimple profile 116B of the first conductive via 116A. Similarly, if there are additional layers formed on the second dielectric layer 110, more dimple profiles (e.g., dimple profile 118B) can be formed directly on the dimple profile 110B. In general, the dimple profile 116B of the first conductive via 116A can affect the flatness of at least some layers formed on the first conductive via 116A.

[0024] In other words, the planarity of the second dielectric layer 110 and the planarity of the second redistribution layer 114 may be reduced by the first conductive vias 116A formed thereunder. Thus, in some embodiments, when viewed from the projection direction between the interconnect structure 106 and the substrate 100, the conductive vias formed in the interconnect structure 106 are staggered with each other because these conductive vias must land on a flat conductive material. For example, the second conductive vias 126A of the second dielectric layer 110 are staggered (i.e., not aligned vertically with each other) with the first conductive vias 116A of the first dielectric layer 108 to avoid the dimple profile 116B, and the first conductive vias 116A are connected to the second redistribution layer 114 by the extension portions 116C of the first conductive vias 116A. It can also be said that the extension portions 116C of the first conductive vias 116A are part of the second redistribution layer 114. Therefore, the second redistribution layer 114 is not affected by the dimple profile 116B and can have a flat upper surface for the second conductive via landing.

[0025] In some embodiments, the third dielectric layer 118 may be disposed on the second dielectric layer 110. In some embodiments, the second dielectric layer 110 is formed between the third dielectric layer 118 and the first dielectric layer 108. The third dielectric layer 118 is configured to have a third redistribution layer 120. In some embodiments, the third redistribution layer 120 functions as a digital and RF fan-out layer. In some embodiments, the third redistribution layer 120 may be used to conduct RF signals having a frequency in a range of about 10 GHz to about 28 GHz. Additionally, the third dielectric layer 118 is the top layer of the interconnect structure 106, and therefore the third dielectric layer 118 also functions as a solder resist layer (i.e., solder mask) for soldering onto the interconnect structure 106. In some embodiments, the third redistribution layer 120 includes a plurality of conductive lines exposed from the dielectric material of the third dielectric layer 118, and the semiconductor chip 102 is mounted on the conductive lines. In other words, the third redistribution layer 120 is configured to receive / transmit digital and RF to / from the semiconductor chip 102 .

[0026] In some embodiments, the dielectric material used in the interconnect structure 106 is an insulating material such as polyimide, epoxy resin, etc. In some embodiments, each of the dielectric layers of the interconnect structure 106 is a thin polymer layer. For example, the material of the first dielectric layer 108 and the second dielectric layer 110 can include polyimide. In some embodiments, the material of the third dielectric layer 118 is the same as the material of the dielectric layer it covers. The selection of the dielectric material of the interconnect structure 106 is related to the thickness requirement of the dielectric layer. That is, in some embodiments of the present disclosure, the thickness of the dielectric layer (e.g., the first dielectric layer 108) is about 50 μm. In some embodiments, the thickness of the dielectric layer is about 30 μm or more. In some embodiments, the thickness of the dielectric layer is about 10 μm or more. In some embodiments, the thickness of the first dielectric layer 108 is about 20 μm to about 60 μm, and the thickness of the second dielectric layer 110 is about 10 μm. Compared to the polyimide dielectric layers in the present disclosure, the thickness of the dielectric layers in typical semiconductors is much thinner. For example, the thickness of dielectric layers in common semiconductors is usually less than about 5 μm (e.g., about 2-3 μm or less), and these thin dielectric layers are usually made of silicon oxide. In other words, some common dielectric materials used in semiconductor structures are not feasible in the present disclosure due to the thickness requirements in forming the antenna package structure.

[0027] Furthermore, the thickness of each of the dielectric layers of the interconnect structure 106 can be different from each other. For example, the thickness of the first dielectric layer 108 can be different from the thickness of the second dielectric layer 110 adjacent to the first dielectric layer 108. In some embodiments, the thickness of the dielectric layer is related to the signal transmission therethrough. For example, as in the embodiment shown in FIG. 2, the first dielectric layer 108 is thicker than the second dielectric layer 110 because the thickness of the first dielectric layer 108 corresponds to the radio frequency (RF) signal passing therethrough. In a scenario where the thickness of the dielectric layer is about 10 μm or less (e.g., 6 μm), the frequency of the RF signal passing therethrough should be about 50 GHz or about 60 GHz to obtain a favorable signal transmission quality. Instead, in a scenario where the frequency of the RF signal transmitted through the dielectric layer (i.e., passing through the dielectric layer by the conductive material therein) is in the range of about 10 GHz to about 28 GHz (or about 10 GHz or about 28 GHz), the thickness of the dielectric layer needs to be increased to about 50 μm to maintain the quality of the signal transmission. In other words, the thickness of the dielectric layer in this application can be adjusted depending on the frequency of the transmitted RF signal designed for the antenna package structure. Furthermore, the thick dielectric layer, i.e., the dielectric layer implemented for transmitting RF signals having frequencies in the range of about 10 GHz to / and about 28 GHz, can be the first dielectric layer 108 or the second dielectric layer 110 depending on which layer is the transmission path designed therein. In some embodiments, the thickness of the second dielectric layer 110 is thicker than the thickness of the third dielectric layer 118.

[0028] In some embodiments, the first redistribution layer 112 is configured to provide ground and provide apertures for electromagnetic coupling (which will be explained in a later paragraph). The apertures may be openings formed on a metal layer in a particular pattern. In some embodiments, the second redistribution layer 114 is configured for connecting power and transitions. In some embodiments, a third redistribution layer 120 can be disposed on the second dielectric layer 110, the third redistribution layer 120 being configured to provide RF and digital fan-out as previously described.

[0029] In some embodiments, the number of redistribution layers of the interconnect structure 106 is three or less. The number of layers of the interconnect structure 106 is typically related to the number of semiconductor chips 102 mounted on the interconnect structure 106. In a situation where 16*16 or 32*32 chips or dies are mounted on a typical PCB, the PCB needs to have seven or eight metal layers to connect these chips or dies through complex wiring in the PCB. However, in some embodiments of the present disclosure, the semiconductor chips 102 mounted on the interconnect structure 106 can be connected by a significant pattern of the top redistribution layer of the interconnect structure 106, so that these semiconductor chips 102 are already interconnected through a number of conductive lines 130 (see FIG. 3 ) adjacent to the top surface of the interconnect structure 106, and the number of redistribution layers of the interconnect structure 106 can be simplified to two or three layers without using the complex routing as described above. These conductive lines 130 are exposed from the dielectric material of the top dielectric layer of the interconnect structure 106.

[0030] As previously mentioned, the conductive vias in the dielectric layers can have a dimple profile on their top surface. In some embodiments, the depth of the dimple profile corresponds to the aspect ratio of the conductive vias when viewed from a cross-sectional view. For example, if the thickness of the first dielectric layer 108 is greater than the thickness of the second dielectric layer 110, the depth of the dimple profile 116B of the first conductive via 116A (which is laterally surrounded by the first dielectric layer 108) is greater than the dimple profile 110B of the second conductive via 126A in the second dielectric layer 110. In some embodiments, a portion of the second dielectric layer 110 is embedded in the first dielectric layer 108 by protruding toward the first dielectric layer 108. In other words, due to the recess provided by the dimple profile 116B, the lowest point of the bottom surface of the second dielectric layer 110 (i.e., the point edge of the dimple profile 116B) may be lower than the top surface of the first dielectric layer 108 (i.e., such lowest point is closer to the substrate 100 than the top surface of the first dielectric layer 108).

[0031] The dimple profile 110B is formed directly on the first dimple profile 116B of the first conductive via 116A. Similarly, if there are additional layers formed on the second dielectric layer 110, more dimple profiles can be formed directly on the second dimple profile 110B. As mentioned above, the dimple profile of the conductive via can affect the flatness of the dielectric layer formed thereon. Even if the dielectric layer formed on the conductive via can compensate for the dimple profile to some extent, however, in a situation where the interconnect structure 106 has only two or three dielectric layers, as in some embodiments in the present disclosure, it is possible that the top surface of the interconnect structure 106 can still exhibit a dimple profile. Thus, in some embodiments, each and every conductive via of the interconnect structure 106 is staggered with respect to one another.

[0032] The interconnect structure 106 and the multiple semiconductor chips 102 are structures disposed on a first surface 100A of the substrate 100, and corresponding to these structures, the antenna array structure 104 is disposed on a second surface 100B of the substrate 100, and thus the substrate 100 is accordingly sandwiched between the antenna array structure 104 and the interconnect structure 106.

[0033] In some embodiments, the antenna array structure 104 includes multiple phased array antennas. A phased array antenna is an array antenna whose single radiator can be fed with different phase shifts. In some embodiments, the phased array antennas of the antenna array structure 104 are wirelessly coupled to the semiconductor chips 102 via the interconnect structure 106 and the substrate 100. The phased array antennas are one-to-one mapped to the semiconductor chips 102. That is, each of the semiconductor chips 102 is electromagnetically coupled to an antenna (i.e., a phased array antenna) via the substrate 100. In one embodiment, each of the semiconductor chips 102 is located directly above (or below) a corresponding antenna, with the substrate 100 and the interconnect structure 106 in between. In other embodiments, each of the semiconductor chips 102 is not located above (or below) a corresponding antenna. For example, the semiconductor chips 102 may be slightly offset from a position that sees the corresponding antenna at the top of the antenna array structure 104.

[0034] As mentioned above, the glass thin substrate in some embodiments of the present disclosure is via-free, which means that it does not have via holes (e.g., does not form multiple TGVs) penetrating the glass substrate, and therefore the first surface 100A and the second surface 100B of the substrate 100 remain completely flat and intact. Electromagnetic coupling technology is thus applied to wirelessly couple the antenna array structure 104 and the semiconductor chip 102 through the interconnect structure 106 and the substrate 100 while the antenna array structure 104 and the semiconductor chip 102 are disposed on two opposite sides of the substrate 100.

[0035] That is, in some embodiments, communication between the antenna array structure 104 and the semiconductor chip 102 is based on RF signals passing through the transparent substrate 100. In some embodiments, one of the redistribution layers is arranged to form one or more apertures on the first surface 100A of the substrate 100, while the apertures are configured to transmit or radiate electromagnetic signals. In some embodiments, the first redistribution layer 112 covered by the first dielectric layer 108 may provide a plurality of apertures 124 formed on the first surface 100A of the substrate 100 to direct RF signals including coupling signals from the interconnect structure 106 to the antenna array structure 104 or coupling signals from the antenna array structure 104 to the interconnect structure 106. For example, each of the apertures 124 may function as a lens to direct RF signals passing through the substrate 100 for communication between the antenna array structure 104 and the semiconductor chip 102. In general, the width of the apertures 124 should not be too narrow, otherwise such apertures 124 may induce diffraction of RF signals. Thus, in some embodiments, the width of the aperture 124 is greater than the lower limit to prevent diffraction from occurring, and smaller than the upper limit to ensure at least a corresponding width for electromagnetic coupling of signals (i.e., transmitting electromagnetic signals). In some embodiments, each of the apertures 124 may be grouped with a correction aperture for transmitting a correction electromagnetic signal accompanying the previously described RF signal passing through the aperture 124. In some embodiments, the width of each of the apertures 124 is the same as the width of the correction aperture grouped with it. In some embodiments, each of the apertures 124 is adjacent to the correction aperture grouped with it. The group consisting of the apertures 124 and the correction aperture can provide a correction function for the antenna array structure 104. In particular, since the phased array antennas are organized in an array on the second surface 100B of the substrate 100, signals belonging to different phased array antennas may interfere with each other, so the self-correcting design through the group of apertures can ensure the operational quality of the antenna array.For example, with appropriate correction calculations, it can provide high quality circularly polarized antenna performance in an array distribution.

[0036] In some alternative embodiments, despite certain considerations such as cost, the semiconductor chip 102 and the antenna array structure 104 do not communicate through RF signals radiated across the transparent glass substrate 100, but rather the signals are transmitted through physical lines formed in the substrate, such as through a TGV, as previously described. These alternative embodiments may still be an option in some rare circumstances.

[0037] Referring to FIG. 4, in some embodiments, a plurality of solder bumps 200 or solder balls (one of which is shown in FIG. 4) can be used to bond the semiconductor chip 102 onto the interconnect structure 106. The plurality of solder bumps 200 are formed in openings in a top dielectric layer, such as the third dielectric layer 118 shown. In some embodiments, an Under Bump Metallization (UBM) layer 122 can be formed under each of the solder bumps 200 in the openings. Compared to Cu pillar bumps, the cost of forming these lead-free solder bumps 200 is less expensive. Furthermore, compared to other metal bump structures, the solder bumps 200 can provide better reliability than eutectic (EU) bumps.

[0038] Since the top dielectric layer is used as a solder resist layer, the top dielectric layer (e.g., third dielectric layer 118) can cover at least a portion of each of the conductive metals (e.g., third re-distribution layer 120) that are connected with the solder material. As shown, the width of each of the openings in the third dielectric layer 118 is smaller than the width of the conductive pads (i.e., the top re-distribution layer, such as the third re-distribution layer 120). Generally, the solder resist layer is used to prevent the risk of shorting between the conductive lines and the pads during and after soldering. In some embodiments of the present disclosure, the top dielectric layer is implemented as a solder resist layer, and the openings in the top dielectric layer can expose the conductive pads for forming the UBM and / or the solder bumps 200.

[0039] The semiconductor chip 102 in the present disclosure can be a RX chip (e.g., a receiver) or a TX chip (e.g., a transmitter) depending on the type of antenna package structure. That is, the semiconductor chip includes multiple transmitting chips for transmitting RF signals to the antenna array structure 104 through the interconnect structure 106 and the substrate 100, or multiple receiving chips for receiving RF signals from the antenna array structure 104 through the interconnect structure 106 and the substrate 100. Furthermore, instead of mixing RX chips and TX chips in one antenna package structure, all of the semiconductor chips 102 mounted on the interconnect structure 106 must be RX chips or TX chips.

[0040] Generally, each of the semiconductor chips 102 is flip-chip bonded onto the glass substrate 100 (through the interconnect structure 106 sandwiched therebetween) for communication with each of the antennas of the antenna array structure 104 located on another side of the substrate 100. As previously mentioned, the semiconductor chips 102 may be bonded to the interconnect structure 106 by soldering. Some alternative bonding techniques other than soldering are also feasible. In some embodiments, the semiconductor chips 102 may be attached to the interconnect structure 106 by metal bonding techniques, as shown in FIG. 5. In some embodiments, as shown in FIG. 6, the semiconductor chip 102 can be mounted on the interconnect structure 106 by a hybrid bonding technique, for example, the top dielectric layer of the interconnect structure 106 can be bonded to the surface dielectric layer of the semiconductor chip 102, while the multiple conductive pads 138 distributed and coplanar on the top dielectric layer (e.g., the first hybrid bonding dielectric layer 128) and the surface dielectric layer (e.g., the second hybrid bonding dielectric layer 132) of the interconnect structure 106, respectively, and the conductive pads 134 of the semiconductor chip 102 can be bumped through an annealing process. In some embodiments, as shown in FIG. 7, the semiconductor chip 102 can be mounted on the interconnect structure 106 through a chip-on-glass (COG) technique. For example, the semiconductor chip 102 can be electrically coupled to the metal pads of the interconnect structure 106 by using a conductive medium 136, such as an anisotropic conductive film (ACF) or a non-conductive film (NCF). The choice of bonding technique is substantially open and therefore the bonding technique for mounting the semiconductor chip 102 on the side of the substrate 100 opposite to the side carrying the antenna array structure 104 is not limited to the exemplary embodiments as shown in Figures 5 to 7.

[0041] According to an embodiment of the present disclosure, an antenna package structure having a glass substrate is provided. The glass substrate is selected in this way due to the requirements of the surface flatness of the substrate and the requirements of the large area of ​​the substrate, and the antenna array structure and the semiconductor chip are formed and mounted on different surfaces of the substrate, respectively. Furthermore, by using electromagnetic coupling technology, the antenna array structure and the semiconductor chip can communicate with each other by electromagnetic signals (e.g., optical signals) radiated across the substrate without using physical via structures in the substrate. Furthermore, compared with some packaging technologies such as HDI-based or LTCC-based PCB or substrate, the antenna package structure of the present disclosure has much fewer layers in wiring and simplified wiring, which allows the antenna package structure to be thinner, with better and faster performance, and attractive yield and cost.

[0042] The foregoing outlines the structure of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other operations and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. 1. An antenna package structure, comprising: a glass substrate having a first surface and a second surface opposite the first surface; an interconnect structure disposed on the first surface of the glass substrate; a plurality of semiconductor chips mounted on the interconnect structure; an antenna array structure formed on the second surface of the glass substrate; Equipped with the plurality of semiconductor chips are coupled to the antenna array structure via the interconnect structure and the glass substrate; The interconnect structure comprises: a first dielectric layer disposed on the first surface of the glass substrate, the first dielectric layer configured to have a first redistribution layer for forming a plurality of apertures for transmitting RF signals through the glass substrate to the antenna array structure; Equipped with The first redistribution layer is electrically connected to a ground voltage.

2. The antenna package structure as claimed in claim 1 , wherein the glass substrate is a via-free glass substrate.

3. 10. The antenna package structure of claim 1, further comprising a plurality of apertures formed in the first surface of the glass substrate for coupling signals from the interconnect structure to the antenna array structure or from the antenna array structure to the interconnect structure.

4. The antenna package structure of claim 1 , wherein the glass substrate comprises a plurality of through-glass vias.

5. The antenna package structure of claim 1, wherein the antenna package structure is configured to transmit an RF signal, and after the RF signal is transmitted to the glass substrate, the RF signal is transmitted through a first dielectric layer having a thickness corresponding to a frequency of the RF signal.

6. The interconnect structure comprises: a second dielectric layer disposed on the first dielectric layer and configured to have a second redistribution layer for conducting a supply power; Further equipped with 2. The antenna package structure as claimed in claim 1, wherein the first dielectric layer is formed between the glass substrate and the second dielectric layer, and a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer.

7. The interconnect structure comprises: a third dielectric layer disposed on the second dielectric layer and configured to have a third redistribution layer for conducting the RF signal having a frequency in a range of about 10 GHz to about 28 GHz; Further equipped with 7. The antenna package structure of claim 6, wherein the second dielectric layer is formed between the third dielectric layer and the first dielectric layer, and a thickness of the second dielectric layer is greater than a thickness of the third dielectric layer.

8. 7. The antenna package structure as claimed in claim 6, wherein the first dielectric layer has a thickness of about 20 μm to about 60 μm, and the second dielectric layer has a thickness of about 10 μm.

9. 2. The antenna package structure of claim 1, wherein the antenna array structure comprises a plurality of phased array antennas, the plurality of phased array antennas being one-to-one mapped to the semiconductor chip.

10. 2. The antenna package structure of claim 1, wherein the semiconductor chip comprises a plurality of transmitting chips for transmitting RF signals to the antenna array structure through the interconnect structure and the glass substrate, or a plurality of receiving chips for receiving RF signals from the antenna array structure through the interconnect structure and the glass substrate.

11. The antenna package structure as claimed in claim 1 , wherein a side length of the glass substrate is greater than about 40 cm.

12. 8. The antenna package structure of claim 7, wherein the third redistribution layer comprises a plurality of conductive lines exposed from a dielectric material of the third dielectric layer, and the semiconductor chip is mounted on the plurality of conductive lines.

13. 1. An antenna package structure, comprising: a substrate having a first surface and a second surface opposite the first surface; a semiconductor chip mounted on the first surface of the substrate; an interconnect structure formed between the substrate and the semiconductor chip, the interconnect structure comprising a plurality of conductive layers; an antenna formed on the second surface of the substrate; Equipped with the conductive layers are connected by a plurality of conductive vias, each of the conductive vias having a dimple profile, and each of the conductive vias is staggered relative to one another in a projection direction; The semiconductor chip is electromagnetically coupled to the antenna via the substrate.

14. The antenna package structure as claimed in claim 13, wherein the thickness of the substrate is less than or equal to about 2 mm.

15. The antenna package structure of claim 13, wherein the interconnect structure comprises three or less conductive layers.

16. The interconnect structure comprises: a first dielectric layer disposed on the first surface of the substrate; a second dielectric layer disposed on the first dielectric layer, a portion of the second dielectric layer protruding toward the first dielectric layer through the dimple profile; The antenna package structure of claim 13, further comprising:

17. 17. The antenna package structure of claim 16, wherein a lowest point of a bottom surface of the second dielectric layer is lower than a top surface of the first dielectric layer in a cross-sectional view.

18. 16. The antenna package structure of claim 15, wherein the interconnect structure comprises a plurality of polyimide films, the thicknesses of each of the plurality of polyimide films being different from each other.

19. 16. The antenna package structure of claim 15, wherein one of the conductive layers is arranged to form an aperture on the first surface of the substrate, the aperture configured to transmit an electromagnetic signal, the aperture having a width greater than a lower limit that prevents diffraction from occurring and less than an upper limit that transmits the electromagnetic signal.

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