Power System

Abstract

To provide a power supply system capable of reducing a variety of PMICs and reducing development costs thereof.SOLUTION: A power supply system includes a single first semiconductor integrated circuit (PMIC 1), at least one second semiconductor integrated circuit (PMICs 2 to 6), a first transmission line 7, and a second transmission line 8. Each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit includes at least one output terminal configured to output an output voltage. The single first semiconductor integrated circuit is configured to supply a clock signal CLK to the at least one second semiconductor integrated circuit via the first transmission line. Based on the clock signal, any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit is configured to transmit a data signal via the second transmission line to another one thereof.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed herein relates to a power supply system having multiple output channels. [Background technology]

[0002] A single PMIC (Power Management Integrated Circuit) is widely used as a power supply system having multiple output channels (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-157907 A (paragraph 0021) Summary of the Invention [Problem to be solved by the invention]

[0004] However, if a single PMIC is used to meet a wide variety of customer needs, the number of PMIC varieties will increase dramatically, posing a challenge as PMIC development costs increase. [Means for solving the problem]

[0005] The power supply system disclosed in this specification has a configuration (first configuration) comprising a single first semiconductor integrated circuit, at least one second semiconductor integrated circuit, a first transmission line, and a second transmission line, wherein the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit each have at least one output terminal configured to output an output voltage, the single first semiconductor integrated circuit is configured to supply a clock signal to the at least one second semiconductor integrated circuit via the first transmission line, and any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit is configured to transmit a data signal to another one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit via the second transmission line based on the clock signal.

[0006] In the power supply system of the first configuration, each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit may be configured (second configuration) to include a confirmation unit configured to confirm that the second transmission line is not transmitting the data signal before starting to transmit the data signal.

[0007] In the power supply system of the second configuration, the confirmation unit may be configured to confirm that the second transmission line is not transmitting the data signal if the voltage applied to the second transmission line over a predetermined period of the clock signal is at a predetermined level (third configuration).

[0008] In the power supply system of the second or third configuration, the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit may each be configured (fourth configuration) to include an arbitration unit configured to arbitrate the authority to transmit the data signal before starting transmission of the data signal when two or more of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit are scheduled to transmit the data signal.

[0009] In the power supply system of the fourth configuration, the arbitration unit may be configured to determine whether or not two or more of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit are scheduled to transmit the data signal based on the level of the voltage applied to the second transmission line (fifth configuration).

[0010] In the power supply system of any of the first to fifth configurations above, each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit may be configured (sixth configuration) to include a synchronization confirmation unit configured to confirm that the data signal is synchronized with the clock signal before starting to transmit the data signal.

[0011] The semiconductor integrated circuit disclosed in this specification has a configuration (seventh configuration) including: a first terminal configured to be connectable to a first transmission line; a second terminal configured to be connectable to a second transmission line; at least one output terminal configured to output an output voltage; a clock signal processing unit configured to output a first clock signal from the first terminal in a first setting and to input a second clock signal to the first terminal in a second setting; and a transceiver unit configured to receive a first data signal input to the second terminal based on the first clock signal in the first setting, and to transmit a second data signal output from the second terminal based on the first clock signal, and to receive the first data signal input to the second terminal based on the second clock signal in the second setting, and to transmit the second data signal output from the second terminal based on the second clock signal.

[0012] The vehicle disclosed in this specification has a configuration (eighth configuration) that includes a power supply system having any one of the first to sixth configurations. [Effects of the Invention]

[0013] According to the invention disclosed in this specification, it is possible to provide a power supply system that can meet a wide variety of customer requirements at low cost. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a power supply system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a device ID. [Figure 3] FIG. 3 is a diagram showing an example of a system number. [Figure 4] FIG. 4 is a diagram illustrating an example of a schematic configuration of a PMIC. [Figure 5] FIG. 5 is a time chart of the voltage applied to the first transmission line and the voltage applied to the second transmission line. [Figure 6] FIG. 6 is a time chart of the voltage applied to the first transmission line and the voltage applied to the second transmission line. [Figure 7] FIG. 7 is a time chart of the voltage applied to the first transmission line and the voltage applied to the second transmission line. [Figure 8] FIG. 8 is an external view of a vehicle according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Fig. 1 is a diagram showing a schematic configuration of a power supply system according to one embodiment. The power supply system 100 shown in Fig. 1 includes PMICs 1 to 6, a first transmission line 7, and a second transmission line 8. The first transmission line 7 and the second transmission line 8 form a single communication bus.

[0016] Each of PMIC1 to 6 has at least one output terminal for outputting an output voltage. Also, each of PMIC1 to 6 has an input terminal for receiving an input voltage. Each of PMIC1 to 6 includes a power supply circuit such as a linear regulator or a switching regulator, and generates at least one type of output voltage from the input voltage.

[0017] PMIC 1 supplies a clock signal CLK to PMICs 2 to 6 via a first transmission line 7. Hereinafter, PMIC 1 may be referred to as the master. Hereinafter, PMICs 2 to 6 may be referred to as slaves, and PMICs 2 to 6 may be referred to as slaves 1 to 5, respectively.

[0018] Based on the clock signal CLK, any one of PMICs 1 to 6 transmits data to another one via the second transmission line 8. That is, in the power supply system 100, data transmission from a master to a slave, data transmission from one slave to another slave, and data transmission from a slave to a master are possible. Although the power supply system 100 is configured to include multiple PMICs 1 to 6, the above data transmission allows it to execute various processes (e.g., processes at startup, processes when an abnormality occurs, etc.) as if they were a single PMIC.

[0019] Next, the device ID and system number will be explained.

[0020] Each of the PMICs 1 to 6 includes a storage unit that stores the device ID and system number in a nonvolatile manner. It is desirable that the device ID and system number stored in the storage unit be rewritable.

[0021] Figure 2 shows an example of a device ID, and Figure 3 shows an example of a system number. PN1 and PN2 in Figures 2 and 3 are different PMIC part numbers. The number of channels (ch number) in Figure 3 is the total number of output terminals that output an output voltage and are provided in the power supply system.

[0022] In the power supply system 100, the storage unit of the PMIC 1 stores "3'b000" as the device ID and "10" as the system number.

[0023] In the power supply system 100, the storage unit of the PMIC2 stores "3'b011" as the device ID and "10" as the system number.

[0024] In the power supply system 100, the storage unit of the PMIC 3 stores "3'b100" as the device ID and "10" as the system number.

[0025] In the power supply system 100, the storage unit of the PMIC 4 stores "3'b101" as the device ID and "10" as the system number.

[0026] In the power supply system 100, the storage unit of the PMIC 5 stores "3'b110" as the device ID and "10" as the system number.

[0027] In the power supply system 100, the storage unit of the PMIC 6 stores "3'b111" as the device ID and "10" as the system number.

[0028] By storing the above-mentioned device IDs and system numbers in the storage units of PMIC1 to PMIC6, power supply system 100 becomes a power supply system that includes six PMICs and has a total of 17 output terminals (number of channels) that output output voltages. Power supply system 100 can be developed by developing two types of PMICs (product numbers PN1 and PN2). Then, by developing two types of PMICs (product numbers PN1 and PN2), it is possible to develop, for example, each of the power supply systems shown in FIG. 3 that includes power supply system 100. In other words, for example, each of the power supply systems shown in FIG. 3 can meet a wide variety of customer requirements at low cost.

[0029] Next, the communication protocol will be described.

[0030] Fig. 4 is a diagram showing an example of the schematic configuration of a PMIC. The PMIC shown in Fig. 4 includes a power supply circuit 11, an abnormality detection unit 12, a control unit 13, a memory unit 14, an input terminal IN, output terminals OUT1 to OUTn, a first terminal T1, and a second terminal T2. The PMIC with part number PN1 includes seven output terminals OUT1 to OUT7, and the PMIC with part number PN2 includes two output terminals OUT1 to OUT2.

[0031] The power supply circuit 11 converts an input voltage VIN applied to an input terminal IN into output voltages VOUT1 to VOUTn, and supplies the output voltages VOUT1 to VOUTn to output terminals OUT1 to OUTn.

[0032] The abnormality detection unit 12 detects an abnormality in the power supply circuit 11 and outputs the detection result to the control unit 13. Examples of abnormalities include an overvoltage of each of the output voltages VOUT1 to VOUTn, a low voltage of each of the output voltages VOUT1 to VOUTn, and an overcurrent of the current supplied to each of the output terminals OUT1 to OUTn.

[0033] The control unit 13 controls the power supply circuit 11. In other words, the control unit 13 manages the power supply circuit 11. The control unit 13 includes a confirmation unit 13A, an arbitration unit 13B, a synchronization confirmation unit 13C, a clock signal processing unit 13D, and a transmission / reception unit 13E.

[0034] Before the control unit 13 starts transmitting data to the second transmission line 8, the confirmation unit 13A confirms that the second transmission line 8 is not transmitting data.

[0035] When two or more of the PMICs 1 to 6 are planning to transmit data to the second transmission line 8, the arbitration unit 13B arbitrates the authority to transmit data before the control unit 13 starts transmitting data to the second transmission line 8.

[0036] Before the control unit 13 starts transmitting data to the second transmission line 8, the synchronization confirmation unit 13C confirms that the control unit 13 is synchronized with the clock signal CLK.

[0037] When the PMIC is set as the master by the device ID stored in the storage unit 14 (when set to the first setting), the clock signal processing unit 13D outputs the clock signal CLK from the first terminal T1.

[0038] When the PMIC is set as a slave by the device ID stored in the storage unit 14 (when the PMIC is set to the second setting), the clock signal processing unit 13D inputs the clock signal CLK from the first terminal T1.

[0039] The transmitter / receiver 13E receives data input to the second terminal T2 based on the clock signal CLK, and transmits data output from the second terminal T2 based on the clock signal CLK.

[0040] Fig. 5 is a time chart of the voltage applied to the first transmission line 7 and the voltage applied to the second transmission line 8. More specifically, Fig. 5 is a time chart of the voltage V7 applied to the first transmission line 7 and the voltage V8 applied to the second transmission line 8 when the master PMIC 1 transmits data.

[0041] In the data communication protocol for the second transmission line 8, the voltage V8 applied to the second transmission line 8 is set to a low level every other cycle of the clock signal CLK (the gray area shown in FIG. 5). Therefore, if the high level of the voltage V8 applied to the second transmission line 8 continues for four cycles of the clock signal CLK, this means that no data communication is taking place on the second transmission line 8.

[0042] 5, if the voltage V8 applied to the second transmission line 8 is at a high level over four cycles of the clock signal CLK, the confirmation unit 13A of the PMIC 1 confirms that the second transmission line 8 is not transmitting data. At the timing when this confirmation is made (timing t1 shown in FIG. 5), the transceiver unit 13E of the PMIC 1 switches the voltage V8 applied to the second transmission line 8 from a high level to a low level. Thereafter, the transceiver unit 13E of the PMIC 1 switches the voltage V8 applied to the second transmission line 8 to a low level every other cycle of the clock signal CLK (the gray area shown in FIG. 5).

[0043] The transmitter / receiver 13E of PMIC1 sets the voltage V8 applied to the second transmission line 8 to a low level for a predetermined time during the arbitration period (the first cycle of the clock signal CLK during the arbitration period). The arbitration unit 13B of PMIC1 verifies, based on the level of the voltage V8 applied to the second transmission line 8 during the arbitration period, that the other PMICs, PMIC2 to PMIC6, are not attempting to start data communication. More specifically, the arbitration unit 13B of PMIC1 verifies that the other PMICs, PMIC2 to PMIC6, are not attempting to start data communication because the voltage V8 applied to the second transmission line 8 is a high level during the third, fifth, seventh, ninth, and eleventh cycles of the clock signal CLK during the arbitration period.

[0044] During the final four cycles of the clock signal CLK in the arbitration period, each of the transceiver units 13E of PMICs 1 to 6 transitions the voltage V8 applied to the second transmission line 8 from LOW level to LOW level to HIGH level to LOW level for each cycle of the clock signal CLK.

[0045] The synchronization confirmation unit 13C of PMIC1 checks whether the voltage V8 applied to the second transmission line 8 transitions in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK during the final four cycles of the clock signal CLK in the arbitration period. If the voltage V8 applied to the second transmission line 8 does not transition in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK, synchronization among PMIC1 to 6 is not achieved, and the transmitter / receiver 13E of PMIC1 stops transmitting data.

[0046] If the voltage V8 applied to the second transmission line 8 transitions between low, low, high, and low levels in this order for each cycle of the clock signal CLK, the transmitter / receiver 13E of the PMIC1 sequentially transmits the address of the PMIC to which data is to be sent and the data to be sent to the PMIC to which data is to be sent during the data communication period. Thereafter, the transmitter / receiver 13E of the PMIC1 transmits a CRC code corresponding to the address and data during the data communication period to the PMIC to which data is to be sent, and the transmitter / receiver 13E of the PMIC to which data is to be sent transmits the CRC check result to the PMIC1 during the CRC check period.

[0047] Fig. 6 is a time chart of the voltage applied to the first transmission line 7 and the voltage applied to the second transmission line 8. More specifically, Fig. 6 is a time chart of the voltage V7 applied to the first transmission line 7 and the voltage V8 applied to the second transmission line 8 when the PMIC 2, which is the slave 1, transmits data.

[0048] 6, if the voltage V8 applied to the second transmission line 8 is at a high level over four cycles of the clock signal CLK, the confirmation unit 13A of the PMIC 2 confirms that the second transmission line 8 is not transmitting data. At the timing when this confirmation is made (timing t1 shown in FIG. 6), the transceiver unit 13E of the PMIC 2 switches the voltage V8 applied to the second transmission line 8 from a high level to a low level. Thereafter, the transceiver unit 13E of the PMIC 2 sets the voltage V8 applied to the second transmission line 8 to a low level every other cycle of the clock signal CLK (the gray portion shown in FIG. 6).

[0049] The transmitter / receiver 13E of PMIC2 sets the voltage V8 applied to the second transmission line 8 to a low level for a predetermined time during the arbitration period (the third cycle of the clock signal CLK during the arbitration period). The arbitration unit 13B of PMIC2 confirms, based on the level of the voltage V8 applied to the second transmission line 8 during the arbitration period, that the other PMICs, PMIC1, 3 to 6, are not attempting to start data communication. More specifically, the arbitration unit 13B of PMIC2 confirms that the other PMICs, PMIC1, 3 to 6, are not attempting to start data communication because the voltage V8 applied to the second transmission line 8 is a high level during the first, fifth, seventh, ninth, and eleventh cycles of the clock signal CLK during the arbitration period.

[0050] During the final four cycles of the clock signal CLK in the arbitration period, each of the transceiver units 13E of PMICs 1 to 6 transitions the voltage V8 applied to the second transmission line 8 from LOW level to LOW level to HIGH level to LOW level for each cycle of the clock signal CLK.

[0051] The synchronization confirmation unit 13C of PMIC2 checks whether the voltage V8 applied to the second transmission line 8 transitions in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK during the final four cycles of the clock signal CLK in the arbitration period. If the voltage V8 applied to the second transmission line 8 does not transition in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK, synchronization among PMIC1 to 6 is not achieved, and the transmitter / receiver unit 13E of PMIC2 stops transmitting data.

[0052] If the voltage V8 applied to the second transmission line 8 transitions between low, low, high, and low levels in each cycle of the clock signal CLK, the transceiver 13E of PMIC2 sequentially transmits the address of the PMIC to which data is to be sent and the data to be sent to the PMIC to which data is to be sent during the data communication period. Then, during the CRC code communication period, the transceiver 13E of PMIC2 transmits a CRC code corresponding to the address and data during the data communication period to the PMIC to which data is to be sent, and the transceiver 13E of the PMIC to which data is to be sent transmits the CRC check result to PMIC1 during the CRC check period.

[0053] Fig. 7 is a time chart of the voltage applied to the first transmission line 7 and the voltage applied to the second transmission line 8. More specifically, Fig. 7 is a time chart of the voltage V7 applied to the first transmission line 7 and the voltage V8 applied to the second transmission line 8 when PMIC2, which is slave 1, and PMIC4, which is slave 3, switch the voltage V8 applied to the second transmission line 8 from a high level to a low level almost simultaneously.

[0054] 7, the confirmation unit 13A of each of the PMICs 2 and 4 confirms that the second transmission line 8 is not transmitting data if the voltage V8 applied to the second transmission line 8 is high for four cycles of the clock signal CLK. When this confirmation is made (timing t1 shown in FIG. 7), the transceiver 13E of each of the PMICs 2 and 4 switches the voltage V8 applied to the second transmission line 8 from high to low. Thereafter, the transceiver 13E of each of the PMICs 2 and 4 keeps the voltage V8 applied to the second transmission line 8 low every other cycle of the clock signal CLK (the gray portion shown in FIG. 7) until the arbitration period ends, and the transceiver 13E of the PMIC 4 keeps the voltage V8 applied to the second transmission line 8 low every other cycle of the clock signal CLK (the gray portion shown in FIG. 7) after the arbitration period ends.

[0055] The transceiver 13E of PMIC2 sets the voltage V8 applied to the second transmission line 8 to a low level during a predetermined time period during the arbitration period (the third cycle of the clock signal CLK during the arbitration period). The transceiver 13E of PMIC4 sets the voltage V8 applied to the second transmission line 8 to a low level during a predetermined time period during the arbitration period (the seventh cycle of the clock signal CLK during the arbitration period). The arbitration unit 13B of PMIC2 determines that the other PMIC, PMIC4, is attempting to start data communication based on the level of the voltage V8 applied to the second transmission line 8 during the arbitration period. More specifically, the arbitration unit 13B of PMIC2 determines that the other PMIC, PMIC4, is attempting to start data communication because the voltage V8 applied to the second transmission line 8 during the seventh cycle of the clock signal CLK during the arbitration period is low. The arbitration unit 13B of PMIC4 determines that the other PMIC, PMIC2, is attempting to start data communication based on the level of the voltage V8 applied to the second transmission line 8 during the arbitration period. More specifically, the arbitration unit 13B of PMIC4 confirms that the voltage V8 applied to the second transmission line 8 is at a low level during the third cycle of the clock signal CLK in the arbitration period, and therefore confirms that the other PMIC, PMIC2, is about to start data communication.

[0056] During the final four cycles of the clock signal CLK in the arbitration period, each of the transceiver units 13E of PMICs 1 to 6 transitions the voltage V8 applied to the second transmission line 8 from LOW level to LOW level to HIGH level to LOW level for each cycle of the clock signal CLK.

[0057] The synchronization confirmation unit 13C of PMIC2 checks whether the voltage V8 applied to the second transmission line 8 transitions in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK during the final four cycles of the clock signal CLK in the arbitration period. If the voltage V8 applied to the second transmission line 8 does not transition in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK, synchronization among PMIC1 to 6 is not achieved, and the transmitter / receiver unit 13E of PMIC2 stops transmitting data.

[0058] If the voltage V8 applied to the second transmission line 8 transitions between low, low, high, and low levels in each cycle of the clock signal CLK, the transceiver 13E of PMIC2 sequentially transmits the address of the PMIC to which data is to be sent and the data to be sent to the PMIC to which data is to be sent during the data communication period. Then, during the CRC code communication period, the transceiver 13E of PMIC2 transmits a CRC code corresponding to the address and data during the data communication period to the PMIC to which data is to be sent, and the transceiver 13E of the PMIC to which data is to be sent transmits the CRC check result to PMIC1 during the CRC check period.

[0059] The storage unit 14 of each PMIC stores the priority order in the event of contention in the start of data communication. In this embodiment, PMIC4 has a higher priority than PMIC2.

[0060] Since PMIC 4, which has a higher priority than PMIC 2, is about to start data communication, PMIC 2 gives up on starting data communication.

[0061] The synchronization confirmation unit 13C of the PMIC 4 checks whether the voltage V8 applied to the second transmission line 8 transitions in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK during the final four cycles of the clock signal CLK during the arbitration period. If the voltage V8 applied to the second transmission line 8 does not transition in the order of LOW level, LOW level, HIGH level, LOW level for each cycle of the clock signal CLK, synchronization among the PMICs 1 to 6 is not achieved, and the transmitter / receiver 13E of the PMIC 4 stops transmitting data.

[0062] If the voltage V8 applied to the second transmission line 8 transitions between low, low, high, and low levels in each cycle of the clock signal CLK, the transmitter / receiver 13E of the PMIC4 sequentially transmits the address of the PMIC to which data is to be sent and the data to be sent to the PMIC to which data is to be sent during the data communication period. Then, during the CRC code communication period, the transmitter / receiver 13E of the PMIC4 transmits a CRC code corresponding to the address and data during the data communication period to the PMIC to which data is to be sent, and the transmitter / receiver 13E of the PMIC to which data is to be sent transmits the CRC check result to the PMIC1 during the CRC check period.

[0063] In the power supply system 100, a confirmation period is provided, which makes it possible to avoid contention in data transmission among multiple PMICs. Furthermore, in the power supply system 100, an arbitration period is provided, which makes it possible to avoid contention in data transmission among multiple PMICs even if, unfortunately, multiple PMICs attempt to start data transmission at almost the same time.

[0064] 8 is an external view of a vehicle X according to one embodiment. The vehicle X is equipped with a power supply system 100. The vehicle X also includes a battery (not shown). The voltage output from the battery (not shown) becomes the input voltage of PMICs 1 to 6. The power supply system 100 serves as a power supply device for a plurality of on-board devices (not shown) mounted on the vehicle X.

[0065] In addition to the above-described embodiments, various modifications can be made to the configuration of the present invention without departing from the spirit of the invention. The above-described embodiments are illustrative in all respects and should be considered not to be limiting. The technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0066] Although the power supply system 100 described above has six PMICs, the total number of PMICs (first semiconductor integrated circuits and second semiconductor integrated circuits) included in the power supply system is not limited to six, and may be any plural number.

[0067] Note that Figure 3 only shows two types of power supply systems with two PMICs (a power supply system with system number "2" and a power supply system with system number "3"), two types of power supply systems with three PMICs (a power supply system with system number "4" and a power supply system with system number "5"), two types of power supply systems with four PMICs (a power supply system with system number "6" and a power supply system with system number "7"), two types of power supply systems with five PMICs (a power supply system with system number "8" and a power supply system with system number "9"), and two types of power supply systems with six PMICs (a power supply system with system number "10" and a power supply system with system number "11"), but these are merely examples. [Explanation of symbols]

[0068] 100 Power System 1 PMIC (example of the first semiconductor integrated circuit) 2-6 PMIC (example of second semiconductor integrated circuit) 7. First Transmission Line 8 Second Transmission Line 11 Power circuit 12 Abnormality detection unit 13 Control Unit 13A Verification Section 13B Mediation Department 13C Synchronization confirmation section 13D Clock signal processing section 13E Transmitter / Receiver 14 Storage section IN input terminal OUT1 to OUTn output terminals T1 Terminal 1 T2 Terminal 2 X vehicle

Claims

1. a single first semiconductor integrated circuit; at least one second semiconductor integrated circuit; A first transmission line; a second transmission line; each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit includes at least one output terminal configured to output an output voltage; the single first semiconductor integrated circuit is configured to supply a clock signal to the at least one second semiconductor integrated circuit via the first transmission line; Based on the clock signal, any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit is configured to transmit a data signal via the second transmission line to the other than the any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit; A power supply system, wherein the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit each include a confirmation unit configured to confirm that the second transmission line is not transmitting the data signal before starting to transmit the data signal.

2. a single first semiconductor integrated circuit; at least one second semiconductor integrated circuit; A first transmission line; a second transmission line; each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit includes at least one output terminal configured to output an output voltage; the single first semiconductor integrated circuit is configured to supply a clock signal to the at least one second semiconductor integrated circuit via the first transmission line; Based on the clock signal, any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit is configured to transmit a data signal via the second transmission line to the other than the any one of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit; A power supply system, wherein each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit is provided with a synchronization confirmation unit configured to confirm that it is synchronized with the clock signal before starting to transmit the data signal.

3. 3. The power supply system of claim 2, wherein each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit includes a confirmation unit configured to confirm that the second transmission line is not transmitting the data signal before starting transmission of the data signal.

4. 4. The power supply system according to claim 1, wherein the confirmation unit is configured to confirm that the second transmission line is not transmitting the data signal if a voltage applied to the second transmission line over a predetermined period of the clock signal is at a predetermined level.

5. 5. The power supply system according to claim 1, wherein each of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit includes an arbitration unit configured to arbitrate the authority to transmit the data signal before starting transmission of the data signal when two or more of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit plan to transmit the data signal.

6. 6. The power supply system according to claim 5, wherein the arbitration unit is configured to determine whether or not a plurality of the single first semiconductor integrated circuit and the at least one second semiconductor integrated circuit are planning to transmit the data signal based on a level of a voltage applied to the second transmission line.

7. A first terminal configured to be connectable to a first transmission line; A second terminal configured to be connectable to a second transmission line; at least one output terminal configured to output an output voltage; a clock signal processing unit configured to output a first clock signal from the first terminal in a first setting and to input a second clock signal to the first terminal in a second setting; a transceiver unit configured to receive, in the first setting, a first data signal input to the second terminal based on the first clock signal and transmit a second data signal output from the second terminal based on the first clock signal, and to receive, in the second setting, the first data signal input to the second terminal based on the second clock signal and transmit the second data signal output from the second terminal based on the second clock signal.

8. A vehicle comprising the power supply system according to any one of claims 1 to 6.

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