Semiconductor Device

Abstract

A semiconductor device (10) is provided with an inverter circuit formed by connecting, in series, a first IGBT (31) that is a first switching element and a second IGBT (32) that is a second switching element. The ON-voltage of the second IGBT (32) is lower than the ON-voltage of the first IGBT (31). The switching speed of the second IGBT (32) is lower than the switching speed of the first IGBT (31). The wiring impedance of a second main current path from an output terminal (13) to a second input terminal (12) via the second IGBT (32) is higher than the wiring impedance of a first main current path from a first input terminal (11) to the output terminal (13) via the first IGBT (31). The resistance value of a first external gate resistor (61) connected to the gate electrode of the second IGBT (32) is lower than the resistance value of a second external gate resistor (62) connected to the gate electrode of the first IGBT (31).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Inverter circuits having upper and lower arms each formed by connecting switching elements in series are widely known. For example, Patent Document 1 discloses a technology for reducing power loss in each of the upper and lower arms in an inverter circuit having upper and lower arms, in which a low on-loss IGBT (Insulated Gate Bipolar Transistor) with a low on-voltage is used as a switching element that switches in response to a long-period signal, and a low switching loss IGBT with a high switching speed is used as a switching element that switches in response to a short-period signal. As explained in Patent Document 1, the low on-loss IGBT and the low switching loss IGBT can be manufactured separately by performing lifetime control during the IGBT manufacturing process. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 06-086569 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the difference between the wiring impedance between the input terminal and output terminal of the upper arm and the wiring impedance between the input terminal and output terminal of the lower arm is not taken into consideration. Therefore, even if a low on-loss IGBT is used for the switching element on the long-period signal side, the on-voltage of the current path increases due to the wiring impedance between the input terminal and output terminal connected to it, and sufficient loss reduction effect cannot be obtained, resulting in a loss difference between the upper and lower arms and a concern that heat distribution will become uneven.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can reduce the loss difference between the upper and lower arms of an inverter circuit. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes: Switching in response to short-period signals A first switching element; Switching in response to long-period signals an inverter circuit including a first switching element and a second switching element connected in series; a first input terminal which is an external connection terminal connected to one main electrode of the first switching element; a second input terminal which is an external connection terminal connected to one main electrode of the second switching element; an output terminal which is an external connection terminal connected to a connection node between the first switching element and the second switching element; a first main current path which is a current path from the first input terminal to an output terminal via the first switching element; the first switching element, a first gate resistor connected to a gate electrode of the first switching element, and a second gate resistor connected to a gate electrode of the second switching element, wherein an on-voltage of the second switching element is lower than an on-voltage of the first switching element, a switching speed of the second switching element is lower than a switching speed of the first switching element, a wiring impedance of the second main current path is higher than a wiring impedance of the first main current path, and a resistance value of the second gate resistor is lower than a resistance value of the first gate resistor. Effect of the Invention

[0007] According to the semiconductor device according to the present disclosure, the difference in loss between the upper and lower arms of the inverter circuit can be reduced.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 11 is a circuit diagram of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> Fig. 1 is a diagram showing a schematic configuration of a semiconductor device 10 according to a first embodiment. Fig. 2 is a circuit diagram of the semiconductor device 10. Note that the same reference symbols are used to designate corresponding elements in Fig. 1 and Fig. 2.

[0011] 2, the semiconductor device 10 includes an inverter circuit having upper and lower arms each including a first IGBT 31 as a first switching element and a second IGBT 32 as a second switching element connected in series. A first diode 41 is connected in anti-parallel to the first IGBT 31 on the upper arm side. A second diode 42 is connected in anti-parallel to the second IGBT 32 on the lower arm side.

[0012] The semiconductor device 10 also includes a first input terminal 11, a second input terminal 12, and an output terminal 13 as main current terminals connected to the outside. The first input terminal 11 is an input terminal on the upper arm side, and is connected to a collector electrode which is one of the main electrodes of the first IGBT 31. The second input terminal 12 is an input terminal on the lower arm side, and is connected to an emitter electrode which is one of the main electrodes of the second IGBT 32. The output terminal 13 is connected to a connection node between the emitter electrode which is the other main electrode of the first IGBT 31 and the collector electrode which is the other main electrode of the second IGBT 32.

[0013] The semiconductor device 10 also includes a first gate signal input terminal 21 and a second gate signal input terminal 22 as control terminals connected to the outside. The first gate signal input terminal 21 is connected to the gate electrode of the first IGBT 31. The second gate signal input terminal 22 is connected to the gate electrode of the second IGBT 32.

[0014] As shown in Fig. 1, in an actual semiconductor device 10, a first base plate 51 on which a first IGBT 31 and a first diode 41 are mounted is disposed between a first input terminal 11 and an output terminal 13, and a collector electrode of the first IGBT 31 and a cathode electrode of the first diode 41 are connected to the first base plate 51. The first base plate 51 is connected to the first input terminal 11 via an internal wiring 81. An emitter electrode of the first IGBT 31 and an anode electrode of the first diode 41 are connected to the output terminal 13 via an internal wiring 82.

[0015] In addition, a second base plate 52 carrying the second IGBT 32 and the second diode 42 is disposed between the output terminal 13 and the second input terminal 12, and the collector electrode of the second IGBT 32 and the cathode electrode of the second diode 42 are connected to the second base plate 52. The second base plate 52 is connected to the output terminal 13 via an internal wiring 84. The emitter electrode of the second IGBT 32 and the anode electrode of the second diode 42 are connected to the second input terminal 12 via an internal wiring 85. The anode electrode of the second diode 42 is connected to the second input terminal 12 via an internal wiring 86.

[0016] The gate electrode of the first IGBT 31 is connected to the first gate signal input terminal 21 via an internal wiring 87. The gate electrode of the second IGBT 32 is connected to the second gate signal input terminal 22 via an internal wiring 88.

[0017] 2, in this embodiment, a first external gate resistor 61 which is an external resistor connected from outside to a first gate signal input terminal 21 is used as a gate resistor of a first IGBT 31. Also, a second external gate resistor 62 which is an external resistor connected from outside to a second gate signal input terminal 22 is used as a gate resistor of a second IGBT 32.

[0018] Here, the current path on the upper arm side, i.e., the current path from the first input terminal 11 to the output terminal 13 via the first IGBT 31, is defined as the "first main current path", and the current path on the lower arm side, i.e., the current path from the output terminal 13 to the second input terminal 12 via the second IGBT 32, is defined as the "second main current path". In the semiconductor device 10 having the configuration of FIG. 1, the first main current path is formed by the first base plate 51, the first IGBT 31, the first diode 41, and the internal wirings 81 to 83 connected between the first input terminal 11 and the output terminal 13. The second main current path is formed by the second base plate 52, the second IGBT 32, the second diode 42, and the internal wirings 84 to 86 connected between the output terminal 13 and the second input terminal 12.

[0019] In this embodiment, the on-voltage and switching speed of each of the first IGBT 31 and the second IGBT 32 are set by lifetime control so that the collector-emitter on-voltage of the second IGBT 32 is lower than the collector-emitter on-voltage of the first IGBT 31 and the switching speed of the second IGBT 32 is lower than the switching speed of the first IGBT 31. In other words, in the relationship between the first IGBT 31 and the second IGBT 32, the first IGBT 31 is a low switching loss IGBT with a high switching speed, and the second IGBT 32 is a low on-loss IGBT with a low on-voltage.

[0020] Also, the wiring impedances of the first IGBT 31 and the second IGBT 32 are set so that the wiring impedance of the second main current path passing through the second IGBT 32 is higher than the wiring impedance of the first main current path passing through the first IGBT 31. Furthermore, the resistance values ​​of the first external gate resistor 61 and the second external gate resistor 62 are set so that the resistance value of the second external gate resistor 62, which is the gate resistance of the second IGBT 32, is lower than the resistance value of the first external gate resistor 61, which is the gate resistance of the first IGBT 31.

[0021] By setting the on-voltage, switching speed, and gate resistance of each of the first IGBT 31 and the second IGBT 32, and the wiring impedance of each of the first main current path and the second main current path, so as to satisfy the above relationship, the difference in on-voltage between the first main current path and the second main current path is reduced, and further, the switching loss of the second IGBT 32, which has increased due to the lifetime control, is reduced. This makes it possible to reduce the difference in loss between the first main current path on the upper arm side and the second main current path on the lower arm side. As a result, the heat distribution in the semiconductor device 10 is made uniform, which contributes to improving the reliability of the semiconductor device 10.

[0022] <Embodiment 2> In the second embodiment, in contrast to the semiconductor device 10 of the first embodiment, the relationship between the first diode 41 and the on-voltage between the anode and cathode of the first diode 41 is further set.

[0023] In the second embodiment, a diode with a small anode-cathode on-voltage is used for the second diode 42 connected to the second main current path with a large wiring impedance, and a diode with a large anode-cathode on-voltage is used for the first diode 41 connected to the first main current path with a small wiring impedance. In other words, the on-voltage of the second diode 42 is set to be lower than the on-voltage of the first diode 41.

[0024] According to this embodiment, it is possible to further reduce the difference in loss between the first main current path on the upper arm side and the second main current path on the lower arm side.

[0025] <Embodiment 3> Fig. 3 is a circuit diagram of a semiconductor device 10 according to an embodiment 3. The structure of the semiconductor device 10 according to the embodiment 3 is similar to that of Fig. 1, and corresponding elements in Fig. 1 and Fig. 3 are denoted by the same reference numerals.

[0026] 3 , a first internal gate resistor 71 which is a built-in resistor built into the chip of first IGBT 31 is used as the gate resistance of first IGBT 31. Also, a second internal gate resistor 72 which is a built-in resistor built into the chip of second IGBT 32 is used as the gate resistance of second IGBT 32. The resistance values ​​of first internal gate resistor 71 and second internal gate resistor 72 are set such that the resistance value of second internal gate resistor 72 is smaller than the resistance value of first internal gate resistor 71.

[0027] In this embodiment, the same effects as those in the embodiment 1 can be obtained. In addition, there is also an effect that it is not necessary to connect the gate resistors of the first IGBT 31 and the second IGBT 32 to the outside of the semiconductor device 10.

[0028] <Fourth embodiment> In the fourth embodiment, the resistance of the internal wiring 87 connecting the gate electrode of the first IGBT 31 and the first gate signal input terminal 21 is used as the gate resistance of the first IGBT 31, and the resistance of the internal wiring 88 connecting the gate electrode of the second IGBT 32 and the second gate signal input terminal 22 is used as the gate resistance of the second IGBT 32. The resistance value of the internal wiring 88 is set lower than the resistance value of the internal wiring 87 so that the resistance value of the gate resistance of the second IGBT 32 is lower than the resistance value of the gate resistance of the first IGBT 31. For example, if the internal wiring 87 and the internal wiring 88 are wires made of the same material, the length of the internal wiring 88 may be made shorter than the length of the internal wiring 87.

[0029] In the present embodiment, the same effects as those of the embodiment 1 can be obtained. In addition, there is also an effect that it is no longer necessary to connect the gate resistances of the first IGBT 31 and the second IGBT 32 to the outside of the semiconductor device 10 or to incorporate the first internal gate resistance 71 and the second internal gate resistance 72 in the first IGBT 31 and the second IGBT 32, respectively.

[0030] The configurations of the gate resistors of the first IGBT 31 and the second IGBT 32 may be different from each other. For example, one of the gate resistors shown in the first, third, and fourth embodiments may be used as the gate resistor of one of the first IGBT 31 and the second IGBT 32, and the other of the gate resistors shown in the first, third, and fourth embodiments may be used as the gate resistor of the other.

[0031] In the above embodiment, the switching elements constituting the inverter circuit are IGBTs, but they may be, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Also, the diodes connected in reverse parallel to the switching elements may be Schottky barrier diodes or PN diodes.

[0032] The switching elements and diodes may be formed using silicon (Si) semiconductors, or may be formed using wide band gap semiconductors such as SiC, gallium nitride materials, diamond, etc. A semiconductor device using a wide band gap semiconductor is superior in operation at high voltages, large currents, and high temperatures compared to a semiconductor device using silicon.

[0033] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0034] The above description is illustrative in all respects, and it is understood that numerous variations not illustrated can be envisioned. [Explanation of symbols]

[0035] 10 semiconductor device, 11 first input terminal, 12 second input terminal, 13 output terminal, 21 first gate signal input terminal, 22 second gate signal input terminal, 31 first IGBT, 32 second IGBT, 41 first diode, 42 second diode, 51 first base plate, 52 second base plate, 61 first external gate resistor, 62 second external gate resistor, 71 first internal gate resistor, 72 second internal gate resistor, 81 to 88 internal wiring.

Claims

1. An inverter circuit comprising a first switching element that switches in response to a short cycle signal and a second switching element that switches in response to a long cycle signal, connected in series; a first input terminal which is an external connection terminal connected to one main electrode of the first switching element; a second input terminal which is an external connection terminal connected to one main electrode of the second switching element; an output terminal which is an external connection terminal connected to a connection node between the first switching element and the second switching element; a first main current path which is a current path from the first input terminal through the first switching element to the output terminal; a second main current path which is a current path extending from the output terminal to the second input terminal via the second switching element; a first gate resistor connected to a gate electrode of the first switching element; a second gate resistor connected to a gate electrode of the second switching element; Equipped with an on-voltage of the second switching element is lower than an on-voltage of the first switching element; a switching speed of the second switching element is lower than a switching speed of the first switching element; a wiring impedance of the second main current path is higher than a wiring impedance of the first main current path; a resistance value of the second gate resistor is lower than a resistance value of the first gate resistor; Semiconductor device.

2. a first diode connected in anti-parallel to the first switching element; a second diode connected in anti-parallel to the second switching element; Further equipped with an on-voltage of the second diode is lower than an on-voltage of the first diode; The semiconductor device according to claim 1 .

3. at least one of the first gate resistor and the second gate resistor is an external resistor externally connected to an external connection terminal connected to the gate electrode of the first switching element or the second switching element; 3. The semiconductor device according to claim 1 or 2.

4. At least one of the first gate resistor and the second gate resistor is a built-in resistor built into a chip of the first switching element or the second switching element.

3. The semiconductor device according to claim 1 or 2.

5. at least one of the first gate resistance and the second gate resistance is a resistance of an internal wiring that connects between the gate electrode of the first switching element or the second switching element and an external connection terminal; 3. The semiconductor device according to claim 1 or 2.

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