Error correction device, control circuit, storage medium, and error correction method

Abstract

An error correction device (20) that performs double-bit error correction decoding using a block error correction code includes a syndrome generation unit (1) that generates a syndrome pattern from a received sequence, an error number determination unit (2) that determines the number of bit errors in the received sequence based on the syndrome pattern, and a double-bit error candidate error correction unit (5) that, when the error number determination unit (2) determines that there is a double-bit error and that correction is possible, calculates a first parameter, which is a constant term of a normalized polynomial obtained by normalizing a second-order error locator polynomial based on the syndrome pattern, and is a normalized parameter, excludes from the first parameters the first parameters for which it is determined that the double-bit error is uncorrectable, and uses a second parameter obtained by degenerating the first parameter by one bit to find a normalized root for the double-bit error.

Description

[Technical field]

[0001] The present disclosure relates to an error correction device, a control circuit, a storage medium, and an error correction method for correcting errors that occur in wireless communication. [Background technology]

[0002] Conventionally, in double-bit error correction using block error correction codes such as BCH (Bose Chaudhuri Hocquenghem) codes, the syndrome pattern S1=α i +α j , S3=α 3i +α 3j From the quadratic error locator polynomial X 2 +σ1X+σ2 and construct the quadratic error locator polynomial X 2 The root of +σ1X+σ2 is sought. i ,α j is an element of the Galois field that corresponds one-to-one to the error position, i ≠ j, and "+" is addition on the Galois field. Also, σ1 = α i +α j and σ2=α i α j where "·" is multiplication over a Galois field.

[0003] For example, in Patent Document 1, a quadratic error locator polynomial X 2 +σ1X+σ2 is normalized to normalized polynomial Y 2 +Y+P is calculated, the root y is calculated by table lookup using the parameter P as an address, and multiplication or addition is performed on the root y, and α indicating the error position is calculated. i ,α j A technology is disclosed to obtain P = σ2 / σ1. 2 where " / " is division over the Galois field. Here, the parameter P is P=(α i α j ) / (α i +α j ) 2 =S3 / S1 3 +1, and the root y is y=α i / (αi +α j ) is calculated by [Prior art documents] [Patent documents]

[0004] [Patent Document 1] WO 01 / 084719 Summary of the Invention [Problem to be solved by the invention]

[0005] However, according to the above conventional technique, the normalized polynomial Y 2 In a table lookup to find the root y from the parameter P of +Y+P, the parameter P is used as an address to output the root y. 8 In a BCH code with a code length of 255 bits and an information bit length of 239 bits, which is constructed over an extension field over the Galois field GF(2 16 ), a BCH code with a code length of 65,535 bits and an information bit length of 65,503 bits has a 16-bit parameter P and a 16-bit root y, requiring a 16-bit table of 65,536 words. This poses the problem that the table size required for table lookup becomes large, and the circuit scale of the device also increases.

[0006] The present disclosure has been made in view of the above, and has an object to provide an error correction device capable of suppressing an increase in circuit size. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the present disclosure provides an error correction device that performs double-bit error correction decoding using a block error correction code. The error correction device is characterized by including: a syndrome generation unit that generates a syndrome pattern from a received sequence; an error number determination unit that determines the number of bit errors in the received sequence based on the syndrome pattern; and a double-bit error candidate error correction unit that, when the error number determination unit determines that there is a double-bit error and that correction is possible, calculates a first parameter that is a constant term of a normalized polynomial that normalizes a quadratic error locator polynomial based on the syndrome pattern, and is a normalized parameter, and excludes the first parameter that is determined to be uncorrectable for the double-bit error from the first parameter, and uses a second parameter that is obtained by degenerating the first parameter by one bit to obtain a normalized root for the double-bit error. Effect of the Invention

[0008] The error correction device according to the present disclosure has an advantage that an increase in circuit size can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration example of an error correction device according to a first embodiment; [Diagram 2] 1 is a flowchart showing the operation of the error correction device according to the first embodiment. [Diagram 3] FIG. 13 is a diagram showing an example of a table required for table lookup when finding a root from normalized parameters as a comparative example. [Figure 4] FIG. 1 is a diagram showing an example of a degenerate normalization root table used in a degenerate normalization root acquisition unit included in the error correction device according to the first embodiment; [Diagram 5] FIG. 1 is a diagram showing an example of the configuration of a processing circuit that realizes an error correction device according to a first embodiment, in the case where the processing circuit is configured with a processor and a memory. [Figure 6] FIG. 1 is a diagram showing an example of a processing circuit for implementing an error correction device according to a first embodiment when the processing circuit is configured with dedicated hardware. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An error correction device, a control circuit, a storage medium, and an error correction method according to embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0011] Embodiment 1 FIG. 1 is a diagram showing a configuration example of an error correction device 20 according to a first embodiment. The error correction device 20 is a device that performs double-bit error correction decoding using a block error correction code such as a BCH code, and corrects errors of 2 bits or less in an input reception sequence. The error correction device 20 includes a syndrome generation unit 1, an error number determination unit 2, a determination result processing unit 3, a double-bit error candidate error correction unit 5, a selection unit 10, an error position conversion unit 11, a delay unit 12, and a correction unit 13. The determination result processing unit 3 includes a single-bit error correction calculation unit 4. The double-bit error candidate error correction unit 5 includes a double-bit error correction normalization calculation unit 6, a correction unacceptability determination unit 7, a degenerate normalization root acquisition unit 8, and a double-bit error position calculation unit 9.

[0012] The syndrome generator 1 generates syndrome patterns S1 and S3 from one of the branched received sequences input to the error correction device 20. The received sequence is, for example, but not limited to, a received sequence received by wireless communication by a receiving device (not shown) equipped with the error correction device 20.

[0013] The error number determination unit 2 determines the number of bit errors in the received sequence input to the error correction device 20 based on the syndrome patterns S1, S3 generated by the syndrome generation unit 1. Specifically, the error number determination unit 2 determines whether there is no error, a single bit error, an uncorrectable error, or a double-bit error candidate from the syndrome patterns S1, S3. A double-bit error candidate is a determination result in which the double-bit error candidate error correction unit 5 determines that a double-bit error is correctable or uncorrectable, that is, a determination result that there is a double-bit error and that there is a possibility of correction.

[0014] The determination result processing unit 3 performs processing on the determination results of the error number determining unit 2 other than double-bit error candidates, specifically, the determination results of no error, single-bit error, and uncorrectable error.

[0015] The single-bit error correction calculation unit 4 calculates an element indicating the position of a single-bit error based on the result of the single-bit error determination made by the error number determination unit 2.

[0016] When the double-bit error candidate error correction unit 5 determines that the double-bit error candidate is correctable based on the result of the double-bit error candidate determination by the error number determination unit 2, it performs the original calculation indicating the double-bit error position, or determines that the double-bit error is uncorrectable.

[0017] The 2-bit error correction normalization calculation unit 6 is a Galois field GF(2 8 ) primitive polynomial X over an extension field 8 +X 4 +X 3 +X 2 +1 is used to calculate a normalization parameter P, which is a constant term of a normalization polynomial obtained by normalizing the quadratic error locator polynomial, and is a normalized parameter. In the following description, the normalization parameter P may be referred to as a first parameter.

[0018] The uncorrectable determining unit 7 determines whether or not the double-bit error candidate is uncorrectable based on the normalization parameter P calculated by the double-bit error correction normalization calculating unit 6.

[0019] When the result of the judgment by the uncorrectable judgment unit 7 is correctable, the degenerate normalized root acquisition unit 8 obtains a root y from a degenerate normalized root table 8a having an address of a parameter P1 obtained by degenerating the normalized parameter P. In the following description, the parameter P1 may be referred to as a second parameter.

[0020] The 2-bit error location calculation unit 9 calculates a Galois field element α i ,α j Request.

[0021] The selection unit 10 selects an output to the error location conversion unit 11 based on the state of each error number.

[0022] When the output from the selection unit 10 is a 1-bit error or 2-bit error, the error position conversion unit 11 converts the Galois field element indicating the error position into an error position using an error position conversion table 11a that converts from a Galois field element indicating the error position to an error position.

[0023] The delay unit 12 delays the other branched received sequence of the received sequence input to the error correction device 20 by the processing time from the syndrome generation unit 1 to the error position conversion unit 11 .

[0024] The error correction unit 13 corrects the corresponding bit of the received sequence delayed by the delay unit 12 based on the error position acquired from the error position conversion unit 11 .

[0025] Next, the operation of the error correction device 20 will be described. FIG. 2 is a flowchart showing the operation of the error correction device 20 according to the first embodiment. FIG. 2 shows an example of the operation of the error correction device 20 in a Galois field GF(2 8 ) in an extension field on which a primitive polynomial X 8 +X 4 +X 3 +X 2 2 is a diagram showing the operation of the error correction device 20 when using a BCH code with a code length of 255 bits and an information bit length of 239 bits, which is composed of +1. Note that in Fig. 2, steps ST1 to ST13 are separated by five dotted squares, and the codes given to each square are the same as the codes of each component of the error correction device 20 shown in Fig. 1. In other words, the codes shown in Fig. 2 indicate the components of the error correction device 20 that perform the operations of each step.

[0026] In the error correction device 20, the syndrome generator 1 generates syndrome patterns S1 and S3 from one of the branched received sequences input to the error correction device 20 (step ST1). The syndrome generator 1 outputs the generated syndrome patterns S1 and S3 to the error number determiner 2.

[0027] The error number determination unit 2 determines the number of errors based on the syndrome patterns S1 and S3 generated by the syndrome generation unit 1. Specifically, when S1=S3=0 (step ST2: Yes), the error number determination unit 2 outputs the syndrome patterns S1 and S3 and the determination result of no error to the determination result processing unit 3. Since the determination result acquired from the error number determination unit 2 is no error (step ST3), the determination result processing unit 3 outputs the syndrome patterns S1 and S3 and the determination result of no error to the selection unit 10 as is.

[0028] If at least one of S1 and S3 is not 0 (step ST2: No) and S1=0, that is, if S1=0 and S3≠0 (step ST4: Yes), the error number determination unit 2 outputs the syndrome patterns S1 and S3 and the determination result of uncorrectable to the determination result processing unit 3. Since the determination result acquired from the error number determination unit 2 is uncorrectable (step ST5), the determination result processing unit 3 outputs the syndrome patterns S1 and S3 and the determination result of uncorrectable to the selection unit 10 as is.

[0029] The error number determination unit 2 determines that S1 is not equal to 0 (step ST4: No), and 3 +S3=0, i.e. S1≠0 and S3≠0 and S1 3 If +S3=0 (step ST6: Yes), the syndrome patterns S1, S3 and the judgment result of the 1-bit error are output to the judgment result processing unit 3. Note that "+" is addition on the Galois field. In the judgment result processing unit 3, the 1-bit error correction calculation unit 4 calculates an element of the Galois field indicating the 1-bit error position for the judgment result of the 1-bit error by the error number judgment unit 2. Specifically, the 1-bit error correction calculation unit 4 finds the Galois field element X1=S1 indicating the 1-bit error position (step ST7) and outputs it to the selection unit 10.

[0030] The error number determination unit 2 is S1 3 +S3 ≠ 0, i.e., S1 ≠ 0 and S3 ≠ 0 and S1 3If +S3≠0 (step ST6: No), the syndrome patterns S1, S3 and the determination result of the double-bit error candidate are output to the double-bit error candidate error correction unit 5.

[0031] The double-bit error candidate error correction unit 5 can also use the syndrome patterns S1 and S3 as input parameters to find the double-bit error position by table lookup. 8 ) in an extension field on which a primitive polynomial X 8 +X 4 +X 3 +X 2 For a BCH code with a code length of 255 bits and an information bit length of 239 bits, which is composed of +1, the double-bit error candidate error correction unit 5 requires a table of 65,536 words of 16-bit output. Therefore, the double-bit error candidate error correction unit 5 reduces the size of the table required for table lookup by performing normalization, compared to the case where the syndrome patterns S1 and S3 are used as input parameters to find the double-bit error positions.

[0032] In the double-bit error candidate error correction unit 5, first, when the error number determination unit 2 determines that a double-bit error is a candidate, the double-bit error correction normalization calculation unit 6 calculates a normalization parameter P=S3 / S1, which is a constant term of a normalization polynomial obtained by normalizing the second-order error locator polynomial, based on the syndrome patterns S1 and S3 obtained from the error number determination unit 2. 3 The double-bit error correction normalization calculation unit 6 outputs the syndrome patterns S1 and S3 and the normalization parameter P obtained by the calculation to the correction uncorrectability determination unit 7. Note that " / " is a division on the Galois field. In addition, in FIG. 2, the normalization parameter P is represented as "Adr[7:0]".

[0033] The double-bit error candidate error correction unit 5 can also find the root y using the normalization parameter P as an address. For example, 8 +X 4 +X 3 +X 2For +1, a table like that shown in FIG. 3 is required. FIG. 3 is a diagram showing an example of a table required for table lookup when determining the root y from the normalization parameter P as a comparative example. In FIG. 3, the normalization parameter P is used as an address, which is represented by an address (P). In FIG. 3, the vertical direction of the address (P) indicates the most significant bits, and the horizontal direction of the address (P) indicates the least significant 4 bits. Here, the address (P) of an input value that outputs 0, i.e., the normalization parameter P, is uncorrectable. In this embodiment, focusing on the address (P) that outputs 0, i.e., the normalization parameter P, the uncorrectable judgment unit 7 judges whether or not a 2-bit error candidate is uncorrectable based on the normalization parameter P.

[0034] In the example of FIG. 3, when P=0 and when the normalization parameter P is an 8-bit address and the LSB (Least Significant Bit) is the 0th bit, the 5th bit from the LSB is 1, the correction is impossible. Therefore, the correction impossible determination unit 7 determines that the correction is impossible (step ST10) when P=0 or when the normalization parameter P is an 8-bit address and the 5th bit from the LSB is 1 (step ST9: Yes), and outputs the syndrome patterns S1 and S3 and the determination result of the correction impossible to the selection unit 10. Note that in FIG. 2, the case of P=0 is represented by "Adr[7:0]=0" and the case where the 5th bit from the LSB is 1 is represented by "Adr[5]=1". As a result, the correction impossible determination unit 7 excludes in advance from the 2-bit correction process the case where the normalization parameter P is an 8-bit address and the 5th bit from the LSB is 1 as being uncorrectable. That is, the uncorrectable determining unit 7 can exclude normalized parameters P in which it is determined that two-bit errors are uncorrectable from the normalized parameters P. In the following description, the LSB may be referred to as the least significant bit.

[0035] If P≠0 and if the 5th bit from the LSB of the normalization parameter P as an 8-bit address is not 1 (step ST9: No), the uncorrectable determination unit 7 determines that the 2-bit error candidate is correctable. The uncorrectable determination unit 7 outputs the syndrome patterns S1 and S3 and the determination result of correctability to the degenerate normalization root acquisition unit 8. If the uncorrectable determination unit 7 determines that the 2-bit error candidate is correctable, the degenerate normalization root acquisition unit 8 obtains a root y from a degenerate normalization root table 8a whose address is a parameter P1 obtained by degenerating the normalization parameter P.

[0036] FIG. 4 is a diagram showing an example of the degenerate normalization root table 8a used by the degenerate normalization root acquisition unit 8 included in the error correction device 20 of the first embodiment. The degenerate normalization root table 8a shown in FIG. 4 is a table for a 7-bit parameter P1 obtained by excluding the 5th bit from the LSB of the normalization parameter P from the table shown in FIG. 3. The degenerate normalization root acquisition unit 8 outputs a root y from the degenerate normalization root table 8a shown in FIG. 4 (step ST11). Note that in FIG. 2, the degenerate normalization root table 8a is represented as {"table with 7-bit address (P1) of Adr[7:6], Adr[4:0]}". The degenerate normalization root acquisition unit 8 outputs the root y and the syndrome patterns S1 and S3 to the 2-bit error position calculation unit 9. When the correction unacceptability determination unit 7 determines that the 2-bit error candidate is correctable, the root y output from the degenerate normalization root acquisition unit 8 is expressed as y=α i / (α i +α j ) In this way, the degenerate normalized root acquisition unit 8 can obtain the normalized root y for a 2-bit error by using the parameter P1 obtained by degenerating the normalization parameter P by 1 bit.

[0037] The 2-bit error position calculation unit 9 calculates an element of a Galois field indicating a 2-bit error position by using the root y acquired from the degenerate normalized root acquisition unit 8 and the syndrome patterns S1 and S3. Specifically, the 2-bit error position calculation unit 9 calculates an element of a Galois field indicating a 2-bit error position, X1=α i =y·S1,X2=α j=X1+S1 is calculated (step ST12) and output to the selection unit 10. Note that "·" indicates multiplication on the Galois field.

[0038] The selection unit 10 performs a selection process on the calculation result acquired from the decision result processing unit 3 or the double-bit error candidate error correction unit 5 (step ST13). When the selection unit 10 acquires the Galois field element X1=S1 indicating the single-bit error position from the single-bit error correction calculation unit 4 of the decision result processing unit 3, the selection unit 10 outputs the Galois field element X1=S1 indicating the single-bit error position to the error position conversion unit 11. The selection unit 10 then selects the Galois field element X1=α indicating the double-bit error position from the double-bit error position calculation unit 9 of the double-bit error candidate error correction unit 5. i =y·S1,X2=α j If we obtain =X1+S1, the Galois field element X1=α i =y·S1,X2=α j =X1+S1 is output to the error position conversion unit 11.

[0039] The error position converter 11 selects, from the selector 10, an element of the Galois field X1=S1 indicating a one-bit error position, or an element of the Galois field X1=α i =y·S1,X2=α j If =X1+S1 is acquired, the error position conversion unit 11 converts the element of the Galois field indicating the error position into an error position using the error position conversion table 11a, and outputs the error position obtained by the conversion to the correction unit 13. Note that even if it is determined that there is no error or that correction is impossible, the error position conversion unit 11 can perform conversion processing for positions other than the error position target by using the error position conversion table 11a.

[0040] The correction unit 13 corrects the corresponding bit of the received sequence delayed by the delay unit 12 based on the error position obtained from the error position conversion unit 11, i.e., inverts the corresponding bit to complete the correction, and outputs it.

[0041] In this way, in the error correction device 20, when the error number determination unit 2 determines that an error is a 2-bit error candidate, the 2-bit error candidate error correction unit 5 calculates a normalization parameter P, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error locator polynomial, based on the syndrome patterns S1 and S3. The 2-bit error candidate error correction unit 5 excludes a normalization parameter P for which it is determined that a 2-bit error cannot be corrected from the normalization parameters P, and obtains a normalized root y for the 2-bit error using a parameter P1 obtained by degenerating the normalization parameter P by 1 bit. Specifically, the 2-bit error candidate error correction unit 5 calculates a normalized root y for the 2-bit error using a primitive polynomial X 8 +X 4 +X 3 +X 2 When +1 is used, if the 5th bit from the LSB is 1 when the LSB is set as the 0th bit in the normalized 8-bit normalization parameter P, it is determined that a 2-bit error cannot be corrected, and the normalized root y is found using a parameter P1 that is degenerated by deleting the 5th bit from the LSB from the normalization parameter P.

[0042] Next, the hardware configuration of the error correction device 20 will be described. In the error correction device 20, the syndrome generation unit 1, the error number determination unit 2, the determination result processing unit 3, the 2-bit error candidate error correction unit 5, the selection unit 10, the error position conversion unit 11, the delay unit 12, and the correction unit 13 are realized by processing circuits. The processing circuit may be a processor and memory that executes a program stored in a memory, or may be dedicated hardware. The processing circuit is also called a control circuit.

[0043] FIG. 5 is a diagram showing a configuration example of a processing circuit 90 in the case where the processing circuit realizing the error correction device 20 according to the first embodiment is configured with a processor 91 and a memory 92. The processing circuit 90 shown in FIG. 5 is a control circuit and includes a processor 91 and a memory 92. When the processing circuit 90 is configured with the processor 91 and the memory 92, each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware. The software or firmware is described as a program and stored in the memory 92. In the processing circuit 90, each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, the processing circuit 90 includes a memory 92 for storing a program that results in the processing of the error correction device 20 being executed. This program can also be said to be a program for causing the error correction device 20 to execute each function realized by the processing circuit 90. This program may be provided by a storage medium in which the program is stored, or may be provided by other means such as a communication medium.

[0044] It can also be said that the above program is a program executed by the error correction device 20: a first step in which the syndrome generation unit 1 generates syndrome patterns S1, S3 from the received sequence; a second step in which the error number determination unit 2 determines the number of bit errors in the received sequence based on the syndrome patterns S1, S3; and a third step in which, if the error number determination unit 2 determines that a double-bit error is a candidate, the double-bit error candidate error correction unit 5 calculates a normalization parameter P, which is a constant term and a normalized parameter of a normalized polynomial obtained by normalizing a quadratic error locator polynomial, based on the syndrome patterns S1, S3, excludes from the normalization parameters P the normalization parameters P that are determined to be unable to correct double-bit errors, and obtains a normalized root y for the double-bit errors by using a parameter P1 obtained by degenerating the normalization parameter P by one bit.

[0045] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. Also, the memory 92 is, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), an EEPROM (Electrically EPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD (Digital Versatile Disc), etc.

[0046] Fig. 6 is a diagram showing an example of a processing circuit 93 in the case where the processing circuit for realizing the error correction device 20 according to the first embodiment is configured with dedicated hardware. The processing circuit 93 shown in Fig. 6 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination of these. The processing circuit may be partly realized with dedicated hardware and partly realized with software or firmware. In this way, the processing circuit can realize each of the above-mentioned functions by dedicated hardware, software, firmware, or a combination of these.

[0047] As described above, according to this embodiment, in processing a double-bit error correction candidate, the error correction device 20 determines in advance that correction is impossible using the normalization parameter P, generates a parameter P1 by reducing the input address by one bit from the normalization parameter P through simple processing, and obtains the root y based on the parameter P1. As a result, the error correction device 20 can obtain the root y using a table that is half the size compared to the case where the root y is obtained using the normalization parameter P, and the circuit scale can be reduced.

[0048] In this embodiment, a BCH code with a code length of 255 bits and an information bit length of 239 bits has been used as an example, but similar processing can also be performed on a 2-bit correction, 3-bit error detection BCH code with an information bit length of 238 bits by adding 1 parity bit.

[0049] Similar processing is also possible for an extended BCH code with 2-bit correction and 3-bit error detection, with an increased parity bit of 1, resulting in a code length of 256 bits and an information bit length of 239 bits.

[0050] Further, even in the case of shortened codes in which the information bit length is shortened, the error position conversion unit 11 needs to perform additional processing for determining whether correction is impossible, but similar processing is possible.

[0051] Embodiment 2 In the first embodiment, the error correction device 20 is a Galois field GF(2 8 ) in an extension field on which a primitive polynomial X 8 +X 4 +X 3 +X 2For a 2-bit error correction candidate in a BCH code with a code length of 255 bits and an information bit length of 239 bits, consisting of +1, it is determined in advance from the normalization parameter P that it is not possible to correct, and the root y is found from the degenerate normalization root table 8a with the table size halved, with the parameter P1 degenerated by 1 bit by simple processing as the address. Although the error correction device 20 can use the degenerate normalization root table with the table size halved for other primitive polynomials as well, when generating the parameter P1 degenerated by 1 bit from the normalization parameter P, whether it can be generated by simple processing varies depending on the primitive polynomial used.

[0052] For example, in the extension field GF(2 16 ) primitive polynomial X 16 +X 12 +X 3 Assume +X+1. When normalization parameter P=0 and P is a 16-bit address, the table that outputs the root y has 65536 words in 16-bit output. However, when the hexadecimal representation is 2000-2FFF, 3000-3FFF, 6000-6FFF, 7000-7FFF, 8000-8FFF, 9000-9FFF, C000-CFFF, or D000-DFFF, the 16-bit root y is all 0 and cannot be corrected. Therefore, the correction unacceptability determination unit 7 of the error correction device 20 performs an exclusive OR operation between the MSB (Most Significant Bit) and the second bit from the MSB, that is, the 13th bit from the LSB when the LSB is the 0th bit, and if the bit is 1, it is excluded from the 2-bit correction process in advance as being unacceptable for correction. In the following description, the MSB may be referred to as the most significant bit.

[0053] The degenerate normalized root acquisition unit 8 of the error correction device 20 can obtain the root y from the 15-bit parameter P1 excluding the MSB of the normalization parameter P by using a degenerate normalized root table 8a in which the root y data of A000 to BFFF, where the root y is non-zero with the normalization parameter P, is moved to the root y output of 2000 to 3FFF, and the root y data of E000 to FFFF, where the root y is non-zero with the normalization parameter P, is moved to the root y output of 6000 to 7FFF.

[0054] In this way, the double-bit error candidate error correction unit 5 is configured to correct the double-bit error candidate 16 ) primitive polynomial X 16 +X 12 +X 3 When +X+1 is used, if the exclusive OR of the 13th bit from the LSB and the MSB is 1 when the LSB is set as the 0th bit in the normalized 16-bit normalization parameter P, it is determined that the 2-bit error is uncorrectable, and the normalized root y is found using a parameter P1 that is degenerated by deleting the MSB from the normalization parameter P.

[0055] As described above, according to this embodiment, the error correction device 20 is a Galois field extension field GF(2 16 ) primitive polynomial X 16 +X 12 +X 3 In processing the +X+1 2-bit error correction candidate, the normalization parameter P is used to determine in advance whether correction is possible, and a parameter P1 is generated by reducing the input address by 1 bit from the normalization parameter P through simple processing, and the root y is obtained based on the parameter P1. This allows the error correction device 20 to obtain the root y using a table that is half the size compared to the case where the root y is obtained using the normalization parameter P, thereby reducing the circuit scale.

[0056] The error correction device 20 can be used in various extension fields GF(2 n) is used, as in the first or second embodiment, it is determined in advance that correction is impossible using the normalization parameter P, and a parameter P1 is generated by reducing the input address by one bit from the normalization parameter P using a simple process. The root y is then calculated based on the parameter P1. Compared to the case where the root y is calculated using the normalization parameter P, this makes it possible to calculate the root y using a table that is half the size, thereby reducing the circuit scale.

[0057] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or the embodiments may be combined with each other. Also, parts of the configurations may be omitted or modified without departing from the spirit of the invention. [Explanation of symbols]

[0058] 1 syndrome generation unit, 2 error number determination unit, 3 determination result processing unit, 4 1-bit error correction calculation unit, 5 2-bit error candidate error correction unit, 6 2-bit error correction normalization calculation unit, 7 correction uncorrectable determination unit, 8 degenerate normalization root acquisition unit, 8a degenerate normalization root table, 9 2-bit error position calculation unit, 10 selection unit, 11 error position conversion unit, 11a error position conversion table, 12 delay unit, 13 correction unit, 20 error correction device, 90, 93 processing circuit, 91 processor, 92 memory.

Claims

1. An error correction device that performs double-bit error correction decoding using a block error correction code, a syndrome generator for generating a syndrome pattern from a received sequence; an error number determination unit that determines the number of bit errors in the received sequence based on the syndrome pattern; a double-bit error candidate error correction unit that, when it is determined by the error number determination unit that there is a double-bit error and that there is a possibility of correction, calculates a first parameter, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error locator polynomial based on the syndrome pattern, excludes a first parameter that is determined to be uncorrectable for the double-bit error from the first parameters, and uses a second parameter obtained by degenerating the first parameter by one bit to find a normalized root for the double-bit error; An error correction device comprising:

2. The two-bit error candidate error correction unit corrects a primitive polynomial X ８ +X ４ +X ３ +X ２ In the case where +1 is used, when at least the least significant bit in the normalized 8-bit first parameter is set to 0th bit and the 5th bit from the least significant bit is 1, it is determined that the 2-bit error is uncorrectable, and the normalized root is obtained by using the second parameter obtained by degenerating the first parameter by deleting the least significant bit from the 5th bit.

2. The error correction device according to claim 1.

3. The two-bit error candidate error correction unit corrects a primitive polynomial X １６ +X １２ +X ３ In the case where +X+1 is used, when an exclusive OR between the 13th bit from the least significant bit and the most significant bit in the normalized 16-bit first parameter is 1 when the least significant bit is set to the 0th bit, the 2-bit error is determined to be uncorrectable, and the normalized root is found using the second parameter obtained by degenerating the first parameter by deleting the most significant bit.

2. The error correction device according to claim 1.

4. A control circuit for controlling an error correction device that performs double-bit error correction decoding using a block error correction code, comprising: Generate syndrome patterns from the received sequence, determining the number of bit errors in the received sequence based on the syndrome pattern; when it is determined that there is a 2-bit error and that it is possible to correct it, calculating a first parameter, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error locator polynomial, based on the syndrome pattern, excluding a first parameter for which it is determined that the 2-bit error is uncorrectable from the first parameters, and finding a normalized root for the 2-bit error by using a second parameter obtained by degenerating the first parameter by 1 bit; A control circuit that causes the error correction device to carry out the above.

5. A storage medium storing a program for controlling an error correction device that performs double-bit error correction decoding using a block error correction code, The program is Generate syndrome patterns from the received sequence, determining the number of bit errors in the received sequence based on the syndrome pattern; when it is determined that there is a 2-bit error and that it is possible to correct it, calculating a first parameter, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error locator polynomial, based on the syndrome pattern, excluding a first parameter for which it is determined that the 2-bit error is uncorrectable from the first parameters, and finding a normalized root for the 2-bit error by using a second parameter obtained by degenerating the first parameter by 1 bit; A storage medium that causes the error correction device to carry out the above-mentioned.

6. An error correction method for an error correction device that performs double-bit error correction decoding using a block error correction code, comprising: a first step of a syndrome generator generating a syndrome pattern from a received sequence; a second step of determining the number of bit errors in the received sequence based on the syndrome pattern by an error number determining unit; a third step of a double-bit error candidate error correction unit, when it is determined by the error number determination unit that there is a double-bit error and that there is a possibility of correction, calculating a first parameter, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error locator polynomial, based on the syndrome pattern, excluding a first parameter that is determined to be unable to correct the double-bit error from the first parameters, and using a second parameter obtained by degenerating the first parameter by one bit, to find a normalized root for the double-bit error; 13. An error correction method comprising:

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