Distributing the current of the device array to the segment mirror

Abstract

A circuit is provided that includes an array of resistive elements to distribute a sum-of-products current across segment mirrors, the array including rows and columns and first stage current mirrors, each of the first stage current mirrors electrically coupled to a segment, the segments including a columnar subset of the resistive elements, the array providing a vector of current outputs equal to an analog vector-matrix product between a vector of voltage inputs to the array and a matrix of analog resistor weights in the array, the voltage inputs encoding the vector of analog input values, each row of resistive elements corresponding to a particular voltage input, determining a score for each of the rows, determining a ranking of the rows of the array according to the score for each row, and mapping each row to a segment according to the ranking.

Description

[Technical field]

[0001] The present invention relates generally to balancing the distribution of multiply-accumulate (MAC) currents among segment mirrors, and more particularly to distributing MAC currents across segment mirrors by shuffling the weights and enablements of MAC operations associated with the currents. [Background technology]

[0002] Charge-based analog multiply-accumulate (MAC) operations may require storing many (e.g., one for every 512 MAC rows) "multiplication" currents on edge capacitors. The storage operation may be done on a segment-by-segment basis (e.g., 64 rows per segment), with each segment current scaled down using a current mirror. By scaling down the entire MAC current to the segment current using a current mirror, smaller edge capacitors can be used to store the segment currents (reducing the area of ​​the capacitor element), avoiding exceeding the dynamic range of voltages that can be usefully read out of the capacitor. Summary of the Invention

[0003] The following provides a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of any particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description presented later. In one or more embodiments described herein, a device, system, computer-implemented method, apparatus, or computer program product, or combination thereof, enables a more even distribution of MAC currents by shuffling weights and associated currents stored in the MAC.

[0004] Aspects of the present invention disclose methods, systems, and computer-readable media related to distributing multiply-accumulate currents across segment mirrors by providing a circuit including an array of resistive elements, the array including rows and columns and a first stage current mirror, each of the first stage current mirrors electrically coupled to a segment, the segment including a columnar subset of the resistive elements, the array providing a vector of current outputs equal to an analog vector-matrix product between a vector of voltage inputs to the array and a matrix of analog resistor weights in the array, the voltage inputs encoding a vector of analog input values, each row of resistive elements corresponding to a particular set of input voltages, determining a score for each of the rows, determining a rank for the rows of the array according to the score, and mapping each row to a segment according to the rank.

[0005] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of several embodiments of the present invention in the accompanying drawings, in which like references generally refer to like components in the embodiments of the present invention. [Brief description of the drawings]

[0006] [Figure 1] 1 provides a schematic diagram of a crossbar memory device according to an embodiment of the present invention. [Diagram 2] 1 provides a schematic diagram of a computing environment according to one embodiment of the present invention. [Diagram 3] 1 provides a flow chart illustrating a sequence of operations according to one embodiment of the present invention. [Figure 4] 1 illustrates a cloud computing environment in accordance with an embodiment of the present invention. [Diagram 5] 3 illustrates an abstraction model layer according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Some embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, in which embodiments of the present invention are shown, however the present invention can be embodied in various forms and should not be construed as being limited to the embodiments disclosed herein.

[0008] An artificial neural network (ANN) is a distributed computing system that contains a large number of neurons interconnected through connection points commonly called synapses. Each synapse encodes the strength of the connection between the output of one neuron and the input of another neuron. The output of each neuron is determined by the total inputs it receives from the other neurons connected to it. Thus, the output of a given neuron is based on the output of the neurons connected to it from the immediately preceding layer and the strength of the connection, which is determined by the synaptic weights. ANNs are trained to solve a particular problem (e.g., pattern recognition) by adjusting the synaptic weights so that a particular class of input produces a desired output.

[0009] ANNs may be implemented in various types of hardware, including crossbar arrays (also called crosspoint arrays or crosswire arrays). A basic crossbar array configuration includes a set of conductive row wires and a set of conductive column wires formed to cross the set of conductive row wires. The intersections of the two sets of wires are separated by crosspoint devices. The crosspoint devices act as weighted connections between the neurons of the ANN.

[0010] 1 illustrates an exemplary non-volatile memory based crossbar array or memory. Row lines 102 cross over column lines 103 to form a number of junctions 101. A resistive memory element 104, such as a non-volatile memory, is coupled between one of the row lines 102 and one of the column lines 103 and disposed in series with a selector 105 at each of the junctions 101. The selector may be a volatile switch or a transistor, of various types known in the art.

[0011] Mapping an exemplary synapse of a neural network onto the crossbar array of FIG. 1, the currents at the outputs 106, 107 of each junction are given as I=G^+V(t) and I=G^-V(t), where G^+ and G^- correspond to the w_ij of a given resistive memory, and V(t) corresponds to the x_i of a given input row line. In this example, the column lines are arranged in adjacent conductance pairs 108. The total output 109, 110 is therefore given by I=ΣG^+V(t) for each conductance pair 108. + V and I = ΣG - V. Segment current mirrors M1, M2, M3 connect the summed output to edge capacitors (not shown).

[0012] In such crossbar memories, the total output current can be very large, and large voltage drops and electromigration can impair the functionality of the array. Furthermore, downstream peripheral circuitry must have a very high dynamic range to sense a single input device or crosspoint (rather than the total read current from many devices).

[0013] Especially in neuromorphic and other applications such as vector-matrix multiplication, crossbar memories do not adapt well to situations where the input signal current from one device is already measurably large. In such a situation, the total signal from all such devices is so large that it uses up all reasonable capacitance in the periphery. Sub-unit current gain can be applied at the periphery before this current is diverted to the integrating capacitors, but further problems arise. For example, the large total current can overload the row and column lines, causing undesirable voltage drops. In some cases, electromigration destruction may occur.

[0014] The use of segment current mirrors allows the overall MAC current to be split into more manageable current segments. By performing the accumulation operation in segments, smaller edge capacitors can be used, reducing the spatial requirements of the capacitor elements and the possibility of exceeding the dynamic range of the capacitor voltage. The segment mirrors may be coupled in a parallel circuit configuration, which may introduce hardware constraints on the performance of the segmented accumulation operation. Such constraints may include nonlinearities and capacitor voltage range constraints, which may lead to inaccuracies in the analog MAC under operating conditions where the current distribution across the set of accumulating segment current mirrors lacks uniformity. The disclosed embodiments allow for shuffling of weights stored in the MAC associated with the accumulating segment currents. The shuffling of weights results in an overall accumulated operation current that is more evenly distributed across the set of accumulating segment current mirrors.

[0015] In one embodiment, the method determines an index order for mapping rows of a matrix of values ​​to rows of resistive elements of a MAC structure. In this embodiment, the matrix of values ​​may be related to weightings of network nodes of a trained neural network, with each column of the matrix corresponding to a synaptic node weight of one neuron of a layer of the multi-layer neural network. In providing the trained neural network for use, the method seeks to map the synaptic node weights derived during network training epochs to hardware circuitry, with elements of the circuitry taking on values ​​associated with their respective node weights.

[0016] In one embodiment, the circuit includes rows and columns of resistive elements, such as resistive non-volatile memory elements, phase change memory, electrochemical memory, spin-transfer torque RAM, resistive RAM, conductive bridge RAM, and similar resistive structures. The method may map analog values ​​associated with node weights to the resistive memory elements, or may map digitized values ​​associated with the analog weights to the resistive memory elements.

[0017] In training a neural network, node weight values ​​are determined for each node in each layer of the network. The node weights are adjusted during training epochs to minimize the network's loss function. Once training is complete, the node weight values ​​are fixed and are then used to evaluate input test data. The set of node weights for the network is implemented as an array of values.

[0018] Training the neural network also results in an array input vector that contains a value associated with each row of the array of weights. The vector values ​​contain row activation values ​​for each row of the array of weights. In the device, the array input is translated as row input voltages, and the voltages are applied to all resistive elements in the row, generating column currents through each resistive element. This device structure causes each resistive element in a column to add a column current that depends on the element's particular weight (resistance) and the row's particular activation (voltage), resulting in an aggregated current. In a device with 512 rows, the 512 individual column currents are aggregated together, potentially resulting in an overly large aggregated column-wise current overall.

[0019] To reduce the overall aggregated column-wise current for any single column of resistive elements, the hardware device may have column-wise segments, with the hardware design subdividing each column into multiple segments of resistive elements. The individual column-wise segment currents are drawn without further aggregation. As an example, a column of 512 resistive elements may be divided into eight segments, with each segment including 64 resistive elements. The hardware may include a first stage current mirror element associated with each segment and connecting the segment to an edge capacitor to receive the aggregated segment current upon application of an appropriate row input voltage. In this example, the device draws eight aggregated column-wise segment currents for each column, with one current corresponding to each of the column-wise segments for each column in the first stage current mirror. A second stage current mirror may be utilized to determine whether current is added to or subtracted from the associated edge capacitor.

[0020] In mapping node weights to the circuit, the method attempts to balance the aggregated segment currents across the set of segments in each column to prevent the accumulation of excessive aggregated segment currents for any particular segment. Preventing excess currents reduces the likelihood that the current mirror circuitry will enter a more nonlinear region, which can adversely affect the MAC computation.

[0021] In one embodiment, one or more components of the system may employ hardware and / or software to solve problems that are highly technical in nature (e.g., scoring rows of an array of values ​​according to one or more of array row weights and array row activation input values, ranking the scored rows according to the scores, and mapping the ranked rows to rows of a device to balance column-wise segment currents across columns of resistive elements of the device). These solutions are not abstract and cannot be performed as a series of mental acts by a human being due to the processing power required to facilitate, for example, MAC current balancing. Furthermore, some of the processing performed may be performed by a computer dedicated to performing defined tasks related to memory current balancing. For example, a dedicated computer may be employed to accomplish tasks related to MAC device current balancing, etc.

[0022] In one embodiment, the hardware device includes an array of resistive elements in a crossbar arrangement of rows and columns. As an example, the device can include an array of 512 rows, with each row including 512 columns. The current mirror elements subdivide the set of resistive elements in each of the columns into subsets or segments of resistive elements. As an example, a first stage current mirror divides the 512 rows of each column into 8 segments of 64 resistive elements for each segment. As discussed above, the resistive elements of the array can include resistive elements such as resistive non-volatile memory elements, phase change memory, electrochemical memory, spin transfer torque RAM, resistive RAM, conductive bridge RAM, and similar resistive structures that can carry an analog or digital mapping of resistive values ​​corresponding to the array of values. As an example, the array of resistive elements can carry a mapping of values ​​ranging from 100 nanosiemens to 10 microsiemens, which corresponds to the range of values ​​of the array in terms of conductance (resistance). Such an array of values ​​can then correspond to the weights of a trained neural network.

[0023] The vector matrix product obtained by applying a vector of voltage inputs to the values ​​of the resistive elements of the array represents a vector of current outputs. The vector of voltage inputs encodes a vector of analog input values ​​(e.g., activation values ​​of a neural network). The vector of voltage inputs includes distinct voltage input values ​​for each row of the resistive element array. In one embodiment, the voltage input values ​​of the vector correspond to column-wise current outputs from another resistive element array upstream in the circuit.

[0024] In one embodiment, the method maps synaptic weights of a layer of a trained neural network to resistive elements of an array of devices. Each resistive element is mapped to a single synaptic weight in the layer of trained weights. The method converts the weight values ​​to conductance (resistance) values ​​within the dynamic range of the resistive elements of the devices. The method further converts the range of activation values ​​of the network layers to input voltages for each layer, generating a vector of input voltages for the array of devices.

[0025] After mapping the input array values ​​to device resistive elements and the row activation values ​​to a voltage input vector, the method determines a score for each row of values, which may depend on the voltage input value for the row, the sum of the resistance values ​​of the resistive elements across the row, or a combination of voltage and resistance (the sum of the currents that result from applying the row input voltage to each resistive element in the row).

[0026] In response to determining the row scores, the method ranks the rows of the array from highest to lowest according to the determined scores. The method then applies a sorting algorithm to the ranked list of row scores to sort the list into a set of column-wise segments of the array to achieve a balanced total row score for each segment. In one embodiment, the sorting algorithm places the highest ranked row in the first segment, the next highest ranked row in the next segment, and the highest ranked N rows in the Nth segment. To balance the total row scores across the Nth segment, the algorithm reverses the order of placement and proceeds until the N+1th row is placed in the Nth segment and the 2Nth row is placed in the first segment. The method indexes the rows into the Nth segment until all rows are placed in the segments. After the initial sort, the method determines a total row score for each segment and also determines a total column-wise current for each segment in each column of the array of resistive elements. After these determinations, the method re-sorts the rows to reduce discrepancies between the total segment row scores, or the total column-wise current, or both. When sorting, the algorithm considers the effect of swapping any pair of rows between segments where there is a difference between the total row scores or total columnwise segment currents. Because swapping rows can affect the total columnwise segment currents for each column in each segment, the method considers the effect on all columnwise segment currents across the two segments that contribute rows to the swap.

[0027] In one embodiment, the method considers the difference between the total row scores for the two segments, the relative contribution of each row of each segment to the total row score for that segment, the total column-wise segment current for each column of each segment, and the relative contribution of each column to their calculated or measured aggregated currents of the column-wise segments. In one embodiment, the method considers rows of two segments at a time when balancing the aggregated row scores and aggregated column-wise segment currents. In one embodiment, the method considers all rows and columns of all segments when identifying rows suitable for swapping to reduce the difference in the aggregated column-wise segment currents, or the aggregated segment row scores, or both. The method may attempt to balance the column-wise segment currents, the row scores, or both. In one embodiment, the method prioritizes balancing the aggregated column-wise segment currents over balancing the aggregated segment row scores.

[0028] In one embodiment, the method maps resistance values ​​from a transformation of node weights to resistive elements of the device, applies the transformed activation inputs as row voltages, and measures the column-wise segment currents for each column of the device array. In one embodiment, the method proceeds virtually, calculating the column-wise segment currents as a function of the input voltages and the resistances of the resistive elements without actually applying voltages to the device.

[0029] In one embodiment, the method derives a vector of input voltages for rows of an array of resistive elements from input data or test data presented for analysis by a trained network implemented in device hardware. In this embodiment, the input data may include analog values, or digital data converted to analog values ​​by a method using a digital-to-analog converter. The input data may include images, strings, documents, etc., that are presented to the network for classification, etc. The method applies a vector of values ​​corresponding to the input data as voltages to an array of resistive elements that corresponds to an input layer of the neural network. In one embodiment, after mapping the weights of the trained network to the hardware circuitry, the input data is passed to the hardware for evaluation. The vector associated with each input data object, such as a document, string, image, etc., changes as the input data changes.

[0030] In one embodiment, the method derives a vector of input voltages for each layer following the input layer in response to the column-wise currents of the preceding layer. The column-wise currents of the first upstream layer determine the row input voltages of the second downstream layer. The column-wise currents from the input layer determine the row input voltages of the next layer of the input layer, and so on. Each column of the preceding layer is mapped to a corresponding row of the next layer. The currents from each column determine the input voltages of the corresponding layer. In this embodiment, once the method has mapped the ranked rows of resistance values ​​associated with the input data array, the method maps the columns of the preceding array of resistive elements to correspond to the mapping of the ranked rows. As an example, the method may rank rows of resistance values ​​to row 64 of the array of resistive elements, and the method may simultaneously map columns from the preceding array of resistive elements, or values ​​from the vector of input data values, to correspond to row 64 of the array of resistive elements. Due to the simultaneous mapping of rows and associated preceding columns, the method maintains the relationship between the rows and associated row input voltages. Swapping rows changes the order of the column-wise elements, which may change the total segment current and the total segment row score. Swapping column positions to match downstream row mappings does not change the scores of rows, since the resistive elements of the columns remain in the same order when the columns are swapped. In use, the method maps vectors derived from input data to rows of an input layer circuit. The values ​​of the vectors from the input layer are specific to the input data. The corresponding output currents from the input layer (and each subsequent layer) are also specific to the input data. Row voltages change across the device in response to changes in the input data.

[0031] For some network structures, such as long-short-term memory network structures, the architecture of the network includes multiple downstream layers that receive input from a single upstream layer. For such network architectures, the corresponding hardware device also includes multiple tiles or arrays of resistive elements corresponding to the required multiple layers of the network node. For such device structures, the method horizontally maps the ordered rows associated with the multiple concatenated tiles, thereby generating the required set of identical tile mappings, all of which receive the same voltage input from the single upstream layer. As described above, since the method maps rows corresponding to the data array to rows of the device, the method also maps columns associated with the upstream tiles to inputs of the rows of the downstream tiles.

[0032] As an example of the disclosed sorting method, the set of current vectors for rows 0-22 of an array are originally presented in the order 0-22. After scoring the rows as described above, the order of the rows is reordered from highest to lowest score from 0-22, resulting in 10, 8, 2, 15, 1, 19, 3, 4, 21, 14, 5, 0, 20, 9, 17, 12, 6, 13, 16, 7, 11, 18, with row 10 being the highest score and row 18 being the lowest score. The rows are then sorted into segments to balance the overall current for each segment. In this example, the 22 rows are sorted into 8 segments. Each of the 8 segments has 4 rows. By sorting the 22 rows by score to balance the segment currents, the distribution order of rows across the eight segments is: Segment 1: rows 10, 12, 6; Segment 2: rows 8, 17, 13; Segment 3: rows 2, 9, 18; Segment 4: rows 15, 20, 7; Segment 5: rows 1, 0, 11; Segment 6: rows 19, 5, 18; Segment 7: rows 3, 4; Segment 8: rows 4, 21. Applying the sorting process to the circuit shown in Figure 1 changes the resistance value of the variable resistors 104 in each row 102 of the circuit. The hardware is not changed, only the resistance value of the variable resistors in each row is changed.

[0033] FIG. 2 provides a schematic diagram illustrating exemplary network resources associated with the implementation of the disclosed invention. The network resources may perform the steps of the disclosed method by evaluating input data arrays associated with the network weightings and mapping rows of weighting values ​​to rows of resistive elements in a hardware device while simultaneously mapping columns from an upstream circuit tile or array to correspond to the mapping of downstream tile rows. Mapping rows of a complex neural network to a hardware device may involve mapping hundreds or thousands of rows per layer across multiple layers while simultaneously mapping columns across corresponding upstream arrays. The calculations required for such mapping may require the use of large amounts of computing power and may require networked resources, including edge cloud or cloud resources, to efficiently accomplish the mapping in a reasonable amount of time.

[0034] The present invention may be implemented in any processor of the disclosed elements that processes instruction streams. As shown in the figure, a networked client device 210 wirelessly connects to a server subsystem 202. A client device 204 wirelessly connects to the server subsystem 202 via a network 214. The client devices 204 and 210 include a current distribution program (not shown) along with sufficient computing resources (processor, memory, network communication hardware) to execute the program. As shown in FIG. 2, the server subsystem 202 includes a server computer 250. FIG. 2 is a block diagram of components of the server computer 250 in a networked computer system 2000 according to an embodiment of the present invention. It should be understood that FIG. 2 provides only an example of one implementation and does not suggest any limitation with respect to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

[0035] Server computer 250 may include processor 254, memory 258, persistent storage 270, communication unit 252, input / output (I / O) interface 256, and communication fabric 240. Communications fabric 240 provides communication between cache 262, memory 258, persistent storage 270, communication unit 252, and input / output (I / O) interface 256. Communications fabric 240 may be implemented with any architecture designed to pass data and / or control information between processors (such as microprocessors, communications and network processors), system memory, peripheral devices, and any other hardware components in the system. For example, communications fabric 240 may be implemented with one or more buses.

[0036] Memory 258 and persistent storage 270 are computer-readable storage media. In this embodiment, memory 258 includes random access memory (RAM) 260. In general, memory 258 may include any suitable volatile or non-volatile computer-readable storage medium. Cache 262 is a fast memory that improves performance of processor 254 by retaining recently accessed data and near recently accessed data from memory 258.

[0037] Program instructions and data used to implement embodiments of the present invention (e.g., current balancing program 275) may be stored in persistent storage 270 for execution and / or access by each of one or more processors 254 of server computer 250 via cache 262. In this embodiment, persistent storage 270 includes a magnetic hard disk drive. Alternatively or in addition to a magnetic hard disk, persistent storage 270 may include a solid state hard drive, a semiconductor memory device, a ROM, an erasable programmable ROM (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0038] The media used by persistent storage 270 may be removable. For example, persistent storage 270 may use a removable hard drive. Other examples include optical disks, magnetic disks, thumb drives, and smart cards, which are inserted into a drive for transfer to another computer-readable storage medium that is also part of persistent storage 270.

[0039] In these examples, the communications unit 252 enables communication with other data processing systems or devices, including resources of the client computing devices 204 and 210. In these examples, the communications unit 252 includes one or more network interface cards. The communications unit 252 may enable communication using either or both physical and wireless communications links. Software balancing programs and other programs and data used to implement the present invention may be downloaded to persistent storage 270 of the server computer 250 via the communications unit 252.

[0040] The I / O interface 256 allows for input and output of data to and from other devices connectable to the server computer 250. For example, the I / O interface 256 allows for connection to external devices 290, such as one or more target hardware devices including a keyboard, a keypad, a touch screen, a microphone, a digital camera, an appropriate tile of resistive elements, or some other suitable input device, or both. The external devices 290 may also include portable computer-readable storage media, such as, for example, thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to implement embodiments of the present invention (e.g., the current balancing program 275 on the server computer 250) may be stored on such portable computer-readable storage media and loaded into the persistent storage 270 via the I / O interface 256. The I / O interface 256 also connects to a display 280.

[0041] Display 280 provides a mechanism for displaying data to a user and may be, for example, a computer monitor. Display 280 may also function as a touch screen, such as the display on a tablet computer.

[0042] 3 provides a flow chart 300 illustrating exemplary activities associated with practicing the present invention. After the program begins, at block 310, the current balancing program 275 method receives an array or matrix of values. In one embodiment, the values ​​are associated with the weights of the network layers of the trained neural network. The array can be viewed as an arrangement of rows and columns of the matrix of values. The method also receives an array vector of input values ​​associated with the array of values. The vector of input values ​​includes a value for each row of the array of values.

[0043] In block 320, the method of current balancing program 275 determines a score for each row of the received matrix values. The score for each row may be associated with the value of the element in the row, an input value for the row from an input vector, or a combination of vector and row value that is the sum of products of values ​​from each element of the row and the vector associated with the row.

[0044] At block 330, the method ranks the rows of the array according to the scores determined at block 320. The rows are ranked from highest score to lowest score. In one embodiment, the method determines the average total segment row score by summing the complete set of row scores and dividing the sum by the number of segments configured in the hardware device to which the method will map the array of values. In this embodiment, the method utilizes the average aggregated segment score as a target for balancing the segment total score as the method's sorting algorithm sorts the set of rows from the array of values ​​to the rows of the hardware device and segments.

[0045] At block 340, the method sorts the ranked rows and assigns or maps the rows to rows of resistor elements of the specified hardware circuit. The sorting algorithm balances the total segment row scores to reduce any differences between the total row scores of each segment of the hardware circuit. The method simultaneously maps columns of the preceding circuit to correspond to the mapping of the rows. For the input layer mapping, the method maps paths for input data to the circuit to match the mapping of the rows.

[0046] In one embodiment, the method maps rows of values ​​from multiple arrays to multiple hardware tiles of resistive elements. The arrays and tiles correspond to layers of a trained neural network. In one embodiment, the method maps rows of a single array to segments of multiple identical tiles to support the use of hardware designs in which a single upstream array of resistive elements passes its output as an input to multiple downstream tiles of resistive elements.

[0047] In one embodiment, the method sorts the rows through multiple iterations, with each iteration reducing the difference between the total segment currents of the device columns of resistive elements, the total segment row scores, or a combination thereof.

[0048] Although this disclosure includes detailed descriptions of cloud computing, implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention may be practiced in conjunction with any other type of computing environment now known or developed in the future.

[0049] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with a service provider. The cloud model may include at least five characteristics, at least three service models, and at least four implementation models.

[0050] The characteristics are as follows:

[0051] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time or network storage, automatically as needed, without the need for human interaction with the service provider.

[0052] Broad network access: Computing power is available over the network and can be accessed through standard mechanisms, facilitating use by heterogeneous thin- and thick-client platforms (e.g., cell phones, laptops, PDAs).

[0053] Resource Pooling: Computing resources from a provider are pooled and offered to multiple consumers using a multi-tenant model. Different physical and virtual resources are dynamically allocated and reallocated depending on demand. Consumers generally have no control or knowledge of the exact location of the resources provided to them, so there is a sense of location independence, although consumers may be able to determine location at a higher level of abstraction (e.g. country, state, data center).

[0054] Rapid elasticity: Computing capacity can be provisioned quickly and elastically, in some cases automatically, to scale out immediately and to be released quickly to scale in immediately. To the consumer, the computing capacity available for provisioning often appears unlimited and can be purchased at any time and in any quantity.

[0055] Metered Services: Cloud systems leverage metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user accounts) to automatically control and optimize resource usage. Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of the services utilized.

[0056] The service model is as follows:

[0057] Software as a Service (SaaS): The functionality offered to the consumer is the availability of a provider's applications running on a cloud infrastructure that can be accessed from a variety of client devices through a thin-client interface such as a web browser (e.g., webmail). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even the individual application functions, except for limited user-specific application configuration settings.

[0058] Platform as a Service (PaaS): The capability offered to the consumer is to deploy applications that the consumer creates or acquires using programming languages ​​and tools supported by the provider onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0059] Infrastructure as a Service (IaaS): The functionality offered to the consumer is the provision of processors, storage, networking, and other basic computing resources onto which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, and deployed applications, and may have partial control over some network components (e.g., host firewalls).

[0060] The deployment model is as follows:

[0061] Private Cloud: The cloud infrastructure is dedicated to a specific organization. It can be managed by that organization or a third party and can exist on-premise or off-premise.

[0062] Community Cloud: The cloud infrastructure is shared by multiple organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance). The cloud infrastructure can be managed by the organizations or a third party and can exist on-premise or off-premise.

[0063] Public cloud: The cloud infrastructure is available to the general public or large industry organizations and is owned by an organization that sells cloud services.

[0064] Hybrid Cloud: This cloud infrastructure combines two or more cloud models (private, community or public), each of which retains its inherent semantics but is bound together by standards or specific technologies that enable data and application portability (e.g. cloud bursting for load balancing between clouds).

[0065] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, low coupling, modularity and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0066] Referring now to FIG. 4, an exemplary cloud computing environment 50 is depicted. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10, to which local computing devices used by cloud consumers (e.g., PDA or cell phone 54A, desktop computer 54B, laptop computer 54C, or automobile computer system 54N, or combinations thereof, etc.) can communicate. The nodes 10 can communicate with each other. The nodes 10 can be physically or virtually grouped (not shown) in one or more networks, such as, for example, a private, community, public, or hybrid cloud, or combinations thereof, as described above. This allows the cloud computing environment 50 to provide infrastructure, platform, or software, or combinations thereof, as a service, for which the cloud consumer does not need to maintain resources on the local computing device. It should be understood that the types of computing devices 54A-N shown in FIG. 4 are merely exemplary, and that the computing nodes 10 and the cloud computing environment 50 can communicate with any type of electronic device over any type of network or network addressable connection (e.g., using a web browser), or both.

[0067] 5 illustrates a set of functional abstraction model layers provided by cloud computing environment 50 (FIG. 4). It should be understood in advance that the components, layers, and functions illustrated in FIG. 5 are merely exemplary, and embodiments of the present invention are not limited thereto. As illustrated, the following layers and corresponding functions are provided:

[0068] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, reduced instruction set computer (RISC) architecture based servers 62, servers 63, blade servers 64, storage devices 65, and networks and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0069] The virtualization layer 70 provides an abstraction layer from which the following virtual entities can be provided, for example: virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0070] By way of example, the management layer 80 may provide the following functions: Resource provisioning 81 allows dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 allows cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. By way of example, these resources may include application software licenses. Security allows for identification and verification of cloud consumers and tasks as well as protection for data and other resources. User portal 83 provides consumers and system administrators with access to the cloud computing environment. Service level management 84 allows for allocation and management of cloud computing resources such that requested service levels are met. Service level agreement (SLA) planning and fulfillment 85 allows for pre-arranging and procurement of anticipated future needs for cloud computing resources according to SLAs.

[0071] The workload layer 90 provides examples of functionality available to a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and current balancing programs 275.

[0072] The present invention may be a system, method or computer program product, or combination thereof, integrated at any possible level of technical detail. The present invention may be beneficially implemented in any single or parallel system that processes instruction streams. The computer program product may include a computer readable storage medium having stored thereon computer readable program instructions for causing a processor to carry out aspects of the present invention.

[0073] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROM, DVD, memory sticks, floppy disks, punch cards or ridges in grooves or other mechanically encoded devices with instructions recorded thereon, and suitable combinations thereof. As used herein, computer-readable storage medium or computer-readable storage device should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a wave guide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electric signal transmitted through a wire.

[0074] The computer-readable program instructions described herein can be downloaded from the computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network network, or a combination thereof). The network may be comprised of copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface of each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in the computer-readable storage medium within the respective computing / processing device.

[0075] The computer readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as the "C" programming language and similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, as a stand-alone software package, or partially on the user's computer. Alternatively, they may be executed partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the computer readable program instructions to perform aspects of the invention.

[0076] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0077] These computer readable program instructions can be provided to a general purpose computer, a processor of a special purpose computer or other programmable data processing apparatus to generate a machine, such that the instructions, executed via a processor of the computer or other programmable data processing apparatus, generate means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions can also be stored in a computer readable storage medium connectable to a computer, a programmable data processing apparatus, or other device or combination that functions in a particular way, such that the computer readable storage medium having the instructions stored thereon configures one of the products including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0078] Computer readable program instructions, such as instructions to perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams on a computer, other programmable apparatus, or other device, may also be loaded into a computer, other programmable data processing apparatus, or other device to perform a series of operational steps on the computer, other programmable apparatus, or other device to generate a computer-implemented process.

[0079] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of an instruction, which constitutes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions shown in the blocks may differ from the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special purpose hardware-based system that executes the specified functions or operations, or executes a combination of special purpose hardware and computer instructions.

[0080] In this specification, phrases such as "one embodiment," "an embodiment," "an example embodiment," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0081] The terms used herein are merely for the purpose of describing particular embodiments and are not intended to limit the present invention. In this specification, the singular forms "a", "an" and "the" are intended to include the plural, unless otherwise clear from the context. It will be further understood that as used herein, the terms "comprise" and / or "comprising" specify the presence of stated features, integers, steps, operations, elements or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof or combinations thereof.

[0082] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and variations are possible without departing from the scope of the present invention. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments described herein.

[0083] In a preferred embodiment of the present invention, a method is provided for balancing currents in a device including an array of resistive elements, the array including rows and columns and a first stage current mirror, each of the first stage current mirrors electrically coupled to a segment, the segment including a column-wise subset of resistive elements, the method comprising: using the array to determine a vector of current outputs equal to an analog vector matrix product between a vector of voltage inputs to the array and a matrix of analog resistor weights in the array, the voltage inputs encoding a vector of analog input values, each row of resistive elements corresponding to a particular voltage input; determining a score for each of the rows; determining a ranking of the rows of the array according to the score of each row; and mapping each row to a segment according to the ranking. Preferably, the voltage inputs are associated with columns of another circuit including an array of resistive elements arranged in rows and columns. Preferably, the resistive elements include non-volatile memory elements. Preferably, the resistive weights correspond to synaptic weights of a neural network. Preferably, the score of each row is determined using at least one of the resistance values ​​of the elements in that row or the voltage inputs applied to the resistive elements in that row. Preferably, the method further comprises assigning each row to the same segment of a plurality of identical circuits.

Claims

1. receiving, by one or more computer processors, an array of values ​​and associated vectors of array entries, the array including rows and columns; determining, by the one or more computer processors, a score for each row of the sequence; and determining, by the one or more computer processors, a ranking of the rows according to the score of each row; and mapping, by the one or more computer processors, the rows to a first circuit comprising an array of resistive elements according to the rank and column segment currents; 4. A computer-implemented method comprising:

2. The method of claim 1 , wherein the resistive element comprises a non-volatile memory element.

3. The method of claim 1 , wherein the array of values ​​comprises synaptic weights of a layer in a neural network.

4. 2. The method of claim 1, further comprising mapping, by the one or more computer processors, columns of a second circuit in response to the mapping of rows.

5. The method of claim 1 , wherein determining the score comprises determining the score as a function of at least one of an array row value and an associated array entry.

6. 2. The method of claim 1, further comprising: assigning, by the one or more computer processors, each row to an identical segment of a plurality of identical circuits.

7. 10. A computer program product for balancing currents in an apparatus, the computer program product comprising: one or more computer readable storage devices; and program instructions collectively stored on the one or more computer readable storage devices, the stored program instructions, when executed by one or more computer processors, causing the one or more computer processors to perform steps of a computer-implemented method according to any of claims 1 to 6.

8. 10. A computer system for balancing currents in a device, the computer system comprising one or more computer readable storage devices and program instructions collectively stored on the one or more computer readable storage devices, the stored program instructions, when executed by one or more computer processors, causing the one or more computer processors to perform steps of a computer-implemented method according to any of claims 1 to 6.

Images