Electroplating controller having power-based headroom control - Patents.com

Abstract

A method for controlling a headroom voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage can include maintaining a headroom voltage of the transistor stage for a load of the electroplating system. The method can further include measuring an instantaneous power dissipation of the transistor stage and generating a difference output representing the difference between the instantaneous power dissipation of the transistor stage and a target power dissipation of the transistor stage. The voltage across the transistor stage and the load can then be adjusted using the difference output such that the headroom voltage of the transistor stage is adjusted to maintain the target power dissipation of the transistor stage.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 17 / 015,612, filed September 9, 2020, and entitled “ELECTROPLATING CONTROLLER WITH POWER BASED HEAD ROOM CONTROL,” the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] The present technology relates to cleaning operations in semiconductor processing, and more particularly to systems and methods for controlling voltage or current in electroplating systems. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of materials on a substrate surface. After forming, etching, and other processing on the substrate, metal or other conductive materials are often deposited or formed to make electrical connections between components. Because this metallization may be performed after many production operations, problems that arise during metallization can result in the waste of expensive substrates or wafers.

[0004] During the formation of a metal material on a wafer or substrate, the substrate may be immersed in a plating bath and then metal formation may be performed on the substrate by an electroplating process. The wafer may then be lifted or otherwise moved and then rinsed in the chamber. Several problems may arise during this process. For example, current electroplating controllers may use voltage controlled headroom to manage the heating of metal oxide semiconductor field effect transistors or (MOSFETs) in the control circuitry that governs the voltage and current flow during the electroplating process. The resulting headroom voltage is controlled to the same value regardless of the power dissipated in the MOSFET. This creates a dependency on the reaction speed of the variable voltage source used to generate the rail voltages that are supplied to the current or voltage of the electroplating system.

[0005] Thus, there is a need for improved systems and methods that can be used to more efficiently control the headroom voltage of an electroplating controller. These systems and methods, as well as other needs, are addressed by the present technology. Summary of the Invention

[0006] In some embodiments, a circuit for controlling a headroom voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage can include a transistor stage that supplies the headroom voltage to a load of the electroplating system. The circuit can further include a power measurement circuit coupled to the transistor stage. The power measurement circuit can provide a signal representative of an instantaneous power dissipation of the transistor stage. The circuit can additionally include a differential circuit that receives the signal representative of the instantaneous power dissipation of the transistor stage from the power measurement circuit and the signal representative of the target power dissipation of the transistor stage and generates a differential output. The circuit can further include an adjustable voltage source that supplies a voltage across the transistor stage and the load. The adjustable voltage source can be configured to use the differential output to adjust the headroom voltage, thereby maintaining the target power dissipation of the transistor stage.

[0007] In some embodiments, a method of controlling a headroom voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage can include maintaining a headroom voltage of the transistor stage for a load of the electroplating system and measuring an instantaneous power dissipation of the transistor stage. The method can further include generating a difference output representative of a difference between the instantaneous power dissipation of the transistor stage and a target power dissipation of the transistor stage. The method can further include adjusting a voltage across the transistor stage and the load using the difference output such that the headroom voltage of the transistor stage is adjusted to maintain the target power dissipation of the transistor stage.

[0008] In some embodiments, the circuit for controlling a headroom voltage of a transistor stage to maintain a target power dissipation across the transistor stage may include a transistor stage supplying the headroom voltage to a load. The circuit may further include a power measurement circuit coupled to the transistor stage. The power measurement circuit may provide a signal representative of an instantaneous power dissipation of the transistor stage. The circuit may additionally include an adjustable voltage source supplying a voltage across the transistor stage and the load. The adjustable voltage source may be configured to adjust the headroom voltage of the transistor stage in response to the instantaneous power dissipation of the transistor stage to maintain the target power dissipation of the transistor stage.

[0009] In any embodiment, any and / or all of the following features may be implemented in any combination, without limitation. Other features described in this disclosure may further be added to any embodiment, without limitation, in any combination. The power measurement circuit may include a voltage measurement circuit coupled to the transistor stage to provide a measurement representative of the voltage across the transistor stage. The power measurement circuit may further include a current measurement circuit coupled to the transistor stage to provide a measurement representative of the current through the transistor stage. The power measurement circuit may further include a multiplier circuit that receives a measurement representative of the voltage across the transistor stage and a measurement representative of the current through the transistor stage to generate a signal representative of the instantaneous power dissipation of the transistor stage. The difference circuit may include an operational amplifier that provides an output to the AC-DC converter. The circuit may further include a differential amplifier that receives a signal representative of a target current through the transistor stage and receives the instantaneous current through the transistor stage. The differential amplifier may provide a gate voltage to the transistor stage to achieve the target current through the transistor stage. The signal representative of the instantaneous power dissipation of the transistor stage may include a voltage proportional to the instantaneous power dissipation. The method / operation may further include determining a voltage across the transistor stage and / or determining a current through the transistor stage. The method / operation may further include multiplying a signal representative of the voltage across the transistor stage with a signal representative of the current through the transistor stage to determine an instantaneous power dissipation of the transistor stage. The method / operation may further include decreasing a headroom voltage of the transistor stage when the current through the transistor stage increases. The method / operation may further include scaling down the signal representative of the instantaneous power dissipation of the transistor stage. The method / operation may further include generating a voltage transient across the transistor stage and the load having a fall time of less than 10 ms. The target power dissipation may be represented by a plurality of series resistors forming a voltage divider. The adjustable voltage source may include an AC-DC power converter. The power measurement circuit may be implemented using a microprocessor or microcontroller.The circuitry may further include a serial interface that receives serial commands from the controller and converts the serial commands into a plurality of analog and digital signals to control the circuitry for controlling the headroom voltage of the transistor stage.

[0010] A further understanding of the nature and advantages of the various embodiments can be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to like components throughout the several views. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When referring to a reference numeral without specifying an existing sub-label, it is intended to refer to all of such multiple similar components. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic isometric view of an electroplating system in which methods and cleaning systems according to embodiments may be utilized and practiced. [Diagram 2] 1 is a partial cross-sectional view of a chamber including aspects of an electroplating apparatus according to some embodiments. [Diagram 3] FIG. 1 illustrates an electroplating apparatus that can include a user interface computer, according to some embodiments. [Figure 4] FIG. 4 is a block diagram of one of the one or more plating channels shown in FIG. 3 according to some embodiments. [Diagram 5] FIG. 2 illustrates a circuit for maintaining a power regulated headroom voltage according to some embodiments. [Figure 6] 1 is an example circuit diagram of a voltage differential amplifier configured to generate a voltage that corresponds to a current through a transistor stage, according to some embodiments. [Figure 7] FIG. 2 illustrates an example of a fall time associated with a constant voltage headroom control system, according to some embodiments. [Figure 8]FIG. 2 illustrates an example of fall times associated with variable voltage headroom to maintain constant power dissipation, according to some embodiments. [Figure 9] FIG. 2 illustrates a method for adjusting headroom voltage for constant power dissipation according to some embodiments. [Figure 10] FIG. 1 illustrates an exemplary computer system in which various embodiments may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Electroplating is a process in which a current or voltage signal is used to control the deposition of a metal or metal compound onto the surface of a substrate. Electroplating is used in many applications including, for example, the manufacture of integrated circuits. In such applications, precise control of metal deposition rate and geometry is desirable. This requires precise control of the electroplating current, especially as microelectronic components on semiconductor substrate components continue to get smaller.

[0013] The electroplating current can advantageously be controlled digitally or via a programmable controller. The programmable output can be used to optimize plating speed. Semiconductor manufacturing equipment can be used to produce a variety of products. With a programmable controller, the equipment can be easily used to electroplate different products. The manufacturing equipment has two or more anodes, a cathode connected to the wafer or substrate, and optionally a thief electrode. The programmable controller of this equipment controls multiple channels simultaneously, which presents additional engineering challenges.

[0014] Electroplating equipment also preferably has the ability to precisely control the output current with a high dynamic range. Electroplating systems are often expected to provide a wide range of output current to provide effective control of electroplating. The current required in a plating process may vary over a wide range, for example, between a few milliamps to tens of amps.

[0015] Electroplating operations can be performed to apply conductive material to vias and other features of a substrate. Electroplating utilizes an electrolytic bath containing ions of the conductive material to electrochemically deposit the conductive material on the substrate and in the features defined in the substrate. The substrate on which the metal is being plated acts as the cathode. Electrical contacts such as rings or pins can allow current to flow through the system. During electroplating, the substrate can be clamped to a head and immersed in an electroplating bath to form the metallization. In the systems described below, the substrate can also be chucked in a seal that can be coupled to the head during processing. When the substrate is moved or lifted after plating, the substrate can be rinsed with water, such as deionized water, before being sent to another plating chamber or other processing location.

[0016] The voltage and / or current supplied to the electroplating process may be controlled with a digital controller. The controller may provide a variable voltage source across the electroplating load and the control transistor in series. A headroom voltage may be maintained at the transistor stage to provide a voltage buffer to accommodate rapid changes in the voltage profile across the load. Conventional techniques may use a constant headroom voltage that is maintained as the voltage across the load changes. However, these techniques limit the speed at which the voltage / current across the load can change. The rise and fall times are around 100 ms, often causing discontinuities in the output. Other techniques may use very large voltage headroom to accommodate faster rise times. However, these techniques result in very high power dissipation in the control system in the form of heat.

[0017] The present techniques overcome these problems by using a dynamic headroom voltage. Instead of maintaining a constant headroom voltage, these techniques can maintain a target power dissipation level in the transistor stage. When the current is very small during the initial stages of the electroplating process, the headroom voltage can be very large. This large headroom voltage can accommodate a very fast rise time. As the current through the transistor stage increases, the headroom voltage can be reduced to maintain a constant power dissipation level. These techniques balance power dissipation with maintaining sufficient headroom voltage to achieve rise and / or fall times of approximately 1 ms.

[0018] FIG. 1 shows a schematic isometric view of an electroplating system 100 in which methods and cleaning systems according to embodiments may be utilized and practiced. The electroplating system 100 may include a system head 110 and a bowl 115. During an electroplating operation, a wafer may be clamped to the system head 110, inverted, and extended into the bowl 115 to perform the electroplating operation. The electroplating system 100 may include a head lifter 120, which may be configured to both lift and rotate the system head 110 or otherwise move or position the head within the system, including tilting operations. The head and bowl may be mounted to a deck plate 125 or other structure that may be part of a larger system incorporating multiple electroplating systems 100 and may share electrolyte, voltage control systems, and / or other tools.

[0019] The rotor allows the substrate clamped to the head to rotate within the bowl or, in different operations, outside the bowl. The rotor can include a contact ring, which can make conductive contact with the substrate. The seal 130 can be connected to the system head 110. The seal 130 can include a chucked wafer to be processed. FIG. 1 shows an electroplating system 100 that can include components that are cleaned directly on a platform. Other configurations are possible, including a platform where the system head 110 is moved to an additional module and the seal 130 or other components are cleaned. Additionally, one or more components, such as the seal 130, can be removed from their respective chambers and placed in a maintenance system or a cleaning system for cleaning. Any number of other operations that prepare or expose components for cleaning can be performed. An exemplary in situ rinse system 135 is also shown with the system 100.

[0020] FIG. 2 illustrates a partial cross-sectional view of a chamber including aspects of an electroplating apparatus 200 according to some embodiments. The electroplating apparatus 200 can be incorporated into an electroplating system, including the electroplating system 100 described above. As illustrated in FIG. 2, a plating tank vessel 205 of the electroplating system is shown with a head 210 having a substrate 215 coupled thereto. The substrate may be coupled to a seal 212 coupled to the head 210 in some embodiments. A rinse frame 220 may be coupled above the plating tank vessel 205 and may be configured to receive the head 210 entering the plating tank vessel 205 during plating. The rinse frame 220 may include a rim 225 extending circumferentially around a top surface of the plating tank vessel 205. A rinse channel 227 may be defined between the rim 225 and the top surface of the plating tank vessel 205. For example, the rim 225 may include an interior sidewall 230 characterized by a sloped profile. As described above, rinsing fluid from the substrate may contact the sidewall 230 and may be received in a plenum 235 extending around the rim 225 to collect the rinsing fluid from the electroplating apparatus 200. A weir 240 may extend around the plating tank vessel 205 and may be fluidly coupled to the plenum 235 or the rinsing channel 227 to further restrict the rinsing fluid from returning to the plating tank. The weir 240 may define a surface 245 across the electroplating apparatus 200 through which the head 210 may extend into the plating tank vessel 205 and through which the head 210 may return to perform a rinsing operation.

[0021] 3 illustrates an electroplating apparatus that can include a user interface computer 312, according to some embodiments. The user interface computer 312 can be coupled to a plating control computer 320, for example, using an Ethernet interface 322. The Ethernet interface 322 can be used for less time-critical equipment communications, such as communications to the user interface computer 312. The single plating control computer 320 can communicate with one or more plating subsystems 360, for example, by an EtherCAT interface 324. Each of the one or more plating subsystems 360 can control one or more anodes in a plating chamber.

[0022] Each plating subsystem 360 can have one or more channels 330, each of which can be connected to a zone within a plating chamber 370. Multiple plating chamber zones may be used to control radial plating uniformity on a substrate. For simplicity, the components of the plating subsystem 360 are referred to herein as PPS (Plating Power Supply Assembly). FIG. 3 shows three different sample PPS configurations. The first PPS configuration shows four channels, which are connected to support two plating chambers 370 using two channels per plating chamber. The second example shows a PPS configuration with two channels to support a single plating chamber. The third sample shows a PPS configuration with three channels to support a plating chamber with three channels per plating chamber.

[0023] FIG. 4 illustrates a block diagram of one of the one or more plating channels 330 shown in FIG. 3 according to some embodiments. The plating channel 330 may be connected to a control board 440. The control board 440 may be coupled to more than one plating channel, but in FIG. 4, the connection to a single plating channel 330 is shown in isolation for clarity. The control board 440 may include circuitry for interfacing between the AC-DC power block 432 and the EtherCAT interface 324. Operating the AC-DC power block 432 may include communicating control messages for controlling the operation of the AC-DC power block 432 from the plating control computer 320 via the EtherCAT interface 324. The AC-DC power block 432 may include an AC-DC power converter. The control messages may include digital control messages that specify whether the output electrical control signal is a voltage or a current, along with analog control messages that specify a target output electrical control signal value and a corresponding duration.

[0024] The control board 440 may include one or more current sensors. To achieve a wider range of plating current, a high-range current sensor 441 and a low-range current sensor 442 may be provided. However, in some embodiments, a single current sensor or three or more current sensors may be used without limitation to receive additional current measurements.

[0025] The control board 440 may further include one or more current switching elements 443 to route the current through the high range current sensor 441. The current switching elements 443 may include one or more MOSFETs controlled by a digital signal DO2p that turns the MOSFETs fully on for low power dissipation of the one or more current switching elements 443. The control board 440 may further include one or more current switching elements 444 to route the current through the low range current sensor 442. These more current switching elements 444 may be controlled by an analog output O1p and a control circuit that places the more current switching elements 444 in series with the AC-DC power block 432. In some embodiments, the more current switching elements 444 may function as a linear step-down regulator.

[0026] The control board 440 may also include EtherCAT digital and analog input / output circuitry within the I / O interface 445. Software running on the plating control computer 320 may control corresponding plating subsystems 360 by turning on digital outputs, setting analog outputs to control plating current or voltage set points, and reading out digital and analog inputs to report and record plating process sensor measurements such as current and voltage. The I / O interface 445 may be configured to distribute these analog and digital signals throughout the control board 440.

[0027] The control board 440 may further include an isolation circuit 446. The optional isolation circuit 446 may be used to prevent electrical interaction between the electroplating power delivery circuit and the interface / control circuit. In addition, the control board 440 may include an operational amplifier circuit 447 and / or an operational amplifier circuit 448 to provide closed-loop control. For example, the operational amplifier circuit 447 may control the AC-DC power block 432. The operational amplifier circuit 448 may control one or more switching elements 444, which may include low-range transistors. The AC-DC power block 432 may generally have an on / off control, which may be controlled by software running on the plating control computer 320 using a digital output DO1p.

[0028] The electroplating apparatus 310 may further include a blocking diode 433 to prevent interaction between the AC-DC power block 432 and other AC-DC power blocks of other channels when they are connected together to a plating chamber. For example, sometimes it may be desirable to simultaneously plate in one zone and stop plating in a different zone. When a zone is scheduled to stop plating, the diode 433 is reversed and the polarity of the voltage resulting from the AC-DC power block 432 will be reversed.

[0029] To initiate an electroplating operation, an operator can input a desired or target plating process into the user interface computer 412. This can include the desired mode (e.g., voltage or current) to be used by the channels of the plating system, the desired set point (e.g., 2.5 A), and the desired duration (e.g., 1 minute). The inputted process parameters can be sent to the plating control computer 320, which can control the time-constrained electroplating operation of the equipment.

[0030] The semiconductor processing equipment can then transport, typically by robot, the substrate to the plating chamber 370 and immerse it in the plating solution. The plating control computer 320 software can control the PPS 360 by sending EtherCAT commands to turn on the digital and analog outputs of the PPS 360 to communicate the desired settings. The digital outputs DO control the operating mode (e.g., current or voltage), range (e.g., high range current or low range current), and power delivery state (e.g., on or off). The analog outputs AO can represent the desired set point current or voltage that the PPS 360 should deliver. The plating control computer 320 can have a calibration table for each channel, mode, and range of each PPS 360 that can be used to communicate the desired set point (e.g., plating current in amperes), taking into account the calibration results for each particular channel. The described method can include referencing the calibration table to obtain, from a control message received at the EtherCAT interface, a corresponding operating point for an electrical circuit that generates the output electrical control signal. A calibration table stored in either the plating control computer 320 or the plating subsystem 360 can be used to convert user programmed set points in amperes or volts to corresponding operational set points for the control circuitry. This conversion may occur in the plating control computer 320 if the EtherCAT interface message is a calibrated set point (e.g., DAC counts) or in the plating subsystem if the EtherCAT interface message is a target amperes or volts.

[0031] If the PPS 360 has multiple current sensors, software running on the plating control computer 320 can determine which range to use for each step of the process based on the desired set point and the minimum operating range of the AC-DC power block 432. For example, when use of the high range is appropriate, the control for sending current through the high range current sensor 441 can be selected and the control input for sending current through the low range sensor 442 can be turned off.

[0032] The circuitry of the control board 440 may use well-established techniques such as proportional-integral-derivative control (PID) to drive the control pins of the AC-DC power block 432 to match the feedback signal to a set point signal. For example, to implement the I term of the PID control of the high range current control mode, the op-amp circuit 447 may be configured to produce a control output 02i=k.sub.2f(A0-FBi), where FBi=FB2i, which is the high range current feedback signal from the high range current sensor 441, and A0 is the set point signal from the plating control computer 320. If the digital output (DO) indicates that the voltage control mode should be used instead of the current mode, then FBi=FB3i, which is the voltage feedback signal FB3i from the feedback sense circuit 450. The op-amp circuit 447 may use operational amplifiers and analog multiplexers to produce the desired control signal. The first and second, or high range and low range, current sensors may generate feedback signals indicative of the magnitude of the output electrical control signal during high range and low range operation, respectively.

[0033] Op-amp circuit 447 and op-amp circuit 448 may be implemented on either side of isolation circuit 446 .

[0034] When the PPS 360 is required to deliver a current mode at a current below the minimum operating range of the AC-DC power block 432, or when a low-range current control circuit is expected to provide more accurate plating results, a PPS control signal that sends current through the low-range current sensor 442 is selected, and the control signal DO2p that sends current through the high-range current sensor 441 is turned off. In this mode, two separate control loops can be used. One loop can include an op-amp circuit 447 that controls the AC-DC power block 432 to provide a fixed drain-source voltage (referred to as a "headroom voltage") to the low-range transistor of one or more switching elements 444. In this mode, the op-amp circuit 447 uses a headroom voltage sensing circuit 449 to provide an output O2i=k.sub.hrf(k.sub.HRnorm-HRi) control signal to the AC-DC power block 432. The value of k.sub.HRnorm may be a desired headroom voltage for normal operation of one or more switching elements 444, and HRi may be a measured headroom voltage from the headroom voltage sensing circuit 449.

[0035] The second loop can include an op-amp circuit 448, which can control the low range transistors of one or more switching elements 444 and act as a post-regulator for the AC-DC power block 432 to direct its output to a current sensor optimized for lower currents. The op-amp circuit 448 can use well-established control techniques for control. For example, to implement the I term of the PID control of the low range current control mode, 01i=k.sub.1f(A0-FBi), where FBi=FB1i, which is the low range current sensor reading, and A0 is the set point signal from the plating control computer 420.

[0036] The control board may include circuitry to minimize transients when shifting between ranges. In semiconductor plating, which varies speed during the plating process, the process typically begins with a low plating current and may then shift to a high plating current later in the process. The AC-DC power block 432 may produce power for both ranges, but the one or more switching elements 444 may require some voltage drop ("headroom") for proper operation. By way of example, the one or more switching elements 444 may be implemented by one or more transistors, such as MOSFET transistors. Hence, the one or more switching elements 444 may also be interchangeably referred to as low-range transistors for purposes of this example. While operating in the low range, this allows the low-range transistors of the one or more switching elements 444 to make adjustments to regulate the current to the desired value, even if the AC-DC power block cannot operate exactly (or at all) at the desired output. The adjustment speed of the AC-DC power block 432 is generally slower than the switching element(s) 444, so when switching from low range to high range, the headroom desired for low range operation can be set such that the AC-DC power block 432 produces a higher current than desired in the subsequent high range step. For example, if the low range current is 2.0 amps and the high range current is 2.5 amps, with a 1 ohm load and 3 volts of headroom, the required PPS output voltage is 2×1=2V. The output of the AC-DC power block 432 to achieve 3V headroom would be 2V+3V=5V. If the unit were to immediately switch to the high range, the expected current would be 5V / 1 ohm=5A, which is higher than the desired 2.5A set point. This would result in a current spike above the desired set point until the AC-DC power block 432 adjusts the output downward to the level required for the high range current step.

[0037] Many semiconductor electroplating processes are more sensitive to current above the set point than to current below the set point. Separate control DACs and circuits for high and low range current control may be used to reduce the chance of the current exceeding the desired set point during range transitions. Additionally, a circuit may be provided to select a desired headroom for the low range mode. The normal headroom setting k.sub.HRnorm provides more margin for the low range transistors to control the output. Just before changing to the high range mode, a lower headroom setting k.sub.HRmin may be selected. This reduces the output of the AC-DC power block 432 to a minimum headroom level (reducing the margin for the low range transistors to control the output in response to load changes). Then, when the PPS controller changes to the high range, the system is less likely to overshoot the desired set point.

[0038] In low-range mode, the low-range transistors can react to changes faster than the AC-DC power block. The circuit can be designed to react faster to "above set point" conditions than to "below set point" conditions, which is often desirable from a process standpoint and to protect the low-range transistors from damage due to power dissipation limitations. In addition, the I term (integral term) of the response speed of the control circuit is automatically slowed down when the headroom drops below a threshold level. This allows it to respond quickly when there is sufficient headroom, but slow down its response to follow the response of the AC-DC power block when there is insufficient headroom. This prevents the accumulation of the I term in the low-range control circuit and the subsequent overshoot that can occur without this feature.

[0039] Power-Based Headroom Voltage By maintaining a headroom voltage for the low range transistors as described above, the circuit can respond to changes in the voltage profile across the load. For example, if the voltage profile across the load starts at 2V and rises to 7V, by maintaining sufficient headroom voltage for the low range transistors, the circuit can respond by increasing the voltage at the load faster than would normally be possible due to the extra voltage maintained in the headroom of the low range transistors. Hence, the headroom voltage provides the advantage of allowing the voltage response curve to rise faster.

[0040] If maintaining extra voltage headroom for the low-range transistor were the only issue, the AC-DC power block 432 could simply set the voltage across the low-range transistor 444 to a maximum value (e.g., 24V), allowing the load's voltage to be quickly ramped up to any voltage level in its range. However, operating the low-range transistor 444 at a very high voltage inevitably results in a large amount of power being dissipated in the low-range transistor 444. For example, when the current through the low-range transistor 444 begins to increase, the power dissipated by the low-range transistor 444 can be defined as the instantaneous voltage multiplied by the instantaneous current. If the headroom voltage of the low-range transistor 444 is constantly maximized, the resulting power dissipated by the low-range transistor 444 can become very high as the current increases. This power can be dissipated as heat in the control board 440. The heat dissipated by the low-range transistor 444 can damage the low-range transistor 444, the printed circuit board, and / or other nearby components if the headroom voltage is unnecessarily high.

[0041] In some implementations, the headroom voltage maintained at the low range transistor is maintained at a constant level above the operating voltage of the load. For example, some implementations can program the AC-DC power block 432 to maintain a headroom voltage of at least 3V above the load voltage of the low range transistor 444. If the load voltage is 2V, the transistor voltage is maintained at about 5V to maintain a constant headroom voltage of 3V. If the load voltage rises from 2V to 5V, the headroom voltage of 3V is sufficient to increase the voltage without delaying the rise time of about 100ms. By maintaining this minimum constant headroom voltage, sufficient headroom can be provided for a slow voltage increase across the load while minimizing the power dissipated by the low range transistor 444.

[0042] Although maintaining a constant headroom voltage reduces the power dissipated in the low-range transistor 444, it often does not provide enough headroom voltage to support a rapid increase in the voltage profile across the load. For example, rise times significantly shorter than 100 ms cannot be supported with the fixed headroom voltage mentioned above. The output of the low-range transistor 444 lags behind the desired voltage profile curve of the output, which results in a discontinuity in the output curve. Therefore, it is difficult to support a rapid rise time of about 1 ms while maintaining a constant headroom voltage.

[0043] To overcome this technical challenge, the embodiments described herein maintain a constant power dissipation in the low-range transistor. The current through the low-range transistor and the voltage across the low-range transistor can be monitored in real time and multiplied to generate the instantaneous power dissipation of the low-range transistor. This power dissipation can be provided to a voltage differential amplifier and used as a feedback input to an adjustable voltage source. Instead of maintaining a constant headroom voltage, the headroom voltage can change dynamically as the current through the low-range transistor changes. For example, at very low currents, a very high headroom voltage may be maintained because the product of these two terms will result in a relatively low power dissipation. As the current begins to rise, the headroom voltage can be reduced to maintain this constant power dissipation. This solution provides a rise time of about 1 ms because the initial headroom voltage is large enough to support a fast initial rise in the output voltage of the load.

[0044] FIG. 5 illustrates a circuit for maintaining a power regulated headroom voltage, according to some embodiments. The circuit can operate as a stand-alone circuit in various applications to regulate the headroom voltage across a transistor or switching stage, thereby maintaining a constant power dissipated in that transistor stage. In one particular implementation, certain elements of the circuit illustrated in FIG. 5 can be used to implement circuit elements of the control board 440 illustrated in FIG. 4. The circuit can include a transistor stage 544, and one or more switching elements 444 of FIG. 4 can be implemented using one or more transistors in the transistor stage 544. By way of example, the transistor stage 544 can be implemented using one or more transistors, such as the IRFP3810 series Power MOSFET from International Rectifier®. The circuit of FIG. 5 can be configured to monitor the headroom voltage maintained in this transistor stage 544.

[0045] A voltage measurement circuit may be provided to measure the voltage across the transistor stage 544. In some embodiments, the voltage measurement circuit may be implemented using a voltage differential amplifier 549 to measure the voltage across the transistor stage 544. For example, the voltage differential amplifier 549 may receive two inputs, a first input coupled to the drain of the final transistor of the transistor stage 544 and a second input coupled to the initial source of the transistor stage 544. The output of the voltage differential amplifier 549 is proportional to the voltage difference across the transistor stage 544 and may therefore be a scaled value representative of the voltage across the transistor stage 544.

[0046] In addition to measuring the voltage across the transistor stage 544, the circuit may include a current measurement circuit that measures the current through the transistor stage 544. The current measurement circuit may be implemented using a voltage differential amplifier 542 configured to generate a voltage proportional to the current passing through the transistor stage 544. FIG. 6 shows an example circuit diagram of a voltage differential amplifier 542 configured to generate a voltage equivalent to the current through the transistor 544, according to some embodiments. A relatively small resistor 602 may be placed in series with the transistor stage 544. The resistor value may be approximately 0.1 ohms in the example embodiment of FIG. 6 and may be implemented with a Y08560R10000F9W foil resistor from Vishay. To measure the voltage across the resistor 602, this example uses an amplifier 604, such as an AMC1100 amplifier for current sensing from Texas Instruments®, along with an instrumentation amplifier, such as an INA826 from Texas Instruments®. Note that these components and component values ​​are provided merely as examples and are not meant to be limiting. Many other implementations of the current measurement circuit may be used with different components. The example of FIG. 6 is shown only to provide an enabling disclosure and represents only one of many possible embodiments within the scope of the present disclosure. It should also be noted that similar circuits may be used for each of the voltage differential amplifiers shown in FIG. 5. For example, each of the voltage differential amplifiers 542 and 549 may be implemented using circuits similar to those shown in FIG. 6 but with different inputs and component values. For the sake of brevity, the circuit of FIG. 6 is not repeated herein for each of these voltage differential amplifier implementations of FIG. 5.

[0047] Returning to FIG. 5, with the output of the voltage differential amplifier 549 representing the instantaneous voltage across the transistor stage 544 and the voltage output of the voltage differential amplifier 542 representing the instantaneous current passing through the transistor stage 544, two components of a standard power measurement are made available in the circuit. The voltage and current measurements can be provided to a multiplier circuit, which generates the product of these two inputs. In this particular example, the multiplier circuit can be implemented with an analog multiplier 575. The analog multiplier 575 can be implemented using components such as an AD633 analog multiplier from Analog Devices®. This device can allow the output to be scaled down by a factor of 10 to keep the output product within the operating voltage range of the device. The output can be a signal representative of the instantaneous power dissipation in the transistor stage 544.

[0048] As used herein, a signal may "represent" a voltage, current, power, or other electrical characteristic of a circuit if the signal is directly or inversely proportional or otherwise convertible to the voltage, current, power, or other electrical characteristic of interest. For example, the scaled voltage output of analog multiplier 575 may be a voltage that can be converted to instantaneous power dissipation. In another example, the output of voltage differential amplifier 549 may represent the voltage across transistor stage 544. The output of voltage differential amplifier 549 may be proportional to, if not the exact voltage across, transistor stage 544. Similarly, the output of voltage differential amplifier 542 may represent the current through transistor stage 544 as a voltage proportional to that current.

[0049] The voltage differential amplifiers 542, 549, which measure the instantaneous voltage and current of the transistor stage 544, together with the analog multiplier 575, can be collectively referred to as a power measurement circuit 581. However, the circuit elements shown in FIG. 5 and FIG. 6 for implementing the power measurement circuit 581 are provided merely as examples and are not meant to be limiting. Many other types of analog / digital circuits may be used to measure the instantaneous power dissipation in the transistor stage 544. For example, a microcontroller or microprocessor can receive analog voltage / current signals from the transistor stage 544 and convert those signals to digital values. The microcontroller or microprocessor can then generate an output signal for controlling the adjustable voltage source 532. In another example, a power measurement integrated circuit can receive the voltage and / or current signals from the transistor stage 544 and output a signal that can be used to directly control the adjustable voltage source 532. Other ways of implementing the power measurement circuit 581 are within the scope of the disclosure.

[0050] As used herein, the term "coupled to" may describe circuit elements that send and receive electrical signals to each other. Two components may be electrically coupled when a signal based on the output of one component is provided as an input to another component. For example, voltage differential amplifier 549 is coupled to transistor stage 544 by receiving a voltage signal from transistor stage 544. Similarly, voltage differential amplifier 542 is coupled to transistor stage 544 by receiving a current signal output from transistor stage 544. It should be noted that two components may be coupled together through additional components. For example, voltage differential amplifier 549 is coupled to voltage differential amplifier 547, even though analog multiplier 575 processes the signal between these two components.

[0051] The output of the analog multiplier 575 can be provided to a difference circuit that calculates the difference between the two signals. A different circuit may be implemented using another voltage difference amplifier 547. The other input of the voltage difference amplifier 547 can receive a fixed voltage source 580. The fixed voltage source 580 can represent a target power dissipation to be maintained in the transistor stage 544. The target power dissipation can be represented as a voltage scaled to correspond to the scaled output of the analog multiplier 575. In the example of FIG. 4, the voltage difference amplifier 547 can represent an operational amplifier circuit 447 that provides a control signal to the AC-DC power block 432, which can implement the adjustable voltage source 532 of FIG. 5. The output of the voltage difference amplifier 547 can provide an error voltage that is converted to an output DC voltage across the transistor stage 544 and the load 576. The voltage difference amplifier 547 can be implemented using components such as an LM358 operational amplifier from Texas Instruments®. Fixed voltage source 580 may be implemented using any type of voltage source, such as a series resistor acting as a voltage divider based on a known reference or rail voltage. In some embodiments, voltage source 580 may be dynamically programmable by the system's software, such that the power dissipated by transistor stage 544 may be set to any value.

[0052] The gate voltage applied to the transistor stage 544 may be received from a voltage differential amplifier 548. The voltage differential amplifier 548 may receive a command from the I / O interface 445 representing a target current through a load 576. The instantaneous current measurement received from the voltage differential amplifier 542 may be provided to the voltage differential amplifier 548, the output of which may provide a gate voltage to the transistor stage 544. By adjusting the gate voltage of the transistor stage 544, the amount of current passing through the transistor stage 544 may be adjusted until it matches the target current value in the command. In the example of FIG. 4, the load 576 may represent the plating chamber described above.

[0053] 7 shows an example of a fall time associated with a constant voltage headroom control system, according to some embodiments. In this example, the voltage of the transistor headroom can be maintained at a constant value as described in the previous embodiment above. When dropping about 15V at 0.9A, the measured fall time 704 is about 52.9ms. In addition, the voltage drop creates a significant overshoot 702. The discontinuity of the overshoot 702 can result in abnormal effects in the electroplating process.

[0054] FIG. 8 illustrates an example of fall times associated with variable voltage headroom to maintain constant power dissipation, according to some embodiments. In this example, the headroom voltage of the transistor is maintained at constant power dissipation using the circuit described above in FIG. 5. In this case, the fall time 804 is about 2.5 ms when dropping about 15V at 1.0A. Notably, this faster voltage drop results in little to no significant overshoot. Therefore, the constant power dissipation provided by the circuit of FIG. 5 can effectively reduce discontinuities in the electroplating process for fast rise / fall times.

[0055] FIG. 9 illustrates a method 900 of adjusting a headroom voltage for constant power dissipation according to some embodiments. The method can include maintaining (902) a headroom voltage of a transistor stage for a load in an electroplating system. As described above, the transistor stage can include one or more switching elements, such as MOSFET transistors, in series and / or parallel. The load can represent a voltage / current supplied to the electroplating system to apply a layer of metal to a substrate or wafer. The headroom voltage can represent a voltage across the transistor stage that is maintained at a voltage above the voltage across the load. The headroom voltage can be maintained to allow the voltage across the load to rise / fall quickly with minimal rise and / or fall times.

[0056] The method may further include measuring (904) the instantaneous power dissipation of the transistor stage. The instantaneous power dissipation of the transistor stage may be measured using a power measurement circuit as described in detail above in FIG. 5 and FIG. 6. For example, the instantaneous power dissipation may be measured by measuring the voltage across the transistor stage, measuring the current through the transistor stage, and multiplying these values ​​together to generate a signal representative of the instantaneous power dissipation of the transistor stage. This signal may be a scaled voltage, which may be mathematically converted to a value of dissipated power. The instantaneous power dissipation may be measured / calculated using individual IC components, discrete board level components, microprocessors, or microcontrollers, and / or using other methods.

[0057] The method may additionally include generating 906 a difference output representative of the difference between the instantaneous power dissipation of the transistor stage and a target power dissipation of the transistor stage. The difference signal may be generated by a voltage differential amplifier as described above in FIG. 5. The target power dissipation may be represented by a fixed voltage source that may be compared to a signal representative of the instantaneous power dissipation. The target power dissipation may also be provided as a programmable input such that the instantaneous power dissipation can be changed at run time.

[0058] The method may further include adjusting 908 a voltage across the transistor stage and a load using the differential output such that a headroom voltage of the transistor stage is adjusted to maintain a target power dissipation of the transistor stage. The voltage may be adjusted by providing the differential output to a programmable AC-DC converter that generates a DC output across the load and the transistor stage as described above.

[0059] It should be appreciated that the specific steps illustrated in FIG. 9 provide a particular method of controlling headroom voltages of transistor stages of an electroplating system to maintain target power dissipation, according to various embodiments. Other sequences of steps may also be performed in accordance with alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in FIG. 9 may include multiple sub-steps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many modifications, variations, and alternatives are still within the scope of the present disclosure.

[0060] The various components of the above-mentioned systems may be implemented by a computing system including a user interface computer 312 and / or a plating control computer 320. FIG. 10 illustrates an exemplary computer system 1000 on which the various components may be implemented. The system 1000 may be used to implement any of the above-mentioned computer systems. As shown in the figure, the computer system 1000 includes a processing unit 1004 that communicates with several peripheral subsystems via a bus subsystem 1002. These peripheral subsystems may include a processing acceleration unit 1006, an I / O subsystem 1008, a storage subsystem 1018, and a communication subsystem 1024. The storage subsystem 1018 includes a tangible computer readable storage medium 1022 and a system memory 1010.

[0061] Bus subsystem 1002 provides a mechanism for allowing the various components and subsystems of computer system 1000 to communicate with each other as intended. Although bus subsystem 1002 is shown diagrammatically as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. Bus subsystem 1002 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a MicroChannel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which may be implemented as a mezzanine bus produced in accordance with the IEEE P1386.1 standard.

[0062] The processing unit 1004, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of the computer system 1000. One or more processors may be included in the processing unit 1004. These processors may include single-core or multi-core processors. In some embodiments, the processing unit 1004 may be implemented as one or more independent processing units 1032 and / or 1034, each processing unit including a single or multi-core processor. In other embodiments, the processing unit 1004 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0063] In various embodiments, the processing unit 1004 may execute various programs according to program code and may maintain multiple programs or processes executing simultaneously. At any given time, some or all of the program code to be executed may reside in the processor 1004 and / or the storage subsystem 1018. Through appropriate programming, the processor 1004 may provide various functions as discussed above. The computer system 1000 may additionally include a processing acceleration unit 1006, which may include a digital signal processor (DSP), a special purpose processor, and / or the like.

[0064] The I / O subsystem 1008 can include user interface input devices and user interface output devices. User interface input devices can include pointing devices such as keyboards, mice or trackballs, touchpads or touchscreens integrated into displays, scroll wheels, click wheels, dials, buttons, switches, keypads, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices can include motion sensing and / or gesture recognition devices such as Microsoft Kinect® motion sensors that allow a user to control and interact with an input device such as a Microsoft Xbox® 360 game controller through a natural user interface using gestures and voice commands. User interface input devices can further include an eye gesture recognition device such as a Google Glass® blink detector that detects a user's eye activity (e.g., "blinking" while taking a picture and / or making a menu selection) and translates eye gestures as input to the input device (e.g., Google Glass®). Additionally, the user interface input devices may include a voice recognition sensing device that allows a user to interact with a voice recognition system (e.g., the Siri® navigator) via voice commands.

[0065] The user interface input devices may further include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, game pads and graphic tablets, as well as audio / visual devices such as speakers, digital cameras, digital video cameras, portable media players, webcams, image scanners, fingerprint scanners, barcode readers 3D scanners, 3D printers, laser distance measuring devices, and eye tracking devices. In addition, the user interface input devices may include medical imaging input devices such as, for example, computed tomography, magnetic resonance imaging, positron emission tomography, and medical ultrasound devices. The user interface input devices may further include audio input devices such as, for example, MIDI keyboard digital musical instruments.

[0066] User interface output devices may include non-visual displays such as a display subsystem, indicator lights, or audio output devices, etc. The display subsystem may be a flat panel device such as one using a cathode ray tube (CRT), liquid crystal display (LCD) or plasma display, a projection device, a touch screen, etc. In general, use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from computer system 1000 to a user or to another computer. For example, user interface output devices may include, but are not limited to, various display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output devices, modems, etc.

[0067] Computer system 1000 can include a storage subsystem 1018 that includes software elements shown as currently located in system memory 1010. The system memory 1010 can store program instructions that are loadable and executable on the processing unit 1004, as well as data generated during the execution of these programs.

[0068] Depending on the configuration and type of computer system 1000, the system memory 1010 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible to and / or currently being operated on and executed by the processing unit 1004. In some implementations, the system memory 1010 may include a number of different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS), containing the basic routines that help to transfer information between elements within the computer system 1000, such as during start-up, may typically be stored in ROM. By way of example, and not limitation, the system memory 1010 also illustrates application programs 1012, which may include client applications, a web browser, mid-tier applications, a relational database management system (RDBMS), and the like, program data 1014, and an operating system 1016. By way of example, operating system 1016 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or mobile operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS operating systems.

[0069] The storage subsystem 1018 may also comprise a tangible computer readable storage medium for storing basic programming and data constructs that provide the functionality of some embodiments. Software (programs, code modules, instructions) that, when executed by a processor, provide the functionality described above may be stored in the storage subsystem 1018. These software modules or instructions may be executed on the processing unit 1004. The storage subsystem 1018 may also comprise a repository for storing data used in accordance with some embodiments.

[0070] Storage subsystem 1018 may further include a computer readable storage medium reader 1020 that may be further connected to a computer readable storage medium 1022. Together with, and optionally in combination with, the system memory 1010, computer readable storage medium 1022 collectively represents remote, local, fixed, and / or removable storage media as well as storage media for containing, storing, transmitting, and retrieving computer readable information on a temporary and / or permanent basis.

[0071] The computer readable storage medium 1022 containing the code or portions of code may also include any suitable medium including, but not limited to, storage media and communication media such as volatile and non-volatile, removable and non-removable media implemented in any manner or technology for storage and / or transmission of information. This may include tangible computer readable storage media such as RAM, ROM, Electronically Erasable Programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible computer readable media. This may further include non-tangible computer readable media such as a data signal, data transmission, or any other medium that may be used to transmit the desired information and that may be accessed by computing system 1000.

[0072] By way of example, the computer readable storage medium 1022 may include hard disk drives that read from or write to non-removable, non-volatile magnetic media, magnetic disk drives that read from or write to removable, non-volatile magnetic disks, and optical disk drives that read from or write to removable, non-volatile optical disks, such as CD ROMs, DVDs, and Blu-Ray® disks, or other optical media. The computer readable storage medium 1022 may include, but is not limited to, Zip® drives, flash memory cards, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, DVD disks, digital video tapes, and the like. The computer readable storage medium 1022 may further include solid state drives (SSDs) based on non-volatile memory, such as flash memory-based SSDs, enterprise flash drives, solid state ROMs, and the like, SSDs based on volatile memory, such as solid state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs that use a combination of DRAM and flash memory-based SSDs. The disk drives and associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computer system 1000.

[0073] The communications subsystem 1024 provides an interface to other computer systems and networks. The communications subsystem 1024 serves as an interface for receiving data from other systems and transmitting data from the computer system 1000 to other systems. For example, the communications subsystem 1024 may enable the computer system 1000 to connect to one or more devices via the Internet. In some embodiments, the communications subsystem 1024 may include radio frequency (RF) transceiver components, global positioning system (GPS) receiver components, and / or other components for accessing wireless voice and / or data networks (e.g., using cellular technology, advanced data network technologies such as 3G, 4G, or EDGE (Enhanced Data Rates for Global Evolution), WiFi (IEEE 802.11 family standard), or other mobile communications technologies, or any combination thereof). In some embodiments, the communications subsystem 1024 may provide a wired network connection (e.g., Ethernet) in addition to or instead of a wireless interface.

[0074] In some embodiments, the communications subsystem 1024 can also receive incoming communications in the form of structured or unstructured data feeds 1026, event streams 1028, and event updates 1030 for one or more users using the computer system 1000.

[0075] As an example, the communications subsystem 1024 may be configured to receive data feeds 1026 in real-time from users of social networks and / or other communications services, such as web feeds such as Twitter® feeds, Facebook® updates, Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third party sources.

[0076] In addition, the communications subsystem 1024 may also be configured to receive data in the form of a continuous data stream, which may include an event stream 1028 of real-time events and / or event updates 1030, which may be continuous or infinite in nature with no explicit end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automotive traffic monitoring, etc.

[0077] The communications subsystem 1024 can also be configured to output structured and / or unstructured data feeds 1026, event streams 1028, event updates 1030, etc. to one or more databases that can communicate with one or more streaming data source computers coupled to the computer system 1000.

[0078] The computer system 1000 can be one of a variety of types, including a handheld portable device (e.g., an iPhone® mobile phone, an iPad® computing tablet, a PDA), a wearable device (e.g., a Google Glass® head mounted display), a PC, a workstation, a mainframe, a kiosk, a server rack, or any other data processing system.

[0079] Due to the ever-changing nature of computers and networks, the description of the computer system 1000 shown in the figures is intended only as a specific example. Many other configurations are possible having more or fewer components than the system shown in the figures. For example, customized hardware may also be used, and / or particular elements may be implemented in hardware, firmware, software (including applets), or a combination. Furthermore, connections to other computing devices, such as network input / output devices, may be used. Other ways and / or methods of implementing the various embodiments will be apparent based on the disclosure and teachings provided herein.

[0080] In the foregoing description, the term "about" may be interpreted to mean within 10% of the stated value. For example, about 10.0V may be interpreted as a range between 9.0V and 11.0V. The term "substantially" may be interpreted to mean at least about 90% of a value. For example, substantially filling an area may be interpreted as filling about 90% of the area.

[0081] In the foregoing specification, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0082] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the several embodiments as set forth in the appended claims.

[0083] Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0084] Further, it is noted that the particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, or the like. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or to the main function.

[0085] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media that can store, contain, or carry instructions and / or data. A code segment or machine-executable instructions can represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment can be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. can be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0086] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0087] In the foregoing specification, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of the several embodiments may be used individually or together. Moreover, the embodiments may be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative and not restrictive.

[0088] Additionally, for purposes of illustration, the method has been described in a particular order. It should be appreciated that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be appreciated that the above-described method may be performed by hardware components or embodied in a sequence of machine-executable instructions that may be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuitry programmed with the instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or any other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the method may be performed by a combination of hardware and software.

Claims

1. 1. A circuit for controlling a headroom voltage of a transistor stage of an electroplating system to maintain target power dissipation across the transistor stage, comprising: a transistor stage for providing headroom voltage to a load of the electroplating system; a power measurement circuit coupled to the transistor stage, the power measurement circuit providing a signal representative of an instantaneous power dissipation of the transistor stage; a difference circuit that receives the signal representative of the instantaneous power dissipation of the transistor stage from the power measurement circuit and receives a signal representative of the target power dissipation of the transistor stage and generates a difference output; an adjustable voltage source supplying a voltage across the transistor stage and the load, the adjustable voltage source being configured to use the differential output to adjust the headroom voltage, thereby maintaining the target power dissipation of the transistor stage; The circuit includes:

2. The power measurement circuit comprises: a voltage measurement circuit coupled to the transistor stage for providing a measurement representative of a voltage across the transistor stage; The circuit of claim 1 further comprising:

3. The power measurement circuit comprises: a current measurement circuit coupled to the transistor stage for providing a measurement representative of a current through the transistor stage; The circuit of claim 2 further comprising:

4. The power measurement circuit comprises: a multiplier circuit that receives the measurement representative of the voltage across the transistor stage and the measurement representative of the current through the transistor stage and generates the signal representative of the instantaneous power dissipation of the transistor stage. The circuit of claim 3 further comprising:

5. 2. The circuit of claim 1, wherein the difference circuit includes an operational amplifier that provides an output to an AC to DC converter.

6. 2. The circuit of claim 1, further comprising a differential amplifier that receives a signal representative of a target current through the transistor stage and receives an instantaneous current through the transistor stage.

7. 7. The circuit of claim 6, wherein the differential amplifier supplies gate voltages to the transistor stages to achieve the target current through the transistor stages.

8. 2. The circuit of claim 1, wherein the signal representative of the instantaneous power dissipation of the transistor stage comprises a voltage proportional to the instantaneous power dissipation.

9. 1. A method of controlling a headroom voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage, comprising: maintaining a headroom voltage of the transistor stage for a load of the electroplating system; measuring an instantaneous power dissipation of said transistor stage; generating a difference output representing a difference between the instantaneous power dissipation of the transistor stage and the target power dissipation of the transistor stage; adjusting a voltage across the transistor stage and the load using the differential output such that the headroom voltage of the transistor stage is adjusted to maintain the target power dissipation of the transistor stage; A method comprising:

10. The method of claim 9 , further comprising determining a voltage across the transistor stage.

11. The method of claim 9 , further comprising determining a current through the transistor stage.

12. 10. The method of claim 9, further comprising multiplying a signal representative of a voltage across the transistor stage with a signal representative of a current through the transistor stage to determine the instantaneous power dissipation of the transistor stage.

13. 10. The method of claim 9, further comprising: decreasing the headroom voltage of the transistor stage when a current through the transistor stage increases.

14. The method of claim 9 , further comprising: scaling down a signal representative of the instantaneous power dissipation of the transistor stage.

15. 10. The method of claim 9, wherein the generation of the voltage transient across the transistor stage and the load has a fall time of less than 10 ms.

16. 1. A circuit for controlling a headroom voltage of a transistor stage of an electroplating system to maintain target power dissipation across the transistor stage, comprising: a transistor stage of the electroplating system that provides a headroom voltage to a load; a power measurement circuit coupled to the transistor stage, the power measurement circuit providing a signal representative of an instantaneous power dissipation of the transistor stage; an adjustable voltage source supplying a voltage across the transistor stage and the load, the adjustable voltage source being configured to adjust the headroom voltage of the transistor stage in response to the instantaneous power dissipation of the transistor stage to maintain the target power dissipation of the transistor stage; The circuit includes:

17. 20. The circuit of claim 16, wherein the target power dissipation is represented by a plurality of series resistors forming a voltage divider.

18. The circuit of claim 16 , wherein the adjustable voltage source comprises an AC-DC power converter.

19. The circuit of claim 16 , wherein the power measurement circuit is implemented using a microprocessor or microcontroller.

20. 20. The circuit of claim 16, further comprising a serial interface that receives serial commands from a controller and converts the serial commands into a plurality of analog and digital signals to control a circuit for controlling the headroom voltage of the transistor stage.

Images