Image display device manufacturing method and image display device

Abstract

A production method for an image display device according to one embodiment comprises: a step for preparing a second substrate in which a semiconductor layer has been formed on a first substrate; a step for bonding the semiconductor layer to a third substrate; a step for removing the first substrate; a step for etching the semiconductor layer and forming a light-emitting element including a light-emitting surface that is opposite to the bottom surface on the third substrate; a step for forming a first insulating film that covers the third substrate and the light-emitting element; a step for forming a circuit element on the first insulating film; a step for forming a second insulating film that covers the circuit element together with the first insulating film; a step for removing a part of the first and second insulating films and exposing the surface that includes the light-emitting surface; a step for forming a via that traverses the first and second insulating films; and a step for forming a wiring layer on the second insulating film.

Description

[Technical field]

[0001] An embodiment of the present invention relates to a manufacturing method for an image display device and an image display device. [Background technology]

[0002] There is a demand for a thin image display device that has high brightness, a wide viewing angle, high contrast, and low power consumption. In order to meet such market demands, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is expected as a self-emitting element. As a manufacturing method for display devices using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a driving circuit has been introduced. However, as the number of micro LED elements increases with the trend toward higher image quality such as full high definition, 4K, 8K, etc., the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and sequentially transferred to a substrate on which a driving circuit, etc. is formed. Furthermore, there is a risk of poor connection between the micro LEDs and the driving circuit, etc., resulting in a decrease in yield.

[0004] A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a driving circuit is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-141492 A Summary of the Invention [Problem to be solved by the invention]

[0006] An embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0007] A manufacturing method for an image display device according to one embodiment of the present invention includes the steps of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate, forming a first metal layer on a third substrate, bonding the semiconductor layer to the first metal layer, removing the first substrate, etching the semiconductor layer to form a light-emitting element including a bottom surface on the first metal layer and a light-emitting surface facing the bottom surface, forming a first insulating film covering the third substrate and the light-emitting element, forming a circuit element on the first insulating film, forming a second insulating film covering the circuit element and the first insulating film, removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light-emitting surface, and forming a wiring layer on the second insulating film.

[0008] A manufacturing method for an image display device according to one embodiment of the present invention includes the steps of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate, forming a second metal layer on the second substrate, bonding the semiconductor layer to a third substrate via the second metal layer, removing the first substrate, etching the semiconductor layer to form a light-emitting element including a bottom surface on the second metal layer and a light-emitting surface facing the bottom surface, forming a first insulating film covering the third substrate and the light-emitting element, forming a circuit element on the first insulating film, forming a second insulating film covering the circuit element and the first insulating film, removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light-emitting surface of the light-emitting element, and forming a wiring layer formed on the second insulating film.

[0009] An image display device according to one embodiment of the present invention comprises a substrate having a first surface, a conductive layer provided on the first surface, a light-emitting element having a bottom surface on the conductive layer and including a light-emitting surface which is a surface facing the bottom surface, a first insulating film covering a side surface of the light-emitting element and the conductive layer, a circuit element provided on the first insulating film, a second insulating film covering the circuit element and the first insulating film, and a wiring layer provided on the second insulating film.

[0010] An image display device according to one embodiment of the present invention comprises a substrate having a first surface, a conductive layer provided on the first surface, a semiconductor layer having a bottom surface on the conductive layer and including a plurality of light-emitting surfaces on a surface facing the bottom surface, a first insulating film covering a side surface of the semiconductor layer and the conductive layer, a plurality of transistors provided on the first insulating film, a second insulating film covering the plurality of transistors and the first insulating film, and a wiring layer provided on the second insulating film. Effect of the Invention

[0011] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer process of light emitting elements and improves yield. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. [Diagram 2] FIG. 11 is a cross-sectional view that illustrates a schematic view of a part of an image display device according to a modified example of the first embodiment. [Diagram 3] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 4] FIG. 2 is a schematic plan view illustrating a portion of the image display device according to the first embodiment. [Figure 5A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 5B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 6]1A to 1C are schematic perspective views illustrating a method for manufacturing the image display device according to the first embodiment. [Figure 7A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 7B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 9A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 9B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 10A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 10B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 12A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the first embodiment. [Figure 12B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the first embodiment. [Figure 13] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 14A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 14B]2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 14C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 14D] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 15] FIG. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 16] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a second embodiment. [Figure 17] FIG. 11 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 18A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 18B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 18C] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 19A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 19B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 20A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 20B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 21A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 21B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 22] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a third embodiment. [Figure 23A]10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 23B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 24A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 24B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 25A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 25B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 26] FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fourth embodiment. [Figure 27A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 27B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 28] FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fifth embodiment. [Figure 29A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 29B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Diagram 30] 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a sixth embodiment. FIG. [Figure 31A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Figure 31B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Figure 32A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Figure 32B]13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Figure 33A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Figure 33B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a sixth embodiment. [Diagram 34] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the sixth embodiment. [Figure 35A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment. [Figure 35B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment. [Figure 35C] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment. [Figure 36A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment. [Figure 36B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the sixth embodiment. [Figure 37] 1 is a graph illustrating the characteristics of a pixel LED element. [Figure 38] FIG. 13 is a block diagram illustrating an image display device according to a seventh embodiment. [Figure 39] FIG. 13 is a block diagram illustrating an image display device according to a modified example of the seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed description thereof will be omitted as appropriate.

[0014] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. 1 shows a schematic configuration of a sub-pixel 20 of an image display device according to this embodiment. A pixel constituting an image displayed on the image display device is made up of a plurality of sub-pixels 20.

[0015] In the following, the three-dimensional coordinate system of XYZ may be used for explanation. The subpixels 20 are arranged in a two-dimensional plane as shown in FIG. 15, which will be described later. The two-dimensional plane on which the subpixels 20 are arranged is defined as the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line AA' in FIG. 4, which will be described later, and is a cross section obtained by connecting cross sections in a plurality of planes perpendicular to the XY plane on one plane. In other figures, as in FIG. 1, in cross sections in a plurality of planes perpendicular to the XY plane, the X-axis and Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z-axis is defined as the XY plane. For convenience, the positive direction of the Z-axis may be referred to as "up" or "upward" and the negative direction of the Z-axis may be referred to as "down" or "downward", but the direction along the Z-axis is not necessarily the direction in which gravity is applied. The length along the Z-axis may be referred to as the height.

[0016] The subpixel 20 has a light emitting surface 151S that is substantially parallel to the XY plane. The light emitting surface 151S is a surface that mainly emits light in the positive direction of the Z axis that is perpendicular to the XY plane.

[0017] As shown in FIG. 1, a subpixel 20 of an image display device includes a substrate 102, a conductive layer 130, a light emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, and a wiring layer 110.

[0018] In this embodiment, the substrate 102 on which the light emitting element 150 is formed is a light-transmitting substrate, for example, a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface that is substantially parallel to the XY plane. The light emitting element 150 is formed on the first surface 102a. The light emitting element 150 is driven by a transistor 103 provided via a first interlayer insulating film 156. The transistor 103 is a thin film transistor (TFT), and is formed on the first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate has been established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing plants.

[0019] The subpixel 20 further includes a color filter 180. The color filter 180 (wavelength conversion member) is provided on the surface resin layer 170 via a transparent thin-film adhesive layer 188. The surface resin layer 170 is provided on the second interlayer insulating film 108 and the wiring layer 110.

[0020] The configuration of the sub-pixel 20 will be described in detail below. The conductive layer 130 is provided on the first surface 102a. The conductive layer 130 includes a connection plate 130a (first portion). The light-emitting element 150 is provided on the connection plate 130a. The connection plate 130a is a film-like, layer-like, or plate-like conductive member having a rectangular or any polygonal, elliptical, circular, or other shape in the XY plane view. The connection plate 130a is electrically connected to the bottom surface 153B of the light-emitting element 150.

[0021] The conductive layer 130 and the connection plate 130a are formed of, for example, Al, an alloy of Al, a laminated film of Al and Ti, or the like. For example, in a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al. Therefore, the connection plate 130a has light reflectivity. By providing a highly light-reflective metal material such as Ag on a metal layer such as Al or Ti, the light reflectivity can be further improved.

[0022] The light emitting element 150 is provided on the connection plate 130a. Preferably, a connection plate 130a is provided for each light emitting element 150.

[0023] The light emitting element 150 includes a bottom surface 153B and a light emitting surface 151S. The light emitting element 150 is a prismatic or cylindrical element having a bottom surface 153B on the connection plate 130a. The bottom surface 153B is provided on the connection plate 130a and is electrically connected to the connection plate 130a. The light emitting surface 151S is a surface of the light emitting element 150 facing the bottom surface 153B.

[0024] Preferably, the outer periphery of the connection plate 130a is set to include the outer periphery of the light-emitting element 150 when projected in the XY plane. The connection plate 130a has light reflectivity, and thereby reflects scattered light downward from the light-emitting element 150 to the light-emitting surface 151S side, thereby substantially improving the light-emitting efficiency.

[0025] Preferably, the outer periphery of the connection plate 130a is set so as not to include the outer periphery of the transistor 103 when the transistor 103 described below is projected onto an XY plane including the connection plate 130a. The transistor 103 is less susceptible to reflected light from the connection plate 130a, and the probability of malfunction or the like can be sufficiently reduced. The outer periphery of the transistor refers to the outer periphery of the TFT channel 104.

[0026] The light emitting element 150 includes a p-type semiconductor layer 153, a light emitting layer 152, and an n-type semiconductor layer 151. The p-type semiconductor layer 153, the light emitting layer 152, and the n-type semiconductor layer 151 are laminated in this order from the bottom surface 153B toward the light emitting surface 151S. Therefore, the p-type semiconductor layer 153 is electrically connected to the connection plate 130a.

[0027] When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane view is, for example, substantially square or rectangular. When the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane view is cylindrical, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape, arrangement, etc. of the light emitting element in the plan view, the degree of freedom of layout is improved.

[0028] The light emitting element 150 may include, for example, In X Al Y Ga 1-X-Y A gallium nitride compound semiconductor including a light emitting layer of, for example, N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, about 467 nm±20 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be any appropriate value.

[0029] The area of ​​the light-emitting layer 152 in the XY plane view is set according to the light-emitting colors of the red, green, and blue sub-pixels. Hereinafter, the area in the XY plane view may be simply referred to as the area. The area of ​​the light-emitting layer 152 is appropriately set depending on the luminosity factor and the conversion efficiency of the color conversion unit 182 of the color filter 180 described later. In other words, the area of ​​the light-emitting layer 152 of the sub-pixels 20 of each light-emitting color may be the same or may differ for each light-emitting color. The area of ​​the light-emitting layer 152 is the area of ​​the region surrounded by the periphery of the light-emitting layer 152 projected onto the XY plane.

[0030] The first interlayer insulating film (first insulating film) 156 covers the first surface 102a and the conductive layer 130. The first interlayer insulating film 156 covers the side surface of the light-emitting element 150. The first interlayer insulating film 156 does not cover the light-emitting surface 151S. The first interlayer insulating film 156 insulates the light-emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light-emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from thermal stress and the like when forming the transistor 103 and the like.

[0031] The first interlayer insulating film 156 is formed of a dielectric material such as an organic insulating material. The organic insulating material used for the first interlayer insulating film 156 is preferably a white resin. Since the white resin reflects the lateral emitted light of the light emitting element 150 and the return light caused by the interface of the color filter 180, etc., using a white resin for the first interlayer insulating film 156 contributes to a substantial improvement in the light emitting efficiency of the light emitting element 150.

[0032] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin, such as SOG (Spin On Glass), or a novolac-type phenol-based resin. The scattering particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. The scattering particles preferably have a diameter of about 1 / 2 the wavelength of the light. For example, TiO 2 , Al 2 SO 3 , ZnO, etc.

[0033] Alternatively, the white resin can be formed by utilizing a large number of fine voids dispersed in a transparent resin. In order to whiten the first interlayer insulating film 156, a SiO 2 film formed by, for example, ALD (Atomic-Layer-Deposition) or CVD (Chemical Vapor Deposition) is layered on the SOG or the like.2 A membrane or the like may also be used.

[0034] The first interlayer insulating film 156 may be a black resin. By making the first interlayer insulating film 156 a black resin, scattering of light in the subpixels 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display sharper images.

[0035] A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided for the purpose of ensuring flatness when the transistor 103 is formed, and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is made of, for example, SiO 2 and the like are insulating films.

[0036] The transistor 103 is formed on a TFT lower layer film 106. In addition to the transistor 103, other circuit elements such as other transistors and a capacitor are formed on the TFT lower layer film 106, and a circuit 101 is formed by wiring and the like. For example, in FIG. 3 described later, the transistor 103 corresponds to a drive transistor 26. In FIG. 3, other circuit elements include a selection transistor 24 and a capacitor 28. The circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a wiring layer 110.

[0037] In this example, the transistor 103 is an n-channel thin film transistor (TFT). The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous Si region formed on the TFT underlayer film 106. For example, laser annealing is used to polycrystallize and activate the amorphous Si region. The TFT formed by the LTPS process has a sufficiently high mobility.

[0038] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT lower layer film 106. The region 104i is provided between the region 104s and the region 104d. The regions 104s and 104d are doped with n-type impurities such as phosphorus (P), and are ohmic-connected to the vias 111s and 111d.

[0039] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate the gate 107 from other adjacent circuit elements. When a potential higher than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, thereby controlling the current flowing between the regions 104s and 104d.

[0040] The insulating layer 105 is, for example, SiO 2 The insulating layer 105 is made of SiO 2 Or Si 3 N 4 The insulating layer may be a multi-layer insulating layer including the above.

[0041] The gate 107 may be made of, for example, polycrystalline Si, or may be made of a high melting point metal such as W or Mo. The polycrystalline Si film of the gate 107 is formed by, for example, CVD or the like.

[0042] The second interlayer insulating film 108 is provided on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of, for example, a white resin or SiO 2 The second interlayer insulating film 108 also functions as a planarizing film for forming the wiring layer 110.

[0043] The first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, and therefore are not provided above the light-emitting surface 151S. In other words, the light-emitting surface 151S is exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 158. As described later, the opening 158 is filled with a surface resin layer 170.

[0044] The vias 111s and 111d are provided penetrating the second interlayer insulating film 108 and the insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes a plurality of wirings that may have different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110a.

[0045] A portion of the wiring 110s is provided above the region 104s. The wiring 110s is connected to a ground line 4 shown in FIG. 3, which will be described later, for example. A portion of the wiring 110d is provided above the region 104d. Another portion of the wiring 110d is provided near the light-emitting surface 151S, but is not connected to the light-emitting surface 151S. A portion of the wiring 110a is provided above the connection plate 130a. The wiring 110a is connected to a power line 3 shown in FIG. 3, which will be described later, for example.

[0046] In each of the cross-sectional views from FIG. 1 onwards, unless otherwise specified, the reference numerals for the wiring layers are shown beside one of the wires included in the wiring layer.

[0047] The transparent electrode 159d is provided over the wiring 110d. The transparent electrode 159d is provided over the light-emitting surface 151S. The transparent electrode 159d is also provided between the wiring 110d and the light-emitting surface 151S, and electrically connects the wiring 110d and the light-emitting surface 151S.

[0048] The translucent electrode 159s is provided over the wiring 110s. The translucent electrode 159s is connected together with the wiring 110s to, for example, the ground line 4 of the circuit of FIG. 3. The translucent electrode 159a is provided over the wiring 110a. The translucent electrode 159a is connected together with the wiring 110a to, for example, the power line 3 of the circuit of FIG. 3. The translucent electrodes 159d, 159s, and 159a are formed of a translucent conductive film. An ITO film, a ZnO film, or the like is preferably used for the translucent electrodes 159d, 159s, and 159a.

[0049] As in this example, the light emitting surface 151S is preferably roughened. When the light emitting surface 151S of the light emitting element 150 is roughened, the light extraction efficiency can be improved.

[0050] By providing the transparent electrode 159d on the light-emitting surface 151S, the connection area between the transparent electrode 159d and the n-type semiconductor layer 151 can be increased, the area of ​​the light-emitting surface 151S can be substantially increased, and the connection resistance can be reduced. Furthermore, since the area of ​​the light-emitting surface 151S can be substantially increased, the light-emitting efficiency can be improved. Since the light-emitting surface 151S is a rough surface, the connection area between the light-emitting surface 151S and the transparent electrode 159d can be increased to reduce the contact resistance, thereby further improving the light-emitting efficiency.

[0051] The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0052] The wiring 110s is connected to the region 104s through a via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the ground line 4 through the via 111s and the wiring 110s.

[0053] The wiring 110d and the transparent electrode 159d are connected to the region 104d through the via 111d. The region 104d is the drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the n-type semiconductor layer 151 through the via 111d, the wiring 110d, and the transparent electrode 159d.

[0054] The via 161a is provided penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 161a is provided between the wiring 110a and the connection plate 130a, and electrically connects the wiring 110a and the connection plate 130a. Therefore, the p-type semiconductor layer 153 is electrically connected to, for example, the power line 3 of the circuit in FIG. 3 through the connection plate 130a, the via 161a, the wiring 110a, and the light-transmitting electrode 159a.

[0055] The wiring layer 110 and the vias 111s, 111d, and 161a are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0056] The surface resin layer 170 covers the second interlayer insulating film 108, the wiring layer 110, and the translucent electrodes 159s, 159d, and 159a. The surface resin layer 170 is also filled in the opening 158. The surface resin layer 170 is provided on the light-emitting surface 151S via the translucent electrode 159d. The surface resin layer 170 filled in the opening 158 is provided on the translucent electrode 159d provided so as to cover the respective side surfaces of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, and protects the interlayer insulating film 156 and the wiring layer 110, and provides a flat surface for bonding the color filter 180.

[0057] The color filter 180 includes a light shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly above the light emitting surface 153S of the light emitting element 150 in accordance with the shape of the light emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 is made into a light shielding portion 181. The light shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a sharp image.

[0058] The color conversion section 182 may have one layer or two or more layers. FIG. 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., the wavelength, of the light emitted by the subpixel 20. When the emission color of the subpixel 20 is red, the color conversion section 182 is preferably made up of two layers, that is, the color conversion layer 183 and the filter layer 184 that transmits red light. When the emission color of the subpixel 20 is green, the color conversion section 182 is preferably made up of two layers, that is, the color conversion layer 183 and the filter layer 184 that transmits green light. When the emission color of the subpixel 20 is blue, the color conversion section 182 is preferably made up of one layer.

[0059] When color conversion section 182 has two layers, the first layer is color conversion layer 183 and the second layer is filter layer 184. First color conversion layer 183 is provided at a position closer to light emitting element 150. Filter layer 184 is laminated on color conversion layer 183.

[0060] The color conversion layer 183 converts the wavelength of light emitted by the light emitting element 150 into a desired wavelength. In the case of a subpixel 20 that emits red light, the color conversion layer 183 converts the light of the wavelength of the light emitting element 150, 467 nm±20 nm, into light of a wavelength of, for example, about 630 nm±20 nm. In the case of a subpixel 20 that emits green light, the color conversion layer 183 converts the light of the wavelength of the light emitting element 150, 467 nm±20 nm, into light of a wavelength of, for example, about 532 nm±20 nm.

[0061] Filter layer 184 blocks the wavelength component of blue emitted light that remains without being color converted by color conversion layer 183 .

[0062] When the color of light emitted by the subpixel 20 is blue, the subpixel 20 may output the light via the color conversion layer 183, or may output the light directly without passing through the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is about 467 nm±20 nm, the subpixel 20 may output the light without passing through the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is 410 nm±20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm±20 nm.

[0063] Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with the filter layer 184 that transmits blue light, minute reflection of external light other than blue light that occurs on the surface of the light-emitting element 150 is suppressed.

[0064] FIG. 2 is a cross-sectional view that diagrammatically shows a part of an image display device according to a modified example of this embodiment. In the case of FIG. 2, the subpixel 20a is different from the first embodiment in the method of connecting the light-emitting element 150a and the wiring 110d1. This modification also differs from the first embodiment in that no translucent electrodes are provided on the wirings 110s, 110d1, and 110a. In other respects, this modification is the same as the first embodiment, and the same components are denoted by the same reference numerals and detailed descriptions are omitted as appropriate. Note that FIG. 2 also shows the structure above the surface resin layer 170. These upper structures are also the same as those in the first embodiment.

[0065] As shown in FIG. 2, the subpixel 20a includes a light-emitting element 150a and a wiring 110d1. A part of the wiring 110d1 is provided above the region 104d. Another part of the wiring 110d1 is provided extending to the light-emitting surface 151S, and its tip is connected to a surface including the light-emitting surface 151S. The surface including the light-emitting surface 151S is a surface in the same plane as the light-emitting surface 151S. The tip of the wiring 110d1 is connected to a surface on this surface other than the light-emitting surface 151S. In this example, the light-emitting surface 151S is not roughened, but may be roughened. If the light-emitting surface 151S is not roughened, the step of roughening the surface can be omitted.

[0066] This embodiment may include any of the configurations of sub-pixels 20, 20a shown above.

[0067] FIG. 3 is a schematic block diagram illustrating the image display device according to the present embodiment. 3, the image display device 1 of this embodiment includes a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged, for example, in a lattice pattern. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

[0068] A pixel 10 includes a number of sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 20R, 20G, and 20B emitting light at a desired brightness.

[0069] One pixel 10 includes three sub-pixels 20R, 20G, and 20B, which are arranged linearly on the X-axis, as shown in Fig. 3. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or, as in this example, sub-pixels of different colors may be arranged in each column.

[0070] The image display device 1 further includes a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and supply power to each sub-pixel 20 from a DC power supply connected between a power supply terminal 3a and a GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with respect to the GND terminal 4a.

[0071] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction arrangement of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction arrangement of the sub-pixels 20.

[0072] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0073] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0074] The subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3 and Figure 4 described below, the selection transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0075] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is an n-channel TFT, and the cathode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a luminance according to the current flowing through it.

[0076] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a ground line 4.

[0077] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light with a luminance corresponding to the current passing through the light-emitting element 22.

[0078] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned sub-pixels 20, causing them to emit light. Each pixel 10 emits light with a color and brightness determined by the color and brightness emitted by the RGB sub-pixels 20, and an image is displayed in the display area 2.

[0079] FIG. 4 is a schematic plan view illustrating a part of the image display device of the present embodiment. In this embodiment, as described in FIG. 1, the light emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction via the first interlayer insulating film 156. In other words, the light emitting element 150 is formed in a layer different from the layer in which the transistor 103 is formed. The light emitting element 150 corresponds to the light emitting element 22 in FIG. 3. The driving transistor 103 corresponds to the driving transistor 26 in FIG. 3, and is also represented as T2. To avoid complication, the translucent electrodes are not shown in FIG. 4.

[0080] 4, the anode electrode of the light emitting element 150 is disposed on the connection plate 130a and is electrically connected to the connection plate 130a. The connection plate 130a is provided in a layer lower than the transistor 103 and the wiring layer 110. The connection plate 130a is electrically connected to the wiring 110a through a via 161a. More specifically, one end of the via 161a is connected to the connection plate 130a, and the other end of the via 161a is connected to the wiring 110a through a contact hole 161a1.

[0081] The cathode electrode of the light-emitting element 150 is provided by the n-type semiconductor layer 151 shown in Fig. 1. The wiring 110d is covered with the translucent electrode 159d shown in Fig. 1. The translucent electrode 159d covers the light-emitting surface 151S. Since the translucent electrode 159d is also provided between the wiring 110d and the light-emitting surface 151S, the cathode electrode of the light-emitting element 150 is electrically connected to the wiring 110d.

[0082] A part of the wiring 110d is connected to the drain electrode of the transistor 103 through a via 111d. The drain electrode of the transistor 103 is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through a via 111s. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the wiring layer 110 includes a ground line 4, and the wiring 110s is connected to the ground line 4.

[0083] In this example, the power line 3 is provided in a layer even higher than the wiring layer 110. Although not shown in Fig. 1, an interlayer insulating film is further provided on the wiring layer 110. The power line 3 is provided on the uppermost interlayer insulating film and is insulated from the ground line 4.

[0084] In this manner, by using the via 161a, the light emitting element 150 can be electrically connected to the wiring 110a provided in a layer above the light emitting element 150. In addition, by providing an opening 158 that exposes the light emitting surface 151S and providing a light-transmitting electrode 159d across the opening 158, the light emitting element 150 can be electrically connected to the transistor 103 provided in a layer above the light emitting element 150 through the wiring 110d.

[0085] Moreover, the outer periphery of the connection plate 130a includes the outer periphery of the light emitting element 150. The outer periphery of the connection plate 130a is set so as not to include the outer periphery of the TFT channel 104. This improves the substantial light emitting efficiency of the light emitting element 150 and prevents malfunction of the transistor including the TFT channel 104 due to light irradiation.

[0086] A method for manufacturing the image display device 1 of this embodiment will be described. 5A and 5B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. 5A, in the manufacturing method of the image display device 1 of this embodiment, a plurality of semiconductor growth substrates 1194 are prepared. Each of the plurality of semiconductor growth substrates (second substrates) 1194 includes a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. The crystal growth substrate 1001 (first substrate) is, for example, a Si substrate or a sapphire substrate. Preferably, a Si substrate is used as the crystal growth substrate 1001. In addition, when a low-temperature crystal growth process such as low-temperature sputtering or ALD (Atomic Layer Deposition) is used as described later, a less expensive glass substrate or the like can also be used as the crystal growth substrate 1001.

[0087] The buffer layer 1140 is formed on one surface of the crystal growth substrate 1001. A nitride such as AlN is preferably used for the buffer layer 1140. By growing the semiconductor layer 1150 through the buffer layer 1140, it is possible to reduce mismatch at the interface between the GaN crystal and the crystal growth substrate 1001.

[0088] The semiconductor layer 1150 is formed on the buffer layer 1140. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, an emission layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the emission layer 1152, and the p-type semiconductor layer 1153 are stacked in this order from the buffer layer 1140 side. The semiconductor layer 1150 is formed, for example, by a chemical vapor deposition (CVD) method, and a metal organic chemical vapor deposition (MOCVD) method is preferably used. Alternatively, even at a process temperature of 700° C. or less, the semiconductor layer 1150 can be epitaxially grown by a low-temperature sputtering method, and thus the manufacturing cost can be reduced by using a glass substrate or device with low heat resistance. The semiconductor layer 1150 includes, for example, GaN, and more specifically, In. X Al Y Ga 1-X-Y Includes N (0≦X, 0≦Y, X+Y<1), etc.

[0089] In the early stage of crystal growth, crystal defects due to mismatch of crystal lattice constants may occur, and crystals with crystal defects exhibit n-type. Therefore, when the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001 as in this example, there is an advantage that the margin in the production process can be made large, and the yield can be easily improved.

[0090] As shown in Fig. 5B, a substrate 102 (third substrate) is prepared. A metal layer (first metal layer) 1130 is formed over a first surface 102a, which is one surface of the substrate 102. The metal layer 1130 is formed of, for example, Al, an alloy of Al, or a laminated film of Al and Ti. Preferably, a metal material with high light reflectivity, such as Ag, is provided on a metal layer such as Al.

[0091] In the plurality of semiconductor growth substrates 1194, the exposed surface of the p-type semiconductor layer 1153 is disposed opposite to the exposed surface of the metal layer 1130. The semiconductor layer 1150 is bonded to the substrate 102 via the metal layer 1130. A metal layer may also be formed on the exposed surface of the p-type semiconductor layer 1153, and the exposed surfaces of the metal layers may be disposed opposite to each other and bonded to each other.

[0092] In the substrate bonding process, for example, the substrates can be bonded to each other by heating and thermocompression bonding the substrates. A low melting point metal or a low melting point alloy may be used in the thermocompression bonding. The low melting point metal may be, for example, Sn or In, and the low melting point alloy may be, for example, an alloy mainly composed of Zn, In, Ga, Sn, Bi, or the like.

[0093] In the substrate bonding process as shown in FIG. 5B, in addition to the above, the bonding surfaces of the substrates may be planarized using chemical mechanical polishing (CMP) or the like, and then the bonding surfaces may be cleaned by plasma treatment in a vacuum to adhere to each other.

[0094] The substrate 102 is, for example, a substantially rectangular glass substrate of about 1500 mm×1800 mm. The semiconductor growth substrate 1194 is rectangular or square with a size of about 10 mm square to 150 mm square, and is, for example, about 4 inches to 6 inches in wafer size. The size of the substrate 102 is appropriately selected depending on the size of the image display device, etc. When the size of the substrate 102 is, for example, a rectangular or square with a size of about 10 mm square to 150 mm square, one semiconductor layer 1150 may be bonded to one substrate 102.

[0095] FIG. 6 is a perspective view illustrating a method for manufacturing the image display device of this embodiment. The diagram above the arrow in Fig. 6 shows that a plurality of substrates 1194 are arranged in a lattice pattern. The diagram below the arrow in Fig. 6 shows that a substrate 102 having a metal layer 1130 formed thereon is arranged. In Fig. 6, the arrows indicate that the plurality of substrates 1194 arranged in a lattice pattern are arranged so that the semiconductor layer 1150 faces the metal layer 1130, and are bonded to each other. Since the crystal quality deteriorates at and near the ends of the semiconductor layer 1150, care must be taken to avoid forming the light emitting element 150 at and near the ends of the semiconductor layer 1150. As shown in Fig. 6, the ends of the semiconductor layer 1150 are formed so as to almost coincide with the ends of the crystal growth substrate 1001. Therefore, the multiple semiconductor growth substrates 1194 are arranged facing the substrate 102 in a lattice pattern, for example, as shown by the solid line in Fig. 6, so as to minimize gaps between adjacent substrates. The semiconductor layer 1150 is bonded to a metal layer 1130 formed on the substrate 102, as shown by the two-dot chain line in Fig. 6.

[0096] When a plurality of semiconductor layers 1150 are bonded to one substrate 102, the substrate 102 to which the plurality of semiconductor layers 1150 are bonded can be divided to produce image display devices of a number and size according to the number of divisions. The substrate 102 to which the plurality of semiconductor layers 1150 are bonded may be divided before or after the incorporation of color filters. Since it is preferable that the end of the semiconductor layer 1150 with a deteriorated crystal quality becomes the end of the display region, the unit of division is preferably set to match the shape of the semiconductor growth substrate 1194. The process of incorporation of color filters will be described later with reference to FIG. 13 and FIG. 14A to FIG. 14D.

[0097] 7A to 8C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. Figures 7A to 8C show two types of modified examples of the substrate bonding step. In the substrate bonding step, the steps of Figures 5A and 5B can be replaced with the steps of Figures 7A and 7B. Also, the steps of Figures 5A and 5B can be replaced with the steps of Figures 8A to 8C.

[0098] In the manufacturing process shown in FIGS. 7A and 7B, the semiconductor layer 1150 is formed on one surface of the crystal growth substrate 1001 without the buffer layer 1140 shown in FIG. 5A therebetween. As shown in Fig. 7A, a plurality of semiconductor growth substrates 1194a are prepared in place of the plurality of semiconductor growth substrates 1194 shown in Fig. 5A. Each of the plurality of semiconductor growth substrates 1194a includes a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is formed directly on one surface of the crystal growth substrate 1001. The semiconductor layer 1150 is formed by a CVD method, an MOCVD method, or the like, as in the case of Fig. 5A.

[0099] 7B, the exposed surface of the p-type semiconductor layer 1153 is disposed opposite to the exposed surface of the metal layer 1130 formed on the first surface 102a. Then, the exposed surface of the p-type semiconductor layer 1153 is bonded to the substrate 102 via the metal layer 1130.

[0100] 8A to 8C, a semiconductor layer 1150 formed on a crystal growth substrate 1001 is transferred to a support substrate 1190. The transferred semiconductor layer 1150 is bonded to a substrate 102 via a metal layer 1130 formed on the substrate 102. As shown in Fig. 8A, a plurality of semiconductor growth substrates 1294 are prepared. The semiconductor growth substrate 1294 includes a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. In the semiconductor growth substrate 1294, the buffer layer 1140 is formed on one surface of the crystal growth substrate 1001, and the semiconductor layer 1150 is formed via the buffer layer 1140. In the semiconductor layer 1150, a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151 are formed in this order from the buffer layer 1140 side.

[0101] 8B, the support substrate 1190 is bonded to the exposed surface of the n-type semiconductor layer 1151. The support substrate 1190 is made of, for example, silica glass or Si.

[0102] After the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 is removed to form the substrate 1295. The crystal growth substrate 1001 is removed by, for example, wet etching or laser lift-off.

[0103] As shown in Fig. 8C, the buffer layer 1140 shown in Fig. 8B is removed by wet etching or the like to form a substrate 1295a. The exposed surface of the p-type semiconductor layer 1153 exposed by removing the buffer layer 1140 is disposed opposite the metal layer 1130 formed on the first surface 102a. The semiconductor layer 1150 is bonded to the substrate 102 via the metal layer 1130.

[0104] In this manufacturing method, a buffer layer 1140 is formed on a crystal growth substrate 1001, and a semiconductor layer 1150 is formed via the buffer layer 1140, but the semiconductor layer 1150 may also be formed directly on the crystal growth substrate 1001 without the buffer layer 1140.

[0105] The steps up to forming the semiconductor growth substrates 1194, 1194a, and 1294 may be performed in the same plant as the plant performing the steps of bonding the semiconductor layer 1150 to the substrate 102 and thereafter, or may be performed in a different plant. For example, the semiconductor growth substrates 1194, 1194a, and 1294 and the substrate 1295 after bonding to the support substrate 1190 may be manufactured in a first plant, and the semiconductor growth substrate 1194 may be carried into a second plant different from the first plant, where the subsequent steps are performed.

[0106] The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and the following method can also be used. That is, after the semiconductor layer 1150 is formed on the crystal growth substrate 1001, the semiconductor layer 1150 is housed in a container with the crystal growth substrate 1001 removed, and is stored, for example, with a support substrate 1190 attached in the container. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102. Alternatively, the semiconductor layer 1150 is stored in the container without being attached to the support substrate 1190. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102 as is.

[0107] Returning to the manufacturing process after the substrate bonding process, the explanation will be continued. 9A to 11B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in Fig. 9A, the crystal growth substrate 1001 shown in Fig. 5B is removed by wet etching, laser lift-off, etc. In addition, the buffer layer 1140 shown in Fig. 5B is also removed by wet etching, etc.

[0108] 6, multiple semiconductor growth substrates 1194 are disposed adjacent to one another and bonded to substrate 102. Position X1 is a position where ends of adjacent semiconductor growth substrates 1194 are disposed. At position X1, ends of semiconductor layer 1150 are also adjacent to one another and close to one another.

[0109] As shown in Fig. 9B, the semiconductor layer 1150 shown in Fig. 9A is processed into a desired shape by etching to form the light emitting element 150. The light emitting element 150 is formed at a position sufficiently away from the region including the position X1. The region including the position X1 to be removed by etching is determined based on the evaluation results of the crystal quality near the end of the semiconductor layer 1150.

[0110] The light emitting element 150 is formed by, for example, a dry etching process, preferably anisotropic plasma etching (Reactive Ion Etching, RIE). The buffer layer 1140 shown in FIG. 9A may be used as a mask when forming the light emitting element 150. In this case, the buffer layer remaining on the light emitting element 150 is removed by wet etching or the like after the light emitting element 150 is formed.

[0111] After the light emitting element 150 is formed, the conductive layer 130 is formed by etching the metal layer 1130 shown in FIG. 9A. In the process of forming the conductive layer 130, the connection plate 130a is formed. In this manner, the connection plate 130a (first portion) is formed on the first surface 102a, and the light emitting element 150 is formed on the connection plate 130a. The outer periphery of the connection plate 130a is set so as to include the outer periphery of the light emitting element 150 when the light emitting element 150 is projected in a plan view.

[0112] As shown in FIG. 10A, a first interlayer insulating film 156 (first insulating film) covering the first surface 102a, the conductive layer 130, the connection plate 130a, and the light emitting element 150 is formed.

[0113] 10B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is formed by, for example, CVD or the like.

[0114] The TFT channel 104 is formed on the TFT underlayer film 106. For example, in the LTPS process, the TFT channel 104 is formed as follows. First, amorphous Si is deposited in the shape of the TFT channel 104. The amorphous Si is deposited by, for example, CVD or the like. The deposited amorphous Si film is polycrystallized by laser annealing, and the TFT channel 104 is formed.

[0115] Thereafter, the source electrode and the drain electrode of the TFT channel 104 are formed by introducing impurity ions such as phosphorus (P) into the regions 104s and 104d using, for example, an ion implantation technique, etc. The process of forming the source electrode and the drain electrode may be performed after the process of forming the gate 107.

[0116] The insulating layer 105 is formed over the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is formed by, for example, CVD or the like. The gate 107 is formed at a position above the TFT channel 104 via the insulating layer 105. An appropriate formation method is used to form the gate 107 depending on the material of the gate 107. For example, when the gate 107 is made of polycrystalline Si, it is formed by laser annealing amorphous Si to polycrystallize it, similar to the TFT channel 104. The transistor 103 is formed in this manner.

[0117] The second interlayer insulating film 108 (second insulating film) is provided so as to cover the insulating layer 105 and the gate 107. The second interlayer insulating film 108 is formed by a suitable manufacturing method depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is made of SiO 2 When the thin film is formed by the above method, techniques such as ALD and CVD are used.

[0118] The flatness of the second interlayer insulating film 108 may be sufficient to form the wiring layer 110, and the flattening step may not necessarily be performed. If the flattening step is not performed on the second interlayer insulating film 108, the number of steps can be reduced. For example, when there is a portion around the light emitting element 150 where the thickness of the second interlayer insulating film 108 is thin, the depth of the via hole penetrating the first interlayer insulating film 156 and the second interlayer insulating film 108 becomes shallow, so that the via hole can have a sufficient opening diameter. Therefore, it becomes easy to ensure electrical connection by the via, and a decrease in yield due to poor electrical characteristics can be suppressed.

[0119] As shown in FIG. 11A, the via hole 162a is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connection plate 130a. The opening 158 is formed so as to reach the light-emitting surface 151S by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 on the light-emitting surface 151S. As in this example, the light-emitting surface 151S may be formed by etching the center of the n-type semiconductor layer 151 in the thickness direction of the n-type semiconductor layer 151. As in this example, the light-emitting surface 151S is preferably roughened.

[0120] The via hole 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104d. The via hole 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104s. The via holes 162a, 112d, and 112s and the opening 158 are formed by, for example, RIE or the like.

[0121] As shown in Fig. 11B, the via 161a (first via) is formed by filling the via hole 162a shown in Fig. 11A with a conductive material. The vias 111d and 111s are also formed by filling the via holes 112d and 112s shown in Fig. 11A with a conductive material, respectively. Thereafter, the wiring layer 110 is formed on the second interlayer insulating film 108, and the wirings 110a, 110d, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of the vias 161a, 111d, and 111s.

[0122] 12A and 12B are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the present embodiment. 12A and 12B show steps for forming the subpixel 20a shown in Fig. 2. In this example, the steps from forming the transistor 103 to forming the second interlayer insulating film 108 are the same as those described above. In the following, the explanation will be given assuming that the steps in Fig. 12A and 12B are performed after the step in Fig. 10B.

[0123] As shown in Fig. 12A, similarly to the case of Fig. 11A, via holes 162a, 112d, and 112s are formed. The opening 158 is formed so as to reach the n-type semiconductor layer 151a. In this example, since the n-type semiconductor layer 151a is not roughened, the etching step for roughening the surface can be omitted.

[0124] As shown in FIG. 12B, the vias 161a, 111d, and 111s are formed by filling the via holes 162a, 112d, and 112s shown in FIG. 12A with a conductive material. Then, the wiring layer 110 is formed, and the wirings 110a, 110d1, and 110s are formed. Here, one end of the wiring 110d1 is connected to the via 111d. The wiring 110d1 is provided by extending from the position connected to the via 111d to the light emitting surface 151S. The other end of the wiring 110d1 is connected to the surface including the light emitting surface 151S. In other words, the wiring 110d1 is directly connected to the n-type semiconductor layer 151.

[0125] In this manner, the modified sub-pixel 20a is formed.

[0126] For example, the circuit in Fig. 3 is a drive circuit that drives a light-emitting element 150 by a selection transistor 24, a drive transistor 26, and a capacitor 28. Such a drive circuit is formed within the subpixels 20, 20a. Part of the circuits other than the drive circuit is formed outside the subpixels 20, 20a, for example, in the peripheral portion of the display area 2 shown in Fig. 1. For example, the row selection circuit 5 shown in Fig. 3 is formed simultaneously with the drive transistors, selection transistors, etc., and is formed in the peripheral portion of the display area 2. In other words, the row selection circuit 5 can be simultaneously incorporated by the above-mentioned manufacturing process.

[0127] The signal voltage output circuit 7 is preferably incorporated into a semiconductor device manufactured by a manufacturing process capable of high integration through microfabrication. The signal voltage output circuit 7 is mounted on a separate substrate together with a CPU and other circuit elements, and is connected to the sub-pixels 20, 20a via connectors or the like provided on the periphery of the display area, for example, before or after the incorporation of a color filter, which will be described later.

[0128] In the image display device 1 of this embodiment, each light emitting element 150 can form an image in the display region 2 by emitting light upward from the light emitting surface 153S. However, if light is scattered below the light emitting surface 153S, the light emitting efficiency is substantially reduced because the substrate 102 has translucency. Therefore, for example, a light reflecting film or a light reflecting plate can be provided on the surface of the substrate 102 facing the first surface 102a, so that the light scattered toward the substrate 102 can be reflected toward the light emitting surface 153S. Such a light reflecting film or the like may be provided on the substrate 102, or may be provided inside a case, a frame, or the like to which the image display device 1 is fixed.

[0129] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In Fig. 13, the diagram above the arrow shows a configuration including a color filter 180, and the diagram below the arrow shows a structure including the light-emitting element 150 and the like formed in the above-mentioned process. In Fig. 13, the arrows indicate the process of bonding a color filter to the structure including the light-emitting element 150 and the like. In FIG. 13, in order to avoid complication, components other than those on the illustrated substrate 102 are omitted. The omitted components are the circuit 101 including the TFT channel 104 and the wiring layer 110 shown in FIG. 1, and the via 161a. Also, FIG. 13 shows a part of a color conversion member such as a color filter 180. In the description related to FIG. 13 and FIG. 14A to FIG. 14D, a structure including the light emitting element 150, the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, the second interlayer insulating film 108, and the surface resin layer 170 is called a light emitting circuit section 172. A structure including the substrate 102, the conductive layer 130, the light emitting circuit section 172, and the components whose illustration is omitted is called a structure 1192. In FIG. 13, the TFT channel 104, the gate 107, the vias 111s and 111d, and the wiring layer 110 of the circuit 101 shown in FIG. 1 are omitted.

[0130] 13, one surface of color filter 180 (wavelength conversion member) is bonded to structure 1192. The other surface of color filter 180 is bonded to glass substrate 186. One surface of color filter 180 is provided with transparent thin film adhesive layer 188, and color filter 180 is bonded to the exposed surface of surface resin layer 170 of structure 1192 via transparent thin film adhesive layer 188.

[0131] In this example, color filter 180 has color conversion sections arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, red color conversion layer 183R is provided as the first layer, and for green, green color conversion layer 183G is provided as the first layer, and filter layer 184 is provided as the second layer in each case. For blue, single-layer color conversion layer 183B may be provided, or filter layer 184 may be provided. Light shielding sections 181 are provided between each color conversion section, and it goes without saying that the frequency characteristics of filter layer 184 can be changed for each color of color conversion section.

[0132] The color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183 R, 183 G, and 183 B of each color with the position of the light emitting element 150 .

[0133] 14A to 14D are schematic cross-sectional views showing a modified example of the manufacturing method for the image display device of this embodiment. 14A to 14D show a method for forming a color filter by an inkjet method.

[0134] As shown in FIG. 14A, a structure 1192 is prepared in which components such as a light emitting element 150 are formed on a substrate 102.

[0135] 14B, light shielding portion 181 is formed on structure 1192. Light shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.

[0136] As shown in FIG. 14C, phosphors corresponding to the luminescent color are ejected from the inkjet nozzle to form the color conversion layer 183. The phosphors color the areas where the light-shielding portion 181 is not formed. For example, fluorescent paint using a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material is used as the phosphor. When a perovskite phosphor material or a quantum dot phosphor material is used, each luminescent color can be realized, and monochromaticity and color reproducibility are high, which is preferable. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0137] As already explained, for blue-emitting subpixels, if no color conversion section is formed, color conversion layer 183 is not formed. Furthermore, when forming a blue color conversion layer for a blue-emitting subpixel, if only one layer of color conversion section is required, the thickness of the coating of the blue phosphor is preferably approximately the same as the thickness of light-shielding section 181.

[0138] As shown in Fig. 14D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coatings is approximately the same as the thickness of the light-shielding portion 181.

[0139] Whether it is a film-type color filter or an inkjet-type color filter, it is desirable that the color conversion layer 183 is as thick as possible in order to improve the color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambertian, whereas the emission angle of the blue light that is not color-converted is limited by the light shielding portion 181. This causes a problem that the display color of the displayed image becomes visual angle dependent. In order to match the light distribution of the subpixel in which the color conversion layer 183 is provided to the light distribution of the blue light that is not color-converted, it is desirable that the thickness of the color conversion layer 183 is about half the opening size of the light shielding portion 181.

[0140] For example, in the case of a high-definition image display device of about 250 ppi (pitch per inch), the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, when the color conversion material is made of spherical phosphor particles, it is preferable that they are stacked in a close-packed structure to suppress light leakage from the light emitting element 150. For this reason, at least three particle layers are required. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably about 5 μm or less, and more preferably about 3 μm or less.

[0141] FIG. 15 is a schematic perspective view illustrating the image display device according to the present embodiment. As shown in Fig. 15, the image display device of this embodiment has a light-emitting circuit section 172 having a large number of sub-pixels 20 provided on a substrate 102. The conductive layer 130 shown in Fig. 13 includes a connection plate 130a. The connection plate 130a is provided for each of the sub-pixels 20 on the substrate 102. A color filter 180 is provided on the light-emitting circuit section 172. Other embodiments and modified examples described later also have a similar configuration to that shown in Fig. 15.

[0142] The effects of the image display device 1 of this embodiment will be described. In the manufacturing method of the image display device 1 of this embodiment, after the semiconductor layer 1150 is bonded to the substrate 102, the semiconductor layer 1150 is etched to form the light emitting element 150. Thereafter, the light emitting element 150 is covered with a first interlayer insulating film 156, and the circuit 101 including circuit elements such as the transistor 103 that drives the light emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, the manufacturing process is significantly shortened compared to the case where the individual light emitting elements are individually transferred to the substrate 102.

[0143] For example, in an image display device with 4K image quality, the number of subpixels exceeds 24 million, and in the case of an image display device with 8K image quality, the number of subpixels exceeds 99 million. It takes a huge amount of time to individually form such a large number of light-emitting elements and mount them on a circuit board. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, if a large number of light-emitting elements are individually mounted, the yield rate decreases due to poor connection during mounting, and further cost increases are unavoidable. However, the manufacturing method for the image display device of this embodiment has the following effects.

[0144] As described above, in the manufacturing method of the image display device 1 of this embodiment, the semiconductor layer 1150 is entirely bonded to the substrate 102, and then the light-emitting elements are formed by etching, so that the transfer process is completed in one step. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time for the transfer process can be shortened and the number of steps can be reduced compared to the conventional manufacturing method in which the number of transfers is the same as the number of light-emitting elements corresponding to the number of pixels.

[0145] Furthermore, the semiconductor layer 1150 is bonded to the substrate 102 at the wafer level without being divided into individual pieces in advance or forming electrodes at positions corresponding to the circuit elements. Therefore, alignment is not required at the bonding stage. Therefore, the bonding process can be easily performed in a short time. Since alignment is not required at the time of bonding, the light emitting element 150 can be easily miniaturized, which is suitable for a high-definition display.

[0146] In this embodiment, for example, the glass substrate formed as described above is covered with an interlayer insulating film, and on the planarized surface, a driving circuit including a TFT and a scanning circuit can be formed using an LTPS process, etc. Therefore, there is an advantage that the existing manufacturing process and plant for flat panel displays can be utilized.

[0147] In this embodiment, the light emitting element 150 formed below the transistor 103 etc. can be electrically connected to the power supply line, ground line, driving transistor etc. formed above by forming vias penetrating the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105 and the second interlayer insulating film 108. By using such a technically established multilayer wiring technique, a uniform connection structure can be easily realized and the yield can be improved. Therefore, a decrease in the yield due to poor connection of the light emitting element etc. is suppressed.

[0148] In this embodiment, a conductive layer 130 is formed on the first surface 102a of the substrate 102. The conductive layer 130 includes a connection plate 130a. The light-emitting element 150 is formed on the connection plate 130a and is electrically connected to the connection plate 130a at a bottom surface 153B. The connection plate 130a is formed of a material having high conductivity, such as a metal material. Therefore, the p-type semiconductor layer 153 of the light-emitting element 150 can be electrically connected to other circuits with low resistance.

[0149] In addition, since the lower p-type semiconductor layer 153 connects the highly conductive connection plate 130a at the bottom surface 153B, there is no need to form a connection portion in the lateral direction, and the thickness of the entire light emitting element 150 can be reduced. Therefore, the thickness of the first interlayer insulating film 156 can also be reduced, and the depth of the via 161a can be made shallower, thereby reducing the diameter. Therefore, the processing accuracy of the via hole for forming the via 161a can be substantially increased.

[0150] The surface of the connection plate 130a can be formed from a material having high light reflectivity, such as Ag. The outer periphery of the connection plate 130a is formed to include the outer periphery of the light emitting element 150 when the light emitting element 150 is projected in a plan view. Therefore, the connection plate 130a also functions as a light reflecting plate, and can reflect scattered light downward from the light emitting element 150 to the light emitting surface 151S, thereby substantially improving the light emitting efficiency of the light emitting element 150.

[0151] Second Embodiment FIG. 16 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that the p-type semiconductor layer 253 provides the light emitting surface 253S and in the configuration of the transistor 203. The same components as those in the other embodiments are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0152] As shown in FIG. 16, the subpixel 220 of the image display device of this embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, and a wiring layer 110.

[0153] The light emitting element 250 is provided on the connection plate 130a. The outer periphery of the connection plate 130a is set to include the outer periphery of the light emitting element 250 when the light emitting element 250 is projected in a plan view. Therefore, the scattered light downward from the light emitting element 250 can be reflected toward the light emitting surface 253S, and the light emitting efficiency of the light emitting element 250 is substantially improved, as in the other embodiments described above.

[0154] The light emitting element 250 includes a light emitting surface 253S. As in the other embodiments described above, the light emitting element 250 is a prismatic or cylindrical element having a bottom surface 251B on the connecting plate 130a. The light emitting surface 253S is a surface opposite to the bottom surface 251B. The bottom surface 251B is connected to the connecting plate 130a.

[0155] The light emitting element 250 includes an n-type semiconductor layer 251, a light emitting layer 252, and a p-type semiconductor layer 253. The n-type semiconductor layer 251, the light emitting layer 252, and the p-type semiconductor layer 253 are laminated in this order from the bottom surface 251B toward the light emitting surface 253S. In this embodiment, the light emitting surface 253S is provided by the p-type semiconductor layer 253.

[0156] The light emitting element 250 has a shape in the XY plane view similar to that of the light emitting element 150 shown in Fig. 1. An appropriate shape is selected depending on the layout of the circuit elements, etc.

[0157] The light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiments described above. That is, the wavelength of light emitted by the light emitting element 250 is, for example, blue light of about 467 nm±20 nm, or blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 250 is not limited to the above values ​​and can be any appropriate value.

[0158] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is a p-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the second interlayer insulating film 108, the vias 111s and 111d, and the wiring layer 110.

[0159] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with p-type impurities such as boron (B). The region 204s is ohmic-connected to the via 111s. The region 204d is ohmic-connected to the via 111d.

[0160] The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0161] In the transistor 203, when a voltage lower than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage of the gate 107 with respect to the region 204s. The TFT channel 204 and the gate 107 are formed of the same materials and by the same manufacturing method as in the other embodiments described above.

[0162] The wiring layer 110 includes wirings 110s, 110d, and 210k. The wirings 110s and 110d are the same as those in the first embodiment. A part of the wiring 210k is provided above the connection plate 130a. The other part of the wiring 210k extends to, for example, a ground line 4 shown in FIG. 17 to be described later, and is connected to the ground line 4.

[0163] The vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108. The via 111s is provided between the wiring 110s and the region 204s. The via 111s electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d and the region 204d. The via 111d electrically connects the wiring 110d and the region 204d. The vias 111s and 111d are formed using the same material and manufacturing method as in the other embodiments described above.

[0164] The via 161k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 161k is provided between the wiring 210k and the connection plate 130a, and electrically connects the wiring 210k and the connection plate 130a.

[0165] The wiring 110s is electrically connected to, for example, a power line 3 shown in Fig. 17, which will be described later. The wiring 110d is electrically connected to the p-type semiconductor layer 253 via a light-transmitting electrode 159d.

[0166] In this embodiment, the transparent electrode 159d is provided over the roughened light emitting surface 253S of the p-type semiconductor layer 253. The transparent electrode 159d is provided over the wiring 110d. The transparent electrode 159d is also provided between the light emitting surface 253S and the wiring 110d, and electrically connects the p-type semiconductor layer 253 and the wiring 110d. In the case of the modification of the first embodiment described above, the wiring 110d1 may be extended and directly connected to the p-type semiconductor layer 253, as in the example shown in FIG. 2.

[0167] FIG. 17 is a schematic block diagram illustrating an image display device according to this embodiment. 17, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, sub-pixels 220 are arranged in a lattice pattern on the XY plane.

[0168] As in the other embodiments described above, pixel 10 includes multiple sub-pixels 220 that emit different colored light. Sub-pixel 220R emits red light. Sub-pixel 220G emits green light. Sub-pixel 220B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 220R, 220G, and 220B emitting light at a desired brightness.

[0169] One pixel 10 includes three sub-pixels 220R, 220G, and 220B, which are arranged linearly on the X-axis as in this example. Each pixel 10 may have sub-pixels of the same color arranged in the same column, or may have sub-pixels of different colors arranged in different columns as in this example.

[0170] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 15, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0171] In this embodiment, the light emitting element 222 is provided on the side of the ground line 4, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the side of the power supply line 3. In other words, the driving transistor 226 is connected to the lower potential side than the light emitting element 222. The driving transistor 226 is a p-channel transistor.

[0172] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power supply line 3.

[0173] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity from that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is a p-channel transistor.

[0174] In this embodiment, the polarity of the driving transistor 226 is p-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the sub-pixel 220 of the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light with a luminance corresponding to the current that has passed.

[0175] A method for manufacturing the image display device of this embodiment will be described. 18A to 21B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In this example, the semiconductor growth substrate 1194a described in relation to Fig. 7A in the above-mentioned other embodiment is used. In the following description, it is assumed that the steps in Fig. 18A and after are applied to the steps after the preparation of the semiconductor growth substrate 1194a shown in Fig. 7A.

[0176] As shown in Figure 18A, in the manufacturing method of the image display device of this embodiment, multiple semiconductor growth substrates 1194a shown in Figure 7A are prepared, and support substrates 1190 are each bonded to the exposed surface of the p-type semiconductor layer 1153 to form substrates 1195a.

[0177] As shown in FIG. 18B, the crystal growth substrate 1001 shown in FIG. 18A is removed from the substrate 1195a by wet etching, laser lift-off, or the like, to form a substrate 1195b.

[0178] 18C, a substrate 102 having a metal layer 1130 formed on a first surface 102a is prepared. A plurality of substrates 1195b are arranged, for example, in a lattice pattern, and the exposed surface of the n-type semiconductor layer 1151 is disposed so as to face the exposed surface of the metal layer 1130. The exposed surface of the n-type semiconductor layer 1151 is bonded to the substrate 102 via the metal layer 1130.

[0179] The step of bonding the semiconductor layer 1150 and the substrate 102 via the metal layer 1130 can be applied to the form and modified example described in the manufacturing method in the first embodiment. For example, a semiconductor growth substrate in which the semiconductor layer 1150 is grown on the crystal growth substrate 1001 via a buffer layer may be used. In this case, it is necessary to remove the buffer layer before bonding to the metal layer 1130. Also, a p-type semiconductor layer may be grown on the crystal growth substrate 1001, and the exposed surface of the n-type semiconductor layer 1151 may be bonded to the metal layer without transferring it to a support substrate. Also, a metal layer may be formed on the exposed surface of the n-type semiconductor layer 1151 of the substrate 1195b, and the metal layers may be bonded to each other, as in the case of the other embodiments described above.

[0180] As shown in Fig. 19A, the support substrate 1190 shown in Fig. 18B is removed by wet etching, etc. Position X1 is a position where the ends of the bonded semiconductor layers 1150 are disposed.

[0181] 19B, the semiconductor layer 1150 shown in FIG 19A is shaped into a desired shape by etching to form the light emitting element 250. The light emitting element 250 is formed by, for example, a dry etching process, and preferably by RIE.

[0182] 19A is etched to form the conductive layer 130. By etching the metal layer 1130, a connection plate 130a forming the conductive layer 130 is formed under the light emitting element 250.

[0183] As shown in FIG. 20A, a first interlayer insulating film 156 is formed to cover the first surface 102a, the conductive layer 130, the connection plate 130a, and the light emitting element 250. As shown in FIG.

[0184] 20B, the TFT lower layer film 106 is formed over the first interlayer insulating film 156 by CVD or the like. The TFT channel 204 is formed on the planarized TFT lower layer film 106. An insulating layer 105 is formed to cover the TFT lower layer film 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0185] As shown in FIG. 21A, the via hole 162k is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connection plate 130a. The opening 158 is formed so as to reach the light-emitting surface 253S by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 on the light-emitting surface 253S. The via hole 112d is formed so as to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 204d. The via hole 112s is formed so as to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 204s. The via holes 162k, 112d, 112s, and the opening 158 are formed, for example, by RIE or the like.

[0186] As shown in Fig. 21B, the via 161k is formed by filling the via hole 162k shown in Fig. 21A with a conductive material. The vias 111d and 111s are also formed by filling the via holes 112d and 112s shown in Fig. 21A with a conductive material, respectively. Thereafter, the wiring layer 110 is formed, and the wirings 210k, 110d, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of the vias 161k, 111d, and 111s.

[0187] A light-transmitting conductive film is formed to cover the second interlayer insulating film 108, the light-emitting surface 253S, and the wiring layer 110. The formed conductive film is subjected to photolithography to form light-transmitting electrodes 159d and 159s.

[0188] A translucent electrode 159d is formed over the light-emitting surface 253S and the wiring 110d. The translucent electrode 159d is also formed between the light-emitting surface 253S and the wiring 110d, and electrically connects the light-emitting surface 253S and the wiring 110d. The translucent electrode 159s is formed over the wiring 110s. The translucent electrode 159k is formed over the wiring 210k. The translucent electrodes 159d, 159s, and 159k are formed at the same time.

[0189] Thereafter, a color filter 180 (wavelength conversion member) and the like are provided to form the sub-pixels 220 of the image display device 201 of this embodiment.

[0190] The effects of the image display device of this embodiment will be described. In the image display device of this embodiment, as in the other embodiments described above, it is possible to shorten the time for the transfer process for forming the light-emitting element 250 and reduce the number of processes. In addition, by making the polarity of the TFT p-channel, it is possible to make the light-emitting surface 253S a p-type semiconductor layer 253.

[0191] (Third embodiment) FIG. 22 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that a conductive auxiliary plate 135a is provided between the connection plate 130a and the light emitting element 150. The same components as those in the first embodiment are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0192] 22, the subpixel 320 of the image display device of this embodiment includes a conductive auxiliary layer 135. The conductive auxiliary layer 135 is a layer provided on the conductive layer 130. The conductive auxiliary layer 135 includes a conductive auxiliary plate 135a, and the conductive auxiliary plate 135a is provided for each light-emitting element 150. The conductive auxiliary plate 135a is provided between the connection plate 130a and the p-type semiconductor layer 153. The p-type semiconductor layer 153 is ohmically connected to the conductive auxiliary plate 135a at the bottom surface 153B, and the connection plate 130a and the p-type semiconductor layer 153 are electrically connected.

[0193] The conductive auxiliary layer 135 and the conductive auxiliary plate 135a are made of a material having a hole injection property. The material having a hole injection property is, for example, ITO. In this embodiment, the material having a hole injection property is ohmic-connected to the p-type semiconductor layer 153, so that the driving voltage of the light-emitting element 150 can be reduced.

[0194] In this example, the conductive auxiliary plate 135a and the connection plate 130a have the same rectangular shape when viewed in the XY plane. Since the conductive auxiliary plate 135a is preferably connected over a wide area across the bottom surface 153B, it is sufficient that the outer periphery of the conductive auxiliary plate 135a coincides with the outer periphery of the bottom surface 153B or includes the outer periphery of the bottom surface 153B.

[0195] The via 161a is provided between the conductive auxiliary plate 135a and the wiring 110a, and electrically connects the conductive auxiliary plate 135a and the wiring 110a. The p-type semiconductor layer 153 is electrically connected to the wiring 110a (first wiring) through the conductive auxiliary plate 135a, the connection plate 130a, and the via 161a. Since the conductive auxiliary plate 135a is intended to be electrically connected to the p-type semiconductor layer 153, one end of the via 161a may, for example, penetrate the conductive auxiliary plate 135a and be connected to the connection plate 130a.

[0196] The light emitting surface 151S is electrically connected to the wiring 110d (second wiring) via the light-transmitting electrode 159d. Other detailed configurations including the transistor 103 are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0197] A method for manufacturing the image display device of this embodiment will be described. 23A to 25B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in Fig. 23A, a semiconductor growth substrate 1194a is prepared. The semiconductor growth substrate 1194a is the same as that described in relation to Fig. 7A. That is, in the semiconductor growth substrate 1194a, a semiconductor layer 1150 is formed on one surface of a crystal growth substrate 1001. In the semiconductor layer 1150, an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153 are laminated in this order from the crystal growth substrate 1001 side.

[0198] A conductive auxiliary film 1235 is formed over the exposed surface of the p-type semiconductor layer 1153 of the semiconductor growth substrate 1194a. A metal layer (second metal layer) 1230 is formed over the exposed surface of the conductive auxiliary film 1235. The conductive auxiliary film 1235 is formed of a material having hole injection properties, such as ITO. The metal layer 1230 is formed of Al, an alloy of Al, a laminated film of Al and Ti, or the like.

[0199] The semiconductor growth substrate 1194a on which the conductive auxiliary film 1235 and the metal layer 1230 are formed is bonded to the first surface 102a of the substrate 102 via the metal layer 1230. Thereafter, the crystal growth substrate 1001 is removed by wet etching, laser lift-off, or the like.

[0200] After preparing substrate 102, a metal layer may be formed over first surface 102a, and the exposed surface of the formed metal layer may be placed opposite an exposed surface of metal layer 1230 formed on semiconductor growth substrate 1194a and bonded to each other.

[0201] In this example, a case where a single semiconductor growth substrate 1194a is bonded to the substrate 102 will be described, but similarly to the other embodiments described above, a plurality of semiconductor growth substrates may be bonded to one substrate 102, for example, arranged in a lattice pattern. In addition, the configuration of the semiconductor growth substrate and the presence or absence of a support substrate can be determined by applying the methods described in the other embodiments described above.

[0202] As shown in Fig. 23B, the semiconductor layer 1150 shown in Fig. 23A is etched by RIE or the like and shaped into a desired shape to form the light emitting element 150. The metal layer 1230 and the conductive auxiliary film 1235 shown in Fig. 23A are etched and shaped to include the outer periphery of the light emitting element 150 to form the conductive layer 130 including the connection plate 130a (second portion) and the conductive auxiliary layer 135 including the conductive auxiliary plate 135a.

[0203] As shown in FIG. 24A, a first interlayer insulating film 156 that covers the first surface 102a, the connection plate 130a, the conductive auxiliary plate 135a, and the light emitting element 150 is formed.

[0204] 24B, in the same manner as in the other embodiments described above, a TFT underlayer film 106 is formed, a TFT channel 104 is formed, an insulating layer 105 is formed, and a gate 107 is formed. A second interlayer insulating film 108 covering the insulating layer 105 and the gate 107 is formed.

[0205] 25A, the via hole 162a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the conductive auxiliary plate 135a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the other embodiments described above.

[0206] As shown in Fig. 25B, the via holes 162a, 112d, and 112s shown in Fig. 25A are filled with a conductive material to form vias 161a (second vias), 111d, and 111s. The wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmitting conductive film is formed on the wiring layer 110, and light-transmitting electrodes 159a, 159d, and 159s are formed.

[0207] The effects of the image display device of this embodiment will be described. According to the image display device of this embodiment, the conductive auxiliary layer 135 and the conductive auxiliary plate 135a are formed of a material having hole injection properties, such as ITO. Since the p-type semiconductor layer 153 is connected to the conductive auxiliary plate 135a, the potential barrier is lowered, and the operating voltage of the light-emitting element 150 can be reduced. The reduction in the operating voltage of the light-emitting element 150 reduces the power consumption of the light-emitting element 150. As the operating voltage of the light-emitting element 150 is reduced, it becomes possible to reduce the driving voltage of the subpixel 20 itself, and the overall power consumption of the image display device can be further reduced.

[0208] (Fourth embodiment) FIG. 26 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the third embodiment in that the via 461a is provided between the conductive auxiliary plate 135a and the wiring 110d. The light emitting element 150 also differs from the third embodiment in that it is driven by a p-type transistor 203. The same components as those in the other embodiments described above are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0209] 26, a subpixel 420 of the image display device of this embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 150, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 461a, and a wiring layer 110. The transistor 203 is a p-channel TFT. The light-emitting element 150 provides a light-emitting surface 151S by an n-type semiconductor layer 151. A bottom surface 153B of the light-emitting element 150 is provided on a conductive auxiliary plate 135a, and the p-type semiconductor layer 153 is electrically connected to the conductive auxiliary plate 135a.

[0210] The light emitting element 150 is provided on a conductive auxiliary plate 135a. The conductive auxiliary plate 135a is provided in the same manner as in the third embodiment. The connection plate 130a is provided directly below the light emitting element 150 and also functions as a light reflecting plate to improve the substantial light emitting efficiency of the light emitting element 150.

[0211] The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 110k, 110d, and 110s. The wiring 110k is connected to, for example, the ground line 4 of the circuit shown in FIG.

[0212] A part of the wiring 110d is provided above the transistor 203, and is connected to the region 204d through a via 111d. Another part of the wiring 110d (third wiring) is provided near the light emitting element 150, and is connected to the conductive auxiliary plate 135a through a via 461a. That is, the via 461a is provided between the conductive auxiliary plate 135a and the wiring 110d, and electrically connects the conductive auxiliary plate 135a and the wiring 110d. The via 461a may penetrate the conductive auxiliary plate 135a and be connected to the conductive auxiliary plate 135a, as in the third embodiment.

[0213] The wiring 110s is connected to, for example, the power supply line 3 of the circuit shown in FIG.

[0214] The translucent electrode 159k is provided over the wiring 110k (fourth wiring). The translucent electrode 159k is provided over the light-emitting surface 151S. The translucent electrode 159k is provided between the wiring 110k and the light-emitting surface 151S. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 via the translucent electrode 159k and the wiring 110k.

[0215] The transparent electrode 159d is provided over the wiring 110d. Therefore, the p-type semiconductor layer 153 is electrically connected to the region 204d, which is the drain electrode of the transistor 203, via the conductive auxiliary plate 135a, the connection plate 130a, the via 461a, the wiring 110d, the transparent electrode 159d, and the via 111d.

[0216] The transparent electrode 159s is provided over the wiring 110s. The wiring 110s and the transparent electrode 159s are connected to the power line 3 shown in Fig. 13, for example. Therefore, the region 204s of the transistor 203 is electrically connected to the power line 3 through the via 111s, the wiring 110s, and the transparent electrode 159s.

[0217] The vias 461a, 111d, and 111s and the wirings 110k, 110d1, and 110s are formed from the same materials and by the same manufacturing method as in the above-mentioned other embodiments and their modified examples.

[0218] As in the other embodiments described above, a color filter 180 and the like are further provided.

[0219] A method for manufacturing the image display device of this embodiment will be described. 27A and 27B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. The manufacturing method of this embodiment is the same as the manufacturing method of the third embodiment up to a midpoint. In the following description, the steps of FIG. 27A and FIG. 27B are performed after the step of forming the second interlayer insulating film 108 in FIG. 24B. However, the difference is that, while an n-channel transistor 103 is formed on the TFT lower layer film 106 in FIG. 24B, a p-channel transistor 203 is formed on the TFT lower layer film 106 in this embodiment. The method of forming the p-channel transistor 203 is the same as in the second embodiment already described, and a detailed description thereof will be omitted.

[0220] 27A, the via hole 462a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the conductive auxiliary plate 135a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the other embodiments described above.

[0221] As shown in Fig. 27B, the via holes 462a, 112d, and 112s shown in Fig. 27A are filled with a conductive material to form vias 461a, 111d, and 111s. The wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmitting conductive film is formed on the wiring layer 110, and light-transmitting electrodes 159k, 159d, and 159s are formed.

[0222] The effects of the image display device of this embodiment will be described. According to the image display device of this embodiment, in addition to the effects of the third embodiment described above, the following effects are obtained. That is, in this embodiment, it is possible to configure a circuit in which the n-type semiconductor layer 151 is the light-emitting surface 151S and the p-channel transistor 203 drives the light-emitting element 150. This allows for a wider variety of circuit layouts and other variations, enabling flexible circuit design. Furthermore, by using the n-type semiconductor layer 151 as the light-emitting surface 151S, the effect of easily roughening the light-emitting surface is obtained, as in the first embodiment. Furthermore, by roughening the light-emitting surface, the light-emitting efficiency is improved, and an effect of suppressing an increase in loss due to contact resistance is also obtained.

[0223] Fifth embodiment The image display device of this embodiment includes a flexible substrate 502 instead of a glass substrate. Light emitting elements and circuit elements such as transistors are formed on a first surface 502a of the substrate 502. Other points are similar to those of the third embodiment described above, and the same components are denoted by the same reference numerals and detailed descriptions thereof are omitted as appropriate.

[0224] FIG. 28 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. As shown in Fig. 28, the image display device of this embodiment includes a subpixel 520. The subpixel 520 includes a substrate 502. The substrate 502 includes a first surface 502a. When the substrate 502 is made of an organic material such as a resin, a layer 507 containing a silicon compound is formed on the first surface 502a. The layer 507 containing a silicon compound is made of SiO 2 and SiN x Since the conductive layer 130 is made of a metal material, the layer 507 containing a silicon compound is provided to improve the adhesion between the substrate 502 and the conductive layer 130.

[0225] The conductive layer 130 and the connection plate 130a are provided on the first surface 502a via a layer 507 containing a silicon compound. A conductive auxiliary plate 135a is preferably provided on the connection plate 130a, and the light emitting element 150 is provided on the conductive auxiliary plate 135a. In this example, the structure and components above the conductive layer 130 and the connection plate 130a are the same as those in the third embodiment described above, and detailed description thereof will be omitted.

[0226] The substrate 502 is flexible. The substrate 502 is formed of, for example, polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, and the like are preferably formed of a material having a certain degree of flexibility according to the flexibility of the substrate 502. The wiring layer 110, which has the longest wiring length, is at the highest risk of being broken when bent. Therefore, it is desirable to adjust the thickness, quality, and material of each film so that the neutral plane including a plurality of protective films, etc., added to the front and back surfaces as necessary, is located at the position of the wiring layer 110.

[0227] In this example, the structure and components above the layer 507 containing a silicon compound are the same as those in the third embodiment, but may be the other embodiments or modifications described above. Also, they may be applied to the configuration of the sixth embodiment described later.

[0228] A method for manufacturing the image display device of this embodiment will be described. 29A and 29B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in FIG. 29A, in this embodiment, a substrate 1002 different from those in the other embodiments described above is prepared. The substrate 1002 (fourth substrate) includes two layers of substrates 102 and 502. The substrate 102 is, for example, a glass substrate. The substrate 502 is provided on the first surface 102a of the substrate 102. For example, the substrate 502 is formed by applying polyimide onto the first surface 102a and baking it. Before forming the substrate 502, SiN xIn this case, the substrate 502 is formed by applying a polyimide material onto the inorganic film and baking it.

[0229] A layer 507 containing a silicon compound is formed over a first surface 502a of the substrate 502. The first surface 502a of the substrate 502 is the surface opposite to the surface on which the substrate 102 is provided.

[0230] By applying the steps described above with reference to, for example, FIGS. 23A to 25B, 13, and 14A to 14D to such a substrate 1002, the superstructure of the sub-pixels 520 is formed.

[0231] 29B, the substrate 102 is removed from the structure on which the upper structure including the color filter and the like (not shown) is formed. The substrate 102 is removed by, for example, laser lift-off or the like.

[0232] The removal of the substrate 102 can be performed at any appropriate time, not limited to the above-mentioned time. After the removal of the substrate 102, there is a step of exposure to high temperature, and if the substrate 502 is made of an organic resin, the substrate 502 may shrink due to heating. Therefore, it is preferable to remove the substrate 102 in a step subsequent to the step of exposure to such high temperature. For example, it is preferable to remove the substrate 102 after the step of forming the wiring layer 110 is completed. By removing the substrate 102 at an appropriate time, defects such as cracks and chips during the manufacturing process may be reduced.

[0233] The effects of the image display device of this embodiment will be described. The image display device of this embodiment has the following effect in addition to the effects of the other embodiments described above: Since the substrate 502 is flexible, it can be bent as an image display device, and can be attached to a curved surface or used in a wearable terminal or the like without any sense of incongruity.

[0234] Sixth embodiment FIG. 30 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. In this embodiment, a display device with higher light emission efficiency is realized by forming a plurality of light emitting surfaces 653S1, 653S2 on a single semiconductor layer 650 including a light emitting layer. In the following description, the same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0235] 30, the image display device of this embodiment includes a subpixel group 620. The subpixel group 620 includes a substrate 102, a semiconductor layer 650, a first interlayer insulating film 156, transistors 203-1 and 203-2, a second interlayer insulating film 108, and a wiring layer 110. The semiconductor layer 650 is provided on a connection plate 630a provided on a first surface 102a of the substrate 102. In each cross-sectional view of this embodiment, in order to avoid complication of display, the reference numerals of the conductive layer 130 and the reference numerals of the connection plate 630a are written side by side.

[0236] In this embodiment, the conductive layer 130 and the connection plate 630a are connected to, for example, the ground line 4 of the circuit of FIG. 17. By turning on the p-channel transistor 203-1, holes are injected into the light-emitting surface 653S1 through the transparent electrode 659d1. Also, by turning on the p-channel transistor 203-2, holes are injected into the light-emitting surface 653S2 through the transparent electrode 659d2. The semiconductor layer 650 causes the light-emitting layer 652 to emit light by the combination of holes and electrons in the vicinity of each of the light-emitting surfaces 653S1 and 653S2 into which the holes are injected. The driving circuit for driving the light-emitting layer 652 may have the circuit configuration shown in FIG. 17, for example. As in the case of the other embodiments described above, the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer may be swapped up and down, and the semiconductor layer may be driven by an n-channel transistor. In that case, the driving circuit may have the circuit configuration shown in FIG. 3.

[0237] The configuration of the sub-pixel group 620 will now be described in detail. The conductive layer 130 is provided on the first surface 102a. The conductive layer 130 includes a connection plate 630a. The semiconductor layer 650 is provided on the first surface 102a via the connection plate 630a. The semiconductor layer 650 has a bottom surface 651B, and the connection plate 630a is connected to the bottom surface 651B. The outer periphery of the connection plate 630a is set to include the outer periphery of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a in the XY plane view. Therefore, the connection plate 630a reflects the scattered light downward from the semiconductor layer 650 to the upper light emitting surfaces 653S1 and 653S2. Therefore, the substantial light emitting efficiency of the semiconductor layer 650 is improved.

[0238] The semiconductor layer 650 includes a plurality of light emitting surfaces 653S1 and 653S2. The semiconductor layer 650 is a prismatic or cylindrical laminate having a bottom surface 651B connected onto the connection plate 630a. The light emitting surfaces 653S1 and 653S2 are surfaces facing the bottom surface 651B. The light emitting surfaces 653S1 and 653S2 are preferably surfaces in a plane substantially parallel to the bottom surface 651B. The plane including the light emitting surface 653S1 and the plane including the light emitting surface 653S2 may be the same plane or different planes. The light emitting surfaces 653S1 and 653S2 are provided spaced apart in the X-axis direction.

[0239] The semiconductor layer 650 includes an n-type semiconductor layer 651, a light emitting layer 652, and a p-type semiconductor layer 653. The n-type semiconductor layer 651, the light emitting layer 652, and the p-type semiconductor layer 653 are stacked in this order from the bottom surface 651B toward the light emitting surfaces 653S1 and 653S2.

[0240] The bottom surface 651B is an n-type semiconductor, and the n-type semiconductor layer 651 is electrically connected to an external circuit, such as the ground line 4 of the circuit in FIG. 17, connected via the bottom surface 651B and the connection plate 130a.

[0241] The p-type semiconductor layer 653 has two light emitting surfaces 653S1 and 653S2 on the upper surface. That is, one subpixel group 620 substantially includes two subpixels. In this embodiment, as in the other embodiments described above, the subpixel groups 620 each substantially including two subpixels are arranged in a lattice pattern to form a display area.

[0242] The first interlayer insulating film 156 (first insulating film) covers the first surface 102a, the conductive layer 130, the connection plate 630a, the side surface of the n-type semiconductor layer 651, the side surface of the light emitting layer 652, and the side surface of the p-type semiconductor layer 653. The first interlayer insulating film 156 covers a part of the upper surface of the p-type semiconductor layer 653. Of the p-type semiconductor layer 653, the light emitting surfaces 653S1 and 653S2 are not covered with the first interlayer insulating film 156. The first interlayer insulating film 156 is preferably a white resin, as in the other embodiments described above.

[0243] The TFT lower film 106 is formed over the first interlayer insulating film 156. The TFT lower film 106 is not provided over the light emitting surfaces 653S1 and 653S2. The TFT lower film 106 is flattened, and the TFT channels 204-1, 204-2, etc. are formed on the TFT lower film 106.

[0244] The insulating layer 105 covers the TFT lower film 106 and the TFT channels 204-1 and 204-2. The gate 107-1 is provided on the TFT channel 204-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 204-2 via the insulating layer 105. The transistor 203-1 includes the TFT channel 204-1 and the gate 107-1. The transistor 203-2 includes the TFT channel 204-2 and the gate 107-2.

[0245] A second interlayer insulating film 108 (second insulating film) covers the insulating layer 105 and the gates 107-1 and 107-2.

[0246] The TFT channels 204-1 and 204-2 include p-type doped regions, and the transistors 203-1 and 203-2 are p-channel TFTs. The transistor 203-1 is located closer to the light emitting surface 653S1 than to the light emitting surface 653S2. The transistor 203-2 is located closer to the light emitting surface 653S2 than to the light emitting surface 653S1.

[0247] A transparent electrode 659d1 is provided over the light-emitting surface 653S1. An opening 658-1 is provided above the light-emitting surface 653S1 and the transparent electrode 659d1. A transparent electrode 659d2 is provided over the light-emitting surface 653S2. An opening 658-2 is provided above the light-emitting surface 653S2 and the transparent electrode 659d2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 are not provided in the openings 658-1 and 658-2. The light-emitting surfaces 653S1 and 653S2 are exposed from the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The openings 658-1 and 658-2 are filled with the surface resin layer 170.

[0248] The light emitting surfaces 653S1 and 653S2 are square, rectangular, other polygonal, circular, etc., in the XY plane view. The shape of the top of the openings 658-1 and 658-2 can also be square, rectangular, other polygonal, circular, etc. In order to reduce the loss of light caused by reflection on the wall surface of the openings 658-1 and 658-2, it is preferable that the openings 658-1 and 658-2 are formed in a tapered shape so that the area becomes wider toward the top, as in this example. In the XY plane view, the shape of the light emitting surfaces 653S1 and 653S2 and the shape of the top of the openings 658-1 and 658-2 may or may not be similar.

[0249] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 610s1, 610d1, 610d2, and 610s2. The wirings 610s1 and 610s2 are connected to the power supply line 3 of the circuit shown in FIG.

[0250] The vias 111d1, 111s1, 111d2, and 111s2 are provided through the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106. The via 111d1 is provided between one region of the transistor 203-1 that is doped with p-type and the wiring 610d1. The via 111s1 is provided between the other region of the transistor 203-1 that is doped with p-type and the wiring 610s1. The via 111d2 is provided between one region of the transistor 203-2 that is doped with p-type and the wiring 610d2. The via 111s2 is provided between the other region of the transistor 203-2 that is doped with p-type and the wiring 610s2.

[0251] The wiring 610d1 is connected to a p-type region corresponding to the drain electrode of the transistor 203-1 through a via 111d1. The wiring 610s1 is connected to a p-type region corresponding to the source electrode of the transistor 203-1 through a via 111s1. The wiring 610d2 is connected to a region corresponding to the drain electrode of the transistor 203-2 through a via 111d2. The wiring 610s2 is connected to a region corresponding to the source electrode of the transistor 203-2 through a via 111s2.

[0252] The transparent electrode 659d1 is provided over the wiring 610d1 together with the light-emitting surface 653S1. The transparent electrode 659d1 is also provided between the light-emitting surface 653S1 and the wiring 610d1, and electrically connects the light-emitting surface 653S1 and the wiring 610d1. The transparent electrode 659s1 is provided over the wiring 610s1. Therefore, the p-type semiconductor layer 653 is electrically connected to the region corresponding to the drain electrode of the channel region 204-1 through the light-emitting surface 653S1, the transparent electrode 659d1, the wiring 610d1, and the via 111d1. The region corresponding to the source electrode of the channel region 204-1 is electrically connected to the power line 3 through the via 111s1, the wiring 610s1, and the transparent electrode 659s1.

[0253] The transparent electrode 659d2 is provided over the wiring 610d2 together with the light-emitting surface 653S2. The transparent electrode 659d2 is also provided between the light-emitting surface 653S2 and the wiring 610d2, and electrically connects the light-emitting surface 653S2 and the wiring 610d2. The transparent electrode 659s2 is provided over the wiring 610s2. Therefore, the p-type semiconductor layer 653 is electrically connected to the region of the channel region 204-2 corresponding to the drain electrode through the light-emitting surface 653S2, the transparent electrode 659d2, the wiring 610d2, and the via 111d2. The region of the channel region 204-2 facing the source electrode is electrically connected to the power line 3 through the via 111s2, the wiring 610s2, and the transparent electrode 659s2.

[0254] The transistors 203-1 and 203-2 are, for example, driving transistors of adjacent subpixels, and are driven sequentially. Holes supplied from one of the two transistors 203-1 and 203-2 are injected into the light-emitting layer 652, and electrons supplied from the connection plate 630a are injected into the light-emitting layer 652, causing the light-emitting layer 652 to emit light.

[0255] In this embodiment, the resistance of the n-type semiconductor layer 651 and the p-type semiconductor layer 653 suppresses the drift current flowing in a direction parallel to the XY plane. Therefore, holes injected from the light-emitting surfaces 653S1 and 653S2 and electrons injected from the connection plate 630a both proceed along the stacking direction of the semiconductor layer 650. Since the outside of the light-emitting surfaces 653S1 and 653S2 rarely become a light emission source, the transistors 203-1 and 203-2 can selectively emit light from the multiple light-emitting surfaces 653S1 and 653S2 provided on one semiconductor layer 650.

[0256] In this way, the light emission source in the semiconductor layer 650 is mostly determined by the arrangement of the light emitting surfaces 653S1, 653S2. Therefore, the connection plate 630a may be provided for each of the light emitting surfaces 653S1, 653S2 according to the positions and shapes of the light emitting surfaces 653S1, 653S2.

[0257] A method for manufacturing the image display device of this embodiment will be described. 31A to 33B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in FIG. 31A, a semiconductor growth substrate (second substrate) 1294a and a substrate 102 (third substrate) are prepared. The semiconductor growth substrate 1294a includes a crystal growth substrate 1001 and a semiconductor layer. The semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151, which are stacked in this order from the crystal growth substrate 1001 side. A metal layer 1230 is formed on the exposed surface of the n-type semiconductor layer 1151. The substrate 102 is the same as that in the other embodiments described above, and detailed description thereof will be omitted.

[0258] The semiconductor growth substrate 1294a on which the metal layer 1230 is formed is disposed so that the exposed surface of the metal layer 1230 faces the first surface 102a of the substrate 102. The semiconductor layer 1150 is bonded to the first surface 102a with the metal layer 1230 interposed therebetween.

[0259] The above is an example in which the metal layer 1230 is formed on the semiconductor layer 1150 side, but the metal layer may be formed on at least one of the substrate 102 side or the semiconductor layer 1150 side.

[0260] As described below, the metal layer functions as a light reflecting plate and is also used for electrical connection of layers below the semiconductor layer 650. Therefore, it may be preferable to thicken the metal layer in order to reduce the resistance. For example, a metal layer may be formed on the first surface 102a as well, and the metal layers may be bonded together to be used as a wiring layer with lower resistance.

[0261] As shown in FIG. 31B, the crystal growth substrate 1001 shown in FIG. 31A is removed. For example, wet etching or laser lift-off is used to remove the crystal growth substrate 1001. The semiconductor layer 1150 shown in FIG. 31A is processed into a desired shape by etching. Thereafter, the metal layer 1230 shown in FIG. 31A is shaped into a connection plate 630a by etching. The connection plate 630a constitutes the conductive layer 130 shown in FIG. 30 and is connected to, for example, the ground line 4 of the circuit in FIG. 17.

[0262] The outer periphery of the connection plate 630a is set so as to include the outer periphery of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a in the XY plane view. It is preferable that the outer periphery of the connection plate 630a is set so as not to include the outer periphery of the transistors 203-1 and 203-2 when the transistors 203-1 and 203-2 are projected onto the connection plate 630a in the XY plane view. The outer periphery of the transistors 203-1 and 203-2 in the XY plane view is the outer periphery of the TFT channels 204-1 and 204-2 in the XY plane view.

[0263] As shown in FIG. 32A, a first interlayer insulating film 156 is formed to cover the first surface 102a, the connecting plate 630a, and the semiconductor layer 650. As shown in FIG.

[0264] As shown in FIG. 32B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the TFT channels 204-1 and 204-2 are formed on the TFT lower layer film 106. The insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channels 204-1 and 204-2. The gate 107-1 is formed on the TFT channel 204-1 through the insulating layer 105. The gate 107-2 is formed on the TFT channel 204-2 through the insulating layer 105. The second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The methods of forming and materials for the TFT channels 204-1 and 204-2, the insulating layer 105, and the gates 107-1 and 107-2 can be the same as those in the other embodiments described above.

[0265] As shown in FIG. 33A, via holes 112d1 and 112s1 are formed through the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106, and reach the TFT channel 204-1. Via holes 112d2 and 112s2 are formed through the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106, and reach the TFT channel 204-2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 are removed, and an opening 658-1 is formed that reaches the light-emitting surface 653S1. The second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 are removed, and an opening 658-2 is formed that reaches the light-emitting surface 653S2.

[0266] 33B, the via holes 112d1, 112s1, 112d2, and 112s2 are filled with a conductive material to form the vias 111d1, 111s1, 111d2, and 111s2. The wiring layer 110 is formed, and the wirings 610d1, 610s1, 610d2, and 610s2 are formed.

[0267] The light-emitting surfaces 653S1 and 653S2 are each roughened. Then, a translucent conductive film is provided to cover the wiring layer 110, and the translucent electrodes 659d1, 659s1, 659d2, and 659s2 are formed. The translucent electrode 659d1 is formed to cover the light-emitting surface 653S1 and electrically connects the light-emitting surface 653S1 and the wiring 610d1. The translucent electrode 659d2 is formed to cover the light-emitting surface 653S2 and electrically connects the light-emitting surface 653S2 and the wiring 610d2.

[0268] Afterwards, superstructures such as color filters are formed.

[0269] In this manner, a sub-pixel group 620 is formed, which includes a semiconductor layer 650 having two light emitting surfaces 653S1 and 653S2.

[0270] In this embodiment, two light-emitting surfaces 653S1 and 653S2 are provided on one semiconductor layer 650, but the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces can be provided on one semiconductor layer 650. As an example, one or two columns of subpixels may be realized with a single semiconductor layer 650. As a result, as will be described later, it is possible to reduce the recombination current that does not contribute to light emission per light-emitting surface and to increase the effect of realizing finer light-emitting elements.

[0271] (Modification) FIG. 34 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the present embodiment. This modification is different from the sixth embodiment in that two p-type semiconductor layers 6653a1, 6653a2 are provided on the light emitting layer 652. In other respects, this modification is the same as the sixth embodiment, and the same components are denoted by the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0272] As shown in Fig. 34, the image display device of this modified example includes a subpixel group 620a. The subpixel group 620a includes a semiconductor layer 650a. The semiconductor layer 650a includes an n-type semiconductor layer 651, a light emitting layer 652, and p-type semiconductor layers 6653a1 and 6653a2. The n-type semiconductor layer 651 and the light emitting layer 652 are stacked in this order from a bottom surface 651B. The p-type semiconductor layers 6653a1 and 6653a2 are both stacked on the light emitting layer 652.

[0273] The p-type semiconductor layers 6653a1 and 6653a2 are formed in islands on the light emitting layer 652 and are spaced apart from each other along the X-axis direction. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 6653a1 and 6653a2, and the p-type semiconductor layers 6653a1 and 6653a2 are separated from each other by the first interlayer insulating film 156.

[0274] The p-type semiconductor layers 6653a1 and 6653a2 have approximately the same shape in the XY plan view, and the shape is approximately square or rectangular, but may be another polygonal shape, a circle, or the like.

[0275] The p-type semiconductor layer 6653a1 has a light emitting surface 6653S1. The p-type semiconductor layer 6653a2 has a light emitting surface 6653S2. The light emitting surface 6653S1 is a surface of the p-type semiconductor layer 6653a1 exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 658-1. The light emitting surface 6653S2 is a surface of the p-type semiconductor layer 6653a2 exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 658-2.

[0276] The shapes of the light emitting surfaces 6653S1 and 6653S2 in the XY plane view are almost the same as the shapes of the light emitting surfaces in the sixth embodiment, and are almost square or the like. The shapes of the light emitting surfaces 6653S1 and 6653S2 are not limited to a square as in this embodiment, but may be a circle, an ellipse, or a polygon such as a hexagon. The shapes of the light emitting surfaces 6653S1 and 6653S2 may be similar to or different from the shapes of the openings 658-1 and 658-2.

[0277] The transparent electrode 659d1 is provided over the light-emitting surface 6653S1 and over the wiring 610d1. The transparent electrode 659d1 is provided between the light-emitting surface 6653S1 and the wiring 610d1, and electrically connects the light-emitting surface 6653S1 and the wiring 610d1. The transparent electrode 659d2 is provided over the light-emitting surface 6653S2 and over the wiring 610d2. The transparent electrode 659d2 is provided between the light-emitting surface 6653S2 and the wiring 610d2, and electrically connects the light-emitting surface 6653S2 and the wiring 610d2.

[0278] A manufacturing method for this modified example will be described. 35A to 36B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this modified example. In this modification, the process up to the step of bonding the substrates together can be the same as in the case of the above-mentioned sixth embodiment. Specifically, the same process can be applied up to the step described in relation to Fig. 31A. The following steps will be described as being applied after the step of Fig. 31A.

[0279] As shown in Fig. 35A, in this modification, the semiconductor layer 1150 shown in Fig. 31A is etched to form the light emitting layer 652 and the n-type semiconductor layer 651. Further etching is performed to form two p-type semiconductor layers 6653a1 and 6653a2.

[0280] When forming the p-type semiconductor layers 6653a1 and 6653a2, etching may be performed deeper. For example, etching for forming the p-type semiconductor layers 6653a1 and 6653a2 may be performed to a depth greater than that reaching the light emitting layer 652 and the n-type semiconductor layer 651. When forming the p-type semiconductor layers by deep etching, it is desirable to etch 1 μm or more outside the outer periphery of the light emitting surfaces 6653S1 and 6653S2 shown in FIG. 34. By moving the etching position outside the outer periphery of the light emitting surfaces 6653S1 and 6653S2, the recombination current can be suppressed.

[0281] After forming the semiconductor layer 650a, the metal layer 1230 shown in FIG. 31A is etched to form the connection plate 630a.

[0282] As shown in FIG. 35B, a first interlayer insulating film 156 is formed to cover the first surface 102a, the connecting plate 630a, and the semiconductor layer 650a.

[0283] 35C, the TFT lower film 106 is formed on the first interlayer insulating film 156, and the TFT channels 204-1 and 204-2 are formed on the TFT lower film 106. Furthermore, the insulating layer 105 is formed on the TFT channels 204-1 and 204-2, and the gates 107-1 and 107-2 are formed on the insulating layer 105. The second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gates 107-1 and 107-2.

[0284] 36A, the via holes 112d1, 112s1, 112d2, and 112s2 are formed in the same manner as in the sixth embodiment. The opening 658-1 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, so as to reach the light-emitting surface 6653S1. The opening 658-2 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, so as to reach the light-emitting surface 6653S2.

[0285] 36B, similarly to the sixth embodiment, the wiring layer 110 is formed, and a light-transmitting conductive film is formed to cover the wiring layer 110. The light-transmitting conductive film is formed into light-transmitting electrodes 659d1, 659s1, 659d2, and 659s2.

[0286] As in the sixth embodiment, an upper structure such as a color filter is formed.

[0287] In this manner, a sub-pixel group 620a having two light emitting surfaces 6653S1 and 6653S2 is formed.

[0288] In this modified example, similarly to the sixth embodiment, the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 650a.

[0289] The effects of the image display device of this embodiment will be described. FIG. 37 is a graph illustrating the characteristics of a pixel LED element. The vertical axis of Figure 37 represents the luminous efficiency [%], and the horizontal axis represents the relative value of the current density of the current flowing through the pixel LED element. As shown in Figure 37, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is almost constant or increases monotonically. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. In other words, there exists an appropriate current density for the pixel LED element that maximizes the luminous efficiency.

[0290] It is expected that a highly efficient image display device can be realized by suppressing the current density to a level where sufficient brightness can be obtained from the light-emitting element. However, as shown in Figure 37, at low current densities, the luminous efficiency tends to decrease as the current density decreases.

[0291] As described in the first to fifth embodiments, the light emitting element is formed by individually separating all layers of the semiconductor layer 1150 including the light emitting layer by etching or the like. At this time, the junction surface between the light emitting layer and the p-type semiconductor layer is exposed at the end. Similarly, the junction surface between the light emitting layer and the n-type semiconductor layer is exposed at the end.

[0292] When such an edge exists, electrons and holes recombine at the edge. However, such recombination does not contribute to light emission. Recombination at the edge occurs almost independently of the current flowing through the light-emitting device. It is considered that recombination occurs according to the length of the junction surface that contributes to the light emission of the edge.

[0293] When two cubic light-emitting elements of the same dimensions are made to emit light, the four side surfaces of each light-emitting element become ends, so that the two light-emitting elements have a total of eight ends, and recombination can occur at the eight ends.

[0294] In contrast, in this embodiment, the semiconductor layers 650 and 650a have four side surfaces, and two light-emitting surfaces have four ends. However, since the region between the openings 658-1 and 658-2 has few electrons and holes injected and hardly contributes to light emission, it can be considered that the number of ends that contribute to light emission is six. Thus, in this embodiment, the number of ends of the semiconductor layer is substantially reduced, thereby reducing recombination that does not contribute to light emission. By reducing recombination that does not contribute to light emission, the drive current for each light-emitting surface is reduced.

[0295] In the case where the distance between the subpixels is shortened for high definition or the current density is relatively high, the distance between the light emitting surface 653S1 and the light emitting surface 653S2 is substantially shortened in the subpixel group 620 of the sixth embodiment. In this case, if the p-type semiconductor layer is shared as in the sixth embodiment, some of the holes injected into the driven light emitting surface may be diverted, causing the light emitting surface that is not driven to emit weak light. In the subpixel group 620a of the modified example, the p-type semiconductor layer is separated into two, and each p-type semiconductor layer has a light emitting surface, so that it is possible to reduce the occurrence of weak light emission in the light emitting surface on the side that is not driven.

[0296] In this embodiment, the semiconductor layer including the light-emitting layer is laminated in the order of the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer from the side of the connection plate 630a, which is preferable from the viewpoint of reducing the manufacturing cost by growing the crystal from the n-type semiconductor layer on the crystal growth substrate without using a support substrate. As in the other embodiments, the lamination order of the n-type semiconductor layer and the p-type semiconductor layer may be changed and the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer may be laminated in this order from the side of the connection plate 630a, as described above. In addition, when the p-type semiconductor layer 653 is connected to the connection plate 630a as the lower layer, it is preferable to provide a conductive auxiliary plate between the connection plate 630a and the p-type semiconductor layer 653 as in the third embodiment.

[0297] Specific examples have been described for the subpixels and subpixel groups of the image display device of each of the above-mentioned embodiments. Each of the specific examples is merely an example, and other configuration examples can be obtained by appropriately combining the configurations and process procedures of these embodiments. For example, in the first to fifth embodiments, a connection plate may be used to connect to a power supply line or a ground line without using a via, and in the sixth embodiment, a via may be used to electrically connect the light-emitting elements.

[0298] Seventh embodiment The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0299] FIG. 38 is a block diagram illustrating an image display device according to this embodiment. FIG. 38 shows the main components of a computer display. 38, an image display device 701 includes an image display module 702. The image display module 702 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 702 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0300] The image display device 701 further includes a controller 770. The controller 770 receives a control signal that is separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each sub-pixel and to control the driving order.

[0301] (Modification) The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0302] FIG. 39 is a block diagram illustrating an image display device according to a modified example of this embodiment. FIG. 39 shows the configuration of a high-definition thin television. As shown in Fig. 39, an image display device 801 includes an image display module 802. The image display module 802 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied by a bus 840. The frame memory 880 stores one frame's worth of display data, and is used for processing such as smooth video playback.

[0303] The image display device 801 has an I / O circuit 810. The I / O circuit 810 is simply indicated as "I / O" in Fig. 39. The I / O circuit 810 provides an interface circuit for connecting to an external terminal, device, etc. The I / O circuit 810 includes, for example, a USB interface for connecting an external hard disk device, etc., and an audio interface.

[0304] The image display device 801 has a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to the receiving unit 820, and separates and generates a necessary signal from the radio waves received by the antenna 822. The signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 820 is separated by the signal processing unit 830 into image data, audio data, etc., and generated.

[0305] By configuring the receiving unit 820 and the signal processing unit 830 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for WiFi, a GPS receiver, etc., the image display device can be configured as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be configured as a mobile information terminal such as a smartphone or a car navigation system.

[0306] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be any of its modified examples or other embodiments.

[0307] According to the embodiment described above, it is possible to realize a manufacturing method for an image display device and an image display device that shortens the transfer process of light emitting elements and improves the yield.

[0308] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0309] 1,201,701,801 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20,20a,220,320,420,520 Subpixel, 22,222 Light-emitting element, 24,224 Selection transistor, 26,226 Drive transistor, 28,228 Capacitor, 101 Circuit, 102,502 Substrate, 102a First surface, 103,203,203-1,203-2 Transistor, 104,204,204-1,204-2 TFT channel, 105 Insulating layer, 107,107-1,107-2 Gate, 108 Second interlayer insulating film, 110 Wiring layer, 130 conductive layer, 130a connection plate, 135 conductive auxiliary layer, 135a conductive auxiliary plate, 150, 250 light emitting element, 151S, 253S, 653S1, 653S2, 6653S1, 6653S2 light emitting surface, 156 first interlayer insulating film, 159d, 159s, 159a, 159k, 659d1, 659d2 transparent electrode, 161a, 161k, 461a via, 180 color filter, 620, 620a subpixel group, 1001 crystal growth substrate, 1140 buffer layer, 1150 semiconductor layer, 1190 support substrate, 1192 structure, 1194, 1194a, 1294, 1294a semiconductor growth substrate

Claims

1. preparing a second substrate having a semiconductor layer including a light emitting layer formed on a first substrate; forming a first metal layer on a third substrate; bonding the semiconductor layer to the first metal layer; removing the first substrate; etching the semiconductor layer to form a light emitting element including a bottom surface on the first metal layer and a light emitting surface facing the bottom surface; forming a first insulating film covering the third substrate and the light emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light emitting surface; forming a wiring layer on the second insulating film; A method for manufacturing an image display device comprising the steps of:

2. After forming the light emitting element, the first metal layer is processed to form a first portion having electrical conductivity and optical reflectivity. Further equipped with The light emitting element is provided on the first portion, The method for manufacturing an image display device according to claim 1 , wherein the outer periphery of the first portion includes the outer periphery of the light emitting element when the light emitting element is projected in a plan view.

3. forming a first via that penetrates the first insulating film and the second insulating film and electrically connects the first portion and the wiring layer; The method for manufacturing an image display device according to claim 2, further comprising:

4. preparing a second substrate having a semiconductor layer including a light emitting layer formed on a first substrate; forming a second metal layer on the second substrate; bonding the semiconductor layer to a third substrate via the second metal layer; removing the first substrate; etching the semiconductor layer to form a light emitting element including a bottom surface on the second metal layer and a light emitting surface facing the bottom surface; forming a first insulating film covering the third substrate and the light emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light emitting surface; forming a wiring layer on the second insulating film; A method for manufacturing an image display device comprising the steps of:

5. forming a layer having hole injection properties on the semiconductor layer before forming the second metal layer; Further equipped with the semiconductor layer is laminated in this order from the third substrate side when bonded to the third substrate, the first semiconductor layer of a first conductivity type, the light emitting layer, and the second semiconductor layer of a second conductivity type different from the first conductivity type; the first conductivity type is p-type, 5. The method for manufacturing an image display device according to claim 4, wherein the second conductivity type is an n-type.

6. After forming the light emitting element, the second metal layer is processed to form a second portion having electrical conductivity and light reflectivity. Further equipped with The light emitting element is provided on the second portion, The method for manufacturing an image display device according to claim 4 , wherein the outer periphery of the second portion includes the outer periphery of the light emitting element when the light emitting element is projected in a plan view.

7. forming a second via that penetrates the first insulating film and the second insulating film and electrically connects the second portion and the wiring layer; The method for manufacturing an image display device according to claim 6, further comprising:

8. 2. The method of claim 1, wherein the step of bonding the semiconductor layer to the third substrate includes bonding a plurality of the second substrates to one of the third substrates.

9. The method for manufacturing an image display device according to claim 1 , wherein the third substrate includes a light-transmitting substrate.

10. the third substrate further includes a fourth substrate having flexibility and provided on the light-transmitting substrate, The method for manufacturing an image display device according to claim 9 , further comprising the step of removing the light-transmitting substrate after bonding the semiconductor layer to the fourth substrate in the step of bonding the semiconductor layer to the third substrate.

11. The method for manufacturing an image display device according to claim 1 , further comprising the step of forming a translucent electrode on the exposed light-emitting surface.

12. The method for manufacturing an image display device according to claim 1 , wherein the semiconductor layer includes a gallium nitride compound semiconductor.

13. The method for manufacturing an image display device according to claim 1 , further comprising the step of forming a wavelength conversion member on the light emitting element.

14. a substrate having a first surface; A conductive layer provided on the first surface; a light emitting element having a bottom surface on the conductive layer and including a light emitting surface facing the bottom surface; a first insulating film covering a side surface of the light emitting element and the conductive layer; A circuit element provided on the first insulating film; a second insulating film covering the circuit element and the first insulating film; A wiring layer provided on the second insulating film; An image display device comprising:

15. the conductive layer includes a first portion that is conductive and light reflective; The light emitting element is provided on the first portion, The image display device according to claim 14 , wherein the outer periphery of the first portion includes an outer periphery of the light emitting element when the light emitting element is projected onto the first portion in a plan view.

16. the light-emitting element is formed by stacking a first semiconductor layer of a first conductivity type, a light-emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type in this order from the first portion side toward the light-emitting surface side; the first conductivity type is p-type, the second conductivity type is n-type, a layer having hole injection properties between the first portion and the first semiconductor layer; The image display device according to claim 15, further comprising:

17. a via provided through the first insulating film and the second insulating film, electrically connecting the first portion and the wiring layer The image display device according to claim 16, further comprising:

18. the wiring layer includes a first wiring connected to the via and a second wiring connected to a surface including the light emitting surface, the first semiconductor layer is electrically connected to the first wiring through the first portion and the via; The image display device according to claim 17 , wherein the second semiconductor layer is electrically connected to the circuit element via a surface including the light emitting surface and the second wiring.

19. the wiring layer includes a third wiring connected to the via and a fourth wiring connected to a surface including the light emitting surface, the first semiconductor layer is electrically connected to the circuit element through the first portion, the via, and the third wiring; The image display device according to claim 17 , wherein the second semiconductor layer is electrically connected to the fourth wiring via a surface including the light emitting surface.

20. The image display device according to claim 14 , wherein the substrate includes a light-transmitting substrate.

21. The image display device according to claim 14 , wherein the substrate includes a flexible substrate.

22. A light-transmitting electrode provided on the light-emitting surface. Further equipped with 15. The image display device according to claim 14, wherein the light emitting element is connected to the wiring layer via the light transmitting electrode.

23. 15. The image display device according to claim 14, wherein the light emitting element includes a gallium nitride compound semiconductor.

24. The image display device according to claim 14 , wherein the circuit elements include thin film transistors.

25. The image display device according to claim 14 , further comprising a wavelength conversion member on the light emitting element.

26. a substrate having a first surface; A conductive layer provided on the first surface; a semiconductor layer having a bottom surface on the conductive layer and including a plurality of light emitting surfaces on a surface opposite to the bottom surface; a first insulating film covering a side surface of the semiconductor layer and the conductive layer; A plurality of transistors provided on the first insulating film; a second insulating film covering the plurality of transistors and the first insulating film; A wiring layer provided on the second insulating film; An image display device comprising:

27. the semiconductor layer is laminated in the order of a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type from the conductive layer toward the plurality of light emitting surfaces; 27. The image display device according to claim 26, wherein the second semiconductor layer is separated by the first insulating film.

Images