Switching power supply circuit

Abstract

To perform a stable phase compensation while suppressing increase of the area of a circuit layout or the number of terminals.SOLUTION: A switching power source circuit supplies electric power from a power source circuit to a load so that a switching operation of a switching element makes a voltage applied to the load a predetermined value. The circuit includes an error amplifier, an oscillation circuit, a comparator, and a phase compensation circuit. The phase compensation circuit includes: a first resistor and a second capacitor for converting the output voltage of the error amplifier to a first current signal and a second current signal; a first current mirror circuit and a second current mirror circuit in which the first current signal and the second current signal are input, respectively; and a second resistor for receiving an output current of the first current mirror and an output current of the second current mirror and generating an output voltage for an input terminal of the comparator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a switching power supply circuit. [Background technology]

[0002] A so-called switching power supply circuit that uses the switching operation of a switching element is known as a power supply circuit for stabilizing the voltage from a power supply to a predetermined value in order to stably operate a load to which power is supplied (for example, Patent Document 1). This type of switching power supply circuit is used in the form of a composite power supply IC, and is mounted, for example, in a vehicle together with other circuits (amplifiers, LDOs (Low Drop-Out), etc.), to step down the power supply voltage of a 12V vehicle battery and supply power to various devices (microcomputers, etc.) that are loads mounted in the vehicle. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-51127 A Summary of the Invention [Problem to be solved by the invention]

[0004] Here, a switching power supply circuit according to the background art will be described with reference to Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are circuit diagrams showing switching power supply circuits 1A' and 1B' according to the reference art together with their peripheral configurations. Note that Fig. 7 and Fig. 8 show a voltage feedback step-down switching power supply circuit, with the left side of the dashed line showing the internal circuit of the IC (integrated circuit) and the right side of the dashed line showing the configuration of the external circuit of the IC.

[0005] The switching power supply circuit 1A' shown in FIG. 7 includes an error amplifier AMP1 and a comparator COMP1. The error amplifier AMP1 has a pair of input terminals, i.e., an inverting input terminal 2 and a non-inverting input terminal 4, and a differential output terminal 6 for extracting a differential output according to the potential difference between the inverting input terminal 2 and the non-inverting input terminal 4. A feedback voltage (output detection voltage) obtained by dividing the output voltage Vout by feedback resistors RFB1 and RFB2 is input to the inverting input terminal 2, and a reference voltage VREF is input to the non-inverting input terminal 4, and a voltage obtained by amplifying the difference between the two is output from the differential output terminal 6. The comparator COMP1 has a non-inverting input terminal 8 to which the output voltage from the differential output terminal 6 is input, and an inverting input terminal 10 to which a triangular wave (or sawtooth wave) voltage having a constant period generated by an oscillation circuit 7 is input, and a voltage according to the comparison result between the two is output from an output terminal 12. The output voltage of the comparator COMP1 is input to a gate drive circuit 14, and the gate drive circuit 14 outputs a gate drive voltage corresponding to this to a terminal GATE.

[0006] The output transistor MP1 is a P-channel MOS transistor (MOSFET) with its source connected to the power supply voltage VBAT, its drain connected to the load resistance RL via the inductance L1, and its gate connected to the terminal GATE. The output transistor MP1 receives a gate drive voltage from the terminal GATE at its gate, and performs a switching operation to connect or disconnect the source-drain in response to the gate drive voltage, thereby supplying power from the power supply VBAT to the load resistance RL at a predetermined output voltage VOUT.

[0007] The switching power supply circuit 1A' has a load resistor RL as a load, and a phase compensation capacitor CFB is provided in a feedback circuit 15 including feedback resistors RFB1 and RFB2. More specifically, the phase compensation capacitor CFB is provided between the input side of the feedback circuit 15 and a node between the feedback resistors RFB1 and RFB2. In a composite power supply IC, it may be required to mount each element such as the feedback resistors RFB1 and RFB2 and the phase compensation capacitor CFB in the IC in order to reduce the number of parts. In this case, when the output voltage VOUT of the switching power supply circuit 1A' becomes relatively high, the voltage applied to the phase compensation capacitor CFB during operation becomes large, so that a phase compensation capacitor CFB with a high withstand voltage is required. Depending on the semiconductor manufacturing process, it may not be possible to manufacture a phase compensation capacitor CFB with such a high withstand voltage, or even if it can be manufactured, the capacitance value per unit area is small, so that the area becomes large in order to realize the required capacitance value, making it difficult to mount it in the IC.

[0008] Furthermore, as shown in FIG. 8, a switching power supply circuit 1B' in which a load includes a light emitting diode (LED: Light Emitting Diode) has the following problem. The switching power supply circuit 1B' includes light-emitting diodes LED1 and LED2 as a load, in comparison with the switching power supply circuit 1A' described above. In order to control the output voltage of the switching power supply circuit 1B' so that the current flowing through the resistance component RLED of the load is constant, the phase compensation capacitor CFB cannot be provided in the feedback circuit 15 as in the switching power supply circuit 1A' of FIG. 7. Therefore, in the switching power supply circuit 1B', a current detection resistor RSENSE is placed between the source of the output transistor MP1 and the power supply voltage VBAT, and a SENSE terminal is added to detect the potential of the node provided between the source of the output transistor MP1 and the current detection resistor RSENSE, so that the source current of the output transistor MP1 is monitored to perform current mode control.

[0009] In a switching power supply circuit configured as a composite power supply IC, it is preferable to reduce the number of terminals as much as possible and allocate them to pins of other circuits, but when the load includes a light-emitting diode as in switching power supply circuit 1B', it becomes necessary to add a SENSE terminal as described above, which increases the number of terminals. Also, for the IC's external circuits, it is preferable to reduce the number of components by limiting the specifications rather than increasing versatility, but switching power supply circuit 1B' requires a current detection resistor RSENSE, which increases the number of components. Also, providing the current detection resistor RSENSE increases power consumption during operation to no small extent, resulting in losses.

[0010] At least one embodiment of the present disclosure has been made in consideration of the above-mentioned circumstances, and has an object to provide a switching power supply circuit that can perform stable phase compensation while suppressing an increase in the circuit layout area and the number of terminals. [Means for solving the problem]

[0011] In order to solve the above problem, a switching power supply circuit according to one embodiment of the present invention comprises: 1. A switching power supply circuit capable of supplying power from a power supply circuit to a load such that a voltage applied to the load becomes a predetermined value by switching operation of a switching element, an error amplifier having an output terminal connected to a first capacitor and capable of outputting from the output terminal a signal based on a difference between an output detection voltage that changes linearly or nonlinearly in response to a voltage applied to the load and a reference voltage; An oscillator circuit capable of generating a triangular wave voltage having a constant period; a comparator capable of controlling the switching operation of the switching element by comparing an output voltage of the error amplifier with the triangular wave voltage of the oscillation circuit; a phase compensation circuit inserted between the output terminal of the error amplifier and the input terminal of the comparator; Equipped with The phase compensation circuit includes: a first resistor for converting the output voltage of the error amplifier into a first current signal; a second capacitor for converting the output voltage of the error amplifier into a second current signal; a first current mirror circuit and a second current mirror circuit to which the first current signal and the second current signal are respectively input; a second resistor to which the output currents of the first current mirror circuit and the second current mirror circuit are input, for generating an output voltage for the input terminal of the comparator; Equipped with. Effect of the Invention

[0012] According to at least one embodiment of the present disclosure, it is possible to provide a switching power supply circuit capable of performing stable phase compensation while suppressing an increase in the circuit layout area and the number of terminals. [Brief description of the drawings]

[0013] [Figure 1] 1 is a circuit diagram showing a configuration of a switching power supply circuit according to a first embodiment. [Diagram 2] 2 is a circuit diagram showing a configuration of a phase compensation circuit in FIG. 1. [Diagram 3] FIG. 11 is a circuit diagram showing a phase compensation circuit included in a switching power supply circuit according to a second embodiment. [Figure 4] FIG. 2 is a diagram showing signal waveforms in the switching power supply circuit. [Diagram 5] FIG. 11 is a circuit diagram of a switching power supply circuit according to a third embodiment. [Figure 6] FIG. 6 is a circuit diagram showing the phase compensation circuit of FIG. 5. [Figure 7] FIG. 1 is a circuit diagram showing a switching power supply circuit according to a reference technique. [Figure 8] FIG. 1 is a circuit diagram showing a switching power supply circuit according to a reference technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, some embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of components described as the embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure.

[0015] First, as a premise of the embodiment of the present disclosure, basic phase compensation in the switching power supply circuit 1A' according to the above-mentioned reference technology will be described with reference to Fig. 7. In the switching power supply circuit 1A', the resonant frequency f0 in the output section 16 formed of the capacitor COUT and the inductance L1 is expressed as follows. TIFF0007624871000001.tif8170

[0016] In phase compensation, the zero generated by the first capacitor CEO and resistor REO connected between the output terminal 6 (EOUT terminal) of the error amplifier AMP1 and the ground point, and the zero generated by the phase compensation capacitor CFB and feedback resistor RFB1 are set near the resonance frequency f0 expressed by equation (1), thereby canceling out the phase delay generated at the resonance frequency of the inductance L1 and capacitor COUT. The frequency f Z1 , and the frequency f of the zero caused by the feedback resistor RFB1 Z2 are expressed as follows, respectively: TIFF0007624871000002.tif9170TIFF0007624871000003.tif8170

[0017] (First embodiment) Next, a switching power supply circuit 1A according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a circuit diagram showing the configuration of the switching power supply circuit 1A according to the first embodiment, and Fig. 2 is a circuit diagram showing the configuration of a phase compensation circuit 20A in Fig. 1.

[0018] The switching power supply circuit 1A is a circuit for supplying power to a load at a predetermined voltage. In FIG. 1, a resistor RL is illustrated as an example of the load of the switching power supply circuit 1A, but the load may include a light-emitting diode LED as shown in a switching power supply circuit 1B' in FIG. 8. The switching power supply circuit 1A includes a phase compensation circuit 20A having a function of performing phase compensation. The phase compensation circuit 20A is disposed so as to be inserted between the output terminal 6 of the error amplifier AMP1 and the non-inverting input terminal 8 of the comparator COMP1, and is applicable to a switching power supply circuit that supplies power to a load including a variety of elements including a resistor and a light-emitting diode.

[0019] As shown in FIG. 2, the phase compensation circuit 20A includes a first resistor R1 for converting the output voltage of the error amplifier AMP1 into a first current signal CS1, a second capacitor C2 for converting the output voltage of the error amplifier AMP1 into a second current signal CS2, a first current mirror circuit CM1 and a second current mirror circuit CM2 to which the first current signal CS1 and the second current signal CS2 are input, respectively, and a second resistor R2 to which the output currents of the first current mirror circuit CM1 and the second current mirror circuit CM2 are input and which generates an output voltage for the comparator COMP1.

[0020] The phase compensation circuit 20A has an SIN terminal which is an input terminal, and an SOUT terminal which is an output terminal. The SIN terminal is connected to transistors MN1 and MN2 which are N-channel MOS transistors (MOSFETs) for buffering the voltage input from the error amplifier AMP1 to the SIN terminal. More specifically, the gate of the transistor MN1 is connected to the SIN terminal, the source of the transistor MN1 is connected to the second capacitor C2, and the drain of the transistor MN2 is connected to the second current mirror circuit CM2. The gate of the transistor MN2 is connected to the SIN terminal, the source of the transistor MN2 is connected to the first resistor R1, and the drain of the transistor MN2 is connected to the first current mirror circuit CM1. The first resistor R1 is connected between the source of the transistor MN2 and the ground point GND, and converts the output voltage from the error amplifier AMP1 into a first current signal CS1. The second capacitor C2 is connected between the source of the transistor MN1 and the ground point GND, and converts the output voltage of the error amplifier AMP1 into a second current signal CS2.

[0021] The first current signal CS1 is mirrored by a first current mirror circuit CM1 including transistors MP2 and MP3, which are P-channel MOS transistors (MOSFETs). The first current mirror circuit CM1 has transistors MP2 and MP3. More specifically, the gate and drain of the transistor MP2 are connected to the drain of the transistor MN2, and the source of the transistor MP2 is connected to the source of the transistor MP3. The gate of the transistor MP3 is connected to the drain of the transistor MN2, the source of the transistor MP2 is connected to the source of the transistor MP2, and the drain of the transistor MP3 is connected to the SOUT terminal.

[0022] The second current signal CS2 is reflected by a second current mirror circuit CM2 including transistors MP4 and MP5, which are P-channel MOS transistors (MOSFETs). The second current mirror circuit CM2 has transistors MP4 and MP5. More specifically, the gate and drain of the transistor MP4 are connected to the drain of the transistor MN1, and the source of the transistor MP5 is connected to the source of the transistor MP5. The gate of the transistor MP5 is connected to the drain of the transistor MN1, the source of the transistor MP4 is connected to the source of the transistor MP4, and the drain of the transistor MP5 is connected to the SOUT terminal.

[0023] On the output side of the first current mirror circuit CM1 and the second current mirror circuit CM2, the second resistor R2 is connected between the SOUT terminal and the ground point GND. In this way, the output terminal SOUT of the phase compensation circuit 20A is configured as a node where the outputs of the second resistor R2 and the current mirror circuits CM1 and CM2 are connected to each other, and is connected to the non-inverting input terminal 8 of the comparator COMP1.

[0024] In the phase compensation circuit 20A having such a configuration, the output voltage of the error amplifier AMP1 is input from the SIN terminal to the gates of the transistors MN1 and MN2. The transistors MN1 and MN2 function as buffers for the voltage signal input from the SIN terminal, and apply a voltage lowered by the gate-source potential difference (Vgs) of the transistors MN1 and MN2 to the second capacitor C2 and the first resistor R1 connected to the respective sources. The drain currents (first current signal CS1 and second current signal CS2) of the transistors MN1 and MN2 are folded back by the first current mirror circuit CM1 and the second current mirror circuit CM2, and flow to the second resistor R2. The current source I1 is configured to pass a DC bias current to the second current mirror circuit CM2 including the transistors MP4 and MP5, and the transfer function of such a phase compensation circuit 20A is expressed as follows: TIFF0007624871000004.tif8170 where v so : Voltage at the SOUT terminal (small signal), v si: voltage at the SIN terminal (small signal), m: drain current ratio of transistors MP4 and MP5.

[0025] According to the above formula (4), the frequency f z3 is calculated as follows: TIFF0007624871000005.tif9170

[0026] Here, m is the ratio of the input (the drain current of the transistor MP4) to the output (the drain current of the transistor MP5) of the second current mirror circuit CM2 formed by the transistors MP4 and MP5, and is a parameter determined by the gate aspect ratio of the transistors MP4 and MP5. z3 Since depends on the value of m, it is possible to change it by adjusting the value of m. Therefore, even if the capacitance value of the second capacitor C2 included in the phase compensation circuit 20A is small, it is possible to generate a zero at a low frequency by adjusting the value of m. This contributes to reducing the layout area of ​​the entire switching power supply circuit by reducing the number of capacitors that require a large layout area.

[0027] As described above, according to this embodiment, the phase compensation capacitor CFB with a high breakdown voltage as in the conventional example is not necessary, and the second capacitor C2 of the phase compensation circuit 20A can have a small capacitance value, reducing the layout area and enabling the configuration of a phase compensation circuit 20A capable of performing stable phase compensation without increasing the number of terminals. By including such a phase compensation circuit 20A, the switching power supply circuit 1A can effectively reduce the overall layout area.

[0028] In the phase compensation circuit 20A shown in FIG. 2, a direct current is applied to the transistor MP4 on the input side of the second current mirror circuit CM2 by the current source I1 connected to the source of the transistor MN1, and a voltage equal to or higher than the threshold is generated between the gate and source of the transistor MP4. If this current is smaller than the drain current of the transistor MN2, no problem occurs. However, since this current always flows regardless of the input voltage of the SIN terminal, it acts as a direct current bias on the voltage of the SOUT terminal and increases in proportion to the value of m. Therefore, if the value of m is set large, the voltage of the SOUT terminal does not drop completely with respect to the triangular wave (or sawtooth wave) voltage to be compared by the comparator COMP1, and the comparator COMP1 cannot output a signal with a low on-duty, which may make it difficult to stably operate the switching power supply circuit 1A. Such a problem can be solved by the switching power supply circuit 1B according to the second embodiment described below.

[0029] Second embodiment 3 is a circuit diagram showing a phase compensation circuit 20B included in the switching power supply circuit according to the second embodiment. Note that the configuration of the switching power supply circuit according to the second embodiment, excluding the phase compensation circuit 20B, is similar to that of the switching power supply circuit 1A according to the first embodiment described above, and therefore will not be described in detail here.

[0030] The phase compensation circuit 20B of the second embodiment further includes a third current mirror circuit CM3, as compared with the above-mentioned phase compensation circuit 20A (see FIG. 2). The third current mirror circuit CM3 includes transistors MN3, MN4, and MN5. More specifically, the gate and drain of the transistor MN3 are connected to the second current source I2, and the source of the transistor MN3 is connected to the ground point GND. The gate of the transistor MN4 is connected to the second current source I2, the source of the transistor MN4 is connected to the ground point GND, and the drain of the transistor MN4 is connected to a node provided between the source of the transistor MN1 and the second capacitor C2. The gate of the transistor MN5 is connected to the gates of the transistors MN3 and MN4, the source of the transistor MN5 is connected to the ground point GND, and the drain of the transistor MN5 is connected to the SOUT terminal. Here, the ratio of the input (the drain current of the transistor MN3) to the output (the drain current of the transistor MN5) of the third current mirror circuit CM3 is set to m, which is the same as the drain current ratio of the transistors MP4 and MP5 of the second current mirror circuit CM2.

[0031] In this circuit configuration, the third current mirror circuit CM3 sinks a current m times that of the current source I2 from the SOUT terminal through the transistor MN5, thereby canceling the DC bias described above. This makes it possible to maintain stable operation of the switching power supply circuit 1A even when the value of m is set to a large value.

[0032] Here, in the above-mentioned phase compensation circuit 20A (phase compensation circuit 20B is also the same), the voltage of the SOUT terminal does not change until the voltage of the SIN terminal reaches the threshold voltage Vthn of the transistors MN1 and MN2. Therefore, when the switching power supply circuit is started, if the voltage of the SIN terminal (EOUT terminal) does not increase from 0V to the threshold voltage Vthn of the transistors MN1 and MN2, the first current mirror circuit CM1 and the second current mirror circuit CM2 do not operate, so the output voltage of SOUT remains at 0V, and then the voltage of the SIN terminal increases to the threshold voltage Vthn of the transistors MN1 and MN2, and finally the output voltage of the SOUT terminal increases. Therefore, it takes time for the output transistor MP1 to start switching operation.

[0033] 1 has a waveform that periodically fluctuates between an upper limit value VOSCH and a lower limit value VOSCL, as shown in FIG. 4. In particular, this triangular (or sawtooth) voltage is always equal to or higher than VOSCL because the output transistor MP1 does not turn on when the voltage at the SOUT terminal becomes 0V. As a result, when the switching power supply circuit 1A in FIG. 1 is started up, the voltage at the EOUT terminal rises from 0V and the output transistor MP1 starts to perform a switching operation. EOSW is expressed as follows using the threshold voltages Vthn of the transistors MN1 and MN2: TIFF0007624871000006.tif7170

[0034] As shown in Figure 1, a first capacitor CEO for phase compensation is connected to the EOUT terminal. Therefore, when the switching power supply circuit 1A starts up, the voltage of the EOUT terminal rises from 0V to the voltage V EOSW It takes time for the error amplifier AMP1 to charge the first capacitor CEO until the voltage at the VOUT terminal reaches the specified value, and a delay occurs before the voltage at the VOUT terminal reaches the specified value. In order to reduce this delay time, it is necessary to reduce the time it takes for the output transistor MP1 to start switching operation. This problem can be suitably solved by the switching power supply circuit 1C according to the third embodiment described below.

[0035] Third embodiment FIG. 5 is a circuit diagram of a switching power supply circuit 1C according to the third embodiment, and FIG. 6 is a circuit diagram showing a phase compensation circuit 20C of FIG.

[0036] The switching power supply circuit 1C further includes a charging circuit 30 for charging the first capacitor CEO at startup. The charging circuit 30 includes transistors MP6 and MP7. More specifically, the transistor MP6 has a gate connected to the CONT terminal, a source connected to the third current source I3, and a drain connected to the SIN terminal. The transistor MP7 has a gate connected to the CONT terminal, a source connected to the third current source I3, and a drain connected to the drain of the transistor MN1.

[0037] The output voltage of the latch circuit 24 is input to the charging circuit 30 from the CONT terminal. The output voltage of the latch circuit 24 is low at startup, and the transistors MP6 and MP7 are in the ON state. At this time, the current source I3 applies a charging current Ic (see FIG. 5) from the SIN terminal to the first capacitor CEO via the transistor MP6.

[0038] The first capacitor CEO is gradually charged by the charging current Ic from the current source I3, and the voltage of the EOUT terminal rises over time. When the SOUT terminal voltage reaches VOCSL, the output voltage of the comparator COMP1 switches from High to Low, and the switching operation of the output transistor MP1 begins. At this time, the voltage of the output terminal 12 of the comparator COMP1 is also input to the IN terminal of the latch circuit 24, and at the timing when the switching operation begins, the output of the OUT terminal of the latch circuit 24 switches from Low to High, and thereafter the High state is maintained. When the output voltage of the latch circuit 24 becomes High in this way, the transistors MP6 and MP7 of the charging circuit 30 are turned OFF, and the charging of the first capacitor CEO ends.

[0039] In this embodiment, the first capacitor CEO is charged by the charging circuit 30 when the switching power supply circuit 1C is started. The charging circuit 30 determines that charging is complete when the switching operation of the output transistor MP1 is detected, and ends the charging operation of the first capacitor CEO. This effectively shortens the time required for the output transistor MP1 to start switching operation. After the charging circuit 30 completes charging the first capacitor CEO, the phase compensation circuit 20C performs phase compensation in the same manner as the phase compensation circuits 20A and 20B described above.

[0040] The charging circuit 30 of this embodiment is built into the phase compensation circuit 20C as shown in Fig. 6. This allows the charging circuit 30 to be mounted in the switching power supply circuit 1C with an efficient layout while suppressing the complication of the circuit configuration of the switching power supply circuit 1C. Note that, although Fig. 6 illustrates a case where the charging circuit 30 is built into the phase compensation circuit 20C, the charging circuit 30 may be mounted in the switching power supply circuit 1C as a separate configuration from the phase compensation circuit 20C, or may be built into another configuration such as the error amplifier AMP1, for example.

[0041] In order to shorten the charging time of the first capacitor CEO by the charging circuit 30, the output current value of the current source I3 can be set large, but if the voltage at the SIN terminal rises sharply as a result, the voltage applied to the second capacitor C2 also increases sharply. This causes a temporary increase in the drain current of the transistor MP5 constituting the second current mirror circuit CM2, which in turn causes the voltage at the SOUT terminal to rise, resulting in a so-called overshoot. This type of overshoot may cause the output of the error amplifier AMP1 to switch to High and the transistor MP6 to switch to the OFF state before the output voltage at the EOUT terminal has risen sufficiently, which may cause charging of the EOUT terminal to end.

[0042] In order to solve such a problem, the phase compensation circuit 20C of this embodiment is configured to cut off the output current from the second current mirror circuit CM2 while the first capacitor CEO is being charged by the charging circuit 30. Specifically, the transistor MP7 stops the operation of the second current mirror circuit CM2 including the transistors MP4 and MP5 while the first capacitor CEO is being charged at startup. At the same time, the gate of the transistor MN6 is connected to the CONT terminal, and by turning the transistor MN6 off while the first capacitor CEO is being charged, the drain current of the transistor MN5 is stopped. This can also prevent the charging current from the current source I3 from being stopped while the first capacitor CEO is being charged.

[0043] As described above, according to each of the above embodiments, since there is no need to perform phase compensation in the feedback circuit 15 (see FIG. 7), it is possible to realize a switching power supply circuit that does not require a high-voltage resistant capacitor and can perform phase compensation for a load including an LED. In particular, in the phase compensation circuit, since the current flowing through the second capacitor C2 can be increased by the second current mirror circuit CM2, the capacitance value of the second capacitor C2 can be small, and the layout area on the integrated circuit can be effectively reduced. By utilizing such characteristics, it is possible to provide a switching power supply circuit that can perform stable phase compensation with a small number of terminals.

[0044] In addition, within the scope of the present disclosure, the components in the above-described embodiments may be replaced with well-known components as appropriate, and the above-described embodiments may be combined as appropriate.

[0045] The contents described in each of the above embodiments can be understood, for example, as follows.

[0046] (1) A switching power supply circuit according to one embodiment includes: A switching power supply circuit (e.g., the switching power supply circuits 1A, 1B, and 1C of the above embodiments) capable of supplying power from a power supply circuit to a load so that a voltage applied to the load becomes a predetermined value by switching operation of a switching element (e.g., the output transistor MP1 of the above embodiments), an error amplifier (for example, the error amplifier AMP1 in the above embodiment) having an output terminal connected to a first capacitor (for example, the first capacitor CEO in the above embodiment) and capable of outputting from the output terminal a signal based on a difference between an output detection voltage that changes linearly or nonlinearly in response to a voltage applied to the load and a reference voltage; An oscillator circuit capable of generating a triangular wave voltage having a constant period (for example, the oscillator circuit 7 in the above embodiment); a comparator (e.g., the comparator COMP1 in the above embodiment) capable of controlling the switching operation of the switching element by comparing the output voltage of the error amplifier with the triangular wave voltage of the oscillator circuit; a phase compensation circuit (for example, the phase compensation circuits 20A, 20B, and 20C in the above-described embodiments) inserted between the output terminal of the error amplifier and the input terminal of the comparator; Equipped with The phase compensation circuit includes: a first resistor (e.g., the first resistor R1 in the above embodiment) for converting the output voltage of the error amplifier into a first current signal; a second capacitor (e.g., the second capacitor C2 in the above embodiment) for converting the output voltage of the error amplifier into a second current signal; a first current mirror circuit (e.g., the first current mirror circuit CM1 in the above embodiment) and a second current mirror circuit (e.g., the second current mirror circuit CM2 in the above embodiment) to which the first current signal and the second current signal are respectively input; a second resistor (e.g., the second resistor R2 in the above embodiment) to which the output currents of the first current mirror circuit and the second current mirror circuit are input, for generating an output voltage for the input terminal of the comparator; Equipped with.

[0047] According to the above aspect (1), it is possible to configure a phase compensation circuit capable of performing stable phase compensation by reducing the layout area of ​​the second capacitor for phase compensation and without increasing the number of terminals.

[0048] (2) In another embodiment, in the above embodiment (1), The phase compensation circuit further includes a current source (for example, the current source I3 in the above embodiment) capable of supplying a current for canceling a DC component from the output current of the second current mirror circuit.

[0049] According to the above aspect (2), even if the gate aspect ratio of the transistor included in the second current mirror circuit is set large, it is possible to ensure stable switching operation in the switching power supply circuit.

[0050] (3) In another embodiment, in the above embodiment (1) or (2), The power supply device further includes a charging circuit (for example, the charging circuit 30 in the above embodiment) for charging the first capacitor at start-up.

[0051] According to the above aspect (3), by charging the first capacitor by the charging circuit when the switching power supply circuit is started up, the time required for the output transistor to start switching operation can be effectively shortened.

[0052] (4) In another embodiment, in the above embodiment (3), When the switching operation is detected, the charging operation of the first capacitor by the charging circuit is terminated.

[0053] According to the above aspect (4), by terminating the charging operation of the first capacitor when the switching operation of the output transistor is started, it is possible to quickly start the switching operation of the output transistor while suppressing unnecessary power consumption.

[0054] (5) In another embodiment, in the above embodiment (3) or (4), The charging circuit is built into the phase compensation circuit.

[0055] According to the above aspect (5), it is possible to mount a charging circuit on the switching power supply circuit with an efficient layout while preventing the circuit configuration of the switching power supply circuit from becoming complicated.

[0056] (6) In another embodiment, in the above embodiment (5), The second current mirror circuit is configured such that an output current from the second current mirror circuit is cut off while the first capacitor is being charged by the charging circuit.

[0057] According to the above aspect (6), even if the charging current is set large in order to shorten the charging time of the first capacitor by the charging circuit, it is possible to effectively prevent overshoot from occurring in the output voltage of the phase compensation circuit. [Explanation of symbols]

[0058] 1. Switching power supply circuit 7 Oscillator Circuit 10 Phase compensation circuit 14 Gate drive circuit 15 Feedback Circuit 16 Output section 24 Latch Circuit 30 Charging circuit AMP1 Error amplifier COMP1 Comparator CEO 1st Capacitor C2 Second capacitor CM1 First current mirror circuit CM2 Second current mirror circuit CM3 3rd current mirror circuit I1, I2, I3 current sources

Claims

1. 1. A switching power supply circuit capable of supplying power from a power supply circuit to a load such that a voltage applied to the load becomes a predetermined value by switching operation of a switching element, an error amplifier having an output terminal connected to a first capacitor and capable of outputting from the output terminal a signal based on a difference between an output detection voltage that changes linearly or nonlinearly in response to a voltage applied to the load and a reference voltage; An oscillator circuit capable of generating a triangular wave voltage having a constant period; a comparator capable of controlling the switching operation of the switching element by comparing an output voltage of the error amplifier with the triangular wave voltage of the oscillation circuit; a phase compensation circuit inserted between the output terminal of the error amplifier and the input terminal of the comparator; Equipped with The phase compensation circuit includes: a first resistor for converting the output voltage of the error amplifier into a first current signal; a second capacitor for converting the output voltage of the error amplifier into a second current signal; a first current mirror circuit and a second current mirror circuit to which the first current signal and the second current signal are respectively input; a second resistor to which the output currents of the first current mirror circuit and the second current mirror circuit are input, for generating an output voltage for the input terminal of the comparator; A switching power supply circuit comprising:

2. 2. The switching power supply circuit according to claim 1, wherein the phase compensation circuit further comprises a current source capable of supplying a current for canceling a DC component from the output current of the second current mirror circuit.

3. 3. The switching power supply circuit according to claim 1, further comprising a charging circuit for charging the first capacitor at startup.

4. 4. The switching power supply circuit according to claim 3, wherein, when the switching operation is detected, a charging operation of the first capacitor by the charging circuit is terminated.

5. 5. The switching power supply circuit according to claim 3, wherein the charging circuit is built into the phase compensation circuit.

6. 6. The switching power supply circuit according to claim 5, wherein the second current mirror circuit is configured such that an output current from the second current mirror circuit is cut off while the first capacitor is being charged by the charging circuit.

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