DC / DC converter control circuits, power supply circuits, electronic devices

Abstract

To provide a boosting type DC / DC converter control circuit capable of suppressing overvoltage of an output voltage.SOLUTION: A pulse modulator 210 includes a first error amplifier 212 for amplifying the error between a feedback signal VFB depending on an output voltage VOUT of a boosting DC / DC converter 100C and a reference voltage VREF, and generates a pulse signal Sp the pulse of which is modulated in accordance with an output signal VERR1 of the first error amplifier 212. A load switch driving circuit 270 for driving a load switch SW1 which is a PMOS transistor M3 connected between a high-side transistor M2 and a load, switches a mode between a first mode in which the PMOS transistor M3 is fully on and a second mode in which a driving voltage according to the output signal VERR1 of the first error amplifier 212 is supplied to the gate of the PMOS transistor M3.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a DC / DC converter. [Background technology]

[0002] A boost converter is used to operate devices that require a higher voltage than the power supply voltage. A boost converter always has conduction between the input line and the output line via an inductor and the body diode of the high-side transistor. Therefore, even when the boost converter is stopped, a voltage equal to the input voltage is generated on the output line and supplied to the load.

[0003] To prevent voltage from being supplied to the load while the step-up DC / DC converter is stopped, a load switch is inserted between the high-side transistor and the output line. Alternatively, instead of a load switch, a high-side switch may be inserted between the input line and the inductor. When the step-up DC / DC converter is stopped, turning off the load switch or high-side switch can prevent voltage from being generated on the output line. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP2005-130622A Summary of the Invention [Problem to be solved by the invention]

[0005] As a result of studying a step-up DC / DC converter equipped with a load switch, the present inventors have come to recognize the following problems. Note that these problems should not be taken as general recognition by those skilled in the art.

[0006] Input voltage V of the step-up DC / DC converter INfluctuates, and the output voltage V OUT Target level V OUT(REF) When the voltage exceeds V IN -V F The input voltage V IN If the load current is high, an overvoltage may be supplied to the load.

[0007] Furthermore, in some cases, a minimum value is set for the switching duty cycle of a step-up DC / DC converter. In this case, if an overcurrent state occurs due to a ground fault or the like, the duty cycle cannot be made smaller than the minimum value, so the overcurrent may continue to flow.

[0008] The present disclosure has been made in light of the above-mentioned problems, and one of its exemplary purposes is to provide a control circuit capable of solving at least one of the above-mentioned problems. [Means for solving the problem]

[0009] An embodiment of the present disclosure relates to a control circuit for a step-up DC / DC converter having a high-side transistor and a low-side transistor. The control circuit includes a first error amplifier that amplifies an error between a reference voltage and a feedback signal corresponding to an output voltage of the step-up DC / DC converter, and includes a pulse modulator that generates a pulse signal that is pulse-modulated according to an output signal of the first error amplifier, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, and a load switch drive circuit that drives a load switch that is a PMOS transistor connected between the high-side transistor and a load. The load switch drive circuit is configured to be switchable between a first mode that fully turns on the PMOS transistor and a second mode that supplies a drive voltage corresponding to the output signal of the first error amplifier to the gate of the PMOS transistor.

[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0011] According to an aspect of the present disclosure, overvoltage of the output voltage can be suppressed. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram of a step-up DC / DC converter according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating the operation of the DC / DC converter of FIG. [Diagram 3] FIG. 3 is a diagram showing the input / output characteristics of a step-up DC / DC converter and a linear regulator. [Figure 4] FIG. 4 is a diagram illustrating the transition of the output voltage VOUT of the DC / DC converter. [Diagram 5] FIG. 5 is a diagram illustrating the transition of the output voltage VOUT of the DC / DC converter. [Figure 6] FIG. 6 is a diagram illustrating the transition of the output voltage VOUT of the DC / DC converter. [Figure 7] FIG. 7 is a circuit diagram of an example of a control circuit for a DC / DC converter. [Figure 8] FIG. 8 is an equivalent circuit diagram of the DC / DC converter immediately after the switch control signal SWCTL transitions to low. [Figure 9] FIG. 9 is a waveform diagram (actual measurement) of the DC / DC converter in FIG. [Figure 10] FIG. 10 is a circuit diagram of a DC / DC converter according to the first comparative technique. [Figure 11] FIG. 11 is a block diagram of a DC / DC converter according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing current-voltage (IV) characteristics of a step-up DC / DC converter. [Figure 13] FIG. 13 is a diagram illustrating overcurrent protection of the DC / DC converter according to the second embodiment. [Figure 14] FIG. 14 is a state transition diagram of the DC / DC converter according to the second embodiment. [Figure 15] FIG. 15 is a state transition diagram of the DC / DC converter according to the third embodiment. [Figure 16] FIG. 16 is a diagram illustrating an example of an electronic device including a DC / DC converter according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified description of some concepts of one or more embodiments for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0014] This summary is not an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0015] A control circuit according to one embodiment is used in a step-up DC / DC converter having a high-side transistor and a low-side transistor. The control circuit includes a first error amplifier that amplifies an error between a reference voltage and a feedback signal corresponding to the output voltage of the step-up DC / DC converter, and includes a pulse modulator that generates a pulse signal that is pulse-modulated according to the output signal of the first error amplifier, a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal, and a load switch drive circuit that drives a load switch that is a PMOS transistor connected between the high-side transistor and a load. The load switch drive circuit is configured to be switchable between a first mode in which the PMOS transistor is fully turned on and a second mode in which a drive voltage corresponding to the output signal of the first error amplifier is supplied to the gate of the PMOS transistor.

[0016] According to this configuration, by operating the load switch drive circuit in the second mode, the PMOS transistor, the first error amplifier, and the load switch drive circuit form a linear regulator (LDO: Low Drop Output), and the output voltage can be stabilized at its target level. This solves at least one of the problems that can occur in a conventional step-up DC / DC converter having a load switch.

[0017] Since this linear regulator operates based on the output signal of the first error amplifier, feedback is applied so that the feedback signal approaches the reference voltage, and therefore the output voltage can be stabilized to the exact same target level as in the first mode.

[0018] In one embodiment, the load switch driver circuit may be in the first mode when (i) the input voltage of the step-up DC / DC converter is lower than a predetermined threshold voltage, and in the second mode when (ii) the input voltage is higher than the threshold voltage. With this configuration, even if the input voltage increases, the output voltage is stabilized at a target level, thereby suppressing overvoltage.

[0019] In one embodiment, the control circuit may further include a first current detection circuit that generates a first current detection signal indicating a coil current flowing through an inductor of the boost DC / DC converter when the boost DC / DC converter is performing a switching operation, and a second current detection circuit that generates a second current detection signal indicating a current flowing through a PMOS transistor when the switching of the boost DC / DC converter is stopped. The pulse modulator may further include a second error amplifier that amplifies an error between an output signal of the first error amplifier and the first current detection signal, and generate a pulse signal having a duty cycle according to an output of the second error amplifier, and the load switch drive circuit may include a third error amplifier that amplifies an error between an output signal of the first error amplifier and the second current detection signal, and in the second mode, a drive voltage according to the output signal of the third error amplifier may be supplied to the gate of the PMOS transistor. By designing both the boost DC / DC converter and the linear regulator in a current mode, not only the first error amplifier but also the phase compensation circuit can be shared.

[0020] In one embodiment, the threshold voltage may be set in the range of 0.9 to 1.1 times the target level of the output voltage. More preferably, the threshold voltage may be set in the range of 0.95 to 1.05 times the target level of the output voltage.

[0021] In one embodiment, the threshold voltage may have hysteresis to prevent unstable operation due to switching between the first and second modes.

[0022] In one embodiment, both the upper and lower thresholds of the threshold voltage having hysteresis may be higher than the target level of the output voltage. Both the step-up DC / DC converter and the linear regulator cannot maintain the output voltage at the target level in a range (called a dead zone) where the difference between the input voltage and the target level of the output voltage is small. In this configuration, the first mode is operated in the dead zone, and the output voltage can be prevented from falling below the target level. This prevents the load from becoming inoperable.

[0023] In one embodiment, both the upper and lower thresholds of the hysteretic threshold voltage may be lower than the target level of the output voltage. In this configuration, the output voltage is prevented from exceeding the target level by operating in the second mode in the dead zone, thereby preventing an overvoltage from occurring when the input voltage suddenly increases.

[0024] In one embodiment, an upper threshold of the threshold voltage with hysteresis may be higher than a target level of the output voltage and a lower threshold of the threshold voltage may be lower than the target level of the output voltage.

[0025] In one embodiment, the control circuit may further include a first overcurrent protection circuit that limits the coil current flowing through the inductor so as not to exceed a first threshold current, and a second overcurrent protection circuit that limits the current flowing through the PMOS transistor in the second mode so as not to exceed a second threshold current. The load switch drive circuit may also be in the second mode when the duty cycle of the low-side control signal has decreased to a predetermined value and the load switch drive circuit is in an overcurrent state. In a situation in which the duty cycle has decreased to a predetermined value in an overcurrent state, if the load switch drive circuit continues to operate in the first mode, the overcurrent state will continue. By selecting the second mode in such a situation, the output current can be limited.

[0026] In one embodiment, the second threshold current may be lower than the first threshold current, which allows hysteresis between the first and second modes to be set for the resistive load, thereby suppressing oscillation.

[0027] In one embodiment, the load switch driver circuit may transition to the first mode when, in the second mode, the input voltage is lower than the threshold voltage and there is no overcurrent state.

[0028] In one embodiment, the load switch driver circuit may apply, in the first mode, to the gate of the PMOS transistor, an on-voltage that is lower than the source voltage of the PMOS transistor by a predetermined voltage step.

[0029] In one embodiment, the load switch driver circuit may enter the third mode when stopping the step-up DC / DC converter, and may apply a voltage according to the input voltage of the step-up DC / DC converter to the gate of the PMOS transistor.

[0030] With this configuration, when the step-up DC / DC converter is stopped, the load switch (PMOS transistor) is not immediately turned off, but a voltage Vc according to the input voltage is applied to the gate of the PMOS transistor, so that the PMOS transistor can operate as a source follower circuit (grounded drain circuit). At this time, the source voltage of the PMOS transistor, i.e., the voltage V at the connection node between the load switch and the high-side transistor, MID teeth, V MID =Vc+V GS ≒V IN +V GS This clamps the voltage V at the node (switching pin) between the high-side transistor and the low-side transistor, preventing overvoltage. SW teeth, V SW =V MID +V F =Vc+V GS +V F ≒V IN +V GS +V F This also suppresses overvoltage on the switching pin. V F is the forward voltage of the body diode of the high-side transistor. Also, the voltage across the inductor, V L teeth, V L =V IN -V SW =V IN -(Vc+V GS +V F)≒-(V GS +V F ) This reduces the coil current to -(V GS +V F ) / L over time.

[0031] In one embodiment, the load switch driver may connect the gate of the PMOS transistor to the input pin when the step-up DC / DC converter is stopped. This allows the input voltage V IN can be applied.

[0032] In one embodiment, the control circuit may further include a high-side transistor, a low-side transistor, and a PMOS transistor. The high-side transistor, the low-side transistor, and the PMOS transistor may be external discrete elements.

[0033] In one embodiment, a pin may not be provided at the connection node between the high-side transistor and the PMOS transistor. MID Since the PMOS transistor of the load switch can be used to clamp the voltage, a circuit element for suppressing the jump of the connection node is not required, and therefore a pin for connecting the circuit element is not required.

[0034] In one embodiment, the control circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors and capacitors for adjusting the circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0035] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are not intended to limit the invention, but are merely examples, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0036] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0037] Similarly, "a state in which component C is provided between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0038] Furthermore, "signal A (voltage, current) corresponds to signal B (voltage, current)" means that signal A has a correlation with signal B, specifically meaning (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof. Those skilled in the art will understand that the scope of "corresponding to" is determined according to the types and applications of signals A and B.

[0039] The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification have been appropriately enlarged or reduced to facilitate understanding, and each waveform shown has been simplified or exaggerated or emphasized to facilitate understanding.

[0040] (Embodiment 1) 1 is a circuit diagram of a step-up DC / DC converter 100C according to the first embodiment. The step-up DC / DC converter (hereinafter simply referred to as a DC / DC converter) 100C receives an input voltage V IN The output voltage is boosted and stabilized to a predetermined voltage level, and then supplied to a load (not shown) connected to an output terminal (output line) 104 .

[0041] The DC / DC converter 100C includes a main circuit 110C and a control circuit 200C. The main circuit 110C includes an inductor L1, a low-side transistor (switching transistor) M1, a high-side transistor (synchronous rectification transistor) M2, an output capacitor C1, and a load switch SW1.

[0042] The control circuit 200C is a functional IC integrated on one semiconductor substrate (die). In this embodiment, the low-side transistor M1, the high-side transistor M2, and the PMOS transistor M3 are integrated in the control circuit 200C. The PMOS transistor M3 is provided as a load switch SW1.

[0043] The control circuit 200C includes a low-side transistor M1, a high-side transistor M2, and a PMOS transistor M3, as well as a pulse modulator 210, a logic circuit 220, a high-side driver 230, a low-side driver 232, a load switch drive circuit 270, a voltage monitoring circuit 280, and resistors R11 and R12.

[0044] The control circuit 200C is provided with a switching pin SW, a ground pin PGND, an input pin VIN, an output pin VOUT, and a sense pin VOUT_SNS.

[0045] An external inductor L1 is connected to the switching pin SW. An output capacitor C1 is connected to the output pin VOUT. A low-side transistor M1 is connected between the switching pin SW and a ground pin PGND. A high-side transistor M2 and a PMOS transistor M3 are directly connected between the switching pin SW and the output pin VOUT. An input pin VIN is connected to the input voltage V IN is supplied.

[0046] The DC / DC converter 100C is a constant voltage output converter, and the pulse modulator 210 controls the output voltage V OUT Target level V OUT(REF) A pulse signal Sp is generated that is pulse modulated so as to approach

[0047] The sense pin VOUT_SNS detects the output voltage V OUT is fed back. The output voltage V OUT is divided by resistors R11 and R12, and the output voltage V OUT The feedback signal V FB The pulse modulator 210 includes a first error amplifier 212 and a pulse generator 213. The first error amplifier 212 generates a feedback signal V FB and the reference voltage V REF The pulse generator 213 amplifies the error of the output signal V ERR1 A pulse signal Sp is generated which is pulse modulated in response to the

[0048] Output voltage V OUT Target level V OUT(REF) is expressed by the following formula: V OUT(REF) =V REF ×(R11+R12) / R12

[0049] There are no particular limitations on the configuration or control method of pulse modulator 210. For example, pulse modulator 210 may be a voltage mode controller, or a peak current mode or average current mode controller. Alternatively, pulse modulator 210 may be a ripple control controller, specifically, hysteresis control (Bang-Bang control), bottom detection fixed on-time control, or peak detection fixed off-time control.

[0050] The modulation method of the pulse modulator 210 is also not particularly limited, and may be pulse width modulation, pulse frequency modulation, or another modulation method.

[0051] The logic circuit 220 generates a high-side control signal HGCTL and a low-side control signal LGCTL based on the pulse signal Sp, and also generates a control signal SWCTL for the PMOS transistor M3.

[0052] The high-side driver 230 drives the high-side transistor M2 based on a high-side control signal HGCTL. The low-side driver 232 drives the low-side transistor M1 based on a low-side control signal LGCTL.

[0053] The load switch driving circuit 270 drives the PMOS transistor M3, which is the load switch SW1, based on the control signal SWCTL. Specifically, when the control signal SWCTL is at an on level (e.g., high), the PMOS transistor M3 is turned on, and when the control signal SWCTL is at an off level (e.g., low), the PMOS transistor M3 is turned off.

[0054] The load switch driving circuit 270 is configured to be able to switch between two modes while the control signal SWCTL is at the on level (high). The load switch driving circuit 270 receives a control signal MODE that specifies the mode.

[0055] The input pin VIN of the control circuit 200C is connected to the input line 102 and receives the input voltage V IN The voltage monitoring circuit 280 detects the input voltage V IN is the threshold voltage V TH and generates a comparison signal VINCOMP according to the comparison result. IN >V TH It is assumed that VINCOMP is high when the voltage monitoring circuit 280 is a voltage comparator.

[0056] The logic circuit 220 receives the comparison signal VINCOMP and calculates the input voltage V IN is a given threshold voltage V TH If the input voltage V IN is the threshold voltage V TH If the threshold voltage V is higher than the threshold voltage V, the load switch driver circuit 270 is in the second mode. TH is the output voltage V OUT Target level V OUT(REF) It is advisable to set it in the vicinity of

[0057] In the first mode, the load switch driver 270 turns on the PMOS transistor M3. For example, the load switch driver 270 turns on the source voltage V MID The voltage Vgs of the PMOS transistor M3 is set to a value lower than the threshold voltage Vgs of the PMOS transistor M3 by a predetermined voltage step ΔV. (th) Greater than.

[0058] In the second mode, the load switch driver 270 outputs the output signal V ERR1 Drive voltage V according to G to the gate of the PMOS transistor M3.

[0059] The above is the configuration of the control circuit 200C. Next, the operation of the control circuit 200C will be described with reference to FIG. 2, which is a diagram illustrating the operation of the DC / DC converter 100C of FIG.

[0060] Before time t0, the input voltage V IN is the threshold value V TH (Here, the target output voltage level V OUT(REF) ), and the comparison signal VINCOMP is low. The DC / DC converter 100C is performing a switching operation as a boost converter, the load switch driver circuit 270 is in the first mode, and the PMOS transistor M3 is fully on.

[0061] The DC / DC converter 100C performs switching based on the pulse signal Sp to generate an output voltage V OUT Target level V IN It has been stabilized to.

[0062] After time t0, the input voltage V IN When the input voltage V starts to rise, the duty cycle of the pulse signal Sp becomes smaller. Then, at time t1, IN Target level V OUT(REF) When the voltage drops to , switching stops. Also, the comparison signal VINCOMP goes high, and the load switch driver circuit 270 switches to the second mode.

[0063] When the load switch driving circuit 270 is in the second mode, the PMOS transistor M3, the first error amplifier 212, and the load switch driving circuit 270 form a linear regulator (LDO: Low Drop Output), and the feedback signal V FB is the reference voltage V REF As a result, the output voltage V OUT is the target level V OUT(REF) is stabilized to.

[0064] The above is the operation of the DC / DC converter 100C. According to the control circuit 200C, the input voltage V INcontinues to rise, the output voltage V OUT is the target level V OUT(REF) Since the load is stabilized, an overvoltage can be prevented from being supplied to the load.

[0065] If two error amplifiers are provided separately for the DC / DC converter and the linear regulator, the circuit area will be large. Furthermore, if the offset voltages of the two error amplifiers are different, it will be difficult to make the target level of the output voltage of the DC / DC converter and the target level of the output voltage of the linear regulator completely the same. In this embodiment, the first error amplifier 212 of the pulse modulator 210 is also used as the error amplifier of the linear regulator. Therefore, the target level of the output voltage of the DC / DC converter and the target level of the output voltage of the linear regulator can be made the same.

[0066] Next, the threshold voltage V TH The input voltage V IN is the threshold voltage V TH If the threshold voltage V TH It is desirable to add hysteresis to the

[0067] Figure 3 shows the input / output characteristics of a step-up DC / DC converter and a linear regulator. Since the step-up DC / DC converter cannot operate in a region narrower than the minimum duty cycle, the output voltage V OUT(BOOST) The minimum level of the input voltage V IN It is higher than V by ΔV1. IN ~V IN It is not possible to output a voltage in the range of +ΔV1.

[0068] On the other hand, the on-resistance of the PMOS transistor M3 is not zero, so the linear regulator’s output voltage V OUT(LDO) The highest level of the input voltage V IN This means that the linear regulator is IN ~V INIt is not possible to output a voltage in the range of -ΔV2.

[0069] Therefore, regardless of whether the first mode or the second mode is selected, the DC / DC converter 100C IN -ΔV2~V IN In the range of +ΔV1, the output voltage V OUT Target level V OUT(REF) This is called the dead zone.

[0070] Threshold voltage V TH When providing hysteresis to the upper threshold V THH and the lower threshold V THL Both are at target level V OUT(REF) FIG. 4 shows the output voltage V OUT In this case, since the converter operates as a boost DC / DC converter in the dead zone, the output voltage V OUT is the target voltage V OUT(REF) This control ensures that the output voltage V OUT This is effective when you do not want to undershoot.

[0071] Threshold voltage V TH When providing hysteresis to the upper threshold V THH and the lower threshold V THL Both are at target level V OUT(REF) FIG. 5 shows the output voltage V OUT In this case, since the regulator operates as a linear regulator in the dead zone, the output voltage V OUT is the target voltage V OUT(REF) This control is performed by the output voltage V OUT This is effective when you do not want to overshoot.

[0072] Threshold voltage V TH When providing hysteresis to the upper threshold V THH and the lower threshold V THL, target level V OUT(REF) 6 shows the output voltage V of the DC / DC converter 100C. OUT In this case, in the dead zone, the regulator operates as a linear regulator and a step-up DC / DC converter. This control is effective when it is desired to reduce both the amount of overshoot and the amount of undershoot.

[0073] In addition, the threshold voltage V TH is the target level V OUT(REF) The closer it is to V, the smaller the amount of overshoot and undershoot can be. OUT(REF) ×0.9 <V TH <V OUT(REF) × 1.1, and more preferably, V OUT(REF) ×0.95 <V TH <V OUT(REF) The threshold voltage V TH Target level V OUT(REF) The closer to the output voltage V OUT Fluctuations in the temperature can be suppressed.

[0074] For example, in Figure 4, V THH = 1.03, V THL In the case of Figure 5, V THH =0.98, V THL In the case of Figure 6, V THH = 1.01, V THL = 0.99.

[0075] Next, a specific configuration example of the control circuit 200C will be described.

[0076] 7 is a circuit diagram of an example of a control circuit 200C of a DC / DC converter. The pulse modulator 210 is a current-mode pulse width modulator. The first current detection circuit 260 detects the coil current I L The first current detection signal V CS(BOOST)The first current detection signal V CS(BOOST) may be based on the current flowing through the low-side transistor M1 or the current flowing through the high-side transistor M2. Alternatively, the first current detection circuit 260 may detect the coil current I L may be detected directly.

[0077] The pulse generator 213 receives the current detection signal V CS(BOOST) The output signal V of the first error amplifier 212 is used as the target value (current command signal) of ERR1 The pulse generator 213 includes a second error amplifier 214 and a PWM (Pulse Width Modulation) comparator 216. The second error amplifier 214 receives a current command signal V ERR1 and the current detection signal V CS(BOOST) The PWM comparator 216 amplifies the error of the output signal V ERR2 is compared with a ramp wave or sawtooth wave periodic signal RAMP to generate a pulse signal Sp.

[0078] 7, the linear regulator formed by the PMOS transistor M3, the first error amplifier 212, and the load switch driver circuit 270 is configured as a current mode. OUT(LDO) A second current detection signal V CS(LDO) Generate.

[0079] The load switch driving circuit 270 includes a voltage source 272 , a selector 274 , and a third error amplifier 276 .

[0080] The third error amplifier 276 receives the current command signal V ERR1 and the second current detection signal V CS(LDO) In the second mode, the load switch driver 270 amplifies the error of the output signal V ERR3to the gate of the PMOS transistor M3. Specifically, in the second mode, the selector 274 connects the output node of the third error amplifier 276 to the gate of the PMOS transistor M3.

[0081] In the first mode, the voltage source 272 generates a gate voltage for turning on the PMOS transistor M3. Specifically, the voltage source 272 generates a source voltage V MID is level-shifted to the source voltage V MID A voltage that is lower by a certain voltage width ΔV than MID -ΔV) In the first mode, the selector 274 selects the output voltage of the voltage source 272 and supplies it to the gate of the PMOS transistor M3.

[0082] The load switch driving circuit 270 is in the third mode when the DC / DC converter 100C is stopped. In the third mode, the load switch driving circuit 270 applies the input voltage V IN Apply a voltage Vc according to the input voltage V IN "Depends on the voltage Vc" means that the voltage Vc is IN This includes the fact that the voltage Vc is generated using the input voltage V IN Not only when the voltage Vc is equal to the input voltage V IN When the voltage Vc is a positive or negative level shifted voltage, or when the voltage Vc is a IN In this embodiment, the voltage Vc may be a voltage obtained by multiplying the input voltage V IN In the third mode, the selector 274 connects the gate of the PMOS transistor M3 to the input pin VIN.

[0083] The state of the selector 274 is controlled according to the switch control signal SWCNT and the comparison signal VINCOMP. When the switch control signal SWCNT is high (on level) and the comparison signal VINCOMP is at a first level (low), the selector 274 selects the voltage V MIDWhen the switch control signal SWCNT is high (on level) and the comparison signal VINCOMP is at the second level (high), the selector 274 selects the voltage V ERR3 (second mode). When the switch control signal SWCNT is low (off level), the selector 274 selects the voltage Vc=V IN (3rd mode).

[0084] The above is the configuration of the control circuit 200C. The advantages of this control circuit 200C will now be described.

[0085] In this configuration example, both the step-up DC / DC converter and the linear regulator operate in a current mode. The first error amplifier 212 can be shared, and the phase compensation circuit connected to the first error amplifier 212 (the CR circuit connected to the output of the first error amplifier 212) also serves as a phase compensation circuit when the linear regulator operates. In other words, there is an advantage in that it is no longer necessary to design separate phase compensation circuits for the step-up DC / DC converter and the linear regulator.

[0086] Next, the advantages of the third mode will be described. When an event occurs that stops the output of the DC / DC converter 100C, the logic circuit 220 sets the switch control signal SWCTL to low. Figure 8 is an equivalent circuit diagram of the DC / DC converter 100C immediately after the switch control signal SWCTL transitions to low.

[0087] The load switch driver 270 applies an input voltage V IN At this time, the PMOS transistor M3 does not immediately turn off, but operates as a source follower circuit. As a result, the source voltage of the PMOS transistor M3, i.e., the voltage V at the connection node between the load switch SW1 and the high-side transistor M2, MID teeth, V MID =Vc+V GS This clamps the input voltage to prevent overvoltage from occurring.

[0088] At this time, the voltage V of the switching pin SW, which is the connection node between the high-side transistor M2 and the low-side transistor M1, SW teeth, V SW =V MID +V F =Vc+V GS +V F ≒V IN +V GS +V F This also suppresses overvoltage on the switching pin SW.

[0089] At this time, the voltage across the inductor V L teeth, V L =V IN -V SW =V IN -(Vc+V GS +V F ) As mentioned above, Vc ≒ V IN If we define it as: V L ≒-(V GS +V F ) This results in the coil current I L , -(V GS +V F ) / L. Then, the coil current I L becomes zero.

[0090] FIG. 9 is a waveform diagram (actual measurement) of the DC / DC converter 100C in FIG. 7. In FIG. 9, the voltages V of the switching pin SW, the input pin VIN, and the output pin VOUT are shown. SW ,V IN ,V OUT and the coil current I L Before time t0, the DC / DC converter 100C is performing a switching operation, and the output voltage V OUT is the target level V OUT(REF) It has been stabilized to.

[0091] When an event that triggers a shutdown is detected at time t0, the gate voltage V HG ,V LG becomes low level, and the voltage Vc=V IN As a result, the switching voltage V SW is V IN +V GS +V F In this section, the coil current I L is -(V GS +V F The current Ic decreases at a slope (A / s) of A / L and reaches zero at time t1. After time t1, the output of the DC / DC converter 100C stops.

[0092] The above is the operation of the DC / DC converter 100C. The advantages of the DC / DC converter 100C become clear when compared with comparative technique 1. Fig. 10 is a circuit diagram of a DC / DC converter 100R according to comparative technique 1. Comparative technique 1 and the configuration in Fig. 7 differ in the voltage applied to the gate of the PMOS transistor M3 when stopping the DC / DC converter 100R. In comparative technique 1, in order to immediately turn off the PMOS transistor M3, a source voltage V MID The same voltage is applied.

[0093] In the comparative technology 1, the PMOS transistor M3 is turned off instantly, so the coil current I L The path of the coil current I L continues to flow toward the source of the PMOS transistor M3. The source voltage V MID This can increase the source voltage V MID As the switching voltage V SW In order to suppress the overvoltage, it is necessary to provide a pin VMID at the source of the PMOS transistor M3 and connect a capacitor C2 to the pin VMID.

[0094] On the other hand, according to the configuration of FIG. 7, the source voltage V MID is clamped, making overvoltage less likely to occur and improving reliability.

[0095] Furthermore, in the configuration of Figure 7, since the overvoltage of the source voltage of the PMOS transistor M3 is suppressed, measures to suppress the overvoltage are not required. In other words, it is not necessary to provide a pin VMID and connect a capacitor C2 to the source of the PMOS transistor M3. This is advantageous in terms of cost compared to the comparative technology 1.

[0096] Next, a modification of the configuration in FIG. 7 will be described.

[0097] (Variation 1.1) In Fig. 7, both the step-up DC / DC converter and the linear regulator are configured in current mode, but this is not limited to this and both may be configured in voltage mode. In this case, it is necessary to design separate phase compensation circuits for the step-up DC / DC converter and the linear regulator.

[0098] (Variation 1.2) The step-up DC / DC converter may be designed in the current mode and the linear regulator in the voltage mode. In that case, the third error amplifier 276 may be omitted and the output signal V of the first error amplifier 212 may be used. ERR1 Alternatively, the output signal V of the first error amplifier 212 may be input to the gate of the PMOS transistor M3. ERR1 A driver circuit and a level shifter that drives the gate of the PMOS transistor M3 may be added based on this. In this case, too, it is necessary to design phase compensation circuits separately for the step-up DC / DC converter and the linear regulator.

[0099] (Variation 1.3) In FIG. 7, in the third mode, the gate of the PMOS transistor M3 is supplied with the input voltage V INHowever, in the third mode, the gate-source voltage of the PMOS transistor M3 may be set to zero, as in Comparative Technology 1. In that case, measures against overvoltage can be taken by adding a pin to the source of the PMOS transistor M3 and attaching an external capacitor, for example.

[0100] (Embodiment 2) 11 is a block diagram of a DC / DC converter 100D according to a second embodiment. In the second embodiment, similarly to the first embodiment, the input voltage V IN is the threshold voltage V TH In addition to exceeding the threshold voltage, in an overcurrent condition, the second mode is selected.

[0101] The control circuit 200D includes a first overcurrent protection circuit 290 and a second overcurrent protection circuit 292 in addition to the components of the control circuit 200C in FIG.

[0102] The first overcurrent protection circuit 290 is configured to protect the inductor L1 from the coil current I L The first threshold current I OCP1 The first overcurrent protection circuit 290 limits the coil current I L The average current of the coil current I L The first overcurrent protection circuit 290 may monitor the peak of the coil current I L When the first threshold current is reached, the logic circuit 220 asserts the overcurrent protection signal OCP1. In response to the assertion of the overcurrent protection signal OCP1, the logic circuit 220 immediately turns off the low-side transistor M1.

[0103] The second overcurrent protection circuit 292 prevents a current I flowing through the PMOS transistor M3 when the DC / DC converter 100D operates as a linear regulator. OUT(LDO) The second threshold current I OCP2For example, the second overcurrent protection circuit 292 limits the output current I OUT(LDO) exceeds the threshold current, the gate-source voltage of the PMOS transistor M3 is reduced. The overcurrent protection characteristic of the second overcurrent protection circuit 292 may be a so-called drooping characteristic or a foldback characteristic.

[0104] In the second embodiment, the load switch driving circuit 270 is IN In addition to when the duty cycle (pulse width) of the pulse signal Sp exceeds the threshold, the second mode is also operated in the following cases. Specifically, the second mode is also entered when the duty cycle of the pulse signal Sp has dropped to a predetermined value and an overcurrent state is present. The logic circuit 220 can determine whether or not an overcurrent state exists by monitoring the overcurrent protection signal OCP1. Then, when the duty cycle (pulse width) of the low-side control signal LGCTL has dropped to the minimum duty cycle (minimum pulse width) in an overcurrent state, the second mode is selected.

[0105] The above is the configuration of the control circuit 200C.

[0106] Next, we will explain overcurrent protection in a boost DC / DC converter. Figure 12 is a diagram showing the current-voltage (IV) characteristics of a boost DC / DC converter. If an overcurrent state occurs while the boost DC / DC converter is performing switching operation, the pulse width (duty cycle) of the low-side control signal LGCTL becomes smaller due to pulse-by-pulse overcurrent protection. As a result, the coil current I L decreases, and the output voltage V OUT However, the control circuit 200D has a minimum pulse width that can be generated as the low-side control signal LGCTL, and cannot output a low-side control signal LGCTL narrower than that. OUT is the input voltage V IN In the event that the output line 104 is shorted to ground, V OUT <V INIn this case, the current limit is not applied and the overcurrent continues to flow.

[0107] 13 is a diagram illustrating overcurrent protection of the DC / DC converter 100D according to the second embodiment. When overcurrent protection is activated during operation of the step-up DC / DC converter, the output voltage V OUT is the input voltage V IN The voltage level of the low-side control signal LGCTL drops to a voltage level slightly higher than the minimum duty cycle. In this state, the duty cycle of the low-side control signal LGCTL becomes a minimum value, and the minimum duty cycle operation is performed. When the logic circuit 220 detects the minimum duty cycle, it switches the load switch driver circuit 270 to the second mode. This causes the DC / DC converter 100D to start operating as a linear regulator. When operating as a linear regulator, the second overcurrent protection circuit 292 provides overcurrent protection, so that the output current I OUT(LDO) The threshold current I OCP2 While keeping the output voltage V OUT can be reduced.

[0108] Here, the second threshold current I OCP2 The first threshold current I OCP1 This allows you to set the hysteresis for the first and second modes for the resistive load, thereby suppressing oscillation.

[0109] FIG. 14 is a state transition diagram of a DC / DC converter 100D according to the second embodiment. In the first mode, V IN >V THH When the duty cycle DUTY of the low-side control signal LGCTL is at the minimum value MIN and the device is in an overcurrent state (OCP1 is asserted), the device transitions to the second mode.

[0110] In the second mode, V IN <V THL And when the overcurrent state is cleared (OCP2 is negated), the device transitions to the first mode.

[0111] (Embodiment 3) In the second embodiment, the input voltage V IN In contrast, in the third embodiment, the mode transition was performed based on the input voltage V IN The mode transition is not performed based on the current limit, but only in an overcurrent state.

[0112] 15 is a state transition diagram of the DC / DC converter according to embodiment 3. In the first mode, when the duty cycle DUTY of the low-side control signal LGCTL is at the minimum value MIN and in an overcurrent state (OCP1 is asserted), the mode transitions to the second mode.

[0113] In the second mode, when the overcurrent state is cleared (OCP2 is negated), the mode transitions to the first mode.

[0114] In the third embodiment, the input voltage V IN The output voltage V OUT Target level V OUT(REF) It is useful for applications and platforms not exceeding

[0115] (Modification) The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step. Such modifications will be described below.

[0116] In relation to the first to third embodiments, the low-side transistor M1 and the high-side transistor M2 may be externally connected as discrete elements.

[0117] In relation to the first to third embodiments, the PMOS transistor M3 may be externally attached as a discrete element. In this case, a part or the whole of the load switch driving circuit 270 may be configured as a discrete element outside the IC of the control circuit 200C.

[0118] Furthermore, in relation to the second and third embodiments, the first overcurrent protection circuit 290 may detect the current flowing through the inductor L1 or the current flowing through the high-side transistor M2, and the second overcurrent protection circuit 292 may detect the coil current flowing through the inductor L1.

[0119] (Application) Next, applications of the DC / DC converters 100C and 100B (hereinafter simply referred to as 100) will be described.

[0120] 16 is a diagram showing an example of an electronic device 700 including a DC / DC converter 100 according to an embodiment. The electronic device 700 is a battery-driven device such as a mobile phone terminal, a digital camera, a digital video camera, a tablet terminal, or a portable audio player. The electronic device 700 includes a housing 702, a battery 704, a microprocessor 706, and a DC / DC converter 100. The DC / DC converter 100 receives a battery voltage V from a battery 704 at its input terminal. BAT (=V IN ) and the output voltage V OUT supplies.

[0121] The type of electronic device 700 is not limited to a battery-powered device, but may be an in-vehicle device, an office automation device such as a facsimile, or an industrial device.

[0122] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and may constitute the scope of the present invention. [Explanation of symbols]

[0123] 100C, 100D DC / DC Converter 102 input lines 104 Output Line 110C,110C main circuit 200C, 200D Control circuit 210 Pulse Modulator 212 First error amplifier 214 Second Error Amplifier 213 Pulse Generator 216 PWM Comparator 220 Logic Circuit 230 High Side Driver 232 Low Side Driver 260 First current detection circuit 262 Second current detection circuit 270 Load switch driver circuit 272 Voltage Source 274 Selector 276 3rd Error Amplifier 280 Voltage Monitoring Circuit 290 1st overcurrent protection circuit 292 2nd overcurrent protection circuit SW1 Load switch M1 Low-side transistor M2 High-side transistor M3 PMOS transistor

Claims

1. A control circuit for a step-up DC / DC converter having a high-side transistor and a low-side transistor, a pulse modulator including a first error amplifier for amplifying an error between a feedback signal corresponding to an output voltage of the step-up DC / DC converter and a reference voltage, the pulse modulator generating a pulse signal that is pulse-modulated according to an output signal of the first error amplifier; a logic circuit that generates a high-side control signal and a low-side control signal based on the pulse signal; a load switch driver circuit for driving a load switch, which is a PMOS transistor connected between the high-side transistor and a load; Equipped with the load switch drive circuit is a control circuit configured to be switchable between (i) a first mode in which the PMOS transistor is fully on, and (ii) a second mode in which a drive voltage corresponding to the output signal of the first error amplifier is supplied to a gate of the PMOS transistor.

2. 2. The control circuit according to claim 1, wherein the load switch drive circuit (i) enters the first mode when an input voltage of the step-up DC / DC converter is lower than a predetermined threshold voltage, and (ii) enters the second mode when the input voltage is higher than the threshold voltage.

3. a first current detection circuit that generates a first current detection signal indicating a coil current flowing through an inductor of the step-up DC / DC converter when the step-up DC / DC converter is performing a switching operation; a second current detection circuit that generates a second current detection signal indicative of a current flowing through the PMOS transistor when switching of the step-up DC / DC converter is stopped; Further equipped with the pulse modulator further includes a second error amplifier that amplifies an error between the output signal of the first error amplifier and the first current detection signal, and generates the pulse signal having a duty cycle according to an output of the second error amplifier; The load switch driving circuit includes:

3. The control circuit according to claim 1, further comprising a third error amplifier that amplifies an error between the output signal of the first error amplifier and the second current detection signal, and in the second mode, the control circuit supplies the drive voltage according to the output signal of the third error amplifier to the gate of the PMOS transistor.

4. 3. The control circuit of claim 2, wherein the threshold voltage is set in the range of 0.9 to 1.1 times a target level of the output voltage.

5. The control circuit of claim 4 , wherein the threshold voltage has hysteresis.

6. 6. The control circuit of claim 5, wherein both upper and lower thresholds of the threshold voltage with hysteresis are lower than the target level of the output voltage.

7. 6. The control circuit of claim 5, wherein both upper and lower thresholds of the threshold voltage with hysteresis are higher than the target level of the output voltage.

8. 6. The control circuit of claim 5, wherein an upper threshold of the threshold voltage with hysteresis is higher than the target level of the output voltage and a lower threshold of the threshold voltage is lower than the target level of the output voltage.

9. a first overcurrent protection circuit that limits a coil current flowing through the inductor so as not to exceed a first threshold current; a second overcurrent protection circuit that limits the current flowing through the PMOS transistor in the second mode so as not to exceed a second threshold current; Further equipped with 8. The control circuit of claim 1, wherein the load switch driver circuit is in the second mode when a duty cycle of the low side control signal is reduced to a minimum value and an overcurrent condition exists.

10. The control circuit of claim 9 , wherein the second threshold current is lower than the first threshold current.

11. the load switch drive circuit (i) goes into the first mode when an input voltage of the step-up DC / DC converter is lower than a predetermined threshold voltage, and (ii) goes into the second mode when the input voltage is higher than the threshold voltage; 11. The control circuit according to claim 9, wherein the load switch drive circuit transitions to the first mode when, in the second mode, the input voltage is lower than the threshold voltage and there is no overcurrent state.

12. 12. The control circuit according to claim 1, wherein in the first mode, the load switch drive circuit applies, to the gate of the PMOS transistor, an on-voltage that is lower by a predetermined voltage step than a source voltage of the PMOS transistor.

13. 13. The control circuit according to claim 1, wherein the load switch drive circuit is in a third mode when the step-up DC / DC converter is stopped, and applies a voltage according to an input voltage of the step-up DC / DC converter to a gate of the PMOS transistor.

14. 14. The control circuit according to claim 1, which is monolithically integrated on a single semiconductor substrate.

15. A main circuit of a DC / DC converter; A control circuit according to any one of claims 1 to 14; A power supply circuit comprising:

16. An electronic device comprising a control circuit according to any one of claims 1 to 14.

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