Display Panel

Abstract

The present invention discloses a display panel including a power supply line, a group of light-emitting lamps, a partition passage wiring, a driving chip, and a ground signal wiring, the driving chip, the group of light-emitting lamps, and the partition passage wiring being arranged between a power supply line and a ground signal wiring arranged at intervals, the driving chip being connected to the ground signal wiring, the group of light-emitting lamps being connected to the power supply line, the partition passage wiring connecting the group of light-emitting lamps and the driving chip, and the power supply line, the ground signal wiring, and the partition passage wiring being arranged on the same layer.

Description

[Technical field]

[0001] The present invention relates to the technical field of displays, and in particular to display panels. [Background technology]

[0002] Mini Light Emitting Diode (Mini LED), also known as "sub-millimeter light emitting diode", refers to a display screen made of LEDs with particle (chip) sizes of 50μm to 200μm, and is located between Micro LED and small pitch LED displays. It is widely used in Mini LED direct displays and Mini LED backlight displays.

[0003] In conventional products, the metal wiring method is a two-layer or more metal wiring method, for example, ground wiring, partition passage wiring, power wiring, etc. are provided on different layers. This wiring method is prone to shorts between different metal layers, i.e., short circuits, and causes problems such as high costs. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiment of the present invention provides a display panel for solving the problem that a short circuit occurs easily when a ground line, a partition passage line and a power line are provided in two or more layers in the prior art. [Means for solving the problem]

[0005] The present invention relates to A power line, a ground signal line that is spaced apart from the power supply line and that is arranged along a first direction together with the power supply line; a driver chip provided between the power supply line and the ground signal wiring and connected to the ground signal wiring; a group of light-emitting lamps provided between the ground signal wiring and the power supply line, one end of the group of light-emitting lamps being connected to the power supply line; a partition passage wiring provided between the power supply line and the ground signal wiring, the partition passage wiring connecting the other end of the light-emitting lamp group and the driving chip; The power supply lines, the partition passage lines and the ground signal lines are provided on the same layer of the display panel.

[0006] If desired, in some embodiments of the present invention, the light-emitting lamp group includes a plurality of groups, the plurality of light-emitting lamp groups are arranged along the first direction, the plurality of partition passage wirings include a plurality of data selection pins are provided on the driving chip, the plurality of data selection pins are arranged along the first direction and / or a second direction intersecting the first direction, and each of the data selection pins is connected to the light-emitting lamp group via the partition passage wiring.

[0007] Optionally, in some embodiments of the present invention, the light-emitting lamp group includes a first light-emitting lamp group and a second light-emitting lamp group, the driving chip includes a first data selection pin and a second data selection pin, and the partition passage wiring includes a first partition passage wiring and a second partition passage wiring; The first light-emitting lamp group and the second light-emitting lamp group are arranged along the first direction, the first data selection pins and the second data selection pins are arranged along the first direction, The first light-emitting lamp group and the first data selection pin are connected via the first division passage wiring, and the second light-emitting lamp group are connected to the second data selection pin via the second division passage wiring.

[0008] Optionally, in some embodiments of the present invention, the light-emitting lamp group further includes a third light-emitting lamp group and a fourth light-emitting lamp group, the driving chip further includes a third data selection pin and a fourth data selection pin, and the partition passage wiring further includes a third partition passage wiring and a fourth partition passage wiring; the first light-emitting lamp group, the second light-emitting lamp group, the third light-emitting lamp group, and the fourth light-emitting lamp group are arranged along the first direction, the first data selection pin and the third data selection pin are arranged in a line along a second direction, and the first data selection pin is located on a side of the third data selection pin closer to the power line; the second data selection pin and the fourth data selection pin are arranged in another row along a second direction, and the second data selection pin is located on a side of the fourth data selection pin that is closer to the power line; The third light-emitting lamp group and the third data selection pin are connected via the third division passage wiring, and the fourth light-emitting lamp group is connected to the fourth data selection pin via the fourth division passage wiring.

[0009] Optionally, in some embodiments of the present invention, the driver chip includes a first portion and a second portion connected to the first portion, the first portion being located at an end of the driver chip close to the power line, the first data selection pin, the second data selection pin, the third data selection pin and the fourth data selection pin being located in the first portion, the driver chip including a ground signal pin connected to the ground signal wiring, the ground signal pin being provided in the second portion.

[0010] Optionally, in some embodiments of the present invention, the driving chip is provided with two power supply signal pins, the two power supply signal pins being arranged in the second portion along the first direction, and the display panel includes a driving chip power wiring arranged between adjacent driving chips for connecting the power supply signal pins of the driving chips.

[0011] Optionally, in some embodiments of the present invention, the driving chip is provided with a staging signal input pin and a staging signal output pin, the staging signal input pin and the staging signal output pin are provided in the second portion along the first direction, and the display panel further includes a driving chip signal wiring provided between adjacent driving chips for connecting the staging signal input pin and the staging signal output pin of the adjacent driving chips.

[0012] Optionally, in some embodiments of the present invention, the driver chip is provided with at least one data signal pin, the data signal pin is provided in the second portion, and the display panel includes data transfer wiring connected to the data signal pin.

[0013] Optionally, in some embodiments of the present invention, the number of the data signal pins is one, one of the data signal pins and the ground signal pin are arranged along the first direction, and the data transfer wiring extends along the first direction and is located on a side of the data signal pin that is away from the ground signal wiring.

[0014] Thus, the present invention provides A power line, a ground signal line provided at a distance from the power supply line; a driver chip provided between the power supply line and the ground signal wiring and connected to the ground signal wiring; a group of light-emitting lamps provided between the ground signal wiring and the power supply line, one end of the group of light-emitting lamps being connected to the power supply line; a partition passage wiring provided between the power supply line and the ground signal wiring, the partition passage wiring connecting the other end of the light-emitting lamp group and the driving chip; The display panel further includes a display panel in which the power supply lines, the partition passage lines and the ground signal lines are provided on the same layer.

[0015] If desired, in some embodiments of the present invention, the light-emitting lamp group includes a plurality of groups, the plurality of light-emitting lamp groups are arranged along a first direction, the plurality of partition passage wirings include a plurality of data selection pins are provided on the driving chip, the plurality of data selection pins are arranged along the first direction and / or a second direction intersecting the first direction, and each of the data selection pins is connected to the light-emitting lamp group via the partition passage wiring.

[0016] Optionally, in some embodiments of the present invention, the light-emitting lamp group includes a first light-emitting lamp group and a second light-emitting lamp group, the driving chip includes a first data selection pin and a second data selection pin, and the partition passage wiring includes a first partition passage wiring and a second partition passage wiring; The first light-emitting lamp group and the second light-emitting lamp group are arranged along the first direction, the first data selection pins and the second data selection pins are arranged along the first direction, The first light-emitting lamp group and the first data selection pin are connected via the first division passage wiring, and the second light-emitting lamp group are connected to the second data selection pin via the second division passage wiring.

[0017] Optionally, in some embodiments of the present invention, the light-emitting lamp group further includes a third light-emitting lamp group and a fourth light-emitting lamp group, the driving chip further includes a third data selection pin and a fourth data selection pin, and the partition passage wiring further includes a third partition passage wiring and a fourth partition passage wiring; the first light-emitting lamp group, the second light-emitting lamp group, the third light-emitting lamp group, and the fourth light-emitting lamp group are arranged along the first direction, and the first light-emitting lamp group and the third light-emitting lamp group, and the second light-emitting lamp group and the fourth light-emitting lamp group are located on opposite sides of the driving chip; the first data selection pin and the third data selection pin are arranged in a line along a second direction, and the first data selection pin is located on a side of the third data selection pin closer to the power line; the second data selection pin and the fourth data selection pin are arranged in another row along a second direction, and the second data selection pin is located on a side of the fourth data selection pin that is closer to the power line; The third light-emitting lamp group and the third data selection pin are connected via the third division passage wiring, and the fourth light-emitting lamp group is connected to the fourth data selection pin via the fourth division passage wiring.

[0018] Optionally, in some embodiments of the present invention, the driver chip includes a first portion and a second portion connected to the first portion, the first portion being located at an end of the driver chip close to the power line, the first data selection pin, the second data selection pin, the third data selection pin and the fourth data selection pin being located in the first portion, the driver chip including a ground signal pin connected to the ground signal wiring, the ground signal pin being provided in the second portion.

[0019] Optionally, in some embodiments of the present invention, the driving chip is provided with two power signal pins, the two power signal pins being arranged in the second portion along the first direction, and the display panel includes a driving chip power wiring arranged between adjacent chips for connecting the power signal pins of the driving chips.

[0020] Optionally, in some embodiments of the present invention, the driving chip is provided with a staging signal input pin and a staging signal output pin, the staging signal input pin and the staging signal output pin are provided in the second portion along the first direction, and the display panel further includes a driving chip signal wiring provided between adjacent driving chips for connecting the staging signal input pin and the staging signal output pin of the adjacent driving chips.

[0021] Optionally, in some embodiments of the present invention, the driver chip is provided with at least one data signal pin, the data signal pin is provided in the second portion, and the display panel includes data transfer wiring connected to the data signal pin.

[0022] Optionally, in some embodiments of the present invention, the number of the data signal pins is one, one of the data signal pins and the ground signal pin are arranged along the first direction, and the data transfer wiring extends along the first direction and is located on a side of the data signal pin that is away from the ground signal wiring.

[0023] Optionally, in some embodiments of the present invention, the number of said data signal pins is two, and the two said data signal pins are provided along said first direction.

[0024] Optionally, in some embodiments of the present invention, the ground signal pin, the staging signal input pin and the staging signal output pin are located in the same column; or the ground signal pin and the data signal pin are located in the same column, or The ground signal pin and the power signal pin are located in the same row. Effect of the Invention

[0025] The present invention discloses a display panel including a power line, a group of light-emitting lamps, a driving chip, a partition passage wiring, and a ground signal wiring, the ground signal wiring is spaced apart from the power line, the driving chip is disposed between the power line and the ground signal wiring and connected to the ground signal wiring, the group of light-emitting lamps is disposed between the driving chip and the power line, one end of the group of light-emitting lamps is connected to the power line, the partition passage wiring is disposed between the power line and the ground signal wiring, and the other end of the group of light-emitting lamps is connected to the driving chip, and the power line, the partition passage wiring, and the ground signal wiring are disposed in the same layer. In the present invention, by disposing the power line, the partition passage wiring, and the ground signal wiring in the same layer, the power line, the partition passage wiring, and the ground signal wiring are disposed in different layers, thereby preventing the problem of short circuiting, and improving the characteristics of the display panel.

[0026] In order to more clearly describe the technical means in the embodiments of the present invention, the following briefly introduces the drawings that need to be used in the description of the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and those skilled in the art can also derive other drawings from these drawings without creative efforts. [Brief description of the drawings]

[0027] [Figure 1] 1 is a first schematic plan view of a display panel according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic plan view of a group of light-emitting lamps of a display panel according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a second schematic plan view of the display panel according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, the technical means in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, but it is clear that the described embodiments are not all of the embodiments of the present invention, but are merely some of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts are all within the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are for explaining and interpreting the present invention, and are not intended to limit the present invention. In the present invention, unless otherwise stated, the directional terms used, such as "upper" and "lower", usually mean the upper and lower sides in the state in which the device is actually used or in operation, specifically the drawing directions in the accompanying drawings, while "inner" and "outer" refer to the contour of the device. In the present invention, the "reaction" may be a chemical reaction or a physical reaction.

[0029] An embodiment of the present invention provides a display panel, the display panel includes a power line, a group of light-emitting lamps, a driving chip, a partition path wiring and a ground signal wiring, the ground signal wiring is parallel to and spaced apart from the power line, the driving chip is disposed between the power line and the ground signal wiring and connected to the ground signal wiring, the group of light-emitting lamps is disposed between the driving chip and the power line, one end of the group of light-emitting lamps is connected to the power line, the partition path wiring is disposed between the power line and the ground signal wiring, the other end of the group of light-emitting lamps is connected to the driving chip, and the power line, the partition path wiring and the ground signal wiring are disposed in the same layer.

[0030] In the present invention, by providing the power supply line, the partition passage wiring and the ground signal wiring in the same layer, the power supply line, the partition passage wiring and the ground signal wiring are provided in different layers, thereby preventing the problem of short circuiting, thereby improving the characteristics of the display panel.

[0031] The details will be explained below.

[0032] Please refer to FIG. 1, which is a first schematic plan view of a display panel according to an embodiment of the present invention. The display panel 10 includes a power line VLED, a light-emitting lamp group 100, a driving chip 200, a partition path wiring 300, and a ground signal wiring GND. The ground signal wiring GND is provided at a distance from the power line VLED. The driving chip 200 is provided between the power line VLED and the ground signal wiring GND, and is connected to the ground signal wiring GND. The light-emitting lamp group 100 is provided between the driving chip 200 and the power line VLED, and one end is connected to the power line VLED. The partition path wiring is provided between the power line VLED and the ground signal wiring GND, and connects the other end of the light-emitting lamp group 100 to the driving chip 200, and the power line VLED, the partition path wiring, and the ground signal wiring GND are provided in the same layer.

[0033] In one embodiment, the power supply line VLED is provided in parallel with the ground signal line GND.

[0034] The power line VLED is for inputting a power signal of an external driving element to the light-emitting lamp group 100. The ground signal wiring GND is a ground wiring. The partition path wiring 300 is for transferring a signal in the driving chip 200 to the light-emitting lamp group 100. The size of the driving chip 200 is less than 1500×1500 μm.

[0035] The light-emitting lamp group 100 is provided with LED lamps, and the number of LED lamps may be 1, 2, 4, 6, 8, 10, 12, 14, or 16, etc. There is no limitation on the distance between the LED lamps. The LED lamp may be a Mini LED lamp.

[0036] In one embodiment, the number of the light-emitting lamp groups 100 is multiple. The multiple light-emitting lamp groups 100 are arranged along a first direction Y. A multiple number of partition passage wirings 300 are included. There are a multiple number of driving chips 200. The multiple driving chips 200 are arranged along the first direction Y. Each driving chip 200 is provided with a multiple number of data selection pins. The multiple data selection pins are arranged in two rows along a second direction X intersecting the first direction Y. Each data selection pin is connected to the light-emitting lamp group 100 via the partition passage wiring 300.

[0037] In one embodiment, the light-emitting lamp group 100 includes a first light-emitting lamp group 110 and a second light-emitting lamp group 120. The light-emitting lamp group 100 is located between the power line VLED and the division passage wiring 300. The driving chip 200 is provided between the light-emitting lamp group 100 and the ground signal wiring GND. The driving chip 200 includes a first data selection pin CH1 and a second data selection pin CH2. The division passage wiring 300 includes a first division passage wiring 310 and a second division passage wiring 320. The first light-emitting lamp group 110 and the second light-emitting lamp group 120 are arranged along a first direction Y, and the first light-emitting lamp group 110 and the second light-emitting lamp group 120 are located on the same side of the driving chip 200. The first data selection pin CH1 and the second data selection pin CH2 are arranged along the first direction Y. Each first light-emitting lamp group 110 is connected to the first data selection pin CH1 via the first division passage wiring 310. Each of the second light-emitting lamp groups 120 is connected to the second data selection pin CH2 via the second division passage wiring 320. The first division passage wiring 310 and the second division passage wiring 320 are located between the power supply line VLED and the ground signal wiring GND. The first division passage wiring 310 includes a part of the first division passage wiring 310 extending along the first direction Y and a part of the first division passage wiring 310 extending along the second direction X, and the first division passage wiring 310 extending along the second direction X is connected to the first data selection pin CH1. The second division passage wiring 320 includes a part of the second division passage wiring 320 extending along the first direction Y and a part of the second division passage wiring 320 extending along the second direction X, and the second division passage wiring 320 extending along the second direction X is connected to the second data selection pin CH2.

[0038] In one embodiment, the light-emitting lamp group 100 includes a third light-emitting lamp group 130 and a fourth light-emitting lamp group 140. The driving chip 200 is further provided with a third data selection pin CH3 and a fourth data selection pin CH4. The partition passage wiring 300 further includes a third partition passage wiring 330 and a fourth partition passage wiring 340. The first light-emitting lamp group 110, the second light-emitting lamp group 120, the third light-emitting lamp group 130 and the fourth light-emitting lamp group 140 are arranged along a first direction Y. The first light-emitting lamp group 110 and the third light-emitting lamp group 130, and the second light-emitting lamp group 120 and the fourth light-emitting lamp group 140 are located on opposite sides of the driving chip 200. The first data selection pin CH1 and the third data selection pin CH3 are arranged in a row along a second direction X. The first data selection pin CH1 is located on the side of the third data selection pin CH3 close to the power line VLED. Each of the first light-emitting lamp groups 110 is connected to the first data selection pin CH1 via the first division passage wiring 310. Each of the third light-emitting lamp groups 130 is connected to the third data selection pin CH3 via the third division passage wiring 330. The second data selection pin CH2 and the fourth data selection pin CH4 are arranged in another row along the second direction X. The second data selection pin CH2 is located on the side of the fourth data selection pin CH4 closer to the power line VLED. The fourth light-emitting lamp group 140 is connected to the fourth data selection pin CH4 via the fourth division passage wiring 340.

[0039] Specifically, the first division passage wiring 310 is located between the third division passage wiring 330 and the power line VLED, and the first division passage wiring 310 is close to one side of the first light-emitting lamp group 110. The third division passage wiring 330 includes a part of the third division passage wiring 330 extending along the first direction Y and a part of the third division passage wiring 330 extending along the second direction X. The third division passage wiring 330 extending along the first direction Y is connected to the third data selection pin CH3. Each fourth division passage wiring 340 includes a part of the fourth division passage wiring 340 extending along the first direction Y and a part of the fourth division passage wiring 340 extending along the second direction X. The fourth division passage wiring 340 extending along the first direction Y is connected to the fourth data selection pin CH4. The fourth division passage wiring 340 is located on the side of the second division passage wiring 320 far from the power line VLED.

[0040] In addition, the arrangement positions between the third light-emitting lamp group 130, the first light-emitting lamp group 110, the second light-emitting lamp group 120 and the fourth light-emitting lamp group 140 can be interchanged with other arrangement orders, and at the same time, the corresponding pins and wiring are also interchangeable.

[0041] In an embodiment, the display panel 10 may be provided with only one of the third light-emitting lamp group 130 and the fourth light-emitting lamp group 140. The display panel 10 may be provided with only one of the third division path wiring 330 and the fourth division path wiring 340. The driving chip 200 may be provided with only one of the third data selection pin CH3 and the fourth data selection pin CH4.

[0042] In one embodiment, the first division passage wiring 310, the second division passage wiring 320, the third division passage wiring 330 and the fourth division passage wiring 340 are arranged in parallel with each other and spaced apart from each other.

[0043] In one embodiment, the driver chip 200 includes a first portion and a second portion connected to the first portion. The first portion is located at an end of the driver chip 200 close to the power line VLED. The first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3, and the fourth data selection pin CH4 are located in the first portion. The driver chip 200 includes a ground signal pin GND. The ground signal pin GND is connected to the ground signal wiring GND. The ground signal pin GND is provided in the second portion. Specifically, the first data selection pin CH1, the third data selection pin CH3, and the ground signal pin GND are sequentially arranged in a line along the second direction X, or the second data selection pin CH2, the fourth data selection pin CH4, and the ground signal pin GND are sequentially arranged in a line along the second direction X, or the ground signal pin GND is independently formed in a line along the second direction X or the first direction Y.

[0044] In one embodiment, the driver chip 200 is provided with two power signal pins Vcc. The two power signal pins Vcc are provided in the second portion along the first direction. The display panel 10 includes a driver chip power wiring 400. The driver chip power wiring 400 is provided between adjacent driver chips 200 and is for connecting the power signal pins Vcc of the driver chips 200. Specifically, the two power signal pins Vcc include a first power signal pin Vcc and a second power signal pin Vcc. The first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, and the ground signal pin GND are sequentially arranged in a row along the second direction X, and the second data selection pin CH2, the fourth data selection pin CH4, and the second power signal pin Vcc are sequentially arranged in a row along the second direction X. Alternatively, the first data selection pin CH1, the third data selection pin CH3 and the first power supply signal pin Vcc are sequentially arranged in a row along the second direction X, and the second data selection pin CH2, the fourth data selection pin CH4, the second power supply signal pin Vcc and the ground signal pin GND are sequentially arranged in a row along the second direction X. The first power supply signal pin Vcc and the second power supply signal pin Vcc are sequentially arranged in a row along the first direction Y. The first power supply signal pin Vcc and the second power supply signal pin Vcc of the adjacent driving chips 200 are connected via a driving chip power supply wiring 400. The driving chip power supply wiring 400 is located between the fourth division passage wiring 340 and the ground signal wiring GND.

[0045] In one embodiment, the driver chip 200 is provided with a staging signal input pin Si and a staging signal output pin So. The staging signal input pin Si and the staging signal output pin So are provided in the second portion along the first direction Y. The display panel 10 includes a driver chip signal wiring 600. The driver chip power wiring 600 is provided between adjacent driver chips 200 to connect the staging signal input pin Si and the staging signal output pin So of the adjacent driver chips 200. Specifically, the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the staging signal output pin So and the ground signal pin GND are sequentially arranged in a row along the second direction X, and the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the staging signal input pin Si and the ground signal pin GND are sequentially arranged in a row along the second direction X. The staging signal output pin So and the staging signal input pin Si are sequentially arranged in a row along the first direction Y. Alternatively, the staging signal output pin So, the ground signal pin GND, and the staging signal input pin Si are sequentially arranged in a row along the first direction Y, that is, the ground signal pin GND, the staging signal input pin Si, and the staging signal output pin So are located in the same row. The staging signal input pin Si and the staging signal output pin So of the adjacent driving chips 200 are connected via the driving chip signal wiring 600. The driving chip signal wiring 600 is located between the driving chip power wiring 400 and the ground signal wiring GND.

[0046] In one embodiment, the driver chip power wiring 400, the data transmission wiring 500 and the driver chip signal wiring 600 are arranged in parallel to each other and extend along a first direction Y.

[0047] In one embodiment, the driving chip 200 is provided with at least one data signal pin Data. The data signal pin Data is provided in the second portion. The display panel includes a data transfer wiring 500. The data transfer wiring 500 is connected to the data signal pin Data. Specifically, the number of the data signal pin Data is one. One data signal pin Data and a ground signal pin GND are provided along a first direction Y. The data transfer wiring 500 extends along the first direction Y and is located on the side of the data signal pin Data that is away from the ground signal wiring GND. Furthermore, the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the staging signal output pin So, and the ground signal pin GND are sequentially arranged in a row along the second direction X. The second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the staging signal input pin Si, and the data signal pin Data are sequentially arranged in a row along the second direction X. That is, the ground signal pin GND and the data signal pin Data are located in the same row, or the first data selection pin CH1, the third data selection pin CH3, the first power supply signal pin Vcc, the staging signal output pin So and the data signal pin Data are sequentially arranged in a row along the second direction X. The second data selection pin CH2, the fourth data selection pin CH4, the second power supply signal pin Vcc, the staging signal input pin Si and the ground signal pin GND are sequentially arranged in a row along the second direction X, that is, the ground signal pin GND and the power supply signal pin Vcc are located in the same row. The data transfer wiring 500 is located between the driving chip signal wiring 600 and the ground signal wiring GND. Each data transfer wiring 500 is connected to the data signal pin Data of the multiple driving chips 200.

[0048] In one embodiment, the driver chip power wiring 400, the data transmission wiring 500 and the driver chip signal wiring 600 extend in a first direction Y and are arranged in parallel.

[0049] In one embodiment, the first data selection pin CH1, the third data selection pin CH3, the first power supply signal pin Vcc, the staging signal output pin So, and the ground signal pin GND constitute a plurality of first pins. The second data selection pin CH2, the fourth data selection pin CH4, the second power supply signal pin Vcc, the staging signal input pin Si, and the data signal pin Data constitute a plurality of second pins. The first pins and the second pins are provided symmetrically.

[0050] In addition, the pins provided in the first portion are compatible, and the positions of the first power supply signal pin Vcc, the second power supply signal pin Vcc, the staging signal output pin So, and the staging signal input pin Si in the second portion are compatible; that is, the positions of the first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3, and the fourth data selection pin CH4 are compatible, and when the positions of the first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3, and the fourth data selection pin CH4 are compatible, the positions of the corresponding first partition passage wiring 310, the second partition passage wiring 320, the third partition passage wiring 330, and the fourth partition passage wiring 340 are also compatible accordingly. The positions of the first power signal pin Vcc, the second power signal pin Vcc, the staging signal output pin So and the staging signal input pin Si are interchangeable, and when the positions of the first power signal pin Vcc, the second power signal pin Vcc, the staging signal output pin So and the staging signal input pin Si are interchangeable, the positions of the driving chip power wiring 400, the driving chip signal wiring 600 and the data transfer wiring 500 are correspondingly changed. The data signal pin Data and the ground signal pin GND are interchangeable and interchangeable, and the positions of the data transfer wiring 500 and the ground signal wiring GND are also interchangeable.

[0051] For example, the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the staging signal output pin So, and the ground signal pin GND are sequentially arranged along the second direction X. The second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the staging signal input pin Si, and the data signal pin Data are sequentially arranged along the second direction X. The first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the staging signal output pin So, and the ground signal pin GND are located on the side of the driving chip 200 close to the first light-emitting lamp group 110 and the third light-emitting lamp group 130. The second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the staging signal input pin Si, and the data signal pin Data are located on the side of the driving chip 200 close to the second light-emitting lamp group 120 and the fourth light-emitting lamp group 140. The first data selection pin CH1 and the second data selection pin CH2 are provided symmetrically. The third data selection pin CH3 and the fourth data selection pin CH4 are provided symmetrically. The first power supply signal pin Vcc and the second power supply signal pin Vcc are provided symmetrically. The staging signal input pin Si and the staging signal output pin So are provided symmetrically.

[0052] Next, the first section passage wiring 310 is located between the power line VLED and the third section passage wiring 330. The driving chip power line 400 is located on the side of the third section passage wiring 330 far from the power line VLED. The second section passage wiring 320 is located between the power line VLED and the fourth section passage wiring 340. The driving chip power line 400 is located on the side of the fourth section passage wiring 340 far from the power line VLED. The driving chip signal wiring 600 is located on the side of the driving chip power line 400 far from the power line VLED. The data transfer wiring 500 is located between the driving chip signal wiring 600 and the ground signal wiring GND. The ground signal wiring GND is located on the side of the driving chip signal wiring 600 farther from the power line VLED, and the first division passage wiring 310, the power line VLED, the third division passage wiring 330, the fourth division passage wiring 340, the driving chip power line 400, the data transfer wiring 500, the driving chip signal wiring 600, the second division passage wiring 320 and the ground signal wiring GND are arranged in the same layer and spaced apart.

[0053] In the present invention, the first section passage wiring 310, the power line VLED, the third section passage wiring 330, the fourth section passage wiring 340, the driving chip power wiring 400, the data transfer wiring 500, the driving chip signal wiring 600, the second section passage wiring 320 and the ground signal wiring GND are provided in the same layer and spaced apart, and corresponding pin positions are provided to reduce jumps in the wiring, thereby preventing the occurrence of problems such as short circuits, improving the yield rate of the display panel 10 and reducing costs.

[0054] The operating principle is that the positive pole of the power supply of the LED lamp is transferred to the light-emitting lamp group 100 through the power line VLED, and the driving chip 200 outputs a constant current source. After the data signal, power signal, ground signal and staging signal are transferred to the driving chip 200, the data signal is processed by the driving chip 200 and converted into each Output output current, which is then transferred to each light-emitting lamp group to emit light normally, that is, to operate the display panel 10.

[0055] Please refer to Fig. 2, which is a schematic plan view of the light-emitting lamp group 100 of the display panel 10 according to the embodiment of the present invention, and Fig. 3 is a second schematic plan view of the display panel 10 according to the embodiment of the present invention. The LEDs in the light-emitting lamp group 100 may be arranged to be connected in series in pairs or in parallel in pairs.

[0056] Please refer to FIG. 3. The difference between the first and second configurations is that the number of data signal pins Data is two. The two data signal pins Data are arranged along a first direction Y. Specifically, the data signal pins Data include a first data signal pin Data and a second data signal pin Data. The first power supply signal pin Vcc, the second power supply signal pin Vcc, the staging signal output pin So, the staging signal input pin Si, the first data signal pin Data and the second data signal pin Data are located in the second portion. The first data selection pin CH1, the third data selection pin CH3, the first power supply signal pin Vcc, the first data signal pin Data and the staging signal output pin So are sequentially arranged in a row along the second direction X, and the second data selection pin CH2, the fourth data selection pin CH4, the second power supply signal pin Vcc, the second data signal pin Data and the staging signal input pin Si are sequentially arranged in a row along the second direction X. The staging signal output pin So, the ground signal pin GND, and the staging signal output pin So are sequentially arranged in a row along the first direction Y. That is, the first data signal pin Data and the second data signal pin Data are provided symmetrically. The data transfer wiring 500 is provided between two adjacent driving chips 200. The first data signal pin Data and the second data signal pin Data of the two adjacent driving chips 200 are connected via the data transfer wiring 500.

[0057] In one embodiment, the driver chip 200 further includes a null pin NG. The null pin NG is located in the first portion. The first data selection pin CH1, the null pin NG, and the second data selection pin CH2 are sequentially arranged in a row along the first direction Y.

[0058] In addition, the positions of the first power supply signal pin Vcc, the second power supply signal pin Vcc, the staging signal output pin So, the staging signal input pin Si, the first data signal pin Data, and the second data signal pin Data in the first part are interchangeable, and at the same time, the positions of the corresponding wiring are also interchangeable.

[0059] For example, the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the first data signal pin Data, and the staging signal output pin So are sequentially arranged along the second direction X. The second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the second data signal pin Data, and the staging signal input pin Si are sequentially arranged along the second direction X. The empty pin NG and the ground signal pin GND are sequentially arranged along the second direction X, and the first data selection pin, the empty pin NG, and the second data selection pin are sequentially arranged along the first direction Y, and the first data selection pin, the empty pin NG, and the second data selection pin are located on a side close to the power line VLED of the driver chip 200. The staging signal output pin So, the ground signal pin GND, and the staging signal input pin Si are sequentially arranged along the first direction Y, and the staging signal output pin So, the ground signal pin GND, and the staging signal input pin Si are located on a side far from the power line VLED of the second portion. The first data selection pin CH1, the third data selection pin CH3, the first power supply signal pin Vcc, the first data signal pin Data, and the staging signal output pin So are located on the side of the driving chip 200 close to the first light-emitting lamp group 110. The second data selection pin CH2, the fourth data selection pin CH4, the second power supply signal pin Vcc, the second data signal pin Data, and the staging signal input pin Si are located on the side of the driving chip 200 close to the second light-emitting lamp group 120. The data transfer wiring 500 is located on the side of the driving chip power supply wiring 400 far from the power supply line VLED, and is located between the data transfer wiring 500 and the ground signal wiring GND. The second section passage wiring is located between the power line VLED and the fourth section passage wiring 340, the driving chip signal wiring 600 is located between the data transfer wiring 500 and the ground signal wiring GND, and the first section passage wiring 310, the power line VLED, the third section passage wiring 330, the fourth section passage wiring 340, the driving chip power supply wiring 400, the data transfer wiring 500, the driving chip signal wiring 600, the second section passage wiring 320 and the ground signal wiring GND are arranged in the same layer and spaced apart.

[0060] In the present invention, the first section passage wiring 310, the power line VLED, the third section passage wiring 330, the fourth section passage wiring 340, the driving chip power wiring 400, the data transfer wiring 500, the driving chip signal wiring 600, the second section passage wiring 320 and the ground signal wiring GND are provided in the same layer and spaced apart, and corresponding pin positions are provided to reduce jumps in the wiring, thereby preventing the occurrence of problems such as short circuits, improving the yield rate of the display panel 10 and reducing costs; and the driving chip 200 is provided with dead pins, which makes the pin arrangement of the driving chip 200 balanced and symmetrical, thereby simplifying the manufacturing process of the driving chip 200, shortening the manufacturing cycle and reducing costs.

[0061] It should be noted that the display panel 10 of the present invention may be a Mini LED backlight product or a Mini LED display screen product.

[0062] The present invention discloses a display panel 10 including a power line VLED, a group of light-emitting lamps 100, a driving chip 200, a partition path wiring 300, and a ground signal wiring GND, and the ground signal wiring GND and the power line VLED are provided at an interval. The driving chip 200 is provided between the power line VLED and the ground signal wiring GND and connected to the ground signal wiring GND, the group of light-emitting lamps 100 is provided between the driving chip 200 and the power line VLED, one end is connected to the power line VLED, the partition path wiring is provided between the power line VLED and the ground signal wiring GND, and the other end of the group of light-emitting lamps 100 is connected to the driving chip 200, and the power line VLED, the partition path wiring, and the ground signal wiring GND are provided in the same layer. In the present invention, the power line VLED, the partition path wiring, and the ground signal wiring GND are arranged in the same layer, and the pin arrangement design of the driving chip 200 is changed so that the power line VLED, the partition path wiring, and the ground signal wiring GND are arranged in different layers, thereby preventing the problem of short circuit occurrence, reducing costs, and improving the characteristics of the display panel 10.

[0063] The above describes in detail the display panel according to an embodiment of the present invention, and the present specification uses specific examples to explain the principles and embodiments of the present invention. However, the above explanation of the examples is merely for understanding the method of the present invention and its core idea. Meanwhile, a person skilled in the art may make changes to the specific embodiments and scope of application based on the concept of the present invention. In summary, the contents of this specification should not be understood as limiting the present invention. [Explanation of symbols]

[0064] Y 1st direction X 2nd direction 10 Display Panel 100 luminous lamps 110 First light emitting lamp group 120 Second light emitting lamp group 130 Third light emitting lamp group 140 Fourth Light Emitting Lamp Group 200 Drive Chip 300 compartment passage wiring 310 1st Section Passage Wiring 320 2nd Section Passageway Wiring 330 3rd Section Passageway Wiring 340 4th Section Passageway Wiring 400 Driving chip power wiring 500 Data transfer wiring 600 Driving chip signal wiring

Claims

1. A display panel, A power line, a ground signal line provided at a distance from the power supply line; a driver chip provided between the power supply line and the ground signal wiring and connected to the ground signal wiring; a group of light-emitting lamps provided between the ground signal wiring and the power supply line, one end of the group of light-emitting lamps being connected to the power supply line; a partition passage wiring provided between the power supply line and the ground signal wiring, the partition passage wiring connecting the other end of the light-emitting lamp group and the driving chip; the power supply line, the partition passage wiring, and the ground signal wiring are provided in the same layer; The driving chip is provided with one data signal pin and a ground signal pin, the display panel includes a data transfer wiring connected to the data signal pin, the data signal pin and the ground signal pin are provided along a first direction, and the data transfer wiring extends along the first direction and is located on a side of the data signal pin that is away from the ground signal wiring.

2. 2. The display panel of claim 1, wherein the light-emitting lamp group is comprised of a plurality of groups, the plurality of light-emitting lamp groups are arranged along a first direction, the plurality of partition passage wirings are comprised of a plurality of data selection pins on the driving chip, the plurality of data selection pins are arranged along the first direction and / or a second direction intersecting the first direction, and each of the data selection pins is connected to the light-emitting lamp group via the partition passage wiring.

3. The light-emitting lamp group includes a first light-emitting lamp group and a second light-emitting lamp group, the driving chip includes a first data selection pin and a second data selection pin, and the partition passage wiring includes a first partition passage wiring and a second partition passage wiring, The first light-emitting lamp group and the second light-emitting lamp group are arranged along a first direction, the first data selection pins and the second data selection pins are arranged along the first direction, 2. The display panel of claim 1, wherein the first group of light-emitting lamps and the first data selection pin are connected via the first division passage wiring, and the second group of light-emitting lamps are connected to the second data selection pin via the second division passage wiring.

4. the light-emitting lamp group further includes a third light-emitting lamp group and a fourth light-emitting lamp group, the driving chip further includes a third data selection pin and a fourth data selection pin, and the partition path wiring further includes a third partition path wiring and a fourth partition path wiring, The first light-emitting lamp group, the second light-emitting lamp group, the third light-emitting lamp group, and the fourth light-emitting lamp group are arranged along the first direction, the first data selection pin and the third data selection pin are arranged in a line along a second direction, and the first data selection pin is located on a side of the third data selection pin closer to the power line; the second data selection pin and the fourth data selection pin are arranged in another row along a second direction, the second data selection pin is located on a side of the fourth data selection pin closer to the power line, 4. The display panel of claim 3, wherein the third group of light-emitting lamps and the third data selection pin are connected via the third division passage wiring, and the fourth group of light-emitting lamps are connected to the fourth data selection pin via the fourth division passage wiring.

5. 5. The display panel of claim 4, wherein the driving chip includes a first part and a second part connected to the first part, the first part is located at an end of the driving chip close to the power line, the first data selection pin, the second data selection pin, the third data selection pin and the fourth data selection pin are located in the first part, the ground signal pin is connected to the ground signal wiring and the ground signal pin is provided in the second part.

6. The display panel described in claim 5, wherein two power supply signal pins are provided on the driving chip, the two power supply signal pins being provided in the second portion along the first direction, and the display panel includes a driving chip power wiring provided between adjacent driving chips for connecting the power supply signal pins of the driving chips.

7. 7. The display panel of claim 6, wherein the driving chip is provided with a staging signal input pin and a staging signal output pin, the staging signal input pin and the staging signal output pin are provided in the second portion along the first direction, and the display panel further includes a driving chip signal wiring provided between adjacent driving chips for connecting the staging signal input pin and the staging signal output pin of the adjacent driving chips.

8. The display panel according to claim 7 , wherein the data signal pin is provided in the second portion.

9. The display panel of claim 1 , wherein the ground signal lines are arranged in a first direction together with the power lines.

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