OLED display panel and OLED display device

Abstract

The present application provides an OLED display panel and an OLED display device, in which a dummy wiring is arranged on a side close to a signal wiring of an anode, at least one dummy wiring and at least one fan-out wiring are arranged corresponding to an anode arrangement position, and the fan-out wiring and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, thereby improving the uniformity of the wiring in the display area, improving the flatness and symmetry of the anode, and improving display defects of the display panel.

Description

[Technical field]

[0001] The present application relates to the technical field of displays, and in particular to OLED display panels and OLED display devices. [Background technology]

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to their advantages of self-luminescence, wide color gamut, low power consumption, and flexible display. In conventional OLED display devices, FIAA (FanoutInAA) technology is sometimes adopted to arrange fan-out wiring in the display area to narrow the bezel. However, in FIAA technology, the density of wiring in the display area varies, which causes display defects in visual effects. In addition, PLP (Pol-less Panel) technology is sometimes introduced in OLED display devices to improve light emission efficiency, but PLP technology has higher requirements for the flatness of the display panel, and further intensifies problems such as pinkish / blue-greenish surrounding light emission at wide viewing angles, color breaking, and diffraction, resulting in display defects of the display panel.

[0003] Therefore, conventional OLED display devices have a technical problem of display defects due to differences in wiring density in FIAA. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present application provide an OLED display panel and an OLED display device for solving a technical problem of display defects caused by differences in wiring density in FIAA, which exists in a conventional OLED display device. [Means for solving the problem]

[0005] To solve the above problems, the present application provides the following technical solutions:

[0006] The embodiment of the present application is 1. An OLED display panel including a display area and a non-display area disposed on one side of the display area, the OLED display panel comprising: Signal wiring, a fan-out wiring arranged on one side of the signal wiring and connected to the signal wiring; the OLED display panel includes a plurality of sub-pixels each including an anode, the anode being disposed on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display region to the display region, the OLED display panel further including a dummy wiring disposed on a side of the anode closer to the signal wiring, the display region including a first region corresponding to a position of the anode, the first region including at least one of the fan-out wiring and at least one of the dummy wiring, the fan-out wiring passing through each of the sub-pixels and the dummy wiring passing through each of the sub-pixels being symmetrical with respect to a center of the anode of each of the sub-pixels.

[0007] In some embodiments, the OLED display panel includes an upper bezel, a left bezel, a lower bezel, and a right bezel arranged to surround the display area, the fan-out wiring includes a first wiring portion and a second wiring portion, the first wiring portion and the second wiring portion are connected to each other, the first wiring portion is arranged along a direction from the left bezel to the right bezel, and the second wiring portion is arranged along a direction from the lower bezel to the upper bezel, and the display area includes a second region corresponding to a position where the first wiring portion is arranged, a third region corresponding to a position where the second wiring portion is arranged, and a fourth region where the fan-out wiring is not arranged.

[0008] In some embodiments, at least a portion of the dummy wiring is arranged in the fourth region, and the dummy wiring arranged in the fourth region is separated from the fan-out wiring at a connection point between the fan-out wiring and the signal wiring.

[0009] In some embodiments, at least a portion of the dummy wirings are arranged in at least one of the second region and the third region, the dummy wirings arranged in the second region and / or the third region are connected to one of the fan-out wirings adjacent to the fan-out wirings, and there is a gap between the dummy wirings and the other of the adjacent fan-out wirings.

[0010] In some embodiments, the length of the first wiring portion decreases along a direction from the lower bezel toward the upper bezel, and the length of the second wiring portion increases along a direction from the left bezel toward a central region of the display area.

[0011] In some embodiments, the dummy wiring includes a third wiring portion and a fourth wiring portion, the third wiring portion has the same arrangement direction as the first wiring portion, the fourth wiring portion has the same arrangement direction as the second wiring portion, at least a portion of the third wiring portion is connected to the fourth wiring portion, the length of the third wiring portion increases along the direction from the lower bezel to the upper bezel, and the length of the fourth wiring portion decreases from the left bezel toward a central region of the display area.

[0012] In some embodiments, one of the second wiring portions and one of the third wiring portions are arranged to intersect, and there is a gap between the other of the second wiring portions and the third wiring portion among the adjacent second wiring portions.

[0013] In some embodiments, one of the second wiring portions and one of the third wiring portions are arranged to cross each other, and along a direction from the left bezel to the right bezel, another of the second wiring portions and another of the third wiring portions are correspondingly connected, and each of the third wiring portions is spaced apart from each other.

[0014] In some embodiments, the dummy wiring and the fan-out wiring are arranged in the same layer, and the distribution density per unit of the dummy wiring is the same as the distribution density per unit of the fan-out wiring.

[0015] In some embodiments, the subpixels include a red subpixel, a blue subpixel, and a green subpixel, and at least one of the dummy wiring passing through the red subpixel, the dummy wiring passing through the blue subpixel, and the dummy wiring passing through the green subpixel is symmetrical with respect to the center of the anode of the corresponding subpixel.

[0016] In some embodiments, the red subpixel includes a first anode and the blue subpixel includes a second anode, the dummy wiring passing through the red subpixel is symmetrical about a center of the first anode, and the dummy wiring passing through the blue subpixel is symmetrical about a center of the second anode.

[0017] In some embodiments, the green subpixel includes a third anode, and the dummy wiring passing through the green subpixel is symmetrical about the center of the third anode, and the dummy wiring passing through the green subpixel along a direction from the lower bezel to the upper bezel is symmetrical about a center line of the third anode.

[0018] In some embodiments, along a direction from the left bezel to the right bezel, at least a portion of the dummy wiring passing through the green subpixels of an adjacent column extends into the red subpixel, and / or at least a portion of the dummy wiring passing through the green subpixels of an adjacent column extends into the blue subpixel, and the dummy wiring extending into the red subpixels and / or the blue subpixels is spaced apart from the dummy wiring passing through the red subpixels and the blue subpixels.

[0019] In some embodiments, the OLED display panel includes a driving circuit layer including a first source-drain layer and a second source-drain layer; The first source-drain layer includes the signal wiring, and the second source-drain layer includes the fan-out wiring and the dummy wiring.

[0020] In some embodiments, the OLED display panel includes a driving circuit layer including a first source-drain layer, a second source-drain layer, and a third source-drain layer, the first source-drain layer including a source and a drain, the second source-drain layer including the signal wiring, and the third source-drain layer including the fan-out wiring and the dummy wiring.

[0021] In some embodiments, the OLED display panel further includes a first planarization layer disposed between the first source-drain layer and the second source-drain layer, and a second planarization layer disposed between the second source-drain layer and the third source-drain layer, the signal wiring includes a data line, and the fan-out wiring is connected to the data line through a via in the second planarization layer.

[0022] In some embodiments, the OLED display panel further includes a power signal line disposed in the second source / drain layer, and the dummy wiring is connected to the power signal line through a via.

[0023] At the same time, the embodiment of the present application is 1. An OLED display device comprising an OLED display panel including a display area and a non-display area disposed on one side of the display area, the OLED display panel comprising: Signal wiring, a fan-out wiring arranged on one side of the signal wiring and connected to the signal wiring; the OLED display panel includes a plurality of sub-pixels including an anode, the anode being disposed on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display region to the display region, the OLED display panel further including a dummy wiring disposed on a side of the anode closer to the signal wiring, the display region including a first region corresponding to a position of the anode, the first region including at least one of the fan-out wiring and at least one of the dummy wiring, the fan-out wiring passing through each of the sub-pixels and the dummy wiring passing through each of the sub-pixels being symmetrical with respect to a center of the anode of each of the sub-pixels.

[0024] In some embodiments, the OLED display panel includes an upper bezel, a left bezel, a lower bezel, and a right bezel arranged to surround the display area, the fan-out wiring includes a first wiring portion and a second wiring portion, the first wiring portion and the second wiring portion are connected to each other, the first wiring portion is arranged along a direction from the left bezel to the right bezel, and the second wiring portion is arranged along a direction from the lower bezel to the upper bezel, and the display area includes a second region corresponding to a position where the first wiring portion is arranged, a third region corresponding to a position where the second wiring portion is arranged, and a fourth region where the fan-out wiring is not arranged.

[0025] In some embodiments, at least a portion of the dummy wiring is arranged in the fourth region, and the dummy wiring arranged in the fourth region is separated from the fan-out wiring at a connection point between the fan-out wiring and the signal wiring. Effect of the Invention

[0026] The present application provides an OLED display panel and an OLED display device, the OLED display panel including a display area and a non-display area arranged on one side of the display area, the OLED display panel including signal wiring and fan-out wiring, the fan-out wiring being arranged on one side of the signal wiring and connected to the signal wiring, the OLED display panel including a plurality of sub-pixels including an anode, the anode being arranged on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display area to the display area, the OLED display panel further including a dummy wiring arranged on a side of the anode closer to the signal wiring, the display area including a first area corresponding to a position of the anode, the first area including at least one fan-out wiring and at least one dummy wiring, the fan-out wiring passing through each sub-pixel and the dummy wiring passing through each sub-pixel being symmetrical with respect to a center of the anode of each sub-pixel. In the present application, a dummy wiring is arranged near the signal wiring of the anode, and at least one dummy wiring and at least one fan-out wiring are arranged corresponding to the anode arrangement position, so that areas where no fan-out wiring is arranged or areas where the fan-out wiring is uneven can be filled with the dummy wiring, improving the uniformity of the wiring in the display area. In addition, the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, thereby improving the flatness and symmetry of the anode and improving the flatness of the light-emitting material, thereby matching the visual effects at each viewing angle and improving display defects of the display panel. [Brief description of the drawings]

[0027] Hereinafter, specific embodiments of the present application will be described in detail in conjunction with the drawings to make the technical solutions and other beneficial effects of the present application clearer. [Figure 1] 1 is a schematic diagram of a conventional OLED display device. [Diagram 2] FIG. 1 is a first schematic diagram of an OLED display panel provided in an embodiment of the present application; [Diagram 3]FIG. 2 is a film layer diagram of a single subpixel in an OLED display panel provided in an embodiment of the present application. [Figure 4a] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4b] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4c] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4d] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4e] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4f] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4g] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4h] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4i] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4j] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4k] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4l] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4m] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Figure 4n] FIG. 4 is an exploded view of each film layer of a single subpixel in FIG. [Diagram 5] FIG. 2 is a second schematic diagram of an OLED display panel provided in an embodiment of the present application. [Figure 6] FIG. 2 is a third schematic diagram of an OLED display panel provided in an embodiment of the present application. [Figure 7] FIG. 4 is a fourth schematic diagram of an OLED display panel provided in an embodiment of the present application. [Figure 8]FIG. 5 is a fifth schematic diagram of an OLED display panel provided in an embodiment of the present application. [Figure 9] FIG. 4 is a circuit diagram of a single subpixel in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Of course, the described embodiments are only a part of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort shall fall within the scope of protection of the present application.

[0029] As shown in FIG. 1, an OLED display device may adopt FIAA technology to narrow the bezel. As can be seen from FIG. 1, in the FIAA technology, the fan-out wiring 122 is disposed in the display area 111, and the fan-out wiring 122 and the data line 121 are connected in the display area 111, and the connection point between the fan-out wiring 122 and the data line 121 is indicated by reference numeral 123. In the process of transmitting a signal, the normal transmission of the signal is realized by the connection between the fan-out wiring 122 and the bonding pad of the bonding area 112. Since the fan-out wiring 122 is disposed in the display area 111 and is disposed in a separate film layer, the space available for disposing the fan-out wiring 122 is large, and when connecting to the bonding pad of the bonding area 112, the length of the part located in the non-display area can be reduced, thereby narrowing the bezel. However, as can be seen from FIG. 1, the density of the fan-out wiring is different due to the different positions of the connection points between the fan-out wiring 122 and the data line 121. This specifically includes the following: First, there is no fan-out wiring in some regions, for example, there is no fan-out wiring 122 in the first region 131 of FIG. 1. Second, although fan-out wiring is arranged in some regions, the arrangement of the fan-out wiring in the horizontal and vertical directions is uneven. For example, in FIG. 1, the fan-out wiring 122 is arranged in the second region 132, but the fan-out wiring on the right side of the horizontal part of the lowest fan-out wiring 122 is arranged vertically instead of horizontally, which makes the fan-out wiring uneven in the horizontal and vertical directions, and causes display defects when the OLED display panel is displayed. In addition, with the introduction of PLP technology into the OLED display device, the viewing angle and brightness of the display panel become larger, which further intensifies problems such as pinkish / blue-greenish emission around the periphery at wide viewing angles, color breaking, diffraction, etc., leading to display defects of the display panel. Therefore, the conventional OLED display device has a technical problem of display defects due to differences in wiring arrangement density in FIAA.

[0030] In response to the above technical problems, the embodiments of the present application provide an OLED display panel and an OLED display device to alleviate the above technical problems.

[0031] As shown in FIG. 2 to FIG. 7, an embodiment of the present application provides an OLED display panel, the OLED display panel 2 includes a display area 281 and a non-display area 282 disposed on one side of the display area 281, and the OLED display panel 2 includes: A signal line (e.g., data line 254a in FIG. 4j), A fan-out wiring 31 is arranged on one side of the signal wiring and connected to the signal wiring (in FIG. 5, the connection point between the fan-out wiring 31 and the signal wiring is indicated by reference numeral 331), The OLED display panel 2 includes a plurality of sub-pixels 41 including an anode 261a, the anode 261a being disposed on a side of the fan-out wiring 31 farther from the signal wiring, the fan-out wiring 31 extending from the non-display area 282 to the display area 281, the OLED display panel 2 further including a dummy wiring 32 disposed on a side of the anode 261a closer to the signal wiring, the display area 281 including a first area 283 corresponding to an arrangement position of the anode, the first area 283 including at least one of the fan-out wiring 31 and at least one of the dummy wiring 32, and the fan-out wiring 31 passing through each of the sub-pixels 41 and the dummy wiring 32 passing through each of the sub-pixels 41 are symmetrical with respect to a center of the anode 261a of each of the sub-pixels 41.

[0032] An embodiment of the present application provides an OLED display panel, in which a dummy wiring is arranged near a signal wiring of an anode, and at least one dummy wiring and at least one fan-out wiring are arranged corresponding to an anode arrangement position, so that an area where a fan-out wiring is not arranged or an area where the fan-out wiring is uneven can be filled with the dummy wiring, and the uniformity of the wiring in the display area can be improved. The fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, so that the flatness and symmetry of the anode can be improved and the flatness of the light-emitting material can be improved, thereby making the visual effects at each viewing angle consistent and improving the display defects of the display panel.

[0033] It should be noted that Fig. 3 is a film layer design diagram for a single subpixel, and Figs. 4a to 4n are exploded views of each film layer in the film layer design diagram of Fig. 3, and since there are two circuits arranged symmetrically in a single subpixel, it can be seen that each film layer in Figs. 4a to 4m is arranged symmetrically, and Fig. 4n is a film layer diagram of an anode. The display panel is divided into left and right sides with the center line of the display panel as the boundary, and although Fig. 5 only shows the arrangement of the fan-out wiring 31 and dummy wiring 32 on the left side, it can be understood that the fan-out wiring 31 and dummy wiring 32 on the right side are arranged symmetrically with the fan-out wiring 31 and dummy wiring 32 on the left side.

[0034] The difference between the fan-out wiring 31 and the dummy wiring 32 will be explained using a single bonding pad 33 as an example, and the fan-out wiring 31 refers to wiring that is connected without interruption from the bonding pad 33 to the signal wiring (the connection point between the fan-out wiring 31 and the signal wiring is indicated by the symbol 331), and the dummy wiring 32 refers to wiring other than the fan-out wiring 31.

[0035] In addition, since the signal wiring and the fan-out wiring are located in different layers and it is difficult to show the signal wiring and the fan-out wiring in the same drawing after the dummy wiring is arranged, in Figure 5, only the connection point between the fan-out wiring 31 and the signal wiring is indicated by the symbol 331, and the arrangement method of the signal wiring can be referred to the arrangement method of the data lines 254a in Figures 3 to 4n.

[0036] In conventional display devices, the arrangement of fan-out wiring is as shown in Figure 1, where some areas have no fan-out wiring and the arrangement of the fan-out wiring is uneven in the horizontal and vertical directions. This causes the film layer under the anode to be uneven and the anode layer to be uneven. When the luminescent material is subsequently manufactured, the luminescent material of each sub-pixel will be uneven, resulting in display defects. In response to the above technical problem, the present application arranges dummy wirings closer to the anode signal wiring and arranges at least one dummy wiring in a first region, so that the dummy wirings of the present application can be arranged at least in a region without fan-out wirings (e.g., a region having only data line 121 in Figure 1) and / or in a region where fan-out wirings are uneven in the horizontal and vertical directions (e.g., a region in Figure 1 where fan-out wirings 122 are arranged, except that other fan-out wirings 122 located on one side of the horizontal portion of one fan-out wiring 122 are arranged vertically rather than horizontally, and other fan-out wirings 122 located on one side of the vertical portion of one fan-out wiring 122 are arranged horizontally rather than vertically). This at least improves the unevenness between the case without fan-out wiring and the case with fan-out wiring, and / or improves the unevenness in the horizontal and vertical directions when fan-out wiring is present (for example, in Figure 5, by arranging the horizontal third wiring portion 321 and the vertical fourth wiring portion 322, the lengths and spacing of the wiring in the horizontal and vertical directions in any area where fan-out wiring 31 is arranged are made close to and even equal, thereby arranging the wiring uniformly in the horizontal and vertical directions), and by making the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel symmetrical with respect to the center of the anode of each subpixel, the flatness and symmetry of the anode is improved and display defects of the display panel are improved.

[0037] In addition, in Figure 5, the connection point between the dummy wiring 32 and other wiring is indicated by the symbol 332, and the connection point between the fan-out wiring 31 and the signal wiring is indicated by the symbol 331. The connection points between the dummy wiring 32 and other wiring, and the connection points between the fan-out wiring 31 and the signal wiring can be distinguished based on whether or not they are connected to the fan-out wiring in Figure 5. As can be seen from Figure 5, the dummy wiring 32 connected to other wiring is not connected to the fan-out wiring 31, and the dummy wiring 32 connected to the fan-out wiring 31 is not connected to the adjacent fan-out wiring 31, and they function only as wiring for planarization and do not affect the signal of the fan-out wiring 31.

[0038] In an embodiment, as shown in FIG. 6 , the OLED display panel 2 includes an upper bezel 291, a left bezel 292, a lower bezel 293, and a right bezel 294 arranged to surround the display area 281, the fan-out wiring 31 includes a first wiring portion 311 and a second wiring portion 312, the first wiring portion 311 and the second wiring portion 312 are connected to each other, the first wiring portion 311 is arranged along a direction from the left bezel 292 to the right bezel 294, and the second wiring portion 312 is arranged along a direction from the lower bezel 293 to the upper bezel 291, and the display area 281 includes a second region 284 corresponding to a position where the first wiring portion 311 is arranged, a third region 285 corresponding to a position where the second wiring portion 312 is arranged, and a fourth region 286 where the fan-out wiring 31 is not arranged.

[0039] In order to cope with the technical problem that the flatness of the anode layer is reduced due to the fan-out wiring being arranged only in a part of the region, and furthermore, display defects are caused, in one embodiment, as shown in FIG. 6, at least a part of the dummy wiring 32 is arranged in the fourth region 286, and the dummy wiring 32 arranged in the fourth region 286 and the fan-out wiring 31 are spaced apart at the connection point 331 between the fan-out wiring 31 and the signal wiring. By arranging the dummy wiring in the fourth region, the region where the fan-out wiring is not arranged is filled with the dummy wiring, wiring is arranged in every region of the display region, the uniformity of the wiring in the display region is improved, and the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, improving the flatness and symmetry of the anode, improving the flatness of the light-emitting material, and thus improving the display effect. And by spacing the dummy wiring from the fan-out wiring at the connection point between the fan-out wiring and the signal wiring, the dummy wiring is prevented from affecting the signal of the fan-out wiring, and the fan-out wiring can operate normally.

[0040] For ease of viewing, FIG. 6 shows only one connection point between the fan-out wiring and the signal wiring. In reality, however, all the fan-out wirings are connected to the signal wiring. For the location of the connection points between each fan-out wiring and the signal wiring, refer to FIG. 5.

[0041] Specifically, in response to the above-mentioned problem that there is no fan-out wiring in some regions, for example, there is no fan-out wiring 122 in the first region 131 of Figure 1, the present application arranges dummy wiring in the fourth region, and as shown in Figure 6, the dummy wiring 32 is arranged other than at the connection point between the fan-out wiring 31 and the signal wiring, and the dummy wiring can be arranged in the same film layer as the fan-out wiring, thereby improving the uniformity of the film layer in which the fan-out wiring is arranged, improving the flatness of the anode layer, and improving the display effect of the display panel.

[0042] In response to the technical problem that uneven arrangement of the fan-out wirings reduces the flatness of the anode layer and further leads to display defects, in one embodiment, as shown in FIG. 5, at least a portion of the dummy wirings 32 are arranged in at least one of the second region 284 and the third region 285, and the dummy wirings 32 arranged in the second region 284 and / or the third region 285 are connected to one of the adjacent fan-out wirings 31, and there is a gap between the dummy wirings 32 and the other fan-out wirings 31 among the adjacent fan-out wirings 31. The dummy wiring is arranged in at least one of the second and third regions to fill in the positions in the fan-out wiring that have only vertical wiring or only horizontal wiring, thereby making the wiring arrangement density in each region of the display panel close and even equal; the dummy wiring can be arranged in the same film layer as the fan-out wiring, or in another film layer, thereby improving the uniformity of the film layer located below the anode, improving the flatness of the anode layer, and improving the display effect of the display panel; and the dummy wiring is connected to one of the adjacent fan-out wirings, and there is a gap between the dummy wiring and the other fan-out wiring of the adjacent fan-out wirings, thereby preventing the dummy wiring from turning on the adjacent fan-out wiring, and allowing the fan-out wiring to normally transmit the signal of the signal wiring.

[0043] Specifically, in response to the above-mentioned problem that fan-out wirings are arranged in some regions but the arrangement of the fan-out wirings in the horizontal and vertical directions is non-uniform, as shown in Fig. 5, the present application arranges dummy wirings 32 in the second region 284 and the third region 285, for example, on the right side of the horizontal portion of the lowest fan-out wiring 31, thereby improving the horizontal uniformity of the fan-out wirings 31. Also, as can be seen from Fig. 5, the third wiring portion 321 is connected to one fan-out wiring 31, and there is a gap between the third wiring portion 321 and the fan-out wiring 31 adjacent to the fan-out wiring 31, thereby preventing the third wiring portion 321 from turning on the adjacent fan-out wiring, and allowing the fan-out wirings to transmit signals normally.

[0044] The length of the first wiring portion refers to the distance from the left end of the first wiring portion to the right end of the first wiring portion, the length of the second wiring portion refers to the distance from the top end of the second wiring portion to the bottom end of the second wiring portion, and similarly, the length of the third wiring portion refers to the distance from the left end of the third wiring portion to the right end of the third wiring portion, and the length of the fourth wiring portion refers to the distance from the top end of the fourth wiring portion to the bottom end of the second wiring portion. In addition, since the third wiring and the fourth wiring are arranged separated from each other, the length of the third wiring portion and the length of the fourth wiring portion may be the sum of the lengths of the respective separated portions.

[0045] In one embodiment, as shown in Figures 5 and 6, the length of the first wiring portion 311 decreases along the direction from the lower bezel 293 to the upper bezel 291, and the length of the second wiring portion 312 increases along the direction from the left bezel 292 to the central region of the display area 281.

[0046] The embodiment of the present application addresses the above-mentioned problem that the fan-out wiring is arranged in a part of the region, but the arrangement of the fan-out wiring in the horizontal and vertical directions is uneven. Specifically, the fan-out wiring includes a first wiring portion and a second wiring portion, and the first wiring portion in the horizontal direction and the second wiring portion in the vertical direction are arranged unevenly. In the embodiment of the present application, the arranged dummy wiring includes a third wiring portion and a fourth wiring portion, and the third wiring portion and the fourth wiring portion are arranged according to the arrangement direction and arrangement density of the first wiring portion and the second wiring portion, and the dummy wiring can be arranged in the same film layer as the fan-out wiring, thereby improving the uniformity of the film layer in which the fan-out wiring is located, improving the flatness of the film layer in which the fan-out wiring is located, and further improving the flatness of the anode layer, and the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, thereby improving the symmetry of the anode, matching the visual effect at each viewing angle, and improving the display effect of the display panel.

[0047] In response to the technical problem of the reduction in flatness due to the non-uniform arrangement of the fan-out wiring and the dummy wiring, in one embodiment, as shown in Figures 5 and 6, the dummy wiring 32 includes a third wiring portion 321 and a fourth wiring portion 322, the third wiring portion 321 has the same arrangement direction as the first wiring portion 311, the fourth wiring portion 322 has the same arrangement direction as the second wiring portion 312, at least a part of the third wiring portion 321 is connected to the fourth wiring portion 322, the length of the third wiring portion 321 increases along the direction from the lower bezel 293 to the upper bezel 291, and the length of the fourth wiring portion decreases from the left bezel to the central region of the display area. By increasing the width of the third wiring portion from bottom to top and reversing the change trend of the width of the third wiring portion to the change trend of the width of the first wiring portion, the third wiring portion can fill the empty area of ​​the first wiring portion, and the uniformity of the lateral portion of the film layer where the fan-out wiring is located is improved. By decreasing the width of the fourth wiring portion from left to right and reversing the width change trend of the fourth wiring portion from that of the second wiring portion, the fourth wiring portion can fill the empty space of the second wiring portion, and improve the uniformity of the vertical portion of the film layer where the fan-out wiring is located, thereby improving the flatness of the anode layer and improving the display effect of the display panel.

[0048] Specifically, the first wiring portion and the second wiring portion can be arranged at a predetermined angle, and the predetermined angle is determined based on the actual design of the fan-out wiring, and the range of the predetermined angle may be 0 degrees to 180 degrees excluding 0 degrees. For example, the first wiring portion and the second wiring portion are arranged in the horizontal and vertical directions, respectively, and the angle between the first wiring portion and the second wiring portion is 90 degrees.

[0049] The above embodiment has been described in detail using an example in which the length of each third wiring portion is increased and the length of each fourth wiring portion is decreased, but the embodiment of the present application is not limited to this, and for example, the length of each third wiring portion may be equal, and the length of each fourth wiring portion may be equal.

[0050] Specifically, in order to address the problem of the first horizontal wiring portion and the second vertical wiring portion being unevenly arranged, as shown in FIG. 5 , the third wiring portion 321 includes a first sub-portion 321a and a second sub-portion 321b, the first sub-portion 321a is arranged to cross the second wiring portion 312, and the first sub-portion 321a is connected to one of the adjacent second wiring portions 312, and the first sub-portion 321a and the second wiring portion 312 adjacent to each other are arranged to be in a uniform arrangement. There is a gap between the fourth wiring portion 322 and one of the adjacent first wiring portions 312, and the fourth wiring portion 322 includes a third sub-portion 322a and a fourth sub-portion 322b, the third sub-portion 322a is connected to one of the adjacent first wiring portions 311, there is a gap between the third sub-portion 322a and the other first wiring portion 311 of the adjacent first wiring portion 311, and the second sub-portion 321b is arranged to cross the fourth sub-portion 322b. As the third wiring portion 321 is arranged to cross the second wiring portion 312 and the fourth wiring portion 322, respectively, the fourth wiring portion 322 is arranged to cross the first wiring portion 311 and the third wiring portion 321, respectively. Thus, the area where the first wiring portion and the second wiring portion are unevenly arranged can be filled by the third wiring portion and the fourth wiring portion. Any position in the film layer in which the fan-out wiring is located has horizontally arranged wires and vertically arranged wires, improving the flatness of the film layer in which the fan-out wiring is located. In addition, by controlling the widths of the third wiring portion and the fourth wiring portion, the flatness of the film layer in which the fan-out wiring is located can be further improved, the flatness of the anode layer can be improved, and the display effect of the display panel can be improved.

[0051] 5, one of the second wiring portions 312 and one of the third wiring portions 321 of the adjacent second wiring portions 312 are arranged to cross each other, and there is a gap between the other of the second wiring portions 312 and the third wiring portion 321 of the adjacent second wiring portions 312. One of the second wiring portions and one of the third wiring portions are arranged to cross each other, and there is a gap between the other of the second wiring portions and the third wiring portion of the adjacent second wiring portions, and the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, so that the third wiring portion arranged in the second wiring portion can be uniformly arranged, the flatness of the film layer where the fan-out wiring is located can be improved, and the flatness and symmetry of the anode layer can be improved, thereby improving the display effect of the display panel.

[0052] Specifically, when the third wiring portion and the second wiring portion are arranged to intersect with each other, the third wiring portion may be arranged symmetrically with respect to the second wiring portion, thereby further improving the flatness and symmetry of the film layer in which the fan-out wiring is located, and improving problems such as different visual effects at wide viewing angles due to poor flatness and symmetry of the anode layer, and display defects such as color breaking up and diffraction.

[0053] 8, one of the adjacent second wiring parts 312 and one of the third wiring parts 321 are arranged to cross each other, and the other of the adjacent second wiring parts 312 and the third wiring part 321 are connected to each other along a direction from the left bezel to the right bezel, and the third wiring parts 321 are spaced apart from each other. By arranging one of the adjacent second wiring parts and one of the third wiring parts to cross each other and connecting the other second wiring parts to the third wiring part, it is possible to improve the uniformity of the impedance of each second wiring part and to avoid display defects caused by impedance mismatch of each fan-out wiring.

[0054] In order to cope with the technical problem that the distribution density of the fan-out wiring is different, the flatness of the anode layer is poor, and furthermore, display defects are caused, in one embodiment, as shown in FIG. 4l and FIG. 5, the dummy wiring 32 and the fan-out wiring 31 are arranged in the same layer, and the distribution density per unit of the dummy wiring 32 is the same as the distribution density per unit of the fan-out wiring 31. By arranging the dummy wiring and the fan-out wiring in the same layer, the uniformity and flatness of the film layer in which the fan-out wiring is located can be improved, and the flatness of the anode layer can be improved. At the same time, by making the distribution density per unit of the dummy wiring the same as the distribution density per unit of the fan-out wiring, the uniformity of the film layer in which the fan-out wiring is arranged can be further improved, the flatness of the anode layer can be improved, and the display effect of the display panel can be improved.

[0055] Specifically, the distribution density per unit refers to the layout density of wiring in a unit area. For example, if there is fan-out wiring of 0.5 square millimeters within 1 square millimeter, the distribution density per unit of the fan-out wiring is 0.5.

[0056] Considering that the dummy wirings are spaced apart during placement, the distribution density per unit of the dummy wirings is slightly smaller than the distribution density per unit of the fan-out wirings, and therefore the difference between the distribution density per unit of the dummy wirings and the distribution density per unit of the fan-out wirings can be made smaller than a certain numerical value, which can be determined and specifically limited based on the flatness of the anode layer.

[0057] In response to the technical problem that the uneven distribution position of the fan-out wirings results in poor flatness of the anode layer and further leads to display defects, in one embodiment, as shown in Fig. 7, the subpixel 41 includes a red subpixel 412, a blue subpixel 411, and a green subpixel 413, and at least one of the dummy wirings 32 passing through the red subpixel 412, the dummy wiring 32 passing through the blue subpixel 411, and the dummy wiring 32 passing through the green subpixel 413 is symmetrical with respect to the center of the anode of the corresponding subpixel 41. By making at least one of the dummy wirings passing through the red subpixel, the blue subpixel, and the green subpixel symmetrical with respect to the center of the anode, the flatness and symmetry of the anode are high, and when a light emitting material is disposed on the anode, the light emitting material can be made relatively flat, so that the OLED display panel can display normally during display, and the technical problem of display defects of the OLED display panel is improved. Specifically, although FIG. 7 shows a sub-pixel, it can be understood that the sub-pixel is a virtual concept and does not belong to the structure of an OLED display panel, and is simply used in the embodiments of the present application to easily explain the arrangement method of dummy wiring.

[0058] 7, the red subpixel 412 includes a first anode 422, the blue subpixel 411 includes a second anode 421, the dummy wire 32 passing through the red subpixel 412 is symmetrical with respect to the center of the first anode 422, and the dummy wire 32 passing through the blue subpixel 411 is symmetrical with respect to the center of the second anode 421. By making the dummy wire passing through the red subpixel symmetrical with respect to the center of the first anode and making the dummy wire passing through the blue subpixel symmetrical with respect to the center of the second anode, the anode layer can be arranged symmetrically with respect to the dummy wire when arranging the anode layer, and the flatness and symmetry of the anode layer can be improved, so that when the luminescent material is arranged on the anode layer, the luminescent material can be relatively flat, so that the OLED display panel can display normally when displaying, and the technical problem of display defects of the OLED display panel can be improved.

[0059] 7 , the green subpixel 413 includes a third anode 423, and the dummy wire 32 passing through the green subpixel 413 is symmetrical with respect to the center of the third anode 423, and the dummy wire 32 passing through the green subpixel 413 along a direction from the lower bezel to the upper bezel is symmetrical with respect to the center line of the third anode 423. While the fan-out wires may be arranged symmetrically with respect to the center line of the green subpixel, the present application arranges the fan-out wires and the dummy wires symmetrically with respect to the center line of the green subpixel, thereby improving the flatness of the film layer where the fan-out wires are located, improving the flatness and symmetry of the anode layer, and improving the technical problem of display defects of the OLED display panel.

[0060] Specifically, the red subpixel and the blue subpixel are located in the same row, and the green subpixel is located between adjacent red subpixels. As shown in FIG. 8, the fan-out wiring 31 and the dummy wiring 32 are arranged in a horizontal direction such that three wirings form one repeating unit 34, one of which is arranged within the red subpixel or the blue subpixel, and the other two wirings are arranged between the blue subpixel and the red subpixel.

[0061] In one embodiment, as shown in FIG. 8 , along the direction from the left bezel to the right bezel, at least a portion of the dummy wiring 32 passing through the green subpixel 413 of an adjacent column extends into the red subpixel 412, and / or at least a portion of the dummy wiring 32 passing through the green subpixel 413 of an adjacent column extends into the blue subpixel 411, and the dummy wiring 32 extending into the red subpixel 412 and / or the blue subpixel 411 is spaced apart from the dummy wiring 32 passing through the red subpixel 412 and the blue subpixel 411. By allowing the dummy wiring passing through the green subpixels of an adjacent column to extend into the red subpixels and / or blue subpixels, the uniformity of the impedance of each second wiring portion can be improved and display defects caused by impedance mismatches of each fan-out wiring can be avoided. Furthermore, by separating the dummy wiring extending into the red subpixels and / or blue subpixels from the dummy wiring passing through the red subpixels and blue subpixels, the dummy wiring is prevented from turning on adjacent fan-out wirings, allowing the fan-out wirings to operate normally.

[0062] Although the above embodiment has described in detail the arrangement of the dummy wiring by taking one pixel design as an example, the embodiment of the present application is not limited thereto, and for example, the dummy wiring passing through the green subpixel is symmetrical with respect to the center of the third anode, the dummy wiring passing through the blue subpixel along the direction from the lower bezel to the upper bezel is arranged symmetrical with respect to the center line of the second anode, and the dummy wiring passing through the red subpixel is arranged symmetrical with respect to the center line of the first anode. In one embodiment, the OLED display panel includes a driving circuit layer, and the driving circuit layer includes a first source-drain layer and a second source-drain layer.

[0063] wherein the signal wiring is formed in the first source / drain layer, and the second source / drain layer includes the fan-out wiring and the dummy wiring, when arranging the signal wiring, the fan-out wiring and the dummy wiring, the signal wiring can be arranged in the first source / drain layer and the fan-out wiring can be arranged in the second source / drain layer, so that the fan-out wiring can be arranged in the display area and the bezel occupied by the fan-out wiring can be reduced, and by arranging the dummy wiring in the second source / drain layer, the film layer where the fan-out wiring is located can be planarized by the dummy wiring, which improves the planarity of the second source / drain layer, improves the planarity of the anode layer, and improves the display effect of the display panel.

[0064] In one embodiment, as shown in Figures 2 to 4n, the OLED display panel 2 includes a driving circuit layer, the driving circuit layer includes a first source drain layer 252, a second source drain layer 254 and a third source drain layer 256, the first source drain layer 252 includes a source and a drain, the second source drain layer 254 includes a signal line (e.g., a data line 254a), and the third source drain layer 256 includes a fan-out line 31 and a dummy line 32. When arranging the signal line, the fan-out line and the dummy line, the signal line can be arranged in the second source drain layer and the fan-out line can be arranged in the third source drain layer, so that the fan-out line can be arranged in the display area and the bezel occupied by the fan-out line can be reduced, and the dummy line can be arranged in the third source drain layer, so that the film layer where the fan-out line is located can be planarized by the dummy line, which improves the planarity of the third source drain layer and the planarity of the anode layer, thereby improving the display effect of the display panel.

[0065] In one embodiment, as shown in FIG. 2 to FIG. 4n, the OLED display panel 2 further includes a first planarization layer 253 and a second planarization layer 255, the first planarization layer 253 is disposed between the first source-drain layer 252 and the second source-drain layer 254, the second planarization layer 255 is disposed between the second source-drain layer 254 and the third source-drain layer 256, the signal wiring includes a data line 254a, the data line 254a is disposed in the second source-drain layer 254, and the fan-out wiring 31 passes through a via 255a of the second planarization layer 255 and is connected to the data line 254a. By including the data line in the signal wiring, arranging the data line in the second source-drain layer, and arranging the fan-out wiring in the third source-drain layer, the fan-out wiring can pass through the via in the second planarization layer to connect to the data line, thereby achieving signal transmission of the data line; and by arranging the fan-out wiring in the display area, the bezel occupied by the fan-out wiring can be reduced, thereby realizing a narrow bezel for the display panel.

[0066] In response to the technical problem that static electricity may be generated due to the suspension arrangement of the dummy wires, in one embodiment, as shown in Figures 2 to 4n, the OLED display panel 2 further includes a power signal line 254b, which is disposed in the second source-drain layer 254, and the dummy wires 32 are connected to the power signal line 254b through a via. By connecting the dummy wires to the power signal line, it is possible to avoid the destruction of the circuit due to static electricity generated by the dummy wires, and the dummy wires are only connected to the power signal line, so that the normal operation of the circuit is not affected.

[0067] Moreover, the working principle and film layer structure of the OLED display panel in the embodiments of the present application are described by the film layer design and circuit design of a single sub-pixel in the OLED display panel.

[0068] As shown in FIGS. 2 to 4n and FIG. 9, FIG. 9 is a pixel driving circuit diagram of a single subpixel in FIG. 3, where the OLED display panel includes a pixel driving circuit, and the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first reset transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, a holding capacitor Cst, a boost capacitor Cboost, a power supply signal line VDD, a low potential signal line VSS, a data line Data, a first scan line PScan(n), a second scan line PScan(n-1), a third scan line NScan(n), a fourth scan line NScan(n-5) and an emission control line EM.

[0069] Here, PScan(n) denotes the current scan line, PScan(n-1) denotes the scan line one level above, and the above scan line is used to control P-type transistors, NScan(n) denotes the current scan line, NScan(n-5) denotes the scan line five levels above, and these two scan lines are used to control N-type transistors.

[0070] The circuit operates as follows: in the first stage, the first reset transistor T4 and the second reset transistor T7 are turned on, the gate of the first transistor T1 is reset by the reset signal output from the first reset signal line VI-G, and the pixel light-emitting unit LED is reset by the reset signal output from the second reset signal line VI-ANO. in the second stage, the second transistor T2 and the third transistor T3 are turned on, and the data signal input from the data line Data is written to the gate of the first transistor T1. in the third stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the pixel light-emitting unit LED is driven to emit light.

[0071] Although the embodiments of the present application have been described in detail using the circuit diagram of FIG. 2 as an example, the embodiments of the present application are not limited thereto, and the design of the present application can also be adopted in a display panel using, for example, a 7T1C (seven transistors and one capacitor) circuit.

[0072] In one embodiment, as shown in FIG. 2, the OLED display panel 2 further includes a substrate 21, a light-shielding layer 22 and a buffer layer 23, where the light-shielding layer 22 is located between the substrate 21 and the buffer layer 23.

[0073] In one embodiment, as shown in FIG. 2 , the width of the projection of the light-shielding layer 22 on the substrate 21 is greater than the maximum width between the trench region of the first semiconductor layer 241 and the trench region of the second semiconductor layer 247, so that the light-shielding layer shields the trench regions of the first semiconductor layer and the second semiconductor layer, and prevents external light from affecting the performance of the first semiconductor layer and the second semiconductor layer.

[0074] In one embodiment, as shown in FIG. 2, the light shielding layer 22 is connected to the first source drain layer 252, and the connection between the light shielding layer and the first source drain layer reduces the impedance of the first source drain layer.

[0075] In one embodiment, as shown in FIG. 2, the OLED display panel 2 further includes a first semiconductor layer 241, a first gate insulating layer 242, a first gate layer 243, a second gate insulating layer 244, a second gate layer 245, a first interlayer insulating layer 246, a second semiconductor layer 247, a third gate insulating layer 248, a third gate layer 249, and a second interlayer insulating layer 251. By using LTPO (Low Temperature Poly-Oxide, LTPO) technology in the OLED display panel, the power consumption of the OLED display panel can be reduced.

[0076] In one embodiment, the material of the first semiconductor layer includes polycrystalline silicon and the material of the second semiconductor layer includes a metal oxide.

[0077] In one embodiment, as shown in FIG. 2, the OLED display panel 2 further includes a third planarization layer 257 , an anode layer 261 , a pixel definition layer 262 , a light emitting material layer 263 and a cathode layer 264 .

[0078] In one embodiment, as shown in FIG. 2, the OLED display panel 2 further includes an encapsulation layer 27, which includes a first inorganic layer, an organic layer, and a second inorganic layer.

[0079] Specifically, FIG. 3 is a film layer design diagram for a single subpixel, and for ease of viewing, only thin film transistors are shown in FIG. 3, and FIG. 4a to FIG. 4n are exploded views of each film layer in the film layer design diagram of FIG. 3, and the structural design of each film layer is described in FIG. 4a to FIG. 4n.

[0080] FIG. 4a is a layer design of the first semiconductor layer. FIG. 4b is a layer design of the first gate layer, where the first gate layer 243 includes a light emission control line 243a and a first scan line 243b. FIG. 4c is a layer design of the second gate layer, where the second gate layer 245 includes a first reset signal line 245a, a first portion 245c of a third scan line and a first portion 245b of a fourth scan line. FIG. 4d is a layer design of the second semiconductor layer, and FIG. 4e is a layer design of the third gate layer, where the third gate layer 249 includes a second portion 249b of a third scan line and a second portion 249a of a fourth scan line. FIG. 4f is a design in which the first source drain layer is connected to the via 251a of the first semiconductor layer, that is, the vias of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer. FIG. 4g shows a design in which the first source drain layer is connected to a via 251b in the second semiconductor layer, ie, a via in the second interlayer insulating layer and the third gate insulating layer.

[0081] FIG. 4h is a layer design of the first source drain layer, where the first source drain layer 252 includes a second reset signal line 252a. FIG. 4i is a design of the via 253a of the first planarization layer. FIG. 4j is a layer design of the second source drain layer, where the second source drain layer 254 includes a data line 254a and a power signal line 254b. FIG. 4k is a design of the via 255a of the second planarization layer. FIG. 4l is a layer design of the third source drain layer, where the third source drain layer 256 includes a fan-out wiring 31 and a dummy wiring 32. FIG. 4m is a design of the via 257a of the third planarization layer. FIG. 4n is a layer design of the anode layer, where the anode layer 261 includes an anode 261a.

[0082] Specifically, the design of the wiring and the vias in each film layer can be determined based on the circuit design in FIG. 9 and the film layer design in FIG. 3, and a duplicated description will be omitted here.

[0083] In addition, since the wiring is described by the film layer diagram and the circuit diagram, the wiring has different symbols, for example, the data line is represented by Data in the circuit diagram and 254a in the film layer diagram, but it is understandable that both are the same data line, and it is only necessary to use different notations in the circuit diagram and the film layer diagram. Similarly, different notations are used for other wiring such as the scanning line, the reset signal line, and the light emission control line, but the duplicated explanation will be omitted here.

[0084] An embodiment of the present application also provides an OLED display device, which includes the OLED display panel according to any one of the above embodiments.

[0085] As can be seen from the above examples, An embodiment of the present application provides an OLED display panel and an OLED display device, the OLED display panel including a display area and a non-display area disposed on one side of the display area, the OLED display panel including signal wiring and fan-out wiring, the fan-out wiring being disposed on one side of the signal wiring and connected to the signal wiring, the OLED display panel including a plurality of sub-pixels including an anode, the anode being disposed on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display area to the display area, the OLED display panel further including a dummy wiring disposed on a side of the anode closer to the signal wiring, the display area including a first area corresponding to a position where the anode is disposed, the first area including at least one fan-out wiring and at least one dummy wiring, and the fan-out wiring passing through each sub-pixel and the dummy wiring passing through each sub-pixel are symmetrical with respect to a center of the anode of each sub-pixel. In the present application, a dummy wiring is arranged near the signal wiring of the anode, and at least one dummy wiring and at least one fan-out wiring are arranged corresponding to the anode arrangement position, so that areas where no fan-out wiring is arranged or areas where the fan-out wiring is uneven can be filled with the dummy wiring, improving the uniformity of the wiring in the display area, and the fan-out wiring passing through each subpixel and the dummy wiring passing through each subpixel are symmetrical with respect to the center of the anode of each subpixel, thereby improving the flatness and symmetry of the anode and improving the flatness of the light-emitting material, thereby matching the visual effects at each viewing angle and improving display defects of the display panel.

[0086] In the above embodiments, the emphasis of the description for each embodiment is different, and for parts that are not described in detail in one embodiment, reference can be made to related descriptions in other embodiments.

[0087] The OLED display panel and the OLED display device provided in the examples of the present application have been described in detail above. In this specification, the principles and embodiments of the present application have been described using specific examples, but the description of the above examples is only for easily understanding the technical solutions of the present application and their main gist, and it is naturally understood that those skilled in the art can modify the technical solutions described in the examples or make equivalent replacements for part of the technical features, and such modifications or equivalent replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the examples of the present application. [Explanation of symbols]

[0088] 2: OLED display panel 21: Substrate 22: Light shielding layer 23: Buffer layer 27: Sealing layer 31: Fan-out routing 32: Dummy wiring 33: Bonding pad 34: Repeating unit 41: Subpixel 111:Display area 112: Bonding area 121: Data line 122: Fan-out routing 131: 1st area 132:Second area 241: First semiconductor layer 242: First gate insulating layer 243: First gate layer 244: Second gate insulating layer 245: Second gate layer 246: First interlayer insulating layer 247: Second semiconductor layer 248: Third gate insulating layer 249: 3rd gate layer 251: Second interlayer insulating layer 252: First source / drain layer 253: First planarization layer 254: Second source / drain layer 255: Second planarization layer 256: Third source / drain layer 257: Third planarization layer 261: Anode layer 262: Pixel definition layer 263: Light-emitting material layer 264: Cathode layer 281:Display area 282: Hidden area 283:First area 284:Second area 285: Third area 286: 4th area 291: Upper bezel 292: Left bezel 293: Lower bezel 294: Right bezel 311: 1st wiring part 312: 2nd wiring part 321: 3rd wiring part 322: 4th wiring part 331: Connection point 411: Blue subpixel 412: Red subpixel 413: Green subpixel 421: Second anode 422: First anode 423: 3rd anode Cst: Holding capacitor T1: First transistor T2: Second transistor T3: Third transistor T4: First reset transistor T5: First light emission control transistor T6: Second light emission control transistor T7: Second reset transistor

Claims

1. 1. An OLED display panel including a display area and a non-display area disposed on one side of the display area, the OLED display panel comprising: Signal wiring, a fan-out wiring arranged on one side of the signal wiring and connected to the signal wiring; the OLED display panel includes a plurality of sub-pixels each including an anode, the anode being disposed on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display area to the display area, the OLED display panel further including a dummy wiring disposed on a side of the anode closer to the signal wiring, the display area including a first area corresponding to a position of the anode, the first area including at least one of the fan-out wiring and at least one of the dummy wiring, and the fan-out wiring passing through each of the sub-pixels and the dummy wiring passing through each of the sub-pixels are symmetrical with respect to a center of the anode of each of the sub-pixels.

2. 2. The OLED display panel of claim 1, comprising an upper bezel, a left bezel, a lower bezel and a right bezel arranged to surround the display area, the fan-out wiring includes a first wiring portion and a second wiring portion, the first wiring portion and the second wiring portion are connected, the first wiring portion is arranged along a direction from the left bezel to the right bezel, and the second wiring portion is arranged along a direction from the lower bezel to the upper bezel, and the display area includes a second region corresponding to a position where the first wiring portion is arranged, a third region corresponding to a position where the second wiring portion is arranged, and a fourth region where the fan-out wiring is not arranged.

3. 3. The OLED display panel of claim 2, wherein at least a portion of the dummy wiring is arranged in the fourth region, and the dummy wiring arranged in the fourth region is separated from the fan-out wiring at a connection point between the fan-out wiring and the signal wiring.

4. 4. The OLED display panel of claim 3, wherein at least a portion of the dummy wirings are arranged in at least one of the second region and the third region, the dummy wirings arranged in the second region and / or the third region are connected to one of the fan-out wirings adjacent to each other, and there is a gap between the dummy wiring and another of the fan-out wirings adjacent to each other.

5. 3. The OLED display panel of claim 2, wherein the length of the first wiring portion decreases along a direction from the lower bezel toward the upper bezel, and the length of the second wiring portion increases along a direction from the left bezel toward a central region of the display area.

6. 6. The OLED display panel of claim 5, wherein the dummy wiring includes a third wiring portion and a fourth wiring portion, the third wiring portion has the same arrangement direction as the first wiring portion, the fourth wiring portion has the same arrangement direction as the second wiring portion, at least a portion of the third wiring portion is connected to the fourth wiring portion, the length of the third wiring portion increases along a direction from the lower bezel to the upper bezel, and the length of the fourth wiring portion decreases from the left bezel to a central region of the display area.

7. 7. The OLED display panel of claim 6, wherein one of the second wiring portions and one of the third wiring portions are arranged to intersect with each other, and there is a gap between the other of the second wiring portions and the third wiring portion.

8. 7. The OLED display panel of claim 6, wherein one of the second wiring portions and one of the third wiring portions are arranged to intersect with each other, and along a direction from the left bezel to the right bezel, another of the second wiring portions and another of the third wiring portions are connected in a corresponding manner, and each of the third wiring portions is spaced apart from each other.

9. 7. The OLED display panel according to claim 6, wherein the dummy wirings and the fan-out wirings are arranged in the same layer, and a distribution density per unit of the dummy wirings is the same as a distribution density per unit of the fan-out wirings.

10. 3. The OLED display panel of claim 2, wherein the subpixels include a red subpixel, a blue subpixel, and a green subpixel, and at least one of the dummy wiring passing through the red subpixel, the dummy wiring passing through the blue subpixel, and the dummy wiring passing through the green subpixel is symmetrical with respect to the center of the anode of the corresponding subpixel.

11. 11. The OLED display panel of claim 10, wherein the red subpixel includes a first anode and the blue subpixel includes a second anode, the dummy wiring passing through the red subpixel is symmetrical with respect to a center of the first anode, and the dummy wiring passing through the blue subpixel is symmetrical with respect to a center of the second anode.

12. 12. The OLED display panel of claim 11, wherein the green subpixel includes a third anode, the dummy wiring passing through the green subpixel is symmetrical with respect to a center of the third anode, and the dummy wiring passing through the green subpixel along a direction from the lower bezel toward the upper bezel is symmetrical with respect to a center line of the third anode.

13. 13. The OLED display panel of claim 12, wherein along a direction from the left bezel to the right bezel, at least a portion of the dummy wiring passing through the green subpixels of an adjacent column extends into the red subpixel, and / or at least a portion of the dummy wiring passing through the green subpixels of an adjacent column extends into the blue subpixel, and the dummy wiring extending into the red subpixel and / or the blue subpixel is separated from the dummy wiring passing through the red subpixel and the blue subpixel.

14. 3. The OLED display panel of claim 2, further comprising a driving circuit layer including a first source-drain layer and a second source-drain layer, the first source-drain layer including the signal wiring, and the second source-drain layer including the fan-out wiring and the dummy wiring.

15. 3. The OLED display panel of claim 2, further comprising a driving circuit layer including a first source-drain layer, a second source-drain layer, and a third source-drain layer, the first source-drain layer including a source and a drain, the second source-drain layer including the signal wiring, and the third source-drain layer including the fan-out wiring and the dummy wiring.

16. 16. The OLED display panel of claim 15, further comprising: a first planarization layer disposed between the first source-drain layer and the second source-drain layer; and a second planarization layer disposed between the second source-drain layer and the third source-drain layer, wherein the signal wiring includes a data line, and the fan-out wiring is connected to the data line by passing through a via in the second planarization layer.

17. 17. The OLED display panel according to claim 16, further comprising a power supply signal line disposed in the second source / drain layer, the dummy wiring passing through a via and connected to the power supply signal line.

18. 1. An OLED display device including an OLED display panel including a display area and a non-display area disposed on one side of the display area, the OLED display panel comprising: Signal wiring, a fan-out wiring arranged on one side of the signal wiring and connected to the signal wiring; an OLED display device, the OLED display panel including a plurality of sub-pixels each including an anode, the anode being disposed on a side of the fan-out wiring farther from the signal wiring, the fan-out wiring extending from the non-display area to the display area, the OLED display panel further including a dummy wiring disposed on a side of the anode closer to the signal wiring, the display area including a first area corresponding to a position of the anode, the first area including at least one of the fan-out wiring and at least one of the dummy wiring, and the fan-out wiring passing through each of the sub-pixels and the dummy wiring passing through each of the sub-pixels being symmetrical with respect to a center of the anode of each of the sub-pixels.

19. 20. The OLED display device of claim 18, wherein the OLED display panel includes an upper bezel, a left bezel, a lower bezel, and a right bezel arranged to surround the display area, the fan-out wiring includes a first wiring portion and a second wiring portion, the first wiring portion and the second wiring portion are connected, the first wiring portion is arranged along a direction from the left bezel to the right bezel, and the second wiring portion is arranged along a direction from the lower bezel to the upper bezel, and the display area includes a second region corresponding to a position where the first wiring portion is arranged, a third region corresponding to a position where the second wiring portion is arranged, and a fourth region where the fan-out wiring is not arranged.

20. 20. The OLED display device of claim 19, wherein at least a portion of the dummy wiring is arranged in the fourth region, and the dummy wiring arranged in the fourth region is separated from the fan-out wiring at a connection point between the fan-out wiring and the signal wiring.

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