Backup power supply device, control method and control program

Abstract

To suppress the number of components and over current occurring when the charging voltage of an electric double layer capacitor is low.SOLUTION: When an input voltage is equal to or more than a first set voltage, a control part performs a control in a first mode to charge an electric double layer capacitor by allowing a first switching element to perform switching operation and by allowing a second switching element to perform switching operation, as a synchronous rectification element, and when the input voltage is less than the first set voltage, the control part performs a control in a second mode to discharge the electric double layer capacitor by allowing the second switching element to perform switching operation and by allowing the first switching element to perform switching operation, as a synchronous rectification element. When the charging voltage of the electric double layer capacitor is less than a second set voltage in the first mode, the control part performs a control in a second switching cycle longer than a first switching cycle in the case where the charging voltage of the electric double layer capacitor is equal to or more than the second set voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a backup power supply device, a control method, and a control program. [Background technology]

[0002] A vehicle is equipped with various devices that operate using power from a battery (e.g., an auxiliary battery). Patent Document 1 describes a backup power supply device for operating the above devices even if the battery is unable to output power due to a traffic accident or the like.

[0003] In the backup power supply device described in Patent Document 1, a coil is shared between a voltage step-up circuit and a voltage step-down circuit, that is, the voltage step-up circuit and the voltage step-down circuit form a voltage step-up / step-down circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6643566 Summary of the Invention [Problem to be solved by the invention]

[0005] The backup power supply device described in Patent Document 1 includes an output rectifier element connected as a current output path from the electric double layer capacitor to the terminal section, with the direction from the boost circuit to the terminal section being the forward direction. However, it is desirable to reduce the number of parts. In addition, when the charging voltage of the electric double layer capacitor is low during the charging mode of the electric double layer capacitor, the current slope when the coil sweeps out energy becomes very gentle, and the coil current hardly drops during the off period of the switching element, and the coil current increases due to switching delays in the next on period of the switching element, and this repetition can result in a large current (overcurrent). It is desirable to suppress this overcurrent while not unnecessarily lengthening the charging current.

[0006] An object of the present invention is to provide a backup power supply device, a control method, and a control program that can reduce the number of parts and suppress overcurrent when the charging voltage of the electric double layer capacitor is low during charging of the electric double layer capacitor. [Means for solving the problem]

[0007] A backup power supply device according to one aspect of the present invention comprises: a terminal section including an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil and having the other end electrically connected to a reference potential; a control unit that performs a first mode control in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on and the second switching element is switched on as a synchronous rectifier element, thereby operating the first switching element, the second switching element, and the coil as a step-up circuit to charge the electric double layer capacitor, and that performs a second mode control in which, when the input voltage is lower than the first set voltage, the second switching element is switched on and the first switching element is switched on and the first switching element is switched on as a synchronous rectifier element, thereby operating the first switching element, the second switching element, and the coil as a step-up circuit to discharge the electric double layer capacitor; Equipped with The control unit is In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. It is characterized by:

[0008] In the backup power supply device, The control unit is The length of the second switching cycle is set to a length obtained by dividing the length of the first switching cycle by N (N is an integer equal to or greater than 2). It is characterized by:

[0009] In the backup power supply device, The control unit is in the first mode, when a charging voltage of the electric double layer capacitor is equal to or higher than the second set voltage, the second switching element is turned off at a second timing when a current flowing through the second switching element becomes zero or is reversed; the signal representing the first timing and the signal representing the second timing are the same signal. It is characterized by:

[0010] A control method according to one aspect of the present invention includes the steps of: A control method for a backup power supply device comprising: a terminal section having an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; and a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil, and the other end electrically connected to a reference potential, a first mode control is performed in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on based on a current flowing through the first switching element and a charging voltage of the electric double layer capacitor, and the second switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to charge the electric double layer capacitor; and a second mode control is performed in which, when the input voltage is lower than the first set voltage, the second switching element is switched on based on a current flowing through the second switching element and an output voltage output from the output terminal, and the first switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to discharge the electric double layer capacitor; In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. It is characterized by:

[0011] A control program according to one embodiment of the present invention comprises: a terminal section having an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; and a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil, and the other end electrically connected to a reference potential, a first mode control is performed in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on based on a current flowing through the first switching element and a charging voltage of the electric double layer capacitor, and the second switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to charge the electric double layer capacitor; and a second mode control is performed in which, when the input voltage is lower than the first set voltage, the second switching element is switched on based on a current flowing through the second switching element and an output voltage output from the output terminal, and the first switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to discharge the electric double layer capacitor; In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. The processing device is caused to execute the above. Effect of the Invention

[0012] The backup power supply device, control method, and control program according to one aspect of the present invention have the advantage of being able to reduce the number of parts and to suppress overcurrent when the charging voltage of the electric double layer capacitor is low during charging of the electric double layer capacitor. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a backup power supply device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of a battery voltage drop monitor and a mode switching timing adjuster of the backup power supply device according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing a circuit configuration of a switching frequency setting unit of the backup power supply device according to the embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a sawtooth wave signal and a periodic pulse signal of the backup power supply device according to the embodiment. [Diagram 5] FIG. 5 is a diagram showing a circuit configuration of a switching current detection unit of the backup power supply device according to the embodiment. [Figure 6] FIG. 6 is a diagram showing a circuit configuration of a current information detector of the backup power supply device according to the embodiment. [Figure 7] FIG. 7 is a diagram illustrating a circuit configuration of an overvoltage detection unit of the backup power supply device according to the embodiment. [Figure 8] FIG. 8 is a diagram illustrating a circuit configuration of an output voltage error detection unit of the backup power supply device according to the embodiment. [Figure 9] FIG. 9 is a diagram illustrating a configuration of an on-timing control unit of the backup power supply device according to the embodiment. [Figure 10] FIG. 10 is a diagram illustrating the operation timing of the control unit of the backup power supply device according to the embodiment. [Figure 11]FIG. 11 is a diagram illustrating the operation timing of the control unit of the backup power supply device according to the embodiment. [Figure 12] FIG. 12 is a diagram illustrating the operation timing of the control unit of the backup power supply device according to the embodiment. [Figure 13] FIG. 13 is a diagram illustrating the operation timing of the control unit of the backup power supply device according to the embodiment. [Figure 14] FIG. 14 is a diagram illustrating an example of a sawtooth wave signal, a current information signal, an error signal, and a main switching control signal of the backup power supply device according to the embodiment. [Figure 15] FIG. 15 is a diagram illustrating a circuit configuration of a drive selection unit of the backup power supply device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A backup power supply device, a control method, and a control program according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiment.

[0015] <Embodiment Mode> FIG. 1 is a diagram illustrating a configuration of a backup power supply device according to an embodiment.

[0016] Backup power supply 1 is connected to battery 2's voltage V IN When the input voltage is equal to or greater than a predetermined input voltage threshold, the electric double layer capacitor 3 is charged using power supplied from the battery 2 via the input terminals 1a and 1b.

[0017] The input voltage threshold corresponds to an example of a "first set voltage" in the present disclosure.

[0018] Backup power supply 1 is connected to battery 2's voltage V IN When the input voltage threshold is less than the input voltage threshold, a DC voltage is output from the output terminal 1c using the power stored in the electric double layer capacitor 3. The power output from the output terminal 1c is supplied to an electronic device (not shown).

[0019] The battery 2 is exemplified by an auxiliary battery mounted on a vehicle, but the present disclosure is not limited thereto. IN The input voltage threshold is exemplified as 9 V, but the present disclosure is not limited thereto.

[0020] Backup power supply 1 is connected from resistor R1 to resistor R 12 The power supply includes a capacitor C1, an electric double layer capacitor 3, a step-up / step-down circuit 4, a terminal unit 5, and a control unit 10. The step-up / step-down circuit 4 includes switching elements Q1 and Q2, and a coil L1. The terminal unit 5 includes input terminals 1a and 1b, an output terminal 1c, and a diode D1.

[0021] The input terminal 1a is electrically connected to a high potential end of the battery 2. The input terminal 1b is electrically connected to a low potential end of the battery 2. The low potential end of the battery 2 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0022] One end of the resistor R1 is electrically connected to the high-potential input terminal 1a. The other end of the resistor R1 is electrically connected to one end of the resistor R2. The other end of the resistor R2 is electrically connected to the low-potential input terminal 1b. The resistors R1 and R2 are connected to a voltage V IN The voltage V1 obtained by dividing the voltage V1 by resistors is output to the control unit 10. In other words, V1=V IN ÷(R1+R2)×R2.

[0023] The anode of the diode D1 is electrically connected to the input terminal 1a, and the cathode of the diode D1 is electrically connected to the node N1.

[0024] The node N1 corresponds to an example of a "connection point" in the present disclosure.

[0025] Diode D1 is connected to the voltage V IN is the voltage V at node N1 N1If the voltage V is higher than the threshold voltage V, the diode D1 passes current from the battery 2 to the node N1. IN is the voltage V N1 If it is lower than this, the current flowing from the node N1 to the battery 2 is cut off.

[0026] One end of the capacitor C1 is electrically connected to the node N1. The other end of the capacitor C1 is electrically connected to the input terminal 1b. The capacitor C1 is connected to a voltage V N1 Stabilize and smooth the

[0027] When the backup power supply 1 charges the electric double layer capacitor 3, the voltage V N1 is the input voltage, i.e., the voltage V IN When the backup power supply device 1 discharges the electric double layer capacitor 3, the voltage V N1 is the output voltage.

[0028] One end of the resistor R3 is electrically connected to the node N1. The other end of the resistor R3 is electrically connected to one end of the resistor R4. The other end of the resistor R4 is electrically connected to the input terminal 1b. The resistors R3 and R4 are connected to a voltage V N1 The voltage V2 obtained by dividing the voltage V2 by resistors is output to the control unit 10. In other words, V2=V N1 ÷(R3+R4)×R4.

[0029] When the backup power supply 1 charges the electric double layer capacitor 3, the voltage V2 is the input voltage, that is, the voltage V IN (=Voltage V N1 When the backup power supply device 1 discharges the electric double layer capacitor 3, the voltage V2 is proportional to the output voltage, that is, the voltage V N1 is a voltage proportional to

[0030] One end of the resistor R5 is electrically connected to the node N1. The other end of the resistor R5 is electrically connected to the drain of the switching element Q1. A voltage V6 at one end of the resistor R5 and a voltage V7 at the other end of the resistor R5 are input to the control unit 10.

[0031] The source of the switching element Q1 is electrically connected to one end of the coil L1. A switching control signal S1 is input to the gate of the switching element Q1 from the control unit 10 via a resistor R6.

[0032] The switching element Q1 corresponds to an example of a "first switching element" in the present disclosure.

[0033] In the present disclosure, each switching element is a MOSFET, but is not limited to this. Each switching element may be a silicon power device, a GaN power device, a SiC power device, an IGBT (Insulated Gate Bipolar Transistor), or the like.

[0034] Each switching element has a parasitic diode (body diode). A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET. The parasitic diode can be used as a freewheeling diode to release the transient back electromotive force when the transistor is turned off.

[0035] The control unit 10 can detect the current flowing between the drain and source of the switching element Q1 based on the voltage across the resistor R5, that is, the difference between the voltage V6 and the voltage V7.

[0036] In the embodiment, the backup power supply device 1 is provided with the resistor R5, but the present disclosure is not limited to this. The control unit 10 may detect the current flowing between the drain and source of the switching element Q1 based on the voltage between the drain and source of the switching element Q1. In this case, the backup power supply device 1 does not need to include the resistor R5. However, the on-resistance of the switching element Q1 changes more with temperature than the resistor R5. Therefore, when high accuracy is required, the backup power supply device 1 may include the resistor R5, and when high accuracy is not required, the on-resistance of the switching element Q1 may be used.

[0037] The drain of the switching element Q2 is electrically connected to the source of the switching element Q1 and one end of the coil L1. The source of the switching element Q2 is electrically connected to one end of a resistor R8. The other end of the resistor R8 is electrically connected to the input terminal 1b. A switching control signal S2 is input to the gate of the switching element Q2 from the control unit 10 via a resistor R7.

[0038] The switching element Q2 corresponds to an example of a "second switching element" of the present disclosure.

[0039] One end of the resistor R9 is electrically connected to the source of the switching element Q2 and one end of the resistor R8. A voltage V4 at the source of the switching element Q2 and one end of the resistor R8 is input to the control unit 10 via the resistor R9.

[0040] Resistance R 10 One end of the resistor R8 is electrically connected to the source of the switching element Q2 and one end of the resistor R8. 10 The signal is input to the control unit 10 via the

[0041] The control unit 10 can detect the current flowing between the drain and source of the switching element Q2 based on the voltage across the resistor R8, that is, the voltage V4 or the voltage V5.

[0042] In the embodiment, the backup power supply 1 is provided with the resistor R8, but the present disclosure is not limited to this. The control unit 10 may detect the current flowing between the drain and source of the switching element Q2 based on the voltage between the drain and source of the switching element Q2. In this case, the backup power supply 1 does not need to include the resistor R8. However, the on-resistance of the switching element Q2 has a larger temperature change than the resistor R8. Therefore, when high accuracy is required, the backup power supply 1 may include the resistor R8, and when high accuracy is not required, the on-resistance of the switching element Q2 may be used.

[0043] The other end of the coil L1 is electrically connected to one end (high potential end) of the electric double layer capacitor 3. The other end (low potential end) of the electric double layer capacitor 3 is electrically connected to the input terminal 1b.

[0044] Resistance R 11 One end of the resistor R is electrically connected to one end of the electric double layer capacitor 3. 11 The other end of the resistor R 12 It is electrically connected to one end of the resistor R 12 The other end of the resistor R is electrically connected to the other end of the electric double layer capacitor 3. 11 and resistor R 12 is the voltage V of the electric double layer capacitor 3 EDLC The voltage V3 obtained by dividing the voltage V3 by resistors is output to the control unit 10. In other words, V3=V EDLC ÷(R 11 +R 12 )×R 12 It is.

[0045] The control unit 10 controls the step-up / step-down circuit 4 based on the voltages V1 to V7.

[0046] In a mode in which the electric double layer capacitor 3 is charged (hereinafter referred to as the “first mode”), the control unit 10 controls the voltage V IN In the first mode, the step-up / step-down circuit 4 is controlled so as to step down the voltage V IN and the output voltage is V EDLC It is.

[0047] In the first mode, the control unit 10 operates the switching element Q1 and the coil L1 as a step-down circuit. In the first mode, the control unit 10 also operates the switching element Q1 as a main switching element and the switching element Q2 as a synchronous rectification element.

[0048] In a mode in which the electric double layer capacitor 3 is discharged (hereinafter referred to as the “second mode”), the control unit 10 controls the voltage V EDLCIn the second mode, the input voltage of the step-up / step-down circuit 4 is controlled to be boosted and output to the output terminal 1c. EDLC and the output voltage is V N1 It is.

[0049] In the second mode, the control unit 10 operates the switching element Q2 and the coil L1 as a boost circuit. In the second mode, the control unit 10 also operates the switching element Q2 as a main switching element and the switching element Q1 as a synchronous rectifier element.

[0050] The control unit 10 includes a battery voltage drop monitoring unit 11, a mode switching timing adjustment unit 12, a switching frequency setting unit 13, a switching current detection unit 14, a current information detection unit 15, an overvoltage detection unit 16, an output voltage error detection unit 17, an on / off control unit 18, a drive selection unit 19, a first level shift unit 20, a second level shift unit 21, an on timing control unit 22, and gate drive circuits B1 and B2.

[0051] The battery voltage drop monitor 11 detects the voltage V of the battery 2 based on the voltage V1. IN The mode switching timing adjustment unit 12 monitors whether the input voltage drops below the input voltage threshold value. Based on the output signal from the battery voltage drop monitoring unit 11, the mode switching timing adjustment unit 12 adjusts the mode signal S representing the first mode or the second mode. MODE is switched at the beginning of the switching period.

[0052] FIG. 2 is a diagram showing a circuit configuration of a battery voltage drop monitor and a mode switching timing adjuster of the backup power supply device according to the embodiment.

[0053] The battery voltage drop monitoring unit 11 includes a comparator 31 and a constant voltage source 32. The voltage of the constant voltage source 32 is input to a non-inverting input terminal (+ terminal) of the comparator 31. The voltage of the constant voltage source 32 is a voltage according to an input voltage threshold. More specifically, the voltage of the constant voltage source 32 is ((input voltage threshold)÷(R1+R2)×R2). A voltage V1 is input to an inverting input terminal (- terminal) of the comparator 31.

[0054] The comparator 31 outputs a low-level signal when the voltage V1 is equal to or higher than the voltage of the constant voltage source 32. IN If the input voltage is equal to or greater than the input voltage threshold, a low level signal is output.

[0055] On the other hand, when the voltage V1 is lower than the voltage of the constant voltage source 32, the comparator 31 outputs a high-level signal. IN If the input voltage threshold is less than the input voltage threshold, it outputs a high level signal.

[0056] The mode switching timing adjustment unit 12 includes a D-type flip-flop 41 and a one-shot circuit .

[0057] The output signal of the comparator 31 is input to a D terminal (signal input terminal) of the D-type flip-flop 41.

[0058] The one-shot circuit 42 outputs a periodic pulse signal S OSC At the timing when the signal (described later) changes from low level to high level, a one-shot pulse is output to a T terminal (trigger input terminal) of a D-type flip-flop 41.

[0059] The D-type flip-flop 41 receives the output signal of the comparator 31 at the timing when the one-shot pulse input from the one-shot circuit 42 changes from low level to high level. The D-type flip-flop 41 outputs a mode signal S indicating the mode from an inverting output terminal (Q-bar terminal). MODE Output.

[0060] Mode signal S MODE When it is at a high level, it indicates the first mode (charging mode), and when it is at a low level, it indicates the second mode (discharging mode).

[0061] Referring again to FIG. 1, the switching frequency setting unit 13 receives a mode signal S MODE Based on this, a periodic pulse signal S representing the switching frequency is generated. OSC Output.

[0062] FIG. 3 is a diagram showing a circuit configuration of a switching frequency setting unit of the backup power supply device according to the embodiment.

[0063] The switching frequency setting unit 13 includes NOT gate circuits (inverting circuits) 51 and 61, constant current sources 52, 53, 56 and 57, transfer gate circuits 54, 55, 58, 64 and 65, a capacitor 59, a comparator 60, and constant voltage sources 62 and 63.

[0064] The switching frequency setting unit 13 corresponds to an example of a "sawtooth wave generating circuit" of the present disclosure.

[0065] The NOT gate circuit 51 receives the mode signal S MODE The transfer gate circuits 54 and 58 invert the mode signal S MODE is in the off state when the mode signal S MODE is at low level (second mode), the switch is turned on.

[0066] The low potential end of the capacitor 59 is electrically connected to the reference potential.

[0067] The constant current source 52 is electrically connected between a power supply potential VDD and the high potential side end of the capacitor 59 .

[0068] One end of the constant current source 53 is electrically connected to the power supply potential VDD. The other end of the constant current source 53 is electrically connected to the high potential side end of the capacitor 59 via the transfer gate circuit 54.

[0069] Mode signal S MODE When the mode signal S is at a high level (first mode), the transfer gate circuit 54 is turned off. Therefore, the capacitor 59 is charged only by the constant current source 52. MODE When the mode signal S is at a low level (second mode), the transfer gate circuit 54 is turned on. Therefore, the capacitor 59 is charged by both the constant current sources 52 and 53. That is, the capacitor 59 is charged by the mode signal S MODE The charging current changes according to the signal value, so the speed at which the voltage rises changes.

[0070] The voltage at the high potential end of the capacitor 59 is the sawtooth signal S SAW It is.

[0071] An inverting input terminal (- terminal) of the comparator 60 is electrically connected to the high potential side end of the capacitor 59. A non-inverting input terminal (+ terminal) of the comparator 60 is electrically connected to a constant voltage source 62 via a transfer gate circuit 64, and is also electrically connected to a constant voltage source 63 via a transfer gate circuit 65.

[0072] The transfer gate circuit 64 is turned on when the output signal of the comparator 60 is at a high level, and is turned off when the output signal of the comparator 60 is at a low level.

[0073] The NOT gate circuit 61 inverts the output signal of the comparator 60 and outputs it to the transfer gate circuits 55 and 65. Therefore, the transfer gate circuits 55 and 65 are turned off when the output signal of the comparator 60 is at a high level, and are turned on when the output signal of the comparator 60 is at a low level.

[0074] The comparator 60 outputs a high-level signal when the voltage of the capacitor 59 is less than the reference voltage (the voltage of the constant voltage source 62 or 63). When the output signal of the comparator 60 is at a high level, the transfer gate circuit 64 is turned on, so that the voltage of the constant voltage source 62 is input to the non-inverting input terminal of the comparator 60 as the reference voltage.

[0075] The comparator 60 outputs a low-level signal when the voltage of the capacitor 59 is equal to or higher than the reference voltage (the voltage of the constant voltage source 62 or 63). When the output signal of the comparator 60 is at a low level, the transfer gate circuit 65 is turned on, so that the voltage of the constant voltage source 63 is input to the non-inverting input terminal of the comparator 60 as the reference voltage.

[0076] In other words, the reference voltage of the comparator 60 is different when the output signal changes from a low level to a high level from when the output signal changes from a high level to a low level.

[0077] The output signal of the comparator 60 is a periodic pulse signal S OSC It is.

[0078] One end of the transfer gate circuit 55 is electrically connected to the high potential end of the capacitor 59 .

[0079] The constant current source 56 is electrically connected between the other end of the transfer gate circuit 55 and the reference potential.

[0080] One end of the transfer gate circuit 58 is electrically connected to the other end of the transfer gate circuit 55 .

[0081] The constant current source 57 is electrically connected between the transfer gate circuit 58 and the reference potential.

[0082] Mode signal S MODE When the mode signal S is at a high level (first mode), the capacitor 59 is discharged only by the constant current source 56. MODEWhen the mode signal S is at a low level (second mode), the transfer gate circuit 58 is turned on. Therefore, the capacitor 59 is discharged by both the constant current sources 56 and 57. That is, the capacitor 59 is discharged by the mode signal S MODE Since the discharge current changes according to the signal value, the speed at which the voltage drops changes.

[0083] In summary, the capacitor 59 is MODE When the sawtooth signal S is at a high level (first mode), the charge and discharge speed is relatively slow. SAW and a periodic pulse signal S OSC The frequency of the signal is relatively low.

[0084] On the other hand, the capacitor 59 is connected to the mode signal S MODE When the voltage Vcc is low (second mode), the charge and discharge speed is relatively fast. Therefore, the sawtooth signal S SAW and a periodic pulse signal S OSC The frequency of the signal is relatively high.

[0085] FIG. 4 is a diagram illustrating an example of a sawtooth wave signal and a periodic pulse signal of the backup power supply device according to the embodiment.

[0086] Sawtooth signal S SAW starts rising from time t0. The sawtooth signal S SAW The rising speed of the periodic pulse signal S depends on the current value of the constant current sources 52 and 53. OSC becomes high level at timing t0.

[0087] Periodic pulse signal S OSC is the sawtooth signal S SAW is the voltage V 100 At timing t1 when the periodic pulse signal S OSC When goes low, the reference voltage V 100 (the voltage of the constant voltage source 62) to the voltage V 101 (the voltage of the constant voltage source 63). SAWThe sawtooth signal S starts to fall at time t1. SAW The speed at which this signal falls depends on the current values ​​of the constant current sources 56 and 57.

[0088] Periodic pulse signal S OSC is the sawtooth signal S SAW is the voltage V 101 At time t2 when the periodic pulse signal S OSC When goes high, the reference voltage becomes voltage V 101 to voltage V 100 The sawtooth signal S SAW starts to rise from timing t2.

[0089] Referring back to FIG. 1, the first level shift unit 20 level-shifts the voltages V6 and V7 to a ground level voltage and outputs the voltages to the switching current detection unit 14.

[0090] The switching current detection unit 14 detects, based on the voltages after the voltages V6 and V7 have been level-shifted, that the current flowing through the resistor R5, i.e., the drain-source current of the switching element Q1, has reached zero or has reversed.

[0091] Furthermore, the switching current detection unit 14 detects, based on the voltage V4, that the current flowing through the resistor R8, that is, the drain-source current of the switching element Q2, has reached zero or has reversed.

[0092] In the first mode, the switching current detection unit 14 outputs an inversion detection signal S when the current flowing between the drain and source of the switching element Q2, which is a synchronous rectifier element, reaches zero or inverts. REV is output to the on / off control unit 18.

[0093] In the second mode, the switching current detection unit 14 outputs an inversion detection signal S when the current flowing between the drain and source of the switching element Q1, which is a synchronous rectifier element, reaches zero or is inverted. REV is output to the on / off control unit 18.

[0094] FIG. 5 is a diagram showing a circuit configuration of a switching current detection unit of the backup power supply device according to the embodiment.

[0095] The switching current detection unit 14 includes comparators 121 and 122 , transfer gate circuits 123 and 124 , and a NOT gate circuit 125 .

[0096] The inverting input terminal (- terminal) of the comparator 121 is electrically connected to a reference potential. The output signal of the first level shift section 20 is input to the non-inverting input terminal (+ terminal) of the comparator 121. The comparator 121 outputs a high-level signal when the output signal of the first level shift section 20 is greater than zero, and outputs a low-level signal when the output signal of the first level shift section 20 is equal to or less than zero.

[0097] The inverting input terminal (- terminal) of the comparator 122 is electrically connected to a reference potential. A voltage V4 is input to the non-inverting input terminal (+ terminal) of the comparator 122. The comparator 122 outputs a high-level signal when the voltage V4 is greater than zero, and outputs a low-level signal when the voltage V4 is equal to or less than zero.

[0098] The NOT gate circuit 125 receives the mode signal S MODE is inverted and output to the transfer gate circuit 124.

[0099] The transfer gate circuit 123 receives the mode signal S MODE When the output signal of the comparator 121 is at a high level, the inversion detection signal S REV The output is as follows:

[0100] The transfer gate circuit 124 receives the mode signal S MODE When the output signal of the comparator 122 is at a low level, the inversion detection signal S REV The output is as follows:

[0101] Referring back to FIG. 1, the second level shift unit 21 shifts the levels of the voltages V6 and V7 to a ground level voltage and outputs the voltages to the current information detection unit 15.

[0102] In the first mode, the current information detector 15 detects current information about the drain-source current of the switching element Q1, which is the main switching element.

[0103] In the second mode, the current information detector 15 detects current information about the drain-source current of the switching element Q2, which is the main switching element.

[0104] FIG. 6 is a diagram showing a circuit configuration of a current information detector of the backup power supply device according to the embodiment.

[0105] The current information detection unit 15 includes a first voltage-current conversion unit 71, diodes 72, 75, and 79, a resistor 73, a second voltage-current conversion unit 74, a NOT gate circuit 77, transfer gate circuits 76 and 80, and a third voltage-current conversion unit 78.

[0106] The first voltage-to-current converter 71 converts the sawtooth wave signal S SAW The voltage is converted into a current and output.

[0107] The anode of the diode 72 is electrically connected to the first voltage-current converter 71. The cathode of the diode 72 is electrically connected to one end of the resistor 73. The connection point between the cathode of the diode 72 and one end of the resistor 73 is a node N2. The other end of the resistor 73 is electrically connected to the reference potential.

[0108] The voltage at node N2 is the current information signal S CINFO It is.

[0109] The second voltage-to-current converter 74 converts the voltages V6 and V7 that have been level-shifted into currents and outputs them.

[0110] The anode of the diode 75 is electrically connected to the second voltage-current converter 74. The cathode of the diode 75 is electrically connected to the node N2.

[0111] The transfer gate circuit 76 is electrically connected between the anode of the diode 75 and a reference potential.

[0112] The NOT gate circuit 77 receives the mode signal S MODE The transfer gate circuit 76 inverts the mode signal S MODE is in the off state when the mode signal S MODE is at low level (second mode), the switch is turned on.

[0113] When the transfer gate circuit 76 is in the off state, the output current of the second voltage-to-current converter 74 flows to the node N2 via the diode 75. When the transfer gate circuit 76 is in the on state, the output current of the second voltage-to-current converter 74 flows to the reference potential.

[0114] The third voltage-current converter 78 converts the voltage V5 into a current and outputs it.

[0115] The anode of the diode 79 is electrically connected to the third voltage-current converter 78. The cathode of the diode 79 is electrically connected to the node N2.

[0116] The transfer gate circuit 80 is electrically connected between the anode of the diode 79 and a reference potential.

[0117] The transfer gate circuit 80 receives the mode signal S MODE is high (first mode), the mode signal S MODE is at low level (second mode), the switch is turned off.

[0118] When the transfer gate circuit 80 is in an on state, the output current of the third voltage-to-current converter 78 flows to the reference potential. When the transfer gate circuit 80 is in an off state, the output current of the third voltage-to-current converter 78 flows to the node N2 via the diode 79.

[0119] To summarize the above, the mode signal S MODE When the current information signal S is at a high level (first mode), the sum of the output current of the first voltage-to-current converter 71 and the output current of the second voltage-to-current converter 74 flows through the node N2. CINFO is the sawtooth signal S SAW This signal is generated by adding information about the drain-source current of the switching element Q1, which is the main switching element, to the above.

[0120] On the other hand, the mode signal S MODE When the current information signal S is at a low level (second mode), the sum of the output current of the first voltage-to-current converter 71 and the output current of the third voltage-to-current converter 78 flows through the node N2. CINFO is the sawtooth signal S SAW This signal is generated by adding information about the drain-source current of the switching element Q2, which is the main switching element, to the above-mentioned signal.

[0121] Referring again to FIG. 1, in the first mode, the overvoltage detection unit 16 detects the output voltage of the step-up / step-down circuit 4 (voltage V EDLC ) detects an overvoltage, the overvoltage detection signal S OVP Output.

[0122] In the second mode, the overvoltage detection unit 16 detects the output voltage of the step-up / step-down circuit 4 (voltage V N1 ) detects an overvoltage, the overvoltage detection signal S OVP Output.

[0123] FIG. 7 is a diagram illustrating a circuit configuration of an overvoltage detection unit of the backup power supply device according to the embodiment.

[0124] The overvoltage detection unit 16 includes a comparator 101, constant voltage sources 102 and 103, transfer gate circuits 104, 105, 106 and 107, and a NOT gate circuit .

[0125] The comparator 101 corresponds to an example of an "overvoltage protection circuit" of the present disclosure.

[0126] An inverting input terminal (− terminal) of the comparator 101 is electrically connected to a constant voltage source 102 via a transfer gate circuit 104 , and is also electrically connected to a constant voltage source 103 via a transfer gate circuit 105 .

[0127] The voltage of the constant voltage source 102 is the output voltage of the step-up / step-down circuit 4 in the first mode (voltage V EDLC In detail, the voltage of the constant voltage source 102 is a voltage according to a first overvoltage threshold, which is an overvoltage threshold of ((first overvoltage threshold)÷(R 11 +R 12 )×R 12 ).

[0128] The voltage of the constant voltage source 103 is the output voltage of the step-up / step-down circuit 4 in the second mode (voltage V N1 ) is an overvoltage threshold. In detail, the voltage of the constant voltage source 103 is ((second overvoltage threshold)÷(R3+R4)×R4).

[0129] The NOT gate circuit 108 outputs the mode signal S MODE is inverted and output to the transfer gate circuits 105 and 107.

[0130] The transfer gate circuit 104 receives the mode signal S MODE When the mode signal S is at a high level (first mode), it is turned on. MODE When is at low level (second mode), it is in the off state.

[0131] The transfer gate circuit 105 receives the mode signal S MODEis at a high level (first mode), the mode signal S MODE When is at low level (second mode), it is turned on.

[0132] A voltage V3 is input to a non-inverting input terminal (+ terminal) of the comparator 101 via a transfer gate circuit 106. In addition, a voltage V2 is input to a non-inverting input terminal of the comparator 101 via a transfer gate circuit 107.

[0133] The transfer gate circuit 106 receives the mode signal S MODE When the mode signal S is at a high level (first mode), it is turned on. MODE When is at low level (second mode), it is in the off state.

[0134] The transfer gate circuit 107 receives the mode signal S MODE is at a high level (first mode), the mode signal S MODE When is at low level (second mode), it is turned on.

[0135] In summary, in the first mode, when the voltage V3 is equal to or higher than the voltage of the constant voltage source 102, that is, when the voltage V EDLC is equal to or greater than the first overvoltage threshold, a high-level overvoltage detection signal S OVP In the second mode, when the voltage V2 is equal to or higher than the voltage of the constant voltage source 103, that is, when the voltage V N1 is equal to or greater than the second overvoltage threshold, a high-level overvoltage detection signal S OVP Output.

[0136] Referring again to FIG. 1, in the first mode, the output voltage error detection unit 17 detects the output voltage of the step-up / step-down circuit 4 (voltage V EDLC ) and the target voltage. ERR Output.

[0137] In the second mode, the output voltage error detection unit 17 detects the output voltage of the step-up / step-down circuit 4 (voltage V N1 ) and the target voltage. ERR Output.

[0138] FIG. 8 is a diagram illustrating a circuit configuration of an output voltage error detection unit of the backup power supply device according to the embodiment.

[0139] The output voltage error detection unit 17 includes error amplifiers (operational amplifiers) 81 and 85, constant voltage sources 82 and 86, resistors 83 and 87, capacitors 84 and 88, transfer gate circuits 89 and 90, and a NOT gate circuit 91.

[0140] The voltage of a constant voltage source 82 is input to a non-inverting input terminal (+ terminal) of the error amplifier 81. The voltage of the constant voltage source 82 is the output voltage (voltage V N1 In detail, the voltage of the constant voltage source 82 is a voltage corresponding to the target voltage ((voltage V N1 The target voltage is (R3+R4)÷(R4)×R4).

[0141] A voltage V2 is input to an inverting input terminal (negative terminal) of the error amplifier 81. Negative feedback is applied between the inverting input terminal and the output terminal of the error amplifier 81 by a resistor 83 and a capacitor 84. The error amplifier 81 outputs a voltage corresponding to the difference voltage between the voltage of a constant voltage source 82 and the voltage V2.

[0142] The voltage of a constant voltage source 86 is input to a non-inverting input terminal (+ terminal) of the error amplifier 85. The voltage of the constant voltage source 86 is the output voltage (voltage V EDLC In detail, the voltage of the constant voltage source 86 is a voltage corresponding to the target voltage of ((voltage V EDLC Target voltage of R 11 +R 12 )×R 12 ).

[0143] A voltage V3 is input to an inverting input terminal (negative terminal) of the error amplifier 85. Negative feedback is applied between the inverting input terminal and the output terminal of the error amplifier 85 by a resistor 87 and a capacitor 88. The error amplifier 85 outputs a voltage corresponding to the difference voltage between the voltage of a constant voltage source 86 and the voltage V3.

[0144] The NOT gate circuit 91 receives the mode signal S MODE The transfer gate circuit 89 inverts the mode signal S MODE is in the off state when the mode signal S MODE is at low level (second mode), the switch is turned on.

[0145] The transfer gate circuit 90 receives the mode signal S MODE is high (first mode), the mode signal S MODE is at low level (second mode), the switch is turned off.

[0146] In summary, the output voltage error detector 17 operates in response to the mode signal S MODE When the voltage V3 is at a high level (first mode), a voltage corresponding to the difference between the voltage V3 and the voltage of the constant voltage source 86 is output as the error signal S ERR That is, the output voltage error detector 17 outputs the voltage V EDLC and the target voltage (e.g., 3 V), the error signal S ERR Output.

[0147] On the other hand, the output voltage error detector 17 detects the mode signal S MODE When the voltage V2 is at a low level (second mode), a voltage corresponding to the difference between the voltage V2 and the voltage of the constant voltage source 82 is represented by the error signal S ERR That is, the output voltage error detector 17 outputs the voltage V N1 and the target voltage (for example, 12 V), the error signal S ERR Output.

[0148] Referring again to FIG. 1, the on-timing control section 22 generates a periodic pulse signal S OSC , inversion detection signal S REV and the on-timing control signal S OTMG is output to the on / off control unit 18.

[0149] In the first mode, when the electric double layer capacitor 3 is at a low voltage, the current slope (downward sloping slope) when the coil L1 discharges energy becomes very gentle, and the current in the coil L1 hardly drops during the off period of the switching element Q1. The current in the coil L1 increases due to switching delays in the next on period of the switching element Q1, and this repetition can result in a large current (overcurrent). The on-timing control unit 22 suppresses this overcurrent.

[0150] FIG. 9 is a diagram illustrating a configuration of an on-timing control unit of the backup power supply device according to the embodiment.

[0151] The on-timing control unit 22 includes a first one-shot circuit 141, a second one-shot circuit 142, a counter 143, a low-voltage detection unit 144, a NOT gate circuit 145, AND gate circuits 146 and 147, and an OR gate circuit 148.

[0152] The first one-shot circuit 141 receives a periodic pulse signal S OSC The first one-shot circuit 141 receives the periodic pulse signal S OSC When the first one-shot signal S changes from low to high, SHT1 The first one-shot signal S SHT1 The pulse width of the main switching control signal S output from the on / off control unit 18 corresponds to the dead time. SW1 and the synchronous rectification switching control signal S SW2 This circuit keeps both inputs low to prevent current from flowing through.

[0153] The second one-shot circuit 142 receives the first one-shot signal SSHT1 The first one-shot circuit 141 receives the first one-shot signal S SHT1 When the second one-shot signal S changes from high to low, SHT2 Output.

[0154] The counter 143 receives the first one-shot signal S SHT1 The counter 143 receives the first one-shot signal S SHT1 When the count signal S is generated, the count signal S CNT That is, the counter 143 outputs the first one-shot signal S SHT1 Divide by N.

[0155] In an embodiment, counter 143 is a 3-bit cycle counter that counts from "0" to "7", although this disclosure is not so limited.

[0156] The counter 143 also receives the inversion detection signal S REV The counter 143 receives the inversion detection signal S REV When this is input, the current count value is reset (cleared).

[0157] The low voltage detection unit 144 detects the voltage V of the electric double layer capacitor 3 based on the voltage V3. EDLC The low voltage detection unit 144 monitors whether the voltage V of the electric double layer capacitor 3 is less than the low voltage threshold. EDLC is less than the low voltage threshold, the low voltage detection signal S LV Output.

[0158] The low voltage threshold corresponds to an example of a "second set voltage" in the present disclosure.

[0159] The NOT gate circuit 145 outputs the low voltage detection signal S LV The inverted signal S 10 Output.

[0160] The AND gate circuit 146 receives the count signal S CNT, low voltage detection signal S LV and the second one-shot signal S SHT2 The AND gate circuit 146 receives the count signal S CNT , low voltage detection signal S LV and the second one-shot signal S SHT2 The signal S is the result of the logical AND operation of 11 Output.

[0161] The AND gate circuit 147 receives the second one-shot signal S SHT2 and signal S 10 The AND gate circuit 147 receives the second one-shot signal S SHT2 and signal S 10 The signal S is the result of the logical AND operation of 12 Output.

[0162] The OR gate circuit 148 receives the signal S 11 and signal S 12 The OR gate circuit 148 receives the signal S 11 and signal S 12 The on-timing control signal S OTMG Output.

[0163] The on / off control unit 18 receives the on-timing control signal S OTMG When the main switching control signal S SW1 Output.

[0164] 10 to 13 are diagrams showing the operation timing of the control unit of the backup power supply device according to the embodiment.

[0165] FIG. 10 shows the voltage V of the electric double layer capacitor 3 in the first mode. EDLC is equal to or higher than the low voltage threshold and the current in the coil L1 is in continuous operation without interruption.

[0166] Voltage V of electric double layer capacitor 3 EDLC is equal to or greater than the low voltage threshold, the low voltage detection unit 144 outputs a low-level low voltage detection signal SLV Therefore, the AND gate circuit 146 outputs a low level signal S 11 The AND gate circuit 147 outputs the second one-shot signal S SHT2 When is high, a high-level signal S 12 and outputs the second one-shot signal S SHT2 When is low, the low-level signal S 12 That is, the OR gate circuit 148 outputs the second one-shot signal S SHT2 When the on-timing control signal S OTMG and outputs the second one-shot signal S SHT2 When the on-timing control signal S OTMG Output.

[0167] Therefore, the voltage V of the electric double layer capacitor 3 EDLC When the main switching control signal S SW1 A switching cycle, which is one period of the periodic pulse signal S OSC This corresponds to one cycle of

[0168] When the current in the coil L1 is in a continuous current operation without interruption, the switching current detection unit 14 outputs a low-level inversion detection signal S REV Output.

[0169] Timing 30 In the case where the periodic pulse signal S OSC When the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0170] At this time, the on / off control unit 18 outputs the synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to be turned off. However, a current IR8 A current I R8 decreases over time.

[0171] Timing 31 In the first one-shot circuit 141, a first one-shot signal S SHT1 The second one-shot circuit 142 changes the second one-shot signal S SHT2 The AND gate circuit 147 changes the signal S 12 The OR gate circuit 148 changes the on-timing control signal S OTMG The on / off control unit 18 changes the on-timing control signal S OTMG When the main switching control signal S SW1 This causes the main switching element Q1 to turn on, and a current I R5 A current I R5 increases over time.

[0172] Timing 32 In the second one-shot circuit 142, a second one-shot signal S SHT2 The AND gate circuit 147 changes the signal S 12 The OR gate circuit 148 changes the on-timing control signal S OTMG from high level to low level.

[0173] Timing 33 In the above, the on / off control unit 18 outputs the main switching control signal S SW1 is changed from high to low. This causes the main switching element Q1 to be turned off, and the current I R5 On the other hand, the current I R8 A current I R8decreases over time.

[0174] Timing 34 In the above, the on / off control unit 18 receives a synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn on, and the current I R8 flows between the drain and source of the switching element Q2.

[0175] FIG. 11 shows the voltage V of the electric double layer capacitor 3 in the first mode. EDLC is equal to or higher than the low voltage threshold and the current in the coil L1 is interrupted, resulting in discontinuous current operation.

[0176] Voltage V of electric double layer capacitor 3 EDLC is equal to or greater than the low voltage threshold, the low voltage detection unit 144 outputs a low-level low voltage detection signal S LV Therefore, the AND gate circuit 146 outputs a low level signal S 11 The AND gate circuit 147 outputs the second one-shot signal S SHT2 When is high, a high-level signal S 12 and outputs the second one-shot signal S SHT2 When is low, the low-level signal S 12 That is, the OR gate circuit 148 outputs the second one-shot signal S SHT2 When the on-timing control signal S OTMG and outputs the second one-shot signal S SHT2 When the on-timing control signal S OTMG Output.

[0177] Therefore, the voltage V of the electric double layer capacitor 3 EDLC When the low voltage threshold is exceeded and the current in the coil L1 is interrupted, the switching cycle is terminated by the periodic pulse signal S OSC This corresponds to one cycle of

[0178] Timing 40 In the case where the periodic pulse signal S OSC When the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0179] At this time, the on / off control unit 18 outputs the synchronous rectification switching control signal S SW2 is changed from high level to low level, whereby the switching element Q2, which is a synchronous rectifier element, is turned off.

[0180] Timing 41 In the first one-shot circuit 141, a first one-shot signal S SHT1 The second one-shot circuit 142 changes the second one-shot signal S SHT2 The AND gate circuit 147 changes the signal S 12 The OR gate circuit 148 changes the on-timing control signal S OTMG The on / off control unit 18 changes the on-timing control signal S OTMG When the main switching control signal S SW1 This causes the main switching element Q1 to turn on, and the current I R5 A current I R5 increases over time.

[0181] Timing 42 In the second one-shot circuit 142, a second one-shot signal S SHT2 The AND gate circuit 147 changes the signal S 12 The OR gate circuit 148 changes the on-timing control signal S OTMG from high level to low level.

[0182] Timing 43 In the above, the on / off control unit 18 outputs the main switching control signal S SW1 is changed from high to low. This causes the main switching element Q1 to be turned off, and the current I R5 On the other hand, the current I R8 A current I R8 decreases over time.

[0183] Timing 44 In the above, the on / off control unit 18 receives a synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn on, and the current I R8 flows between the drain and source of the switching element Q2.

[0184] Timing 45 In the current I R8 becomes zero, the switching current detection unit 14 outputs the inversion detection signal S REV The on / off control unit 18 changes the inversion detection signal S REV When changes from low to high, the synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn off, and the current I R8 is suppressed from flowing in the negative direction.

[0185] FIG. 12 shows the voltage V of the electric double layer capacitor 3 in the first mode. EDLC 13 shows the operation timing of the control unit 10 when the voltage Vcc is less than the low voltage threshold and the current in the coil L1 is in continuous operation without interruption.

[0186] Voltage V of electric double layer capacitor 3 EDLC is less than the low voltage threshold, the low voltage detection unit 144 outputs a high-level low voltage detection signal S LVTherefore, the AND gate circuit 147 outputs a low level signal S 12 The AND gate circuit 146 outputs the second one-shot signal S SHT2 is high level and the count signal S CNT When is high, a high-level signal S 11 and outputs the second one-shot signal S SHT2 is low level or count signal S CNT When is low, the low-level signal S 11 That is, the OR gate circuit 148 outputs the second one-shot signal S SHT2 is high level and the count signal S CNT When the on-timing control signal S OTMG and outputs the second one-shot signal S SHT2 is low level or count signal S CNT When the on-timing control signal S OTMG Output.

[0187] Therefore, the voltage V of the electric double layer capacitor 3 EDLC When the voltage Vcc is less than the low voltage threshold and the current in the coil L1 is in continuous operation, the switching cycle is completed by the periodic pulse signal S OSC This corresponds to 8 cycles.

[0188] When the current in the coil L1 is in a continuous current operation without interruption, the switching current detection unit 14 outputs a low-level inversion detection signal S REV Output.

[0189] Throughout FIG. 12, a counter 143 generates a first one-shot signal S SHT1 When the count value is "1", the counter 143 outputs a count signal S CNT to a high level.

[0190] Timing 50 In the case where the periodic pulse signal S OSCWhen the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0191] At this time, the on / off control unit 18 outputs the synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to be turned off. However, a current I R8 A current I R8 decreases over time.

[0192] At this time, the counter 143 has a count value of "1", so the count signal S CNT to a high level.

[0193] Timing 51 In the first one-shot circuit 141, a first one-shot signal S SHT1 The second one-shot circuit 142 changes the second one-shot signal S SHT2 The counter 143 changes the count signal S CNT The AND gate circuit 146 outputs the signal S 11 Therefore, the OR gate circuit 148 changes the on-timing control signal S OTMG The on / off control unit 18 changes the on-timing control signal S OTMG When the main switching control signal S SW1 This causes the main switching element Q1 to turn on, and a current I R5 A current I R5 increases over time.

[0194] Timing 52In the second one-shot circuit 142, a second one-shot signal S SHT2 The AND gate circuit 146 changes the signal S 11 The OR gate circuit 148 changes the on-timing control signal S OTMG from high level to low level.

[0195] Timing 53 In the above, the on / off control unit 18 outputs the main switching control signal S SW1 is changed from high to low. This causes the main switching element Q1 to be turned off, and the current I R5 On the other hand, the current I R8 A current I R8 decreases over time.

[0196] Timing 54 In the above, the on / off control unit 18 receives a synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn on, and the current I R8 flows between the drain and source of the switching element Q2.

[0197] Timing 55 In the case where the periodic pulse signal S OSC When the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0198] At this time, the on / off control unit 18 outputs the synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier, to be turned off. However, a current I R8 is flowing.

[0199] FIG. 13 shows the voltage V of the electric double layer capacitor 3 in the first mode. EDLC is less than the low voltage threshold and the current in the coil L1 is interrupted, resulting in discontinuous current operation.

[0200] Voltage V of electric double layer capacitor 3 EDLC is less than the low voltage threshold, the low voltage detection unit 144 outputs a high-level low voltage detection signal S LV Therefore, the AND gate circuit 147 outputs a low level signal S 12 The AND gate circuit 146 outputs the second one-shot signal S SHT2 is high level and the count signal S CNT When is high, a high-level signal S 11 and outputs the second one-shot signal S SHT2 is low level or count signal S CNT When is low, the low-level signal S 11 That is, the OR gate circuit 148 outputs the second one-shot signal S SHT2 is high level and the count signal S CNT When the on-timing control signal S OTMG and outputs the second one-shot signal S SHT2 is low level or count signal S CNT When the on-timing control signal S OTMG Output.

[0201] Therefore, the voltage V of the electric double layer capacitor 3 EDLC When the low voltage threshold is less than the low voltage threshold and the current in the coil L1 is interrupted, the switching cycle is terminated by the periodic pulse signal S OSC However, as will be described later, the switching cycle can be terminated (aborted) midway.

[0202] Throughout FIG. 13, a counter 143 counts up a first one-shot signal S SHT1When the count value is "1", the counter 143 outputs a count signal S CNT to a high level.

[0203] Timing 60 In the case where the periodic pulse signal S OSC When the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0204] At this time, the counter 143 has a count value of "1", so the count signal S CNT to a high level.

[0205] Timing 61 In the first one-shot circuit 141, a first one-shot signal S SHT1 The second one-shot circuit 142 changes the second one-shot signal S SHT2 The counter 143 changes the count signal S CNT The AND gate circuit 146 outputs the signal S 11 Therefore, the OR gate circuit 148 changes the on-timing control signal S OTMG The on / off control unit 18 changes the on-timing control signal S OTMG When the main switching control signal S SW1 This causes the main switching element Q1 to turn on, and a current I R5 A current I R5 increases over time.

[0206] Timing 62 In the second one-shot circuit 142, a second one-shot signal S SHT2 The AND gate circuit 146 changes the signal S 11The OR gate circuit 148 changes the on-timing control signal S OTMG from high level to low level.

[0207] Timing 63 In the above, the on / off control unit 18 outputs the main switching control signal S SW1 is changed from high to low. This causes the main switching element Q1 to be turned off, and the current I R5 On the other hand, the current I R8 A current I R8 decreases over time.

[0208] Timing 64 In the above, the on / off control unit 18 receives a synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn on, and the current I R8 flows between the drain and source of the switching element Q2.

[0209] Timing 65 In the current I R8 becomes zero, the switching current detection unit 14 outputs the inversion detection signal S REV The on / off control unit 18 changes the inversion detection signal S REV When the synchronous rectification switching control signal S SW2 This causes the switching element Q2, which is a synchronous rectifier element, to turn off, and the current I R8 is suppressed from flowing in the negative direction.

[0210] The counter 143 also receives the inversion detection signal S REV When the level of the count signal changes from low to high, the count value is reset to “0.” In other words, the control unit 10 ends (stops) the current switching cycle and starts the next switching cycle.

[0211] Timing 66 In the case where the periodic pulse signal S OSC When the first one-shot signal S changes from a low level to a high level, the first one-shot circuit 141 outputs the first one-shot signal S SHT1 from low level to high level.

[0212] Timing 67 In the first one-shot circuit 141, a first one-shot signal S SHT1 The second one-shot circuit 142 changes the second one-shot signal S SHT2 Since the counter 143 has a count value of "1", the counter 143 changes the count signal S CNT The AND gate circuit 146 outputs the signal S 11 Therefore, the OR gate circuit 148 changes the on-timing control signal S OTMG The on / off control unit 18 changes the on-timing control signal S OTMG When the main switching control signal S SW1 This causes the main switching element Q1 to turn on, and a current I R5 A current I R5 increases over time.

[0213] Referring again to FIG. 1, the on / off control unit 18 receives the on timing control signal S OTMG , inversion detection signal S REV , current information signal S CINFO , overvoltage detection signal S OVP and the error signal S ERR A main switching control signal S for controlling the main switching element based on SW1 , and a synchronous rectification switching control signal S for controlling the synchronous rectification element. SW2 to the drive selection unit 19.

[0214] In the first mode, the ON / OFF control unit 18 controls the switching element Q1 and turns on the switching element Q2 during a part of the period in which the switching element Q1 is off. That is, the ON / OFF control unit 18 operates the switching element Q1 as a main switching element and the switching element Q2 as a synchronous rectification element to perform synchronous rectification control.

[0215] In the second mode, the ON / OFF control unit 18 controls the switching element Q2 and turns on the switching element Q1 during a part of the period in which the switching element Q2 is off. In other words, the ON / OFF control unit 18 operates the switching element Q2 as a main switching element and the switching element Q1 as a synchronous rectification element to perform synchronous rectification control.

[0216] The on / off control unit 18 receives the main switching control signal S SW1 , and the synchronous rectification switching control signal S SW2 The frequency of the periodic pulse signal S OSC The frequency of the periodic pulse signal S OSC The frequency of the main switching control signal S is higher in the second mode than in the first mode. SW1 , and the synchronous rectification switching control signal S SW2 The frequency of the second mode is higher than that of the first mode.

[0217] The on / off control unit 18 controls the main switching element and the synchronous rectification element so that the output voltage of the step-up / step-down circuit 4 approaches the target voltage. ERR In the first mode, the voltage V EDLC The error signal S is a signal that corresponds to the difference between the target voltage and the output voltage. ERR In the second mode, the output voltage of the step-up / step-down circuit 4 is the voltage V N1 and the target voltage.

[0218] The on / off control unit 18 outputs the inversion detection signal S REVIn other words, in the first mode, the on / off control unit 18 controls the synchronous rectification element to be turned off when the inversion detection signal S REV When the inversion detection signal S becomes high level, the ON / OFF control unit 18 controls the switching element Q2, which is a synchronous rectification element, to be turned off. REV When the input voltage Vcc reaches a high level, the switching element Q1, which is a synchronous rectifier element, is controlled to be turned off.

[0219] The on / off control unit 18 outputs an overvoltage detection signal S OVP When the signal goes high, the main switching element and the synchronous rectifier element are stopped from operating.

[0220] The on / off control unit 18 outputs a sawtooth wave signal S SAW The current information signal S is calculated by adding the drain-source current of the main switching element to CINFO The main switching element and the synchronous rectifier element are current-mode controlled based on the above.

[0221] FIG. 14 is a diagram illustrating an example of a sawtooth wave signal, a current information signal, an error signal, and a main switching control signal of the backup power supply device according to the embodiment.

[0222] FIG. 14(a) shows a sawtooth signal S SAW When no drain-source current of the main switching element is added to the main switching control signal S, that is, in the case of voltage mode control, SW1 FIG.

[0223] The on / off control unit 18 outputs a sawtooth wave signal S SAW The timing t when 10 In the above, the main switching control signal S SW1 to a high level.

[0224] The on / off control unit 18 outputs a sawtooth wave signal S SAW is the error signal S ERR The time t 11 In the above, the main switching control signal S SW1Set to low level.

[0225] FIG. 14(b) shows the sawtooth signal S SAW When the drain-source current of the main switching element is added to the SW1 FIG.

[0226] The signal 111 indicates the drain-source current of the main switching element. CINFO is the sawtooth signal S SAW This signal is obtained by adding signal 111 to the signal.

[0227] The on / off control unit 18 receives the current information signal S CINFO The timing t when 20 In the above, the main switching control signal S SW1 to a high level.

[0228] The on / off control unit 18 receives the current information signal S CINFO is the error signal S ERR The time t 21 In the above, the main switching control signal S SW1 The main switching control signal S SW1 When the signal 111 goes low, the main switching element is turned off, and the signal 111 goes low.

[0229] Referring again to FIG. 1, the drive selection unit 19 receives the mode signal S MODE When is high level (first mode), the main switching control signal S SW1 to the gate drive circuit B1, and outputs the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B2.

[0230] The drive selection unit 19 receives the mode signal S MODE When is low level (second mode), the main switching control signal S SW1 to the gate drive circuit B2, and outputs the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B1.

[0231] FIG. 15 is a diagram illustrating a circuit configuration of a drive selection unit of the backup power supply device according to the embodiment.

[0232] The drive selection unit 19 includes AND gate circuits (logical product circuits) 131, 132, 134, and 135, OR gate circuits (logical sum circuits) 133 and 136, and a NOT gate circuit 137.

[0233] The NOT gate circuit 137 receives the mode signal S MODE is inverted and output to one input terminal of the AND gate circuit 132 and one input terminal of the AND gate circuit 134.

[0234] One input terminal of the AND gate circuit 131 receives a mode signal S MODE is input to the other input terminal, the main switching control signal S SW1 is entered.

[0235] The other input terminal of the AND gate circuit 132 receives the synchronous rectification switching control signal S SW2 is entered.

[0236] The other input terminal of the AND gate circuit 134 receives the main switching control signal S SW1 is entered.

[0237] One input terminal of the AND gate circuit 135 receives a mode signal S MODE is input to the other input terminal, and the synchronous rectification switching control signal S SW2 is entered.

[0238] An output signal of the AND gate circuit 131 is input to one input terminal of the OR gate circuit 133, and an output signal of the AND gate circuit 132 is input to the other input terminal.

[0239] The OR gate circuit 133 receives the mode signal S MODE When is high level (first mode), the main switching control signal S SW1is output to the gate drive circuit B1.

[0240] The OR gate circuit 133 receives the mode signal S MODE When is low level (second mode), the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B1.

[0241] An output signal of the AND gate circuit 134 is input to one input terminal of the OR gate circuit 136, and an output signal of the AND gate circuit 135 is input to the other input terminal.

[0242] The OR gate circuit 136 receives the mode signal S MODE When is high level (first mode), the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B2.

[0243] The OR gate circuit 136 receives the mode signal S MODE When is low level (second mode), the main switching control signal S SW1 is output to the gate drive circuit B2.

[0244] Referring again to FIG. 1, the gate drive circuit B1 receives the mode signal S MODE When is high level (first mode), the main switching control signal S SW1 The amplified switching control signal S1 is output to the gate of the switching element Q1.

[0245] The gate drive circuit B1 is driven by the mode signal S MODE When is low level (second mode), the synchronous rectification switching control signal S SW2 The amplified switching control signal S1 is output to the gate of the switching element Q1.

[0246] The gate drive circuit B2 is driven by the mode signal S MODE When is high level (first mode), the synchronous rectification switching control signal S SW2 The amplified switching control signal S2 is output to the gate of the switching element Q2.

[0247] The gate drive circuit B2 is driven by the mode signal S MODE When is low level (second mode), the main switching control signal S SW1 The amplified switching control signal S2 is output to the gate of the switching element Q2.

[0248] (effect) [1] The backup power supply device described in Patent Document 1 performs switching control of only the second switching element during discharging, and does not control (operate) the first switching element. In other words, the backup power supply device described in Patent Document 1 performs asynchronous rectification operation.

[0249] On the other hand, during discharging (second mode), the backup power supply 1 of the embodiment controls switching element Q2 and turns on switching element Q1 during part of the period when switching element Q2 is off. In other words, the backup power supply 1 of the embodiment operates switching element Q1 as a synchronous rectification element and performs synchronous rectification.

[0250] As a result, the backup power supply 1 of the embodiment does not require an output rectifier element, as compared with the backup power supply described in Patent Document 1, and the number of parts can be reduced.

[0251] During charging, the backup power supply device described in Patent Document 1 controls the switching of only the first switching element and does not control (operate) the second switching element, causing the second switching element to function as a diode. In other words, the backup power supply device described in Patent Document 1 performs asynchronous rectification operation.

[0252] On the other hand, during charging (first mode), the backup power supply 1 of the embodiment controls switching element Q1 and turns on switching element Q2 during part of the period when switching element Q1 is off. In other words, the backup power supply 1 of the embodiment operates switching element Q2 as a synchronous rectification element and performs synchronous rectification.

[0253] As a result, the backup power supply 1 of the embodiment can reduce losses and improve efficiency compared to the backup power supply described in Patent Document 1.

[0254] [2] In the case of the backup power supply 1 of the embodiment, if the synchronous rectifier element is left on during discontinuous current operation (light load), a reverse current flows, regenerating energy to the input side and reducing efficiency. Also, in the backup power supply 1 of the embodiment, when the charging voltage of the electric double layer capacitor 3 rises, the regenerated energy becomes greater than the charging energy, and charging up to the target voltage becomes impossible. Therefore, the backup power supply 1 of the embodiment detects the timing when the coil L1 discharges energy and the current between the drain and source of the synchronous rectifier element becomes zero or reverses, that is, the reversal detection signal S REV becomes high level, the synchronous rectifier element is controlled to be turned off. This allows the backup power supply 1 of the embodiment to suppress reverse current and suppress a decrease in efficiency. Also, the backup power supply 1 of the embodiment can charge the charging voltage of the electric double layer capacitor 3 up to the target voltage.

[0255] [3] In the first mode, the backup power supply 1 of the embodiment can charge while limiting the charging current. However, in the second mode, the backup power supply 1 of the embodiment must supply the power required by the electronic device while boosting the power, which can cause a large current to flow through the circuit.

[0256] Therefore, in the backup power supply 1 of the embodiment, if the switching frequency is to be maintained in the second mode, the size of the coil L1 must be increased. On the other hand, in the backup power supply 1 of the embodiment, it is desirable not to increase the switching frequency too much in the first mode from the viewpoint of noise suppression.

[0257] Therefore, the switching frequency setting unit 13 sets the switching frequency in the second mode to a frequency higher than the switching frequency in the first mode. This allows the backup power supply device 1 of the embodiment to reduce the size of the coil L1 and suppress noise.

[0258] [4] In the first mode, the backup power supply device 1 of the embodiment uses the voltage V of the electric double layer capacitor 3, which is the output voltage of the step-up / step-down circuit 4. EDLC In the second mode, the backup power supply device 1 of the embodiment performs control based on the difference voltage between the target voltage and the voltage V3, which is the output voltage of the step-up / step-down circuit 4. N1 and the target voltage (specifically, based on voltage V2).

[0259] However, if the input side of one error amplifier is switched between the above two voltages when switching between modes, problems can arise. That is, when switching between modes, the input voltage of the error amplifier is switched to a completely different voltage level, so the output voltage of the error amplifier before switching between modes and after switching between modes are completely different voltages. This can result in a delayed response and unstable operation of the output voltage of the error amplifier.

[0260] Therefore, the output voltage error detection unit 17 (see FIG. 8) includes two error amplifiers 81 and 85, and switches the output side of the error amplifiers 81 and 85 when switching modes. This allows the error amplifiers 81 and 85 to always (even when not being used for control) continue to output output voltages corresponding to their respective input voltages, making it possible to suppress response delays and unstable operation when switching modes.

[0261] [5] Unlike an error amplifier, a comparator can switch the input voltage to another voltage level. Therefore, the overvoltage detection unit 16 (see FIG. 7) includes one comparator 101, and switches the input voltage of the comparator 101 depending on the mode. That is, in the first mode, the voltage V of the electric double layer capacitor 3 is EDLC In the second mode, the output voltage V N1 The voltage obtained by dividing the above voltage by resistors is switched on the input side of the comparator 101.

[0262] As a result, the backup power supply device 1 of the embodiment is capable of detecting an overvoltage in both the first mode and the second mode by using a single comparator 101, and can suppress the circuit.

[0263] [6] In general, phase compensation is easier in current mode control than in voltage mode control, and it is possible to set an increased response (increased frequency gain). Therefore, the on / off control unit 18 uses the current information signal S CINFO However, the current detection point is different between the first mode and the second mode.

[0264] Therefore, the current information detector 15 (see FIG. 6) detects the sawtooth wave signal S SAW The current information to be added to the switching circuit 15 is switched depending on the mode. That is, in the first mode, the current information detection circuit 15 detects current information of a current flowing between the drain and source of the switching element Q1, which is the main switching element. In addition, in the second mode, the current information detection circuit 15 detects current information of a current flowing between the drain and source of the switching element Q2, which is the main switching element.

[0265] As a result, the backup power supply 1 of the embodiment can achieve current mode control in both the first mode and the second mode.

[0266] [7] The first and second modes are completely different controls. Therefore, if you try to switch modes in the middle of a switching cycle, it will be abnormal operation, even if it is just for one switching cycle.

[0267] Therefore, the mode switching timing adjustment unit 12 (see FIG. 2) adjusts the mode change condition, that is, the voltage V IN Even if the magnitude relationship between the input voltage threshold and the input voltage changes, the start of the next switching period, that is, the periodic pulse signal S OSC Wait until the rising edge of the mode signal S MODE In this way, the backup power supply device 1 of the embodiment can suppress the abnormal operation.

[0268] [8] When the voltage of the electric double layer capacitor 3 is low, the current I R8 The slope (downward sloping slope) of the curve becomes very gentle, and the current in coil L1 hardly drops at all during the off period of switching element Q1. The current in coil L1 then increases due to switching delays during the next on period of switching element Q1, and this repetition can result in a large current (overcurrent). When limiting the current in switching element Q1, due to leading edge blanks (mask periods) and comparator delays, the current gradually exceeds the current limit, and an overcurrent can occur.

[0269] Therefore, the on-timing control unit 22 determines the voltage V EDLC When the voltage V of the electric double layer capacitor 3 is less than the low voltage threshold, EDLC The first switching cycle (periodic pulse signal S OSC The second switching cycle (corresponding to one cycle of the periodic pulse signal S OSC This allows the control unit 10 of the embodiment to secure time for discharging energy from the coil L1, thereby suppressing overcurrent.

[0270] However, this may result in a longer charging time for the electric double layer capacitor 3. Therefore, the on-timing control unit 22 reduces the current I R8 When the inversion detection signal S REV becomes high level), the current second switching cycle is ended (stopped) and the next second switching cycle is started. This allows the on-timing control unit 22 to prevent the charging time of the electric double layer capacitor 3 from becoming long.

[0271] [9] The on-timing control unit 22 sets the second switching cycle to be the first switching cycle divided by N (N is an integer equal to or greater than 2). This allows the on-timing control unit 22 to easily achieve the second switching cycle by adding a counter 143, thereby reducing the circuit size.

[0272]

[10] The on-timing control unit 22 controls the voltage V EDLC is less than the low voltage threshold, the inversion detection signal S REV When the inversion detection signal S becomes high level, the second switching cycle is terminated (stopped). REV is the same as the signal indicating the timing to turn off the switching element Q2, which is a synchronous rectifier element, in the first mode in the embodiment. That is, the on-timing control unit 22 can use the switching current detection unit 14. This allows the on-timing control unit 22 to reduce the circuit size.

[0273] <Additional Notes> In the embodiment, the control unit 10 is configured with a hardware circuit, but the present disclosure is not limited to this. The control unit 10 may be configured with a processing device (such as a central processing unit (CPU), digital signal processor (DSP)) and a program.

[0274] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0275] 1 Backup Power Supply 2 Battery 3. Electric double layer capacitor 4. Buck-boost circuit 5 Terminal section 10 Control section 11. Battery voltage drop monitor 12 Mode switching timing adjustment section 13 Switching frequency setting section 14 Switching current detection section 15 Current information detection section 16 Overvoltage detection section 17 Output voltage error detection section 18 On / off control section 19 Drive selection section 20 First level shift section 21 Second level shift section 22 On-timing control section Q1, Q2 switching elements L1 coil

Claims

1. a terminal section including an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil and having the other end electrically connected to a reference potential; a control unit that performs a first mode control in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on and the second switching element is switched on as a synchronous rectifier element, thereby operating the first switching element, the second switching element, and the coil as a step-up circuit to charge the electric double layer capacitor, and that performs a second mode control in which, when the input voltage is lower than the first set voltage, the second switching element is switched on and the first switching element is switched on and the first switching element is switched on as a synchronous rectifier element, thereby operating the first switching element, the second switching element, and the coil as a step-up circuit to discharge the electric double layer capacitor; Equipped with The control unit is In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. A backup power supply device comprising:

2. The control unit is The length of the second switching cycle is set to a length obtained by dividing the length of the first switching cycle by N (N is an integer equal to or greater than 2).

2. The backup power supply device according to claim 1 .

3. The control unit is in the first mode, when a charging voltage of the electric double layer capacitor is equal to or higher than the second set voltage, the second switching element is turned off at a second timing when a current flowing through the second switching element becomes zero or is reversed; the signal representing the first timing and the signal representing the second timing are the same signal.

3. The backup power supply device according to claim 1 or 2.

4. a terminal section having an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; and a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil, and the other end electrically connected to the reference potential, a first mode control is performed in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on based on a current flowing through the first switching element and a charging voltage of the electric double layer capacitor, and the second switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to charge the electric double layer capacitor; and a second mode control is performed in which, when the input voltage is lower than the first set voltage, the second switching element is switched on based on a current flowing through the second switching element and an output voltage output from the output terminal, and the first switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to discharge the electric double layer capacitor; In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. A control method comprising:

5. a terminal section having an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and an input rectifier element having an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the first connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; and a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil, and the other end electrically connected to the reference potential, a first mode control is performed in which, when an input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched on based on a current flowing through the first switching element and a charging voltage of the electric double layer capacitor, and the second switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to charge the electric double layer capacitor; and a second mode control is performed in which, when the input voltage is lower than the first set voltage, the second switching element is switched on based on a current flowing through the second switching element and an output voltage output from the output terminal, and the first switching element is switched on based on a synchronous rectification element, thereby operating the first switching element, the second switching element and the coil as a step-up circuit to discharge the electric double layer capacitor; In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, control is performed with a second switching cycle that is longer than a first switching cycle when the charging voltage of the electric double layer capacitor is equal to or greater than the second set voltage, and the current second switching cycle is terminated and a next second switching cycle is started at a first timing when the current flowing through the second switching element becomes zero or is reversed. A control program that causes a processing device to execute the above operations.

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