Semiconductor device having integrated magnetic flux concentrator and method of manufacture thereof - Patents.com

Abstract

To provide semiconductor devices with integrated magnetic flux concentrators (IMFC or IMC), and methods of manufacturing the same.SOLUTION: A method of manufacturing a semiconductor substrate comprising at least one integrated magnetic flux concentrator (IMFC) is provided, the method comprising: a) providing a semiconductor substrate having an upper surface (step 901); b) making at least one cavity on the upper surface (step 902); c) depositing one or more layers of one or more materials, including sputtering at least one layer of a soft magnetic material; and d) removing substantially all of the soft magnetic material situated outside the at least one cavity, while leaving at least a portion of the soft magnetic material inside the at least one cavity (step 904).SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductor devices having integrated magnetic flux concentrators (IMFCs or IMCs) and to methods for manufacturing such devices. More specifically, the present invention relates to the field of semiconductor devices including at least one horizontal Hall element and at least one integrated magnetic flux concentrator, and to methods for manufacturing such devices. [Background technology]

[0002] Semiconductor devices (e.g., magnetic sensor devices) comprising a semiconductor substrate and at least one horizontal Hall element, and at least one integrated magnetic flux concentrator (IMFC or IMC) are known in the art, for example from US2002 / 021124(A1), filed about 20 years ago. Examples of such devices are linear position sensor devices, angular position sensor devices, current sensor devices, etc.

[0003] It is known that a horizontal Hall element (no IMC on top) can be used to measure the magnetic field components (Bz) oriented perpendicular to the semiconductor substrate, while vertical Hall elements and magnetoresistance elements can measure the magnetic field components (Bx, By) parallel to the semiconductor substrate.

[0004] It is also known (from the patent literature) that two horizontal Hall elements arranged on either side of the magnetic disk and near its periphery can be used to measure the magnetic field component (Bx or By) oriented parallel to the semiconductor substrate.

[0005] Over the years, many variations of sensor devices containing one or more horizontal Hall elements and one or more integrated magnetic flux concentrators (IMFCs) have been developed, but the way in which the IMFCs are implemented in these devices has not seen much change, other than tape being replaced by electroplating.

[0006] There is always room for improvement or alternatives. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2002 / 021124 Summary of the Invention

[0008] SUMMARY OF THE PRESENT EMBODIMENTS Embodiments of the present invention aim to provide a method for manufacturing a semiconductor substrate (eg, a semiconductor wafer or a semiconductor die) that includes at least one integrated magnetic flux concentrator (abbreviated as IMFC or IMC).

[0009] Embodiments of the present invention also aim to provide semiconductor substrates (eg, semiconductor wafers or semiconductor dies), and semiconductor devices including such semiconductor substrates, and more particularly, magnetic sensor devices.

[0010] SUMMARY OF THE PRESENT EMBODIMENTS An embodiment of the present invention aims to provide a method for manufacturing a semiconductor device including at least one coil and an integrated magnetic core, or at least one transmitter coil and at least one receiver coil and an integrated magnetic core.

[0011] SUMMARY OF THE PRESENT EMBODIMENTS An embodiment of the present invention aims to provide a method for manufacturing a semiconductor device including at least one horizontal Hall element and at least one integrated magnetic flux concentrator (IMFC or IMC).

[0012] Embodiments of the present invention aim to provide a method for manufacturing a semiconductor device including multiple integrated magnetic flux concentrators (IMFCs) that has an extended lifetime and / or improved reliability when used in automotive applications (e.g., when used in an industrial or automotive environment).

[0013] Embodiments of the present invention preferably provide a method for producing a ferromagnetic alloy having a thickness of 1.0-10 μm, or 1.0-100 μm, or 1.5-100 μm, or 2.0-100 μm, or 5.0-100 μm, or 10 μm, while maintaining excellent mechanical properties (e.g., low risk of detachment or delamination), and / or maintaining excellent magnetic properties (e.g., saturation, hysteresis), and / or maintaining excellent reliability (e.g., long life) even when used in industrial or automotive environments. The present invention provides a method for manufacturing a semiconductor wafer including a plurality of integrated magnetic flux concentrators (IMFCs) having a thickness (in a direction perpendicular to the semiconductor wafer) or a total thickness in the range of 15 μm to 100 μm, or 20 μm to 100 μm, or 25 μm to 100 μm, or 30 μm to 100 μm, or 35 μm to 100 μm, or 40 μm to 100 μm, or 55 μm to 100 μm, or 50 μm to 100 μm.

[0014] SUMMARY OF THE PRESENT EMBODIMENTS An embodiment of the present invention aims to provide a method for manufacturing a semiconductor wafer containing multiple integrated magnetic flux concentrators (IMFCs) that is compatible with CMOS processes.

[0015] Embodiments of the present invention aim to provide methods of manufacturing one or more of a current sensor device, an integrated transformer device (also called a "microtransformer" device), an integrated proximity sensor device, an integrated magnetic sensor device, an integrated angular sensor device, and an integrated linear sensor device, optionally packaged on a single chip.

[0016] Embodiments of the present invention aim to provide an integrated magnetic sensor device capable of measuring one or more characteristics of a magnetic field with an increased signal-to-noise ratio (SNR) and / or with improved accuracy and / or larger signal amplitude without increasing power consumption, and a method for manufacturing such an integrated magnetic sensor device.

[0017] An embodiment of the present invention aims to provide such an integrated magnetic sensor device or such a position sensor device that is suitable for use in an industrial and / or automotive environment.

[0018] Certain embodiments of the present invention aim to provide an integrated magnetic sensor device with an improved signal-to-noise ratio, especially for the Bz component oriented in a direction perpendicular to the semiconductor substrate.

[0019] Certain embodiments of the present invention aim to provide an integrated magnetic sensor device having a plurality of integrated magnetic concentrators having at least two different heights (measured in a direction perpendicular to the semiconductor substrate).

[0020] Certain embodiments of the present invention aim to provide an integrated magnetic sensor device with a reduced risk of delamination when used in industrial or automotive applications.

[0021] Certain embodiments of the present invention aim to provide an integrated magnetic sensor device that reduces losses in the device or reduces heating of the device.

[0022] Certain embodiments of the present invention aim to provide an integrated magnetic sensor device that provides improved manufacturing yields.

[0023] These and other objects are achieved by embodiments of the present invention.

[0024] According to a first aspect, the present invention provides a method for manufacturing a semiconductor substrate (e.g., a semiconductor wafer or semiconductor die) including at least one integrated magnetic flux concentrator, the method comprising the steps of: a) providing a semiconductor substrate having a top surface, b) creating at least one cavity on the top surface, c) depositing one or more layers of one or more materials including sputtering at least one layer of soft magnetic material, and d) removing substantially all of the soft magnetic material outside the at least one cavity while leaving at least a portion of the soft magnetic material inside the at least one cavity.

[0025] A major advantage of using this method is that the "filling factor" or "coverage area" of the soft magnetic material, or the percentage of the projected area containing the IMFC to the total area (with or without the IMFC), can be, for example, greater than 4%, or greater than about 7%, or greater than about 10%, while maintaining a good manufacturing yield. The "top surface" referred to is located on the same side as the "active surface" that contains the integrated semiconductor components, for example, preferably at least one horizontal Hall element. Examples of semiconductor substrates obtained by this method are shown in Figure 10(d), Figure 11(d), Figure 12(d), Figure 13(d), and Figure 14(d).

[0026] In one embodiment, step d) comprises removing substantially all of the soft magnetic material outside the at least one cavity while leaving at least 50%, or at least 60%, or at least 70%, or at least 80%, or at least 90%, or substantially all of the soft magnetic material inside the at least one cavity.

[0027] In one embodiment, step a) may comprise providing a semiconductor substrate having a sacrificial layer on its top surface (e.g. as its uppermost layer) and / or growing or depositing an insulating layer (e.g. SiO2 or SiNi or SU-8) on top of the semiconductor substrate, which insulating layer then becomes the (new) upper surface (or uppermost layer).

[0028] In one embodiment, step d) comprises removing the sacrificial layer, thereby also removing the soft magnetic material deposited on the sacrificial layer outside the cavity.

[0029] In one embodiment, the soft magnetic material may be selected from the group consisting of Fe, Fe alloys, Ni, Ni alloys, FeNi, FeNi alloys, Co, Co alloys, metallic glasses, mu metals.

[0030] In one embodiment, step a) comprises providing at least one horizontal Hall element in a semiconductor substrate.

[0031] In one embodiment, step a) comprises providing at least two horizontal Hall elements on a semiconductor substrate.

[0032] In one embodiment, step d) comprises removing substantially all of the soft magnetic material outside the at least one cavity by applying chemical mechanical polishing (CMP).

[0033] The inventors came up with the idea of ​​constructing cavities, filling them with soft magnetic material, and then applying CMP to remove the excess soft magnetic material outside the cavities as a way to "pattern" magnetic structures on a substrate. Note that CMP is normally used to flatten a surface.

[0034] Moreover, if the cavity is not completely filled, but only partially filled, the grinding does not need to reach the top of the soft magnetic material inside the cavity, thus avoiding the grinding from adversely affecting the properties of the magnetic material in the cavity.

[0035] Examples of semiconductor substrates obtained by this method are shown in Figures 10(d), 11(d), 12(d) and 13(d).

[0036] In one embodiment, step d) comprises removing substantially all of the soft magnetic material outside the at least one cavity by applying a lift-off.

[0037] This may involve, inter alia, inserting the semiconductor substrate into a bath that dissolves the sacrificial layer underneath the excess soft magnetic material (which is also removed from the substrate). An example of a semiconductor substrate obtained by this method is shown in Figure 14(d).

[0038] In one embodiment, step b) includes applying a photoresist layer on the top surface and patterning the photoresist layer.

[0039] As known in the art, "patterning photoresist" may include (i) exposing portions of the photoresist or irradiating the photoresist with a mask, (ii) optionally baking the photoresist, and (iii) developing or etching the photoresist by removing the exposed or unexposed portions.

[0040] In one embodiment, step b) comprises creating at least one cavity to have a predetermined first height (H1) in a direction perpendicular to the semiconductor substrate, and step c) comprises depositing one or more layers over a second height (H2) in a direction perpendicular to the semiconductor substrate, the second height (H2) being greater than the first height (H1).

[0041] This is an advantage when the second height (of the IMFC) is smaller than the first height (of the cavity), since in this case the sputtered soft magnetic material may exhibit superior properties, e.g., reduced hysteresis, compared to (i) similar processes / devices in which the soft magnetic material is deposited by electroplating and / or (ii) similar processes / devices in which the top surface of the IMFC is in physical contact with a mechanical polishing device.

[0042] Depending on the roughness of the mechanical polishing used, the difference between the first height and the second height may be selected.

[0043] If step d) involves using a lift-off process, making the second height (of the IMFC) smaller than the first height (of the cavity) provides the advantage that any (undesirable) interconnections between the IMFC deposited inside the cavity and any excess IMFC material above the sacrificial layer are relatively thin and weak and will be destroyed when the material below the excess IMFC is dissolved.

[0044] In one embodiment, the second height is at least 1 μm, or at least 2 μm, or at least 3 μm, or at least 4 μm, or at least 5 μm less than the first height.

[0045] In one embodiment, the second height is substantially equal to the first height within a tolerance of ±1 μm.

[0046] In one embodiment, the second height is greater than the first height, for example at least 1 μm, or at least 2 μm, or at least 3 μm, or at least 4 μm, or at least 5 μm. This is an advantage when the second height (of the IMFC) is greater than the first height (of the cavity), because in this case the top of the IMFC will be very flat, since the top surface will be flat after polishing (CMP).

[0047] In one embodiment, the second height is a value in the range of about 2.0 μm to about 80 μm.

[0048] In one embodiment, step a) comprises providing a semiconductor substrate comprising at least one magnetic sensor element and an interconnect stack comprising at least three or at least four metal layers, and step b) comprises creating at least one cavity to extend at least partially into the interconnect stack. This provides the advantage that the bottom of the magnetic flux concentrator is located close to the magnetic sensor element, resulting in a larger signal. An example of a semiconductor substrate obtained by this method is shown in Figure 13(d).

[0049] In one embodiment, step b) comprises creating at least one cavity to extend to one of the metal layers of the interconnect stack. In this embodiment, one of the metal layers is used as an etch stop. This offers the advantage that the distance between the magnetic flux concentrator and the magnetic sensor element is smaller and / or very well defined. This in turn may help to improve the accuracy of the sensor device (e.g., by providing a larger gain and therefore a larger signal-to-noise ratio (SNR)). This may also help to avoid the need for calibration tests during manufacturing. An example of a semiconductor substrate obtained by this method is shown in FIG. 13(d).

[0050] In one embodiment, step b) comprises creating a plurality of cavities such that the total projected area of ​​the cavities (in a direction perpendicular to the semiconductor substrate) amounts to at least 5%, or at least 7%, or at least 10%, or at least 12%, or at least 14%, or at least 16%, or at least 18%, or at least 20%, or at least 23%, or at least 25%, or at least 28%, or at least 30%, or at least 35%, or at least 40% of the total area of ​​the semiconductor substrate. This is a major advantage of using sputtering to deposit the soft magnetic material, since sputtering does not impose much of an upper limit on the maximum coverage area, as opposed to, for example, electroplating, which becomes very difficult or even impossible to use.

[0051] In one embodiment, step c) includes depositing a polymer layer, or a stress relief layer (e.g., Al or AlN or Al2O3 or SiO2 or Ta2O5, or a layer including or consisting of an Al-based, Si-based or Ta-based material) as a first layer of the one or more layers. Applying a polymer layer, e.g., a polyimide layer, can help to reduce mechanical stress between at least one layer of sputtered soft magnetic material and materials that directly contact it (e.g., at the bottom and / or sides). In this way, the life of the semiconductor device thus manufactured can be extended. The aluminum (Al) or aluminum nitride (AlN) or Al2O3 or SiO2 or Ta2O5 layer, etc., can be deposited by sputtering. Examples of semiconductor substrates obtained by this method are shown in Figure 11(d), Figure 12(d) and Figure 13(d).

[0052] In one embodiment, the polymer layer (1130) is a polyimide layer. Polyimide layers are typically deposited by spin coating.

[0053] In one embodiment, step c) comprises providing at least one layer of Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based, Si-based or Ta-based material immediately below the layer of soft magnetic material and / or providing at least one layer of Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based, Si-based or Ta-based material immediately above the layer of soft magnetic material. An example of a semiconductor substrate obtained by this method is shown in Figure 13(d).

[0054] In one embodiment, step c) comprises: The method includes forming a stack of layers by repeating at least twice: (i) sputtering a stress relief layer (e.g., including or consisting of Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based or Si-based or Ta-based material); and (ii) sputtering a layer of soft magnetic material.

[0055] The stress relief layer (e.g., Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based, Si-based, or Ta-based material) can have a thickness of about 0.5 nm to about 40 nm, or about 1.0 nm to about 40 nm, or about 1.0 nm to about 20 nm, or about 1.0 nm to about 10 nm, or about 2.0 nm to about 20 nm, or about 2.0 nm to about 10 nm, or about 2.0 nm to about 4.0 nm, for example, equal to about 2 nm, or equal to about 3 nm, or equal to about 4 nm, or equal to about 5 nm.

[0056] The layer of soft magnetic material may have a thickness of about 50 nm to about 1000 nm, or about 50 nm to about 500 nm, or about 50 nm to about 200 nm, or about 50 nm to about 75 nm, or about 75 nm to about 100 nm, or about 100 nm to about 125 nm, or about 125 nm to about 150 nm, or about 150 nm to about 200 nm, or about 200 nm to about 250 nm, or about 250 nm to about 300 nm, or about 300 nm to about 350 nm, or about 350 nm to about 400 nm, or about 400 nm to about 450 nm, or about 450 nm to about 500 nm. An advantage of providing such a multilayer stack is that it can help reduce mechanical stress between at least two layers of sputtered soft magnetic material and materials that directly contact them (e.g., at the bottom, top, and / or sides). In this manner, wear can be reduced and the life of the semiconductor devices so manufactured can be extended.

[0057] Advantageously, this stack provides superior mechanical properties (e.g., reduced risk of delamination) and / or superior magnetic properties (e.g., one or more of superior magnetic gain, relatively small hysteresis, relatively large saturation, etc.).

[0058] This is particularly advantageous when using AlN or another electrically insulating material as the stress relief layer, since in this way the magnetic material layers are electrically insulated from each other, so that eddy currents can only flow inside the individual layers. This means that the heating due to eddy currents when exposed to a time-varying magnetic field (e.g. when measuring AC currents) is reduced (at least for some field orientations), and therefore the thermal differentials are reduced, and therefore the mechanical stresses are also reduced, leading to reduced mechanical wear and longer life.

[0059] In one embodiment, step c) comprises repeating the steps of depositing a stress relief layer and depositing a soft magnetic material layer at least 3 times, or at least 4 times, or at least 5 times, or at least 10 times, or at least 12 times, or at least 15 times, or at least 20 times.

[0060] In one embodiment, step b) comprises creating at least one cavity having sloping sidewalls that form an angle (φ) different from 90° with the semiconductor substrate.

[0061] The sloped sidewalls may define an angle relative to the semiconductor substrate in the range of about 30° to about 85°, or in the range of about 45° to about 85°, or in the range of about 60° to about 85°, or in the range of about 75° to about 85°. The sloped sidewalls may be formed, for example, by anisotropic etching, or anisotropic wet etching, or any other suitable method.

[0062] An example of a semiconductor substrate obtained by this method is shown in FIG.

[0063] In one embodiment, step b) comprises creating (eg, by isotropic etching) at least one cavity having rounded or curved sidewalls.

[0064] In one embodiment, the method includes, in step b), creating a cavity with a sloping sidewall, and in step c), providing a stress relief layer, for example comprising or consisting of polyimide, Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based, Si-based or Ta-based material. This is particularly advantageous in that it not only reduces the mechanical stress exerted by layers located below the soft magnetic material layer, but also by layers flanking the soft magnetic material layer. An example of a semiconductor substrate obtained by this method is shown in FIG. 12(d). It should be noted that the features of "sloping sidewall" and "presence of a stress relief layer" work synergistically when both are present, but they may also be used separately.

[0065] In one embodiment, step a) includes providing a semiconductor substrate including at least one or at least two horizontal Hall elements, and step b) includes creating at least one cavity above the at least one or at least two horizontal Hall elements such that the cavity has a shape having an outer edge that is substantially aligned with (i.e., located substantially vertically above) a geometric center of the at least one or at least two horizontal Hall elements.

[0066] In one embodiment, the cavity has a disk or ring shape and the semiconductor substrate includes at least two horizontal Hall elements below and on either side of the cavity. This embodiment is ideally suited to measure magnetic field components Bx or By oriented parallel to the semiconductor substrate.

[0067] In one embodiment, step a) includes providing a semiconductor substrate including at least one horizontal Hall element, and step b) includes creating at least one cavity above the horizontal Hall element such that the cavity has a shape with a geometric center that aligns with a geometric center of the horizontal Hall element.

[0068] The shape of the cavity may have a height H in a direction perpendicular to the semiconductor substrate (Z) and a maximum transverse dimension D (e.g., the diameter of a circle, or the maximum diagonal of a polygon) in a direction parallel to the semiconductor substrate (X, Y). In an embodiment, the height of the cavity is at least 25 μm, or at least 27 μm, or at least 30 μm, or at least 32 μm, or at least 35 μm, or at least 40 μm, or at least 45 μm, or at least 50 μm, or at least 60 μm. In another or further embodiment, the ratio (H / D) of the height (H) to the maximum transverse dimension (D) is at least 25%, or at least 30%, or at least 40%, or at least 50%, or at least 60%, or at least 70%, or at least 80%, or at least 90%, or at least 100%, or at least 110%.

[0069] An embodiment of what such a semiconductor device may look like is illustrated in co-pending patent application EP20205330.2, filed by the same applicant on November 3, 2020, which is incorporated herein by reference in its entirety.

[0070] In one embodiment, the shape of the resulting integrated magnetic flux concentrator is generally cylindrical, or generally conical, or generally frusto-conical, or has a rotational symmetric shape, or has a circular symmetric shape about a longitudinal axis, or has a generally prismatic shape with a regular polygonal cross-section, or has a generally mushroom shape, or includes a predominantly cylindrical portion, or includes a predominantly conical portion, or includes a predominantly frusto-conical portion.

[0071] In one embodiment, the conical shape or truncated conical shape or portion tapers towards the horizontal Hall element (Hc).

[0072] In an embodiment, the cross-section of the integrated magnetic flux concentrator geometry in a plane parallel to the semiconductor substrate has a diameter (D) or maximum diagonal in the range of 15 to 40 μm, or 15 to 35 μm, or 16 to 34 μm, or 17 to 33 μm, or 18 to 32 μm, or 19 to 31 μm, or 20 to 30 μm.

[0073] In one embodiment, the orthogonal projection of the horizontal Hall element onto the substrate lies entirely within the periphery of the orthogonal projection of the bottom surface of the integrated magnetic flux concentrator onto the substrate.

[0074] In one embodiment, the orthogonal projection of the bottom surface of the integrated flux concentrator onto the substrate lies entirely within the periphery of the orthogonal projection of the horizontal Hall element onto the substrate.

[0075] In one embodiment, the perimeter of the orthogonal projection of the horizontal Hall element onto the substrate intersects with the perimeter of the orthogonal projection of the bottom surface of the integrated magnetic flux concentrator onto the substrate.

[0076] In one embodiment, the distance between the horizontal Hall element and the integrated magnetic flux concentrator is a value in the range of 1 to 20 μm.

[0077] In one embodiment, step a) includes providing a semiconductor substrate having a first plurality of integrated magnetic concentrator elements deposited by electroplating.

[0078] In one embodiment, the method may include the further step of depositing a sacrificial layer (e.g., a photoresist layer) and patterning the sacrificial layer to form a plurality of cavities aligned with only, or at least a subset, or all of the electroplated IMC elements, the lateral dimensions of the cavities may be the same or different from the dimensions of the underlying electroplated IMC elements.

[0079] In one embodiment, the method may further include sputtering a soft magnetic material (e.g., the same soft magnetic material or another soft magnetic material) onto the electroplated material, optionally preceded by applying a stress relief layer (e.g., polymer, polyimide, Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based or Si-based or Ta-based material) between the electroplated layer and the sputtered layer.

[0080] In one embodiment, the method may further include providing a stack of multiple alternating layers, one layer being a stress relief layer (e.g., Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-, Si- or Ta-based material) deposited by sputtering, and the other layer being a soft magnetic material (e.g., Fe or Fe-based, Ni or Ni-based, Co or Co-based, FeNi or FeNi-based, metallic glass or mu-metal) deposited by sputtering.

[0081] This may be particularly useful when forming two different types of integrated magnetic concentrators, for example a first type of IMFC having, for example, a ring or disk shape (e.g., diameter about 150-250 μm, and thickness about 20-25 μm) located on top of the interconnect stack (as is usually done in the prior art), and a second type of IMFC having, for example, a pillar shape (e.g., cylindrical or prism shape with a diameter of about 20-60 μm and a thickness of about 27-60 μm) extending partially into the interconnect stack, for example in the manner described in more detail in the above-mentioned co-pending patent application EP20205330.2 (see, for example, FIG. 13(b)). This second IMFC is thus in contact with one of the metal layers of the interconnect stack, which acts as a seed layer. Fabricating the bottom of the second IMFC by electroplating provides a good "base" and good adhesion to the respective metal layers (of the "interconnect stack") of this IMFC, thereby reducing the risk of delamination when used in harsh environments. The top of the second IMFC can be formed by sputtering, either as a single layer or as a stack of multiple layers in which layers of soft magnetic material (e.g., Fe, Ni, Co, etc.) are interleaved with stress relief layers (e.g., including Al or AlN or Al2O3 or SiO2 or Ta2O5, or Al-based or Si-based or Ta-based materials).

[0082] It is an additional advantage that the upper part of the second IMFC may have a (slightly) different shape and / or size than the lower part of the second IMFC. For example, if both parts have a cylindrical shape and the upper part has a slightly larger diameter than the lower part, an overall mushroom shape is formed, which may help to increase the magnetic gain Gz in the Z direction (perpendicular to the semiconductor substrate).

[0083] In one embodiment, the method includes a first series of steps including a) providing a semiconductor substrate, b) creating at least one first cavity, c) sputtering at least one layer of soft magnetic material, and d) removing at least a portion of the soft magnetic material outside the first cavity, and a second series of steps including f) depositing a sacrificial layer, b) creating a second cavity, c) sputtering at least one layer of soft magnetic material, and d) removing at least a portion of the soft magnetic material outside the second cavity.

[0084] An advantage of this embodiment is that the bottom portions of some or all of the IMFC elements can be formed by a first series of steps, and optionally the top portions of some or all of the IMFC elements, having different dimensions and / or being made of different materials, can be formed by a second series of steps.

[0085] According to a second aspect, the present invention also provides an integrated semiconductor substrate (e.g., a semiconductor wafer or semiconductor die) including an integrated magnetic flux concentrator comprising one or more layers of one or more materials, the integrated magnetic flux concentrator having the following characteristics: i) an interconnect stack including at least three or at least four metal layers, the integrated magnetic flux concentrator extending at least partially through the interconnect stack; ii) an interconnect stack including at least three or at least four metal layers, the integrated flux concentrator extending to one of the metal layers of the interconnect stack; iii) at least one stress relief layer immediately below the layer of soft magnetic material and at least one stress relief layer immediately above the layer of soft magnetic material; iv) a plurality of two alternating layers including a first layer including a stress-relieving material (e.g., Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based or Si-based or Ta-based material) and a second layer including a soft magnetic material (e.g., Fe or an Fe alloy, Ni or an Ni alloy, FeNi or an FeNi alloy, Co or a Co alloy, or a metallic glass or a mu metal, etc.); v) the integrated flux concentrator has sloped sidewalls (i.e., forms an angle other than 90° with respect to the semiconductor substrate); vi) the integrated semiconductor substrate further includes at least one horizontal Hall element, and the integrated flux concentrator has a shape having an outer edge substantially aligned with the at least one horizontal Hall element; vii) the integrated semiconductor substrate further includes at least one horizontal Hall element, and the integrated flux concentrator has a shape having a geometric center substantially aligned with a geometric center of the horizontal Hall element; viii) providing an integrated semiconductor substrate further comprising one or more of: a polished top surface; or a polished surface having a passivation layer thereon;

[0086] According to a third aspect, the present invention also provides an integrated semiconductor device comprising an integrated semiconductor substrate according to the second aspect and a housing.

[0087] In one embodiment, the integrated semiconductor device may be a magnetic sensor device, a current sensor device, a proximity sensor device, a linear position sensor device, or an angular position sensor device.

[0088] In one embodiment, the integrated semiconductor device may be an integrated transformer device (also known as a microtransformer device) and further includes at least one integrated coil, or at least two integrated coils, e.g., a transmitter coil and a receiver coil, which may be inductively coupled to each other. The orthogonal projection of the receiver coil onto the semiconductor substrate may be located inside the orthogonal projection of the transmitter coil (or vice versa), and the orthogonal projection of the integrated magnetic flux concentrator may be located inside the orthogonal projection of the internal coil.

[0089] In one embodiment, the integrated semiconductor device may further include a lead frame.

[0090] In one embodiment, the integrated semiconductor device may further include a molding compound.

[0091] According to another aspect, the present invention also relates to a current sensor system comprising a current sensor device according to the third aspect and a current conductor (eg a busbar).

[0092] According to another aspect, the present invention also relates to a proximity sensor system comprising a proximity sensor device according to the third aspect and a metal target movably arranged relative to the proximity sensor device.

[0093] According to another aspect, the present invention also relates to a linear position sensor system comprising a linear position sensor device according to the third aspect and a magnetic structure (e.g. a permanent magnet structure) including a plurality of alternating goals, wherein the sensor device is movable relative to the magnetic structure or vice versa.

[0094] According to another aspect, the present invention also relates to an angular position sensor system comprising an angular position sensor device according to the third aspect and a magnetic structure comprising a plurality of alternating goals, e.g. a multi-pole ring or disc magnet, rotatable relative to the sensor device.

[0095] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0096] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. [Brief description of the drawings]

[0097] [Figure 1] Figure 1(a) shows a perspective view of a magnetic sensor structure or arrangement that may be manufactured by a method according to the invention, including a disk-shaped integrated magnetic flux concentrator (IMFC) and two horizontal Hall elements located on either side of the disk near its periphery, and Figure 1(b) shows the sensor structure of Figure 1(a) in cross-sectional side view. [Diagram 2] FIG. 2 shows a perspective view of a variation of the magnetic sensor structure of FIG. 1(a) including a disk-shaped integrated magnetic flux concentrator (IMFC) and four horizontal Hall elements located near its periphery and angularly spaced apart in multiples of 90°, which can be manufactured by the method according to the invention. [Diagram 3] 3(a)-3(d) show examples of magnetic sensor structures including an integrated flux concentrator having a central axis aligned with the center of a horizontal Hall element that may be fabricated by a method according to the present invention. [Figure 4] Figure 4(a) shows an example of a magnetic sensor structure that may be manufactured by a method according to the invention, including a first magnetic flux concentrator in the form of a ring, two horizontal Hall elements arranged near the periphery of the ring, and a second magnetic flux concentrator in the form of a cylinder or frusto-conical shape having a central axis aligned with the center of the third horizontal Hall element. Figure 4(b) is a cross-sectional side view of the sensor structure of Figure 4(a). [Diagram 5]FIG. 5 shows a perspective view of a variant of the magnetic sensor structure of FIG. 4(a) that can be manufactured by the method according to the invention, comprising a ring-shaped integrated magnetic flux concentrator (IMFC), four horizontal Hall elements located near the periphery of the ring and angularly spaced apart in multiples of 90°, and a second magnetic flux concentrator in the form of a cylinder or frusto-cone shape having a central axis aligned with the center of the third horizontal Hall element. [Figure 6] FIG. 6 shows a top view of another magnetic sensor structure capable of measuring and passively amplifying three orthogonal magnetic field components Bx, By, Bz, which can be manufactured by the method according to the invention. [Figure 7] FIG. 7 shows a top view of a variant of the magnetic sensor structure of FIG. 6, capable of measuring and passively amplifying three orthogonal magnetic field components Bx, By, Bz, which can be manufactured by the method according to the invention. [Figure 8] Figure 8 is a schematic diagram of an integrated semiconductor device including a semiconductor substrate including a first magnetic sensor structure (shown on the left in Figure 8) including a first IMFC having a first shape and a first height, and a second magnetic sensor structure (shown on the right in Figure 8) including a second IMFC having a second shape and a second height that may be smaller than, substantially equal to, or larger than the first height, which may be manufactured by a method according to the present invention. [Figure 9] FIG. 9 shows a flow chart of the method proposed by the present invention for manufacturing a semiconductor substrate having at least one integrated magnetic flux concentrator (IMFC). [Figure 10] Figures 10(a)-10(d) show intermediate semiconductor substrates that can be obtained by performing some or all of the steps of the method of Figure 9. More specifically, they illustrate semiconductor substrates containing IMFC structures obtained by creating cavities, sputtering magnetic material, and mechanical polishing (CMP) or etching. [Figure 11]Figures 11(a)-11(d) show intermediate semiconductor substrates that can be obtained by performing some or all of the steps of the method of Figure 9. More specifically, they illustrate semiconductor substrates containing IMFC structures obtained by creating cavities, depositing stress relief material, sputtering magnetic material, and mechanical polishing (CMP) or etching. [Figure 12] Figures 12(a)-12(d) show intermediate semiconductor substrates that can be obtained by performing some or all of the steps of the method of Figure 9. More specifically, they illustrate semiconductor substrates containing IMFC structures obtained by creating cavities with sloping sidewalls, depositing a stress relief material, sputtering a magnetic material, and mechanical polishing (CMP) or etching. [Figure 13] Figures 13(a)-13(d) illustrate intermediate semiconductor substrates that can be obtained by performing some or all of the steps of the method of Figure 9. More specifically, they illustrate semiconductor substrates that include an IMFC structure obtained by creating a cavity that extends partially into the interconnect stack, sputtering multiple layers that include alternating stress relief and magnetic materials, and mechanical polishing (CMP) or etching. [Figure 14] Figures 14(a)-14(d) show an intermediate semiconductor substrate that can be obtained by performing some or all of the steps of the method of Figure 9. More specifically, they illustrate a semiconductor substrate including an IMFC structure obtained by depositing a sacrificial layer, creating a cavity, sputtering a magnetic material, and lifting off the sacrificial layer. [Figure 15] FIG. 15 shows a schematic diagram of an integrated transformer that can be manufactured by the method according to the invention.

[0098] The drawings are only schematic and non-limiting. In the drawings, the size of some elements may be exaggerated and not drawn to scale for illustrative purposes. Any reference signs in the claims should not be construed as limiting the scope. The same reference signs in different drawings refer to the same or similar elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0099] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual reductions to the practice of the invention.

[0100] Moreover, terms such as first, second, etc. in this description and claims are used to distinguish between similar elements and not necessarily to describe arrangements in time, space, ranking, or in any other manner, It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation with arrangements other than those described or illustrated herein.

[0101] Moreover, terms such as up, down, and the like in this description and claims are used for descriptive purposes and not necessarily used to describe relative positions, with it being understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in orientations other than those described or illustrated herein.

[0102] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means recited thereafter, and does not exclude other elements or steps. It is thus interpreted as specifying the presence of the referenced and stated features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to a device consisting of only components A and B. This means that in the context of the present invention, the relevant components of the device are only A and B.

[0103] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0104] Similarly, in describing exemplary embodiments of the present invention, it should be understood that various features of the invention may be grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in understanding one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0105] Furthermore, some embodiments described herein include some features included in other embodiments but do not include some other features included in other embodiments, but combinations of features of different embodiments are meant to be within the scope of the present invention and form different embodiments, as would be understood by one of ordinary skill in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0106] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail in order not to obscure an understanding of the present description.

[0107] Wherever possible, the same or similar reference numbers (modulo 100) are used in different embodiments to indicate the same or similar structural features.

[0108] In this document, the terms "integrated magnetic concentrator" (IMC) and "integrated magnetic flux concentrator" (IMFC) are synonymous. In the context of the present invention, these terms primarily refer to structures comprising soft magnetic material deposited by electroplating and / or by sputtering on a semiconductor substrate.

[0109] In this document, the terms "vertically upward" or "vertical" or "orthogonal" or "Z-direction" refer to a direction perpendicular to a semiconductor substrate (e.g., a silicon wafer) unless expressly stated otherwise or clear from the context.

[0110] In this document, unless expressly stated otherwise or clear from the context, "magnetic field component Bz" refers to the magnetic field component typically oriented in a direction perpendicular to the semiconductor substrate, and "magnetic field components Bx and By" refer to the magnetic field components typically oriented in a direction parallel to the semiconductor substrate.

[0111] The present invention relates to the field of semiconductor substrates (e.g., semiconductor wafers or semiconductor dies) comprising at least one integrated magnetic flux concentrator (abbreviated as IMFC or IMC) and preferably further comprising at least one or at least two horizontal Hall elements, and to semiconductor devices (e.g., packaged semiconductor devices comprising one or more such semiconductor dies), as well as methods for manufacturing such semiconductor substrates (e.g., wafers, dies) and such semiconductor devices.

[0112] FIG. 1(a) shows a perspective view of a magnetic sensor structure 100 or sensor arrangement including a disk-shaped integrated magnetic flux concentrator 111 and two horizontal Hall elements H1, H2 located on either side of the disk near its periphery. As known in the art, this sensor structure is capable of measuring a magnetic field component Bx oriented along the X-axis and a magnetic field component Bz oriented along the Z-axis. The signal Bx can be calculated, for example, using the following formula: Bx=A*(S2-S1), where A is a predetermined constant, S1 is the signal obtained from the first Hall element H1, and S2 is the signal obtained from the second Hall element H2. The signal Bz can be calculated, for example, using the following formula: Bz=K*(S1+S2), where K is a predetermined constant, S1 is the signal obtained from the first Hall element H1, and S2 is the signal obtained from the second Hall element H2.

[0113] A known method for producing such a semiconductor substrate is as follows. a) providing a semiconductor substrate including one or more horizontal Hall elements, the semiconductor substrate including an "interconnect stack" (also known as a "metal stack") including four metal layers separated by insulating layers, the interconnect stack including a passivation layer; b) providing a seed layer over the passivation layer; c) depositing a soft magnetic material (eg, Fe) on the seed layer by electroplating.

[0114] The thickness or total thickness of the IMC can be determined by selecting appropriate parameters of the electroplating step, including the amplitude and duration of the current. The advantages of electroplating are, among others, that (i) it is a relatively fast technique, and (ii) electroplating does not require very high temperatures that may be detrimental to the correct functioning of the underlying components, and (iii) since the soft magnetic material is deposited only above the seed layer, no additional steps are required to remove excess material.

[0115] However, this technique also presents several problems.

[0116] One such issue is that it requires significant effort to find the optimal process parameters for the electroplating step, which, in turn, depend heavily on the specific design or layout at hand and therefore need to be re-optimized for each new design or product.

[0117] Another problem encountered by the inventors is that when the "IMC coverage" is greater than about 2%-3%, it becomes increasingly difficult to manufacture integrated semiconductor substrates having IMCs with high yields.

[0118] Another problem encountered by the inventors is that known techniques do not easily allow for building two different types of IMC structures with different heights on the same semiconductor substrate.

[0119] To address one or more of the above problems, the present invention provides a method for manufacturing a semiconductor substrate (e.g., a semiconductor wafer or semiconductor die) including at least one integrated magnetic flux concentrator (IMFC), comprising: a) providing a semiconductor substrate having a top surface (or top layer); b) creating at least one cavity in the top surface (or top layer); c) sputtering at least one layer of soft magnetic material; d) removing substantially all of the soft magnetic material outside the at least one cavity while leaving at least a portion (preferably at least 50%, or at least 70%, or at least 80%, or at least 90%, or at least 95%, or substantially all) of the soft magnetic material inside the at least one cavity.

[0120] Optionally, step d) comprises applying a chemical and mechanical polishing (CMP) or lift-off.

[0121] Optionally, step c) may comprise depositing one or more stress relief layers.

[0122] This combination of features is not trivial for the following reasons, among others: - There is a general perception that sputtering requires very long times which makes the process very expensive and therefore not an economically viable solution for competitive markets such as industrial or automotive applications; - because the IMFC is applied onto the semiconductor substrate, i.e. after the semiconductor substrate has been manufactured, and taking into account that sputtering is carried out in a vacuum at high temperatures, there is a significant risk that the underlying electronics will be adversely affected, especially in view of the long times required for sputtering compared to electroplating (typically ten times greater), and moreover, this is all the more true if the height of the IMFC structures to be constructed is larger than the typically currently used height of around 20 μm; - Applying soft magnetic material by sputtering is one thing, but because the deposition of the sputtered material is not limited to locations above the seed layer, the inventors had to come up with a way to "pattern" the sputtered material. They came up with the idea of ​​building a cavity, sputtering the material over the entire surface, and then applying CMP or lift-off to remove the excess material. Note that CMP is typically used for planarization purposes; similarly, lift-off is not typically used for patterning purposes. - Finally, even if it is possible to deposit a relatively thick (e.g. height ≥ 25 μm) IMC by sputtering, the resulting product must be suitable for operating in an industrial or automotive environment, which means among other things that the reliability and lifetime of the sensor device must not be adversely affected, meaning for example that the IMC must not delaminate when used in the temperature range from -40 °C to +140 °C.

[0123] The advantages of the proposed method without an electroplating step are that less effort is needed to find the optimal process parameters, no seed layer formation is required, and the "IMC coverage" can be higher than e.g. 5%, or higher than e.g. 10%, or higher than 15%, or higher than 20%.

[0124] It has surprisingly been found that the proposed method can be used not only to build IMC structures such as the disk shape shown in FIG. 1, which has a typical height of about 20 μm and a typical diameter of about 200 μm, but also to build IMC structures having heights of at least 20 μm, or at least 25 μm, or at least 30 μm, or at least 40 μm, or at least 50 μm, or at least 60 μm.

[0125] In particular, it has been surprisingly found that when the height of the constructed IMC structure is at least 25 μm, or at least 30 μm, or at least 40 μm, electronic components mounted below the semiconductor substrate (e.g., horizontal Hall elements, bias circuits, operational amplifiers, etc.) are not adversely affected (or are not significantly affected), despite the relatively long times required to sputter the soft magnetic material.

[0126] These are the main underlying ideas and principles and advantages of embodiments of the present invention. Particular embodiments may provide further or other advantages, as will be explained in more detail below.

[0127] Before describing a method for manufacturing an integrated semiconductor substrate including an integrated magnetic flux concentrator, some illustrative examples of possible IMFC structures are shown in Figures 1(a)-8, although the invention is not limited thereto.

[0128] FIG. 9 shows a flow chart illustrating a method for manufacturing an integrated semiconductor substrate having the IMFC illustrated in, for example, FIGS.

[0129] 10 to 14 show intermediate semiconductor substrates which can be obtained by carrying out the method shown in FIG. 9 or variations thereof.

[0130] FIG. 15 shows a schematic diagram of an integrated transformer as another example of a device in which an integrated flux concentrator can be used.

[0131] Now, reference is made to the figure.

[0132] 1(a) shows a magnetic sensor structure 100, already discussed above, including a semiconductor substrate (not shown explicitly) having two horizontal Hall elements H1, H2 and a disk-shaped IMFC 111. The disk-shaped IMFC 111 can be made in a classical manner using electroplating or according to the method proposed by the present invention.

[0133] Preferably, the height (or thickness) of disk 111 is in the range of 2.0 μm to 50 μm, or 5 μm to 40 μm, or 10 μm to 30 μm, or 15 μm to 25 μm, or 20 μm to 25 μm, and preferably, the diameter of disk 111 is in the range of 100 μm to 250 μm, or 150 μm to 250 μm, or 200 μm to 250 μm.

[0134] FIG. 1(b) illustrates the sensor structure 100 of FIG. 1(a) in cross-sectional side view.

[0135] Figure 2 shows a perspective view of a variant of the magnetic sensor structure of Figure 1(a) including a disk-shaped integrated magnetic flux concentrator 211 and four horizontal Hall elements H1-H4 located near the periphery of the disk-shaped IMFC and angularly spaced apart by multiples of 90°. This sensor structure is capable of measuring and passively amplifying the magnetic field component Bx oriented along the X-axis, measuring and passively amplifying the magnetic field component By oriented along the Y-direction, and measuring the magnetic field component Bz oriented along the Z-axis. The disk-shaped IMFC 211 can be made in a classical way using electroplating or according to the method proposed by the present invention.

[0136] The same preferred dimensions as mentioned for the disk of FIG. 1 apply.

[0137] 3(a)-3(d) show examples of magnetic sensor structures 300a-300d, each including a respective integrated magnetic flux concentrator 311a-311d having a central axis aligned with the center of the horizontal Hall element Hc. These sensor structures can measure and passively amplify the magnetic field component Bz oriented in the Z direction. These IMFC structures can be made in a classical manner using electroplating or according to the method proposed by the present invention. It is noted that more detailed information regarding the sensor structures or devices shown in FIGS. 3(a)-8 can be found in co-pending patent application EP20205330.2, filed on November 3, 2020 by the same applicant and incorporated herein by reference in its entirety.

[0138] Preferably, the height (in the Z direction) of the IMFCs 311a to 311d is in the range of 2.0 μm to 80 μm, or 5 μm to 60 μm, or 10 μm to 50 μm, or 20 μm to 50 μm, or 30 μm to 80 μm, for example, equal to about 25 μm, or equal to about 30 μm, or equal to about 35 μm, or equal to about 40 μm, or equal to about 45 μm, and preferably, the maximum transverse The dimensions (e.g., diameter in the case of a cylindrical shape, or average diameter in the case of a truncated cone shape, or maximum diagonal in the case of a prism shape) are in the range of 2.0 μm to 80 μm, or 5 μm to 60 μm, or 10 μm to 50 μm, or 20 μm to 50 μm, for example, equal to about 25 μm, or equal to about 30 μm, or equal to about 35 μm, or equal to about 40 μm, or equal to about 45 μm.

[0139] In certain embodiments, the ratio (H / D) of the height (H) to said maximum transverse dimension (D) is at least 25%, or at least 30%, or at least 40%, or at least 50%, or at least 60%, or at least 75%, or at least 90%, or at least 100%, or at least 110%, ensuring a good magnetic gain Gz.

[0140] FIG. 4(a) shows an example of a magnetic sensor structure 400 (or sensor arrangement) that can be manufactured by the method according to the invention, including a first magnetic flux concentrator 411 in the form of a ring, two horizontal Hall elements H1, H3 arranged near the periphery of the ring 411, and a second magnetic flux concentrator 412 in the form of a cylinder or prism or truncated cone shape having its central axis aligned with the center of the third horizontal Hall element Hc.

[0141] The sensor structure 400 can measure and passively amplify a magnetic field component Bx oriented in the X-direction and can measure and passively amplify a magnetic field component Bz oriented in the Z-direction. The height of the ring 411 may be substantially equal to, or smaller than, or larger than, the height of the frustoconical shape 412. The ring 411 may have a height in the range of about 20 μm to about 30 μm (e.g., equal to about 25 μm) and an outer diameter in the range of about 150 μm to about 250 μm (e.g., equal to about 220 μm). The height of the cylindrical or frustoconical or prismatic IMFC 412 may be a value in the range of about 30 μm to about 60 μm and the diameter (or average diameter or maximum diagonal) may be a value in the range of about 20 μm to about 40 μm (e.g., equal to about 30 μm).

[0142] As will become further apparent, in embodiments where both IMFC structures 411, 412 have the same height, they may both be formed simultaneously, for example, both by electroplating or both by sputtering. In another embodiment, the ring-shaped IMFC 411 is formed by electroplating and the IMFC 412 is formed by sputtering. In another embodiment, the ring-shaped IMFC 411 is formed by sputtering and the IMFC 412 is formed by electroplating. In yet another embodiment, the ring-shaped IMFC 411 and the lower portion of the IMFC 412 are both formed by electroplating and the upper portion of the IMFC 412 is formed by sputtering.

[0143] It is an advantage of the embodiment in which the height of the ring-shaped IMC 411 and the height of the central IMC 412 are the same, that all the IMC structures can be formed simultaneously.

[0144] Preferably, the height H of the ring 411 is in the range of 2 μm to 50 μm, or 5 μm to 40 μm, or 10 μm to 30 μm, or 15 μm to 25 μm, or 20 μm to 25 μm, for example, a value equal to about 20 μm, preferably, the outer diameter of the ring 411 is in the range of 100 μm to 250 μm, or 150 μm to 250 μm, or 200 μm to 250 μm, for example, a value equal to about 200 μm, preferably, the width W of the ring 411 is in the range of 2 μm to 50 μm, or 5 μm to 40 μm, or 10 μm to 30 μm, or 15 μm to 25 μm, or 20 μm to 25 μm. The width W may be equal to or greater than the height H.

[0145] The preferred dimensions of central element 412 are the same as those mentioned in FIG.

[0146] FIG. 4(b) is a cross-sectional side view of the sensor structure 400 of FIG. 4(a).

[0147] FIG. 5 shows a perspective view of a variant 500 of the magnetic sensor structure of FIG. 4(a) that includes a ring-shaped integrated magnetic flux concentrator 511, four horizontal Hall elements H1-H4 located near the periphery of the ring 511 and angularly spaced apart by multiples of 90°, and a second magnetic flux concentrator 512 in the form of a cylinder or prism or truncated cone having a central axis aligned with the center of the fifth horizontal Hall element Hc, which can be manufactured by a method according to the invention.

[0148] The sensor structure 500 can measure and passively amplify a magnetic field component Bx oriented along the X-axis, can measure and passively amplify a magnetic field component By oriented along the Y-axis, and can measure a magnetic field component Bz oriented along the Z-axis. The height of the ring 511 may be substantially equal to, less than, or greater than the height of the central IMFC 512.

[0149] Similar to what is referred to in FIG. 4, the first and second IMFCs 511, 512 may both be formed by electroplating, or both by sputtering, or one may be formed by electroplating and the other by sputtering, or the ring 511 and the lower portion of the second IMFC 512 may be formed by electroplating, and then the upper portion of the second IMFC 512 may be formed by sputtering onto the lower portion.

[0150] The preferred dimensions of central element 512 are the same as those mentioned in FIG. 3, and the preferred dimensions of ring 511 are the same as those mentioned in FIG.

[0151] FIG. 6 shows a top view of another magnetic sensor structure 600 capable of measuring and passively amplifying three orthogonal magnetic field components Bx, By, Bz that can be manufactured by the method according to the invention.

[0152] The structure 600 includes a central horizontal Hall element Hc and a first (e.g., cylindrical, frusto-conical or prism-shaped) IMFC 611 located above and aligned with the central horizontal Hall element Hc, and further includes four horizontal Hall elements H1-H4 and four elongated IMFC elements 612a-612d oriented radially outward relative to the four horizontal Hall elements, forming a so-called "sun shape".

[0153] Similar to what is referred to in FIG. 4, the first IMFC 611 and the second IMFC elements 612a-612d may all be formed by electroplating, or all by sputtering, or the central IMFC 611 may be formed by electroplating and the elongated IMFC elements 612a-612d may be formed by sputtering, or the elongated elements 612a-612d and the lower part of the central IMFC 611 may be formed by electroplating, and then the upper part of the central IMFC 611 may be formed by sputtering over the lower part.

[0154] Preferably, the height (or thickness) of the elongate elements 612a-612d is in the range of 2 μm to 50 μm, or 5 μm to 40 μm, or 10 μm to 30 μm, or 15 μm to 25 μm, or 20 μm to 25 μm, the width W of the elongate elements 612a-612d is in the range of 2 μm to 50 μm, or 5 μm to 40 μm, or 10 μm to 30 μm, or 15 μm to 25 μm, or 20 μm to 25 μm, and the length L of the elongate elements 612a-612d is in the range of 40 μm to 250 μm. Preferably, the width W of the elongate elements 612a-612d is equal to or greater than the height of the elongate elements.

[0155] The preferred dimensions of central element 611 are the same as those mentioned in FIG.

[0156] The height of the elongated IMFC elements 612a-612d may be less than, substantially equal to, or greater than the height of the central IMFC 611.

[0157] It is an advantage of the embodiment in which the height of the central IMC 611 and the height of the elongated IMC elements 612a-612d are the same, that all the IMC structures can be formed simultaneously.

[0158] FIG. 7 shows a top view of a magnetic structure 700, which is a variation of the magnetic sensor structure 600 of FIG. 6, capable of measuring and passively amplifying three orthogonal magnetic field components Bx, By, Bz, which can be manufactured by the method according to the invention.

[0159] The structure includes a central horizontal Hall element Hc and a first (e.g., cylindrical, frusto-conical or prism-shaped) IMFC 711 positioned above and aligned with the central horizontal Hall element Hc, and further includes four horizontal Hall elements H1-H4 and four elongated IMFC elements 712a-712d oriented radially inward relative to the four horizontal Hall elements H1-H4.

[0160] The central IMFC 711 and the elongated IMFC elements 712a-712d may be manufactured in the same manner as that of FIG.

[0161] The central IMFC 711 and the elongated IMFC elements 712a-712d may have the same dimensions as mentioned in FIG.

[0162] 8 is a schematic diagram of an integrated semiconductor device 800 that includes a semiconductor substrate 822 embedded in a housing 870. The housing may further include a lead frame (not shown) having elongated leads having outer portions (known as "pins") that extend from the housing.

[0163] The semiconductor substrate 822 includes a first magnetic sensor structure (shown on the left in FIG. 8) including a first IMFC 811 having a first shape and a first height, and further includes a second magnetic sensor structure (shown on the right in FIG. 8) including a second IMFC 812 having a second shape and a second height that may be less than, substantially equal to, or greater than the first height. The first IMFC 811 may have a disk or ring shape, or another shape. The second IMFC 812 may have a cylindrical, frusto-conical, or prismatic shape, or another shape.

[0164] The main purpose of Figure 8 is to show an example of a semiconductor device 800 having a semiconductor substrate 822 including different IMFC structures adjacent to each other, in contrast to the examples shown in Figures 4(a) to 5 where the central IMFC is located inside a ring-shaped IMFC, or in contrast to the examples in Figures 6 and 7 where the central IMFC is located at the centre of an elongated IMFC element.

[0165] Most of what has been said above applies mutatis mutandis here too. For example, both IMFC structures 811, 812 may be manufactured by electroplating, or both IMFC structures 811, 812 may be manufactured by sputtering, or one of them may be manufactured by electroplating and the other by sputtering, or the first IMFC 811 and the lower part of the second IMFC 812 may be manufactured by electroplating and the upper part of the second IMFC 812 may be manufactured by sputtering.

[0166] 1(a) to 8 illustrate some examples of IMFC structures that can be manufactured by prior art methods or by the method according to the invention described below. It should be noted, however, that the invention is not limited to the manufacture of these exemplary structures, but also applies to other structures manufactured according to the methods described further.

[0167] 9 shows a flow chart of a method 900 for manufacturing a semiconductor substrate having at least one integrated magnetic flux concentrator (IMFC) proposed by the present invention. The method 900 includes at least the following steps: a) Providing a semiconductor substrate having a top surface or top layer (901). The top surface or top layer may comprise, for example, SiO2 or SiN or SU-8. b) creating at least one cavity on the top surface (902); c) sputtering (903) at least one layer of soft magnetic material, which may include, for example, one or more of Fe, Ni, FeNi, Fe-based alloys, Ni-based alloys, FeNi-based alloys, Co-based alloys, metallic glasses, mu-metals, etc. d) removing substantially all of the soft magnetic material outside the at least one cavity while leaving at least a portion of the soft magnetic material inside the at least one cavity (904).

[0168] The method may further include a step f) of providing or growing (906) a sacrificial layer, for example a SiO2 layer, or a photoresist layer.

[0169] The method may further include step e) of applying (905) a stress relief layer, for example a polymer, for example polyimide, Al, or AlN, or Al2O3, or SiO2, or Ta2O5, or an Al-based, or Si-based, or Ta-based material, see also Figure 11(c) and Figure 12(c).

[0170] Step d) may include applying a chemical and mechanical polishing (CMP).

[0171] Step d) may involve applying a lift-off technique (see also FIG. 14(d)).

[0172] Step b) may include applying a photoresist layer (902) and patterning the photoresist layer using lithography.

[0173] Figures 10(a)-14(d) show intermediate semiconductor structures that can be obtained by performing some or all of the steps of the method of Figure 9. The invention is not limited to the specific examples shown in Figures 10(a)-14(d) and the method steps used to construct these structures, but these examples illustrate the various method steps and their effects.

[0174] FIG. 10(a) shows a semiconductor substrate 1000a, e.g., a semiconductor wafer or a semiconductor die. The substrate 1000a shown in FIG. 10(a) preferably has an active surface including at least one horizontal Hall element 1001 and an interconnect stack 1023 (also known as a "metal stack") above the active surface. The interconnect stack preferably includes at least four metal layers M1-M4 (not explicitly shown), with M1 being the metal layer closest to the horizontal Hall element. The substrate 1000a further includes a top layer 1024, e.g., a passivation layer, or SiO2 or SiN, or a photoresist layer, e.g., SU-8. The substrate 1000a may be a CMOS wafer. Of course, in practice, the semiconductor substrate may be much more complex than the simple example shown here and may include more than one horizontal Hall element.

[0175] FIG. 10(b) shows the semiconductor substrate 1000a of FIG. 10(a) after providing a cavity 1026 on its upper surface. The cavity may be formed, for example, by etching. In the illustrated example, the central axis of the cavity is aligned with the center of the horizontal Hall element 1001, as for example when making the IMFC shown in FIGS. 3(a)-3(d) or when making the central IMFC shown in FIGS. 4(a)-7, but this is not essential. In fact, when building the IMFC structure shown in FIG. 1(a) or FIG. 2, the outer periphery of the cavity 1026 is located above or near the horizontal Hall element.

[0176] In the example shown in FIG. 10(b), the cavity 1026 extends to the top of the interconnect stack 1023 (also referred to as the "metal stack"), although this is not essential. Indeed, in some embodiments, the cavity 1026 may extend partially into the interconnect stack. This aspect is not shown in FIG. 10(b) but is described in more detail in patent application EP19176438.0 filed May 24, 2019 by the same applicant, which is incorporated herein by reference in its entirety (see in particular Figures 3 and 5 and 7 and the corresponding description), and in patent application EP20205330.2 filed November 3, 2020 by the same applicant, which is also incorporated herein by reference in its entirety (see in particular Figures 13(a)-13(d) and the corresponding description). To understand the present invention, it is sufficient to know that the cavity typically extends to one of the metal layers, which acts as an etch stop.

[0177] Figure 10(c) illustrates the semiconductor substrate 1000b of Figure 10(b) after depositing one or more layers of one or more materials, including sputtering at least one layer of soft magnetic material. In the particular example of Figure 10(c), a single layer of soft magnetic material is sputtered, although the invention is not so limited (see, e.g., Figure 11(c) or Figure 13(c)).

[0178] Depending on the height (or thickness) of the one or more deposition layers and their depth of penetration into the interconnect stack (if applied), the top of the deposited material in the cavity extends below or above the top of layer 1024. The height of the deposition layer can be determined by controlling the sputtering parameters, including the duration of sputtering, in a manner known per se in the art. In some embodiments, the top of the one or more deposition layers is lower than, substantially at the same height as, or higher than the top of layer 1024. In the particular example of FIG. 10(c), the cavity does not penetrate into the interconnect stack and the height of the deposition layer is greater than the height of layer 1024, so that the top of the deposition material inside cavity 1026 is above the top of layer 1024.

[0179] Figure 10(d) shows the semiconductor substrate 1000c of Figure 10(c) after removal of all, or at least most, of the soft magnetic material outside of the cavity 1026. This removal can be done by chemical and mechanical polishing (CMP), as shown diagrammatically by the scissors symbol. The result is a semiconductor substrate 1000d having integrated magnetic flux concentrators 1027.

[0180] It is an advantage of embodiments that the polishing does not physically contact the soft magnetic material (e.g., when the top of the deposited layer inside the cavity is lower than the top of layer 1024), which may improve the magnetic properties.

[0181] It is an advantage of the embodiment that the grinding physically contacts the soft magnetic material (e.g., when the top of the deposited layer inside the cavity is higher than the top of layer 1024) because this provides an IMFC with a flat top surface.

[0182] Optionally, layer 1024 may also be removed or partially removed. This is typically the case when a sacrificial layer (e.g., a photoresist layer) is applied on top of the semiconductor substrate 1000a of FIG. 10(a). The advantage of not removing this layer 1024 is that the IMFC 1027 is mechanically supported on its sides and thus the risk of the IMFC 1027 detaching from the semiconductor substrate over time is reduced. The advantage of removing this layer 1024 is that the IMFC 1027 does not experience mechanical stress from the sidewalls, which may be beneficial for its magnetic properties (e.g., saturation, hysteresis, etc.). Optionally, a (further) protective layer, for example a SiN layer, may be applied over the substrate (not shown).

[0183] Optionally, a stress relief layer (not shown), for example a continuous stress relief layer, for example a polymer layer, for example a polyimide layer, may be present between interconnect stack 1023 and layer 1024 .

[0184] In summary, FIG. 10(d) therefore illustrates a semiconductor substrate 1000d (e.g., a semiconductor wafer or a semiconductor die) including an IMFC structure 1027 that can be obtained by b) creating a cavity, and c) sputtering a magnetic material, and d) applying chemical and mechanical polishing (CMP).

[0185] Although not explicitly shown, one of ordinary skill in the art having the benefit of this disclosure will understand that a semiconductor wafer can be cut into a plurality of semiconductor dies, which can be mounted and overmolded onto a leadframe in known manner to form a packaged device. Depending on the functionality implemented on the semiconductor substrate, the packaged device can be, for example, a sensor device, a current sensor device, a linear position sensor device, an angular position sensor device, a proximity sensor device, a proximity switch, a microtransformer, and the like, all of which are contemplated by the present invention.

[0186] 11(a) to 11(d) show intermediate semiconductor substrates 1100a to 1100d which are a variation of FIGS. 10(a) to 10(d) and relate to another method according to an embodiment of the present invention which is a variation of FIG.

[0187] The main difference between the semiconductor substrates of Figures 11(a)-(d) and 10(a)-(d) is that a stress relief layer is also deposited. More specifically, Figures 11(a) and 11(b) are identical to Figures 10(a) and 10(b).

[0188] FIG. 11(c) shows the semiconductor substrate 1100c obtained after depositing one or more layers of one or more materials on the semiconductor substrate 1100b of FIG. 10(b), where the first (lower) layer is a stress relief layer 1130 and at least one of the other layers is a soft magnetic material deposited by sputtering.

[0189] The stress relief layer 1130 may be or include a polymer or polyimide layer, which may be deposited by spin coating, for example. The stress relief layer may be or include Al or an Al alloy, which may be deposited by electroplating or by sputtering, for example. The stress relief layer may be or include AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based or Si-based or Ta-based material, which may be deposited by sputtering, for example.

[0190] The stress relief layer 1130 may have a thickness in the range of about 0.5 nm to about 100 nm, or about 0.5 nm to about 40 nm, or about 1.0 nm to about 40 nm, or about 1.0 nm to about 20 nm, or about 1.0 nm to about 10 nm, or about 2.0 nm to about 20 nm, or about 2.0 nm to about 10 nm, or about 2.0 nm to about 4.0 nm, for example, equal to about 2 nm, or equal to about 3 nm, or equal to about 4 nm, or equal to about 5 nm.

[0191] A major advantage of applying such a stress relief layer 1130 is that the mechanical stress at the interface between the soft magnetic material and the semiconductor material (e.g., mainly Si) is reduced, reducing the risk of delamination and improving the reliability and / or lifetime of the device.

[0192] Figure 11(d) shows the semiconductor substrate 1100c of Figure 11(c) after removal of all, or at least most, of the soft magnetic material 1125 outside the cavity 1126. This removal can be done by chemical and mechanical polishing (CMP), as shown diagrammatically by the scissors symbol. The result is a semiconductor substrate 1100d having integrated magnetic flux concentrators 1127 on top of the stress relief material 1130.

[0193] Several variations similar to those described in Figures 10(a) to 10(d) are possible, either alone or in combination, such as: The cavity 1126 may extend partially into the interconnect stack 1123 . The total height of the deposited layers (including the stress relief layer and the soft magnetic material) may be less than, substantially equal to, or greater than the height of layer 1124. Optionally, layer 1124 may be removed from substrate 1100d, for example by etching. - Optionally, a (further) protective or passivation layer may be provided on the substrate 1100d. Optionally, the edge of the outer periphery of the cavity may be adjacent to at least one horizontal Hall element, rather than being on the central axis of the cavity.

[0194] In summary, Figure 11(d) therefore illustrates a semiconductor substrate 1100d including an IMFC structure 1127 which can be obtained by b) creating a cavity, and e) providing a stress relief layer, and c) sputtering a magnetic material, and d) applying chemical and mechanical polishing (CMP).

[0195] 12(a)-12(d) show intermediate semiconductor substrates 1200a-1200d which are associated with another method according to an embodiment of the present invention, which is a variation of FIG. 9. The main difference between the semiconductor substrates of FIGS. 12(a)-(d) and 11(a)-(d) is that (i) the cavity 1226 of FIGS. 12(a)-(d) has upright walls that form an angle φ with respect to the semiconductor substrate, which angle φ may be obtained, for example, by anisotropic etching, and which is different from 90°, for example in the range of 40° to 85°; and (ii) the semiconductor substrate of FIGS. 12(a)-(d) has at least two horizontal Hall elements; and (iii) The edge of the cavity (rather than the central axis of the cavity) is located near the horizontal Hall element.

[0196] Differences (ii) and (iii) are related to each other but are structurally and functionally unrelated to difference (i).

[0197] An advantage of the embodiment shown in FIG. 12(d) is that the IMFC 1227 experiences less mechanical compression from the material 1224 on the sidewalls (which is beneficial for its magnetic properties) while at the same time improving the mechanical connection and therefore reducing the risk of detachment from the semiconductor substrate due to the larger surface area.

[0198] In summary, FIG. 12(d) therefore illustrates a semiconductor substrate including an IMFC structure 1227 which can be obtained by b) creating a cavity with beveled edges, and e) providing a stress relief layer, and c) sputtering a magnetic material, and d) applying chemical and mechanical polishing (CMP).

[0199] 13(a) to 13(d) show a variation of FIGS. 10(a) to 10(d) and show intermediate semiconductor substrates 1300a to 1300d relating to another method according to an embodiment of the present invention, which is a variation of FIG.

[0200] The main difference between the semiconductor substrate 1300a of Fig. 13(a) and the semiconductor substrate 1000a of Fig. 10(a) is that the semiconductor substrate 1300a of Fig. 13(a) explicitly shows a passivation layer 1328 on its top surface. The semiconductor substrate 1300a may be a CMOS wafer.

[0201] The main difference between the semiconductor substrate 1300b of Figure 13(b) and the semiconductor substrate 1000b of Figure 10(b) is that the cavity 1326 of the semiconductor substrate 1300b of Figure 13(b) extends partially into the interconnect layer 1323, for example until it reaches one of the metal layers M1-M4. In the illustrated example, the cavity extends to the metal layer M3, which acts as an etch stop.

[0202] The main difference between the semiconductor substrate 1300c of FIG. 13(c) and the semiconductor substrate 1000c of FIG. 10(c) is that instead of only one layer, multiple layers 1331.i, 1325.i (i being an integer) are applied. In the particular example shown, a stack of two alternating layers N times is sputtered. One layer 1332.i is a stress relief layer, and the other layer 1325.i is or includes a soft magnetic material, such as, for example, Fe or Ni or FeNi, or Fe-based or Ni-based or FeNi-based, or Co-based, or mu-metal or metallic glass. Some or all of the stress relief layers 1331.i may have a thickness of about 0.5 nm to about 100 nm, or about 1 nm to about 20 nm, or about 2 nm to about 10 nm, and may include, for example, Al or AlN or Al2O3 or SiO2 or Ta2O5, or Al-based or Si-based or Ta-based materials, which may be applied by sputtering. Some and all of the soft magnetic layers 1325.i may have a thickness of about 50 nm to about 1000 nm, or about 50 nm to about 500 nm, or about 50 nm to about 200 nm. As mentioned above, the total stack of these sputtered layers may have a height in the range of, for example, 2.0 μm to 80 μm. If necessary, additional layers may or should be applied over the passivation layer 1328 in step a) before creating the cavity 1326.

[0203] In one embodiment, the thickness of some or all of the layers including or consisting of a soft magnetic material layer is at least 2.0 times, or at least 2.5 times, or at least 3 times, or at least 4 times, or at least 5 times, or at least 7 times, or at least 8 times, or at least 10 times the thickness (e.g., the thinnest or thickest or average or median thickness) of one of the metal layers (M1-M3 or M1-M4) of the interconnect stack.

[0204] As can be seen from Figures 13(c) and 13(d), if the total thickness of the stack layers deposited in the cavity 1326 is less than the penetration depth inside the interconnect stack 1323 plus the height of the passivation layer 1328 and any additional layers applied thereon, the polishing will not physically contact the stack layers. As mentioned above, this can be beneficial to the magnetic properties of the stack. The stack of layers 1327 has soft magnetic properties and is therefore also referred to herein as an integrated magnetic flux concentrator "IMFC."

[0205] The advantages of the embodiment shown in FIG. 13(d) are: (i) the original passivation layer 1328 is largely left intact, and thus the addition of another passivation layer on the substrate may be optionally omitted; and (ii) the IMFC 1327 is partially embedded within the interconnect stack 1323 (which may provide good mechanical grip), thus reducing the risk of detachment without providing excessive mechanical pressure from the sidewalls; (iii) IMFC1327 includes two alternating layers of a multiple N, one of which is a stress relief layer and the other of a soft magnetic material. This provides the best of both worlds: a stack that is flexible enough to absorb some mechanical pressure / stress and has good magnetic properties. Thus, IMFC1327 may include a total number of 2*N layers, where N is an integer value of at least 2, for example in the range of 2 to 100, for example in the range of 5 to 50, or in the range of 10 to 40, or in the range of 15 to 30, for example equal to about 20, or equal to about 25.

[0206] In summary, FIG. 13(d) therefore illustrates a semiconductor substrate 1300d including an IMFC structure 1327 which can be obtained by b) creating a cavity 1326 extending into the interconnect stack, and c) sputtering a multiple N-fold of two layers: one stress relief layer and one soft magnetic layer, and d) applying chemical and mechanical polishing (CMP).

[0207] 14(a)-14(d) show a variation of FIGS. 10(a)-10(d), which in turn show intermediate semiconductor substrates 1400a-1400d relating to another method according to one embodiment of the present invention, which is a variation of FIG. 9.

[0208] The main difference between the semiconductor substrate of Figures 14(a-c) and the semiconductor substrate of Figures 10(a-c) is that the semiconductor substrate of Figures 14(a-c) explicitly shows a sacrificial or resist layer 1429 on its top surface. The semiconductor substrate 1400a may be a CMOS wafer.

[0209] Another difference between the method associated with the intermediate substrate in Figures 10(a-d) and the method associated with the intermediate substrate in Figures 14(a-d) is that the semiconductor substrate 1400d in Figure 14(d) is obtained by removing a sacrificial or resist layer, and the material sputtered thereon, by a lift-off process instead of a chemical and mechanical polishing step (CMP).

[0210] In a preferred embodiment, the top of the deposition layer in the cavity does not reach the bottom of the deposition layer of the sacrificial or resist layer, which means that in a preferred embodiment the sum of the penetration depth into the interconnect stack (if applied) and the height of the deposition layer is less than the height of layer 1429. This reduces the risk that material deposited on the sacrificial or resist layer outside of cavity 1426 will not be completely removed by the lift-off process.

[0211] In one embodiment, a chemical and mechanical polishing (CMP) step is performed on the semiconductor substrate 1400c to at least partially remove some of the excess material outside the cavity and reduce the risk of some of the excess material adhering to the soft magnetic material 1427 within the cavity.

[0212] In summary, Figure 14(d) therefore illustrates a semiconductor substrate 1400d including an IMFC structure 1427 which can be obtained by f) providing a resist or sacrificial layer, b) creating a cavity, and c) sputtering a magnetic material, and d) lifting off the sacrificial or resist layer.

[0213] Those skilled in the art having the benefit of this disclosure will appreciate from the examples of Figures 10(a)-14(d) that further variations are contemplated by combining features from a particular step shown in one embodiment with steps of other embodiments. For example, in all embodiments, the cavity may or may not extend partially into the interconnect stack, and / or in all embodiments, the edges of the cavity may or may not be beveled or slanted, and / or in all embodiments, a stress relief layer may or may not be applied as the first layer, and / or in all embodiments, a single magnetic layer may be sputtered or a plurality of at least two alternating layers (stress relief layer and soft magnetic layer) may be sputtered.

[0214] The present invention also proposes a method, in which a first IMC element, e.g. 811 in FIG. 8, is made by electroplating in a known manner, and a second IMC element, e.g. 812 in FIG. 8, is made using the method proposed by the present invention.

[0215] The invention also proposes a method in which a first IMFC element, e.g. 811 in FIG. 8, is made entirely (or exclusively) by electroplating, and a second IMFC element, e.g. 812 in FIG. 8, is made partially by electroplating and partially as proposed by the invention. More specifically, in this embodiment, first the first IMFC element and the lower part of the second IMFC element are made by electroplating, the electroplated substrate (e.g. a semiconductor wafer) is used in step a) of the method of the invention in FIG. 9, then in step f) a sacrificial layer, e.g. a photoresist layer, is deposited, in step b) a cavity is made that extends to the top of the (electroplated) lower part of the second IMFC, and in step c) additional material is added by sputtering on top of its lower (electroplated) part to make the semiconductor wafer. Such a "hybrid method" offers the advantage that a semiconductor substrate with first and second IMFC elements with different heights can be produced. Note that the same variations mentioned above can also be applied here, e.g., the cavity may or may not have slanted walls, the top layer of the second IMFC may be a single layer or may include multiple alternating layers, etc.

[0216] For the sake of completeness, Fig. 15 is a schematic diagram of an integrated transformer 1500 manufactured by a method according to the invention. Methods for making semiconductor devices including one or more integrated coils are known and therefore need not be described in further detail here. The main reason for providing the drawing of Fig. 15 is to illustrate that by using the method according to the invention, it is possible to implement soft magnetic cores 1511 inside those coils. No further details are considered necessary.

[0217] The drawings are only schematic and non-limiting. In the drawings, the size of some elements may be exaggerated and not drawn to scale for illustrative purposes. Any reference signs in the claims should not be construed as limiting the scope. The same reference signs in different drawings refer to the same or similar elements.

Claims

1. A method (900) for manufacturing a semiconductor substrate (1000d, 1100d, 1200d, 1300d; 1400d) including at least one integrated magnetic flux concentrator (1027; 1127; 1227; 1327; 1427), the method comprising: a) providing (901) a semiconductor substrate (1000a; 1100a; 1200a; 1300a; 1400a) having a top surface; b) creating (902) at least one cavity (1026; 1126; 1226; 1326; 1426) in said top surface; c) depositing (903) one or more layers (1331; 1325) of one or more materials, including sputtering at least one layer (1025; 1125; 1225; 1325; 1425) of a soft magnetic material; d) removing (904) substantially all of the soft magnetic material outside of the at least one cavity (1026; 1126; 1226; 1326; 1426), while leaving at least a portion of the soft magnetic material inside the at least one cavity; Step c) is i) sputtering a stress relief layer (1331.1); and ii) sputtering a layer (1325.1) of soft magnetic material at least twice to form a stack of layers, Method (900).

2. Step d) comprises removing (904) substantially all of the soft magnetic material outside the at least one cavity (1026; 1126; 1226; 1326) by applying a chemical mechanical polishing (CMP); 2. The method of claim 1 (900).

3. Step d) includes removing (904) substantially all of the soft magnetic material outside of the at least one cavity (1426) by applying a lift-off; 3. The method (900) of claim 1 or 2.

4. Step b) includes applying a photoresist layer to the top surface (902) and patterning the photoresist layer; The method (900) according to any one of claims 1 to 3.

5. Step b) comprises creating (902) said at least one cavity (1026; 1126; 1226; 1326; 1426) to have a first predetermined height (H1) in a direction (Z) perpendicular to said semiconductor substrate (1000a; 1100a; 1200a; 1300a; 1400a), Step c) comprises depositing (903) the one or more layers over a second height (H2) in the direction (Z) perpendicular to the semiconductor substrate; The second height (H2) is greater than the first height (H1); The method (900) according to any one of claims 1 to 4.

6. Step a) comprises providing (901) a semiconductor substrate (1300a) comprising at least one magnetic sensor element and an interconnect stack (1323) comprising at least three or at least four metal layers (M1-M4); Step b) includes creating (902) the at least one cavity (1326) to extend at least partially into the interconnect stack (1326); The method (900) according to any one of claims 1 to 5.

7. Step b) comprises creating (902) said at least one cavity (1326) to extend to one of said metal layers (M1, M2, M3, M4) of said interconnect stack; 7. The method of claim 6 (900).

8. Step c) comprises depositing (903) a polymer layer (1130), or a polyimide, or a stress relief layer (1331.1) as a first layer of said one or more layers; The method (900) according to any one of claims 1 to 7.

9. Step c) comprises providing (903) at least one layer (1331.1) of Al or AlN or Al2O3 or SiO2 or Ta2O5 or an Al-based or Si-based or Ta-based material directly below said layer (1325.1) of soft magnetic material; and / or Step c) comprises providing at least one layer (1331.2) of Al or AlN or Al2O3 or SiO2 or Ta2O5, or an Al-based or Si-based or Ta-based material directly on said layer (1325.1) of soft magnetic material; The method according to any one of claims 1 to 8.

10. Step b) comprises creating (902) the at least one cavity (1226) with sloping sidewalls that form an angle (φ) with the semiconductor substrate different from 90°, or Step b) includes creating (902) the at least one cavity (1226) having rounded or curved sidewalls; The method (900) according to any one of claims 1 to 9.

11. Step a) comprises providing (901) a semiconductor substrate comprising at least one or at least two horizontal Hall elements (H1; H3), Step b) comprises creating (902) at least one cavity (1226) above the at least one or at least two horizontal Hall elements (H1; H3) such that the cavity (1226) has a shape with an outer edge substantially aligned with a geometric center of the at least one or at least two horizontal Hall elements (H1; H3); The method (900) according to any one of claims 1 to 10.

12. Step a) includes providing (901) a semiconductor substrate including at least one horizontal Hall element (Hc); Step b) comprises creating (902) the at least one cavity above the horizontal Hall element (Hc) such that the cavity has a shape with a geometric center aligned with the geometric center of the horizontal Hall element; The method (900) according to any one of claims 1 to 11.

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