Solid-state imaging device and imaging apparatus

Abstract

A solid-state imaging device (200) comprises: a plurality of pixels (101) disposed in a matrix; control lines (114) provided for each pixel row or each pixel column, the controls lines being connected to the pixels belonging to the corresponding pixel row or pixel column; drive circuits (111) having at least two stages of buffer elements (112a-112c) connected in series and outputting control signals to the control lines (114), the drive circuits being provided for the respective control signals; and first wiring lines (113) that, in at least two of the drive circuits (111), short-circuit output lines of the corresponding buffer elements (112) of either stage.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device, such as a charge coupled device (CCD) or complementary metal oxide semiconductor (CMOS) image sensor, and an imaging device. [Background technology]

[0002] Among the various methods for detecting objects, the Time Of Flight (TOF) method is well known, which measures distance by using the time of flight of light to the object (subject) to be measured. In the distance calculation of the TOF method, at least two exposure signals are acquired for the reflected light from the object, and the time difference or phase difference between the light emission and the light reception (the time required for the light to travel to the object and back) is calculated from the amount of the acquired exposure signals to perform the distance calculation.

[0003] In a solid-state imaging device for distance measurement, all pixels are exposed to light at the same time, so a solid-state imaging device compatible with a global shutter is used, and all pixels are shuttered at the same time. Since a difference in the shutter timing for each pixel appears as a difference in the distance for each pixel, it is necessary to reduce the time difference of the shutter in order to improve the accuracy of distance measurement.

[0004] To solve this problem, Patent Document 1 discloses a technique for reducing the time lag by providing a column skew correction circuit that adjusts the delay time of the drive signal that controls the shutter for each column. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2015 / 119243 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in Patent Document 1, the delay time of the drive signal needs to be adjusted for each column, so calibration is required for each solid-state imaging device. To perform calibration, it is necessary to actually perform distance calculations and feed back the results to the delay adjustment unit, which takes time and labor. It also increases the circuit size. If the temperature or voltage changes, the delay time also changes, so calibration is required each time. If calibration is not performed, the delay time will differ for each column, and distance measurement accuracy will decrease.

[0007] The present disclosure has been made with attention to the above-mentioned problems, and aims to provide a solid-state imaging device and an imaging apparatus that reduce the delay difference between columns of drive signals while eliminating the need for calibration to adjust the delay time of the drive signals for each column, thereby achieving high ranging accuracy. [Means for solving the problem]

[0008] In order to solve the above problems, a solid-state imaging device according to one embodiment of the present disclosure includes a plurality of pixels arranged in a matrix, a control line provided for each pixel row or pixel column and connected to the pixels belonging to the corresponding pixel row or pixel column, a drive circuit provided for each of the control lines and having at least two stages of buffer elements connected in series and outputting a control signal to the control line, and a first wiring that shorts out output lines of corresponding buffer elements in any of the stages in at least two of the drive circuits.

[0009] An imaging device according to an aspect of the present disclosure includes the solid-state imaging device, and a signal processing circuit that generates a distance image or a luminance image based on a signal received by the solid-state imaging device. Effect of the Invention

[0010] According to the present disclosure, it is possible to reduce the delay difference between each row of drive signals without the need for calibration, thereby achieving high distance measurement accuracy. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment. [Diagram 2] FIG. 2 is a block diagram showing a detailed configuration example of the solid-state imaging device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing an example of a pixel configuration and an example of an electrode driving line configuration according to the first embodiment. In FIG. [Figure 4A] FIG. 4A is a diagram showing a detailed configuration example of a pixel array and a drive circuit array according to the first embodiment. [Figure 4B] FIG. 4B is a diagram showing another configuration example of the drive circuit array according to the first embodiment. [Figure 4C] FIG. 4C is a diagram showing a modification of the pixel array and the drive circuit array according to the first embodiment. [Diagram 5] FIG. 5 is a flowchart showing an exposure operation in the first embodiment. [Figure 6] FIG. 6 is a timing chart showing the drive pulses during the exposure operation. [Figure 7] FIG. 7 is a diagram showing details of a drive circuit array according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing details of a drive circuit array according to the third embodiment. [Figure 9] FIG. 9 is a flowchart showing an exposure operation in the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the drawings. Note that the following embodiments are essentially preferred examples, and are not intended to limit the scope of the present disclosure, its applications, or its uses. Note that components with the same reference numerals in the embodiments operate in the same manner, and therefore duplicated descriptions will be omitted.

[0013] (Embodiment 1) 1. Configuration of the imaging device 1000 Fig. 1 is a block diagram showing an example of the configuration of an imaging device 1000 according to the embodiment 1. Fig. 1 also shows an object 190 for distance measurement.

[0014] As shown in the figure, the imaging device 1000 includes a light source driver 150, a light source unit 160, an optical lens 170, a signal processing circuit 180, and a solid-state imaging device 200. The solid-state imaging device 200 also includes a pixel array 100, a drive circuit array 110, a timing generation circuit 120, an AD conversion unit 130, and a vertical scanning circuit 140.

[0015] The light source driver 150 supplies a drive signal to the light source unit 160 in accordance with a signal from the timing generating circuit 120 instructing light emission.

[0016] The light source unit 160 generates pulsed light for distance measurement in accordance with a drive signal from the light source driver 150 .

[0017] The lens 170 is a lens for collecting the reflected pulsed light from the object 190 which corresponds to the pulsed light from the light source unit 160 .

[0018] The signal processing circuit 180 calculates the distance to the object 190 based on the signal received from the solid-state imaging device 200 .

[0019] The pixel array 100 includes a plurality of pixels arranged in a matrix on a semiconductor substrate. In the following description, pixels arranged in a row direction among the plurality of pixels will be referred to as pixel rows, and pixels arranged in a column direction will be referred to as pixel columns.

[0020] The drive circuit array 110 includes an arrangement of drive circuits provided for each pixel column, and supplies the pixel array 100 with control signals that control the signal charges generated in each pixel.

[0021] The timing generating circuit 120 generates a light emission signal that instructs light irradiation (here, irradiation of near-infrared light is exemplified) onto the object 190. The light emission signal drives the light source unit 160 via the light source driver 150. At this time, the timing generating circuit 120 generates an exposure signal that instructs the pixel array 100 to expose the object 190 to reflected light. For example, the timing generating circuit 120 generates an exposure signal multiple times within one frame period, and accumulates a pixel signal corresponding to the sum of the multiple exposure amounts in each pixel.

[0022] The AD conversion unit 130 converts analog pixel signals outputted from the pixel array 100 on a pixel row basis into digital pixel signals.

[0023] The vertical scanning circuit 140 sequentially scans the pixel rows of the pixel array 100 and outputs pixel signals to the AD conversion unit 130 on a pixel row basis.

[0024] 1, the solid-state imaging device 200 irradiates an object 190 with near-infrared light from a light source unit 160 in the presence of background light. The light reflected from the object 190 is incident on the pixel array 100 via an optical lens 170. The reflected light incident on the pixel array 100 forms an image, and the formed optical image is converted into a pixel signal. The output of the solid-state imaging device 200 is converted into distance data by a signal processing circuit 180, and may also be converted into a visible distance image or brightness image depending on the application.

[0025] The signal processing circuit 180 does not necessarily have to be provided outside the solid-state imaging device 200 , and some or all of the distance calculation function may be built into the solid-state imaging device 200 .

[0026] An example of the solid-state imaging device 200 is a so-called CMOS image sensor.

[0027] [1.1 Configuration of solid-state imaging device 200] 2 is a block diagram showing a detailed configuration example of the solid-state imaging device 200 according to embodiment 1. The solid-state imaging device 200 includes a pixel array 100, a drive circuit array 110, a timing generating circuit 120, and an AD conversion section .

[0028] The pixel array 100 has a plurality of pixels 101 arranged in a matrix. Here, the pixel 101 is a unit element provided, as necessary, with a device structure for reading out a signal generated by photoelectric conversion, such as a photosensitive element such as a photodiode or a photogate, a photoelectric conversion film made of amorphous silicon, or an organic photoelectric conversion film, and a structure for enabling an initialization operation. These pixels are examples of photosensitive elements, and the pixel array 100 is an example of a photosensitive element array.

[0029] The drive circuit array 110 includes at least one drive circuit 111 provided for each pixel column, and first wiring 113. The drive circuit array 110 controls charge accumulation and charge discharge of the multiple pixels 101.

[0030] The multiple drive circuits 111 output control signals having the same phase to realize a global shutter. Each drive circuit 111 applies a drive pulse as a control signal to the electrode of the pixel 101 via an electrode drive line 114 as a control line for pixel control. The electrode drive line 114 includes one or more control lines. More specifically, the drive circuit 111 supplies a control signal to the pixel array 100 for controlling resetting and reading out of signal charges generated in the pixels 101 of the corresponding pixel column. This control signal controls the simultaneous operation of all the pixels 101 to realize a global shutter. In the following, a wiring for transmitting a control signal or a drive pulse signal output from the drive circuit array 110 is referred to as an electrode drive line 114. At least one drive circuit 111 is provided for each pixel column. The number of drive circuits 111 corresponding to one pixel column depends on the configuration of the pixel 101. In addition, the "reading out" by the above control signal means the transfer of signal charges in the pixel 101, for example, the transfer (or reading out) of signal charges from a photodiode to a floating diffusion layer.

[0031] The first wiring 113 is a wiring that shorts out signal lines having control signals with the same phase in two or more of the multiple driving circuits 111. The delay times of the signal lines shorted by the first wiring 113 are averaged compared to when the signal lines are not shorted. In other words, the delay time difference between the shorted driving circuits 111 can be reduced without the need for calibration described in the prior art. In addition, since a circuit for calibration is not required, the circuit scale can be reduced.

[0032] Note that the two or more drive circuits 111 may be, for example, a set of drive circuits 111 corresponding to even-numbered pixel columns, a set of drive circuits 111 corresponding to odd-numbered pixel columns, or a set of drive circuits 111 operating in a thinning-out operation mode.

[0033] The timing generating circuit 120 generates the light emission signal and exposure signal already explained, based on instructions from the signal processing circuit 180 .

[0034] The AD conversion unit 130 includes a column ADC 131 provided for each pixel column, a memory array 132 , and an output circuit 133 .

[0035] The column ADC 131 is provided for one or more columns of pixels 101, and converts analog pixel signals output from the pixels 101 via vertical signal lines 102 into digital pixel signals. In the example shown in Fig. 2, the column ADC 131 is provided for each column. The converted digital pixel signals are transferred to the memory array 132 and sequentially output to the signal processing circuit 180 as pixel signals via the output circuit 133.

[0036] The vertical scanning circuit 140 sequentially scans the pixel array 100 in units of pixel rows, and reads and initializes pixel signals. The read pixel signals are sent to the column ADC 131 via vertical signal lines 102 provided for each column, and are converted into digital signals.

[0037] [1.2 Configuration of pixel 101] FIG. 3 is a diagram showing an example of the configuration of the pixel 101 and an example of the configuration of the electrode driving line 114. As shown in FIG.

[0038] The pixel 101 includes a photoelectric conversion section 300, a reset electrode 310, a first readout electrode 330, a second readout electrode 350, a first charge accumulation section 340, a second charge accumulation section 360, a first selection transistor 370, a second selection transistor 380, a floating diffusion layer 390, a reset transistor 400, and a source follower 410.

[0039] The photoelectric conversion unit 300 converts light into electric charges and accumulates the electric charges.

[0040] The reset electrode 310 is a gate electrode of a reset transistor that connects the charge discharging section 320 and the photoelectric conversion section 300 .

[0041] The first readout electrode 330 is a gate electrode of a first transfer transistor that reads out charges from the photoelectric conversion unit 300 to the first charge accumulation unit 340 .

[0042] The second readout electrode 350 and the gate electrode of a second transfer transistor that reads out charges from the photoelectric conversion unit 300 to the second charge accumulation unit 360 .

[0043] The first charge accumulation section 340 is a capacitance element or a diffusion layer that holds the charge read out from the photoelectric conversion section 300 .

[0044] The second charge accumulation section 360 is a capacitance element or a diffusion layer that holds the charge read out from the photoelectric conversion section 300 .

[0045] The first selection transistor 370 connects the first charge accumulation unit 340 and the gate electrode of the source follower 410 under the control of a first selection signal. The first selection signal is supplied to the gate electrode of the first selection transistor 370 from the vertical scanning circuit 140.

[0046] The second selection transistor 380 connects the second charge accumulation unit 360 and the gate electrode of the source follower 410 under the control of a second selection signal. The second selection signal is supplied to the gate electrode of the second selection transistor 380 from the vertical scanning circuit 140.

[0047] The floating diffusion layer 390 holds the charges transferred from the first charge accumulation section 340 via the first selection transistor 370 , and holds the charges transferred from the second charge accumulation section 360 via the second selection transistor 380 .

[0048] The reset transistor 400 resets the floating diffusion layer 390 in accordance with the reset signal. The reset signal is supplied from the vertical scanning circuit 140 to the gate electrode of the reset transistor 400.

[0049] The source follower 410 converts the charge held in the floating diffusion layer 390 into a voltage and outputs it to the vertical signal line 102 .

[0050] The electrode driving lines 114 include a reset control line 114A, a first readout control line 114B, and a second readout control line 114C.

[0051] When a drive pulse is applied to the reset electrode 310 via the reset control line 114 A, the charge accumulated in the photoelectric conversion unit 300 is discharged to the charge discharging unit 320 .

[0052] When a drive pulse is applied to the first readout electrode 330 via the first readout control line 114B, the charge accumulated in the photoelectric conversion unit 300 is transferred to the second charge accumulation unit 360.

[0053] When a drive pulse is applied to the second readout electrode 350 via the second readout control line 114C, the charge accumulated in the photoelectric conversion unit 300 is transferred to the second charge accumulation unit 360.

[0054] [1.3 Configuration of the driving circuit array 110] FIG. 4A is a diagram showing a detailed configuration example of the drive circuit array 110. As shown in FIG.

[0055] The pixel 101 in the figure is assumed to have the same configuration as the example shown in Figure 3. A reset control line 114A, a first readout control line 114B, and a second readout control line 114C are assumed to be connected to each pixel 101 as electrode drive lines 114 from a drive circuit array 110.

[0056] The drive circuit array 110 includes three drive circuits 111A to 111C for each pixel column. The three drive circuits 111A to 111C correspond to a reset control line 114A, a first readout control line 114B, and a second readout control line 114C, respectively. When there is no need to particularly distinguish between the drive circuits 111A to 111C, they are simply referred to as drive circuits 111.

[0057] A reset control signal having a drive pulse ΦODG is input to the drive circuit 111A of each pixel column from the timing generation circuit 120. Each drive circuit 111A outputs a reset control signal to the reset electrode 310 via the reset control line 114A for each pixel 101 in the corresponding pixel column.

[0058] A first readout control signal having a drive pulse ΦTG1 is input to the drive circuit 111B of each pixel column from the timing generation circuit 120. Each drive circuit 111B outputs a first readout control signal to the first readout electrode 330 via the first readout control line 114B for each pixel 101 in the corresponding pixel column.

[0059] A second readout control signal having a drive pulse ΦTG2 is input to the drive circuit 111C of each pixel column from the timing generation circuit 120. Each drive circuit 111C outputs a second readout control signal to the second readout electrode 350 via the second readout control line 114C for each pixel 101 in the corresponding pixel column.

[0060] Each driving circuit 111 includes at least two stages of buffer elements 112. The driving circuit 111 in the figure includes three stages of buffer elements 112a to 112c. The driving capabilities of the buffer elements 112a to 112c are configured to increase in the order of the buffer elements 112a, 112b, and 112c. The driving capability of the buffer element 112 can be increased by increasing the size of the output transistor in the buffer element 112. The driving capability of the buffer element 112 can also be increased by providing a plurality of output transistors in parallel in the buffer element 112.

[0061] When there is no need to distinguish between the buffer elements 112a to 112c, they are simply referred to as the buffer elements 112. Here, the buffer elements 112 may be inverter circuits that invert the polarity, or buffer circuits that do not change polarity.

[0062] The first wiring 113 is at least one wiring that shorts signal lines that transmit signals of the same phase in two or more drive circuits 111. In the figure, the first wiring 113 includes three types of first wiring 113A, 113B, and 113C corresponding to a reset control line 114A, a first readout control line 114B, and a second readout control line 114C. Furthermore, the first wiring 113 includes three types of first wiring 113D, 113E, and 113F corresponding to the reset control line 114A, the first readout control line 114B, and the second readout control line 114C.

[0063] Ignoring delay time differences, each of the drive circuits 111A drives a reset control signal with the same phase as the drive circuits 111A of the other columns. Similarly, each of the drive circuits 111B corresponding to each column drives a first read control signal with the same phase as the drive circuits 111B of the other columns. The same is true for the drive circuit 111C.

[0064] The first wiring 113A shorts out wirings having signals of the same phase in two or more driving circuits 111A. In the figure, the first wiring 113A shorts out output lines of the second-stage buffer elements 112b in each driving circuit 111A. This makes it possible to average out delay time differences in the output lines of the buffer elements 112b of the driving circuits 111A.

[0065] The first wiring 113B shorts the output lines of the second-stage buffer elements 112b in each of the drive circuits 111B. Similarly, the first wiring 113C shorts the output lines of the second-stage buffer elements 112b in each of the drive circuits 111C.

[0066] The first wiring 113D shorts the output lines of the first-stage buffer elements 112a in each driving circuit 111A, thereby making it possible to average out delay time differences in the output lines of the buffer elements 112a of the driving circuits 111A.

[0067] The first wiring 113E shorts the output lines of the first-stage buffer elements 112a in each of the drive circuits 111B. Similarly, the first wiring 113F shorts the output lines of the first-stage buffer elements 112a in each of the drive circuits 111C. The impedances of the first wirings 113A-113C are configured to be smaller than the impedances of the first wirings 113D-113D. For example, the line widths of the first wirings 113A-113C may be larger than the line widths of the first wirings 113D-113D. Alternatively, each of the first wirings 113D-113F may be configured from a single wiring, and each of the first wirings 113A-113C may be configured from a plurality of parallel wirings.

[0068] The load driven by each driving circuit 111 is a large load, since it is the same number of gate loads and wiring loads as the number of pixels driven. Therefore, the buffer element 112 at the final stage of the driving circuit 111 is required to have a high driving capability. If the buffer element 112 at the final stage is directly driven by the driving pulse generated by the timing generating circuit 120, the load is too large and the voltage rise time and fall time are long, resulting in a large time lag in the driving pulse between columns. Therefore, the driving circuit 111 needs to gradually increase the driving capability from the first stage to the last stage of the buffer elements 112 connected in multiple stages. For example, the transistor size constituting the buffer element 112 is gradually increased from the first stage buffer element 112a to the last stage buffer element 112c.

[0069] The first wiring 113 shorts the outputs of the buffer elements 112 that drive signals of the same phase, and reduces the time lag between columns of the drive pulses. In other words, the first wiring 113 is a wiring that averages the delay. The time lag between columns occurs due to manufacturing variations in the transistors that constitute the drive circuit 111, differences in wiring resistance and capacitance due to layout differences, and differences in power supply drops. The first wiring 113 shorts the nodes in the drive circuit with low impedance, and the potentials of the nodes fluctuate so as to match. Therefore, even if there is a time lag between columns of the drive circuit 111, the first wiring 113 works to reduce the time lag. The first wiring 113 is wired in the horizontal direction of the drive circuit array 110, so that the time lag is reduced throughout the drive circuit array.

[0070] However, if there is a time lag between the columns, a potential difference occurs between the columns, and a through current flows through the first wiring 113. In particular, the larger the time lag, the larger the potential difference and the larger the through current. If a large current flows due to the through current, it may lead to wiring meltdown or transistor destruction. In addition, in the drive circuit 111, the time lag between the columns accumulates each time the number of stages of the buffer elements 112 is increased, so the time lag is smaller in the previous stage of the drive circuit 111. Therefore, when the columns are short-circuited by the first wiring 113 from the previous stage of the drive circuit 111, the time lag is small, so the through current flowing through the first wiring 113 can be suppressed to a small value.

[0071] The first wiring 113 may be not only one but also multiple wirings. Although even one first wiring 113 is effective in reducing the time lag, as described above, the time lag accumulates with each additional stage of buffer elements 112, so that the time lag can be reduced by short-circuiting between columns for each buffer element 112. In addition, since the driving capability is higher in the later stages of the driving circuit 111, the impedance of the first wiring 113 is lowered in the later stages. By lowering the impedance by thickening the first wiring 113 in the later stages through which a large through current flows, wiring meltdown and the like can be prevented.

[0072] The final-stage buffer element 112c connected to the electrode drive line 114 has high driving capability, and if it is shorted between columns, a large amount of through current will flow, which may cause wiring meltdown or transistor destruction. For this reason, the electrode drive lines 114 are not shorted between columns, but are made independent for each column.

[0073] Next, another example of the configuration of the drive circuit array 110 will be described.

[0074] Fig. 4B is a diagram showing another configuration example of the drive circuit array 110 according to the first embodiment. This figure differs from the drive circuit array 110 of Fig. 4A in that each of the multiple drive circuits 111A-111C includes M drive circuit groups divided into M (M is an integer equal to or greater than 2), and that each of the first wirings 113A-113C is provided for each of the M drive circuit groups, and shorts the output lines of the buffer elements belonging to the drive circuit group. The following mainly describes the differences.

[0075] Each of the multiple drive circuits 111A to 111C includes two divided drive circuit groups. In Fig. 4B, M=2. Specifically, the multiple drive circuits 111A are divided into a drive circuit group made up of drive circuits 111 corresponding to odd-numbered columns and a drive circuit group made up of drive circuits 111 corresponding to even-numbered columns. The multiple drive circuits 111B are also divided into a drive circuit group corresponding to odd-numbered columns and a drive circuit group corresponding to even-numbered columns. The same is true for the multiple drive circuits 111C.

[0076] The first wiring 113A in Fig. 4A corresponds to two first wirings 113Ao and 113Ae in Fig. 4B. The first wiring 113Ao shorts the output lines of the buffer elements 112b belonging to the drive circuit groups corresponding to the odd-numbered columns. The first wiring 113Ae connects the output lines of the buffer elements 112b belonging to the drive circuit groups corresponding to the even-numbered columns.

[0077] The first wirings 113B correspond to the first wirings 113Bo corresponding to the odd-numbered columns and the first wirings 113Ae corresponding to the even-numbered columns.

[0078] Similarly, the first wiring 113C corresponds to the first wiring 113Co and the first wiring 113Ce.

[0079] The first wiring 113D in Fig. 4A corresponds to two first wirings 113Do and 113De in Fig. 4B. The first wiring 113Do shorts the output lines of the buffer elements 112a belonging to the drive circuit groups corresponding to the odd-numbered columns. The first wiring 113De connects the output lines of the buffer elements 112a belonging to the drive circuit groups corresponding to the even-numbered columns.

[0080] The first wirings 113E correspond to the first wirings 113Eo corresponding to the odd-numbered columns and the first wirings 113Ee corresponding to the even-numbered columns.

[0081] Similarly, the first wiring 113F corresponds to the first wiring 113Fo and the first wiring 113Fe.

[0082] 4B shows an example in which the pixel column is divided into two equal parts. In this case, in a thinning operation mode in which an image is generated with half the number of pixels in the row direction, the load on the first wiring 113 of the drive circuit array 110 can be reduced.

[0083] The M division does not have to be equal, and M may be equal to or greater than 3. For example, when generating an image in which the number of pixels in the row direction is reduced to 1 / 4, all pixel columns may be divided into two at a ratio of 1:3, or all pixel columns may be divided into three at a ratio of 1:2:1.

[0084] [1.4 Operation of the solid-state imaging device 200] Next, the operation of the solid-state imaging device 200 during an exposure period will be described with reference to FIGS.

[0085] Fig. 5 is a flowchart showing the exposure operation in the embodiment 1. Also, Fig. 6 is a timing chart showing the drive pulses during the exposure operation in the embodiment 1.

[0086] First, a reset step ST00 is performed as an initial operation immediately before time t1. The driving pulse ΦODG applied to the reset electrode 310 is in a High state, and the photoelectric conversion unit 300 is in a reset state. In addition, the driving pulse ΦTG1 applied to the first readout electrode 330 and the driving pulse ΦTG2 applied to the second readout electrode 350 are in a Low state, and the photoelectric conversion unit 300 is electrically disconnected from the first charge accumulation unit 340 and the second charge accumulation unit 360. In this state, the signal charge generated in the photoelectric conversion unit 300 is discharged to the charge discharge unit 320 via the reset electrode 310, and is not stored in the photoelectric conversion unit 300.

[0087] Next, at time t1, the process proceeds to light emission accumulation start step ST01. The reset electrode 310 goes to a low state, and charge discharge from the photoelectric conversion unit 300 to the charge discharge unit 320 is stopped. The photoelectric conversion unit 300 goes into a state in which it accumulates the generated signal charge. At the same time, a light emission trigger signal is applied from the timing generation circuit 120 to the light source driver 150, and infrared pulsed light is irradiated from the light source unit 160. After irradiation of the infrared pulsed light, reflected light is incident on the pixel array 100 with a time difference according to the distance to the object 190.

[0088] Next, at time t2, the process proceeds to a first read step ST03. The first read electrode 330 goes to a High state, and the photoelectric conversion unit 300 and the first charge accumulation unit 340 are electrically connected. The signal charge accumulated in the photoelectric conversion unit 300 is transferred to the first charge accumulation unit 340.

[0089] Next, at time t3, the first readout electrode 330 goes low, the photoelectric conversion unit 300 and the first charge accumulation unit 340 are electrically disconnected, and the readout of the signal charge S0 is completed. At the same time, a trigger signal is applied from the timing generation circuit 120 to the light source driver 150, and the irradiation of the infrared pulsed light from the light source unit 160 is stopped. The signal charge S0 has an amount of charge proportional to the time (Tp-Tf) obtained by subtracting the arrival time Tf from the irradiation of the infrared pulsed light until the reflected light reaches the pixel array 100 from the irradiation time Tp of the infrared pulsed light.

[0090] Next, at time t4, the process proceeds to a second read step ST03. The second read electrode 350 goes to a High state, and the photoelectric conversion unit 300 and the second charge accumulation unit 360 are electrically connected. The signal charge accumulated in the photoelectric conversion unit 300 is transferred to the second charge accumulation unit 360.

[0091] Next, at time t5, the second readout electrode 350 goes low, electrically disconnecting the photoelectric conversion unit 300 and the second charge accumulation unit 360, completing the readout of the signal charge S1. The signal charge S1 has an amount of charge proportional to the arrival time Tf.

[0092] Next, at time t6, the process proceeds to a reset step ST04. The reset electrode 310 goes to a high state, the photoelectric conversion unit 300 and the charge discharging unit 320 are electrically connected, the photoelectric conversion unit 300 goes to a reset state, and no charge is accumulated in the photoelectric conversion unit 300.

[0093] When exposure is repeated, the process moves again to the light emission accumulation start step ST01, and the operations from the light emission accumulation start step ST01 to the reset step ST04 are repeated. The operations from the light emission accumulation step ST01 to the reset step ST04 are performed multiple times within one frame period, and signal charges S0 and S1 according to the total amount of exposure multiple times are accumulated in the first charge accumulation section 340 and the second charge accumulation section 360, respectively. When the repeated exposure ends, the exposure is completed.

[0094] After the exposure period ends, the first selection transistor 370 is set to a high state to start reading out the signal charge S0. The signal charge S0 is transferred to the floating diffusion layer 390 and converted into a voltage by the source follower 410. The signal charge S0 converted into a voltage is converted into a digital signal by the column ADC 131 via the vertical signal line 102. When the reading out of the signal charge S0 is completed, the reset transistor 400 is set to a high state to reset the floating diffusion layer 390 to its initial state. The pixel array 100 is scanned sequentially in the vertical direction, and the signal charges S0 of all the pixels 101 are converted into digital signals.

[0095] Next, after returning the first selection transistor 370 to a low state, the second selection transistor 380 is set to a high state to start reading out the signal charge S1. The signal charge S1 is transferred to the floating diffusion layer 390 in the same manner as the signal charge S0, and is converted into a voltage by the source follower 410. The signal charge S1 converted into a voltage is converted into a digital signal by the column ADC 131 via the vertical signal line 102. When the reading out of the signal charge S1 is completed, the reset transistor 400 is set to a high state to reset the floating diffusion layer 390 to its initial state. The pixel array 100 is scanned sequentially in the vertical direction, and the signal charges S1 of all the pixels 101 are converted into digital signals.

[0096] Here, the distance Z from the imaging device 1000 to the object 190 can be calculated from the arrival time Tf according to the following formula (1), where the speed of light is c.

[0097]

number

[0098] The signal charge S0 is proportional to Tp-Tf, which is the irradiation time Tp minus the arrival time Tf, and the signal charge S1 is proportional to the arrival time Tf, so the signal charge ratio S1 / S0 is equal to the ratio Tf / (Tp-Tf) of the arrival time to the irradiation time. The arrival time Tf is expressed by the following formulas (2a) and (2b) using the irradiation time Tp and the signal charges S1 and S0.

[0099]

number

[0100] Therefore, the distance Z to the object 190 is expressed by the following formula (3) based on the signal charges S0 and S1 and the irradiation time Tp.

[0101]

number

[0102] In the absence of the first wiring 113, a time lag occurs between the columns. When there is a time lag Δt, the signal charge S1 is proportional to Tf-Δt obtained by subtracting the time lag Δt from the arrival time Tf, and the signal charge S0 is proportional to Tp-Tf+Δt obtained by adding the time lag Δt to Tp-Tf obtained by subtracting the arrival time Tf from the irradiation time Tf, so the signal charge ratio S1 / S0 is given by the following formulas (4a) and (4b).

[0103]

number

[0104] A time lag Δt is added to the actual arrival time Tf, and a measured distance difference ΔZ is generated in the distance Z to the object 190 as shown in the following equation (5).

[0105]

number

[0106] For example, if the speed of light is c=299,792,458 m / s and the time lag is Δt=100 ps, ​​the measured distance difference ΔZ will be about 15 mm. By using the first wiring 113, the time lag Δt between columns can be reduced, and the measured distance difference ΔZ can be reduced. As a result, high distance measurement accuracy can be achieved without the need for calibration or an increase in circuit size.

[0107] [1.5 Modifications of the solid-state imaging device 200] Next, a modification of the solid-state imaging device 200 will be described.

[0108] Fig. 4C is a diagram showing a modified example of the pixel array and the drive circuit array according to the first embodiment. The drive circuit array 110 in Fig. 4C is different from Fig. 4A in that it has a reset control line 14A for each pixel row instead of a reset control line 114A for each pixel column, a drive circuit 11A for each pixel row instead of a drive circuit 111A for each pixel column, a first wiring 13A instead of the first wiring 113A, and a first wiring 13D instead of the first wiring 113D. Below, the following description will focus on the differences, avoiding duplication of explanations of the same points.

[0109] The reset control line 14A is provided for each pixel row, and transmits a reset control signal having a driving pulse ΦODG output from the vertical scanning circuit 140 via the driving circuit 11A to the pixels 101 belonging to the corresponding pixel row.

[0110] The driving circuit 11A is provided for each pixel row and is provided in the final stage in the vertical scanning circuit 140. Each driving circuit 11A outputs a reset control signal to the reset electrode 310 via a reset control line 14A for each pixel 101 belonging to the corresponding pixel row. The driving circuit 11A may be provided between the vertical scanning circuit 140 and the pixel array 100.

[0111] Each driving circuit 11A includes at least two stages of buffer elements 11. The driving circuit 11A in the figure includes three stages of buffer elements 11a to 11c. The driving capabilities of the buffer elements 11a to 11c are configured to increase in the order of the buffer elements 11a, 11b, and 11c. When there is no particular distinction between the buffer elements 11a to 11c, they are simply referred to as buffer elements 11. Here, the buffer elements 11 may be inverter circuits in which the polarity is inverted, or may be buffer circuits in which the polarity is not inverted.

[0112] The first wiring 13A is a type of first wiring, and is at least one wiring that shorts signal lines that transmit signals of the same phase in two or more drive circuits 11 together.

[0113] The first wiring 13D is a type of first wiring, and is at least one wiring that shorts signal lines that transmit signals of the same phase in two or more drive circuits 11. When there is no need to particularly distinguish between the first wiring 13A and the first wiring 13D, they are simply referred to as the first wiring 13.

[0114] Ignoring the delay time difference, any drive circuit 11A drives a reset control signal with the same phase as the drive circuits 11A in the other columns.

[0115] The first wiring 13A shorts out wirings having signals of the same phase in two or more driving circuits 11A. In the figure, the first wiring 13A shorts out output lines of the second-stage buffer elements 11b in each driving circuit 11A. This makes it possible to average out delay time differences in the output lines of the buffer elements 11b of the driving circuits 11A.

[0116] The first wiring 13D shorts the output lines of the first-stage buffer elements 11a in each drive circuit 11A, thereby making it possible to average out delay time differences in the output lines of the buffer elements 11a of the drive circuits 11A.

[0117] The impedance of the first wiring 13A is configured to be smaller than the impedance of the first wiring 13D. For example, the line width of the first wiring 13A may be larger than that of the first wiring 13D. Alternatively, the first wiring 13D may be configured as a single wiring, and the first wiring 113A may be configured as a plurality of parallel wirings.

[0118] The load driven by each driving circuit 11A is large because the number of gate loads and wiring loads is the same as the number of pixels to be driven. Therefore, high driving capability is required for the final stage buffer element 11c of the driving circuit 11A. If the final stage buffer element 11c is directly driven by the driving pulse generated by the timing generating circuit 120, the load is too large and the voltage rise time and fall time are long, resulting in a large time lag in the driving pulse between columns. Therefore, the driving circuit 11A needs to gradually increase the driving capability from the first stage to the last stage of the buffer elements 11 connected in multiple stages. For example, the transistor size constituting the buffer element 11 is gradually increased from the first stage buffer element 11a to the last stage buffer element 11c.

[0119] The first wiring 13 shorts the outputs of the buffer elements 11 that drive signals of the same phase, and reduces the time lag between columns of driving pulses. In other words, the first wiring 13 is a wiring that averages delays. In addition, the time lag between columns occurs due to manufacturing variations in the transistors that constitute the driving circuit 11, differences in wiring resistance and capacitance due to layout differences, and differences in power supply drops. The first wiring 13 shorts the nodes in the driving circuit with low impedance, and the potentials of the nodes fluctuate so as to match. Therefore, even if there is a time lag between columns of the driving circuits 111, the first wiring 13A works to reduce the time lag. In addition, the first wiring 13 is wired in the vertical direction of the driving circuit array 110, so that the time lag is reduced throughout the driving circuit array 110.

[0120] As described above, the solid-state imaging device 200 of this embodiment comprises a plurality of pixels 101 arranged in a matrix, control lines 114 provided for each pixel row or each pixel column and connected to the pixels 101 belonging to the corresponding pixel column, drive circuits 111 provided for each of the control signals and having at least two stages of buffer elements 112a to 112c connected in series and outputting control signals to the control lines 114, and a first wiring 113 shorting out output lines of corresponding buffer elements 112 in any of the stages in the at least two drive circuits 111.

[0121] This makes it possible to reduce the delay difference, which is the time lag of the control signal for each control line 114, due to the short circuit of the first wiring 113. Therefore, it is possible to reduce the delay difference of the control signal for each column without the need for calibration, and to achieve high distance measurement accuracy.

[0122] Here, the first wiring 113 is a wiring that averages the delay of the control lines 114 for each row or column.

[0123] Here, the multiple pixels 101 include optical black pixels and normal pixels other than the optical black pixels, and the wiring length of the first wiring may be longer than one of the four sides of the effective area formed by the normal pixels that is parallel to the first wiring.

[0124] This allows the first wiring to be connectable to an output line of the buffer element 112 corresponding to any one of all pixel columns.

[0125] Here, the multiple drive circuits 111 include M drive circuit groups divided into M (M is an integer equal to or greater than 2), and the first wiring 113 is provided for each of the M drive circuit groups, and may short-circuit the output lines of the buffer elements belonging to the drive circuit group.

[0126] This is suitable for generating an image having fewer than the total number of pixels by using a pixel column corresponding to a group of drive circuits, for example.

[0127] Here, one of the M drive circuit groups may be configured with a drive circuit 111 that is driven in a pixel thinning operation mode.

[0128] According to this, for example, when generating a low-resolution image, in a thinning-out operation mode in which 1 / m (m is an integer of 2 or more) of all pixel columns are used and the other pixel columns are not used, only the necessary driving circuits 111 can be shorted with the first wiring. This suppresses the parasitic capacitance of the first wiring and enables the thinning-out operation mode to be executed at higher speed.

[0129] Here, the first wiring may be provided for each of two or more stages up to the total number of stages of the at least two stages of the buffer elements 112.

[0130] Here, the impedance of the first wiring 113 may be smaller than the impedance of the first wiring corresponding to the buffer element 112 on the upstream side.

[0131] This makes it possible to further reduce the occurrence of the delay time difference.

[0132] Here, the wiring width of the first wiring 113 may be larger than the wiring width of the corresponding first wiring 113 on the previous stage side.

[0133] This makes it possible to further reduce the occurrence of the delay time difference.

[0134] Here, the driving capability of the buffer element 112 may be higher than the driving capability of the buffer element 112 in the preceding stage.

[0135] This makes it possible to further reduce the occurrence of the delay time difference.

[0136] Here, the pixel 101 has a photoelectric conversion unit 300 that converts light into electric charges, and a readout electrode 330 / 350 for reading out the electric charges from the photoelectric conversion unit 300, and the control line 114 may be connected to the readout electrode 330 / 350.

[0137] Here, the pixel 101 has a reset electrode 310 for resetting the charge in the pixel, and a control line may be connected to the reset electrode 310 .

[0138] Here, the pixel 101 has a photoelectric conversion unit 300 that converts light into an electric charge, a first readout electrode 330 for reading out the electric charge from the photoelectric conversion unit 300, and a reset electrode 310 for resetting the electric charge in the pixel, and the control line 114 has a first readout control line 114B connected to the first readout electrode 330 and a reset control line 114A connected to the reset electrode 310 for each pixel column, and the solid-state imaging device 200 may be configured to have a drive circuit 111B connected to the first readout control line 114B and a drive circuit 111A connected to the reset control line 114A for each pixel column.

[0139] Here, the pixel 101 further has a second readout electrode 350 for reading out charges from the photoelectric conversion unit 300, the control line 114 further has a second readout control line 114C connected to the second readout electrode 350 for each pixel column, and the solid-state imaging device 200 may further have a drive circuit 111C connected to the second readout control line 114C for each pixel column.

[0140] Moreover, the imaging apparatus according to the first embodiment includes the above-described solid-state imaging device 200, and a signal processing circuit 180 that generates a distance image or a luminance image based on a signal received by the solid-state imaging device 200.

[0141] The first wiring in which the output lines of corresponding buffer elements 112 in any stage are short-circuited is not limited to one, but may include two or more parallel-connected first wirings 113. The two or more parallel-connected first wirings 113 may be formed in one wiring layer, or may be formed in multiple wiring layers.

[0142] (Embodiment 2) [2. Configuration of the driving circuit array 110] Fig. 7 shows a configuration of a drive circuit array 110 according to embodiment 2. As shown in Fig. 7, drive circuit array 110 according to embodiment 2 differs from drive circuit array 110 in Fig. 4A in that wiring interchange sections 510a-510c are added. The following description will focus on these differences. When there is no need to distinguish between wiring interchange sections 510a-510c, they will simply be referred to as wiring interchange sections 510.

[0143] Each of the wiring switching units 510a to 510c switches the output wiring of the buffer element 112 in the driving circuit 111 with the buffer element 112 in the same stage but not in the same column, thereby switching the wiring with the wiring of the driving circuit 111 in a different column. In other words, each of the wiring switching units 510a to 510c crosses the wiring between the driving circuits 111 so as to essentially switch the buffer element 112 in the driving circuit 111 with the corresponding buffer element 112 in the same stage in the other driving circuit 111.

[0144] 7 shows an example in which the wiring interchange sections 510a-510c are provided in three locations, but the number of locations may be two, four or more. Also, although an example in which the wiring is interchanged between adjacent driving circuits 111 corresponding to the same pixel column is shown, the wiring may be interchanged with driving circuits 111 that are not adjacent to each other.

[0145] The exposure operation in the second embodiment is performed in accordance with the steps of FIG.

[0146] As described above, the solid-state imaging device according to the present embodiment averages the delay times of the drive signals that differ for each column by switching the paths through which the drive signals pass, thereby reducing the difference in delay times between columns, in response to differences between columns of the drive circuits 111 due to layout differences and manufacturing variations. This is particularly effective in reducing the difference in delay times between columns when the drive signals have different phases and the columns cannot be short-circuited by the first wiring 113. As a result, the delay difference between drive signals with different phases can be reduced, and distance measurement accuracy can be improved.

[0147] As described above, the solid-state imaging device 200 according to the second embodiment may include a wiring switching section 510 that crosses wiring between driving circuits 111 so as to essentially switch a buffer element 112 in a driving circuit 111 with a corresponding buffer element 112 in the same stage in another driving circuit 111.

[0148] Here, two or more wiring interchange sections 510 may be provided, and the wiring interchange sections 510 may be inserted into the input lines or output lines of at least two of the buffer elements 112 of the multiple driver circuits 111.

[0149] (Embodiment 3) [3. Configuration of the driving circuit array 110] Fig. 8 shows a configuration of a drive circuit array 110 according to embodiment 3. As shown in Fig. 8, the wiring interchange section 510 of embodiment 3 differs from that of Fig. 7 in that it includes wiring interchange sections 510d and 510e instead of wiring interchange sections 510a to 510c. The following description will focus on the differences. When there is no need to distinguish between wiring interchange sections 510d and 510e, they will simply be referred to as wiring interchange section 510.

[0150] The wiring switching unit 510d includes three selection circuits 530 for each pixel column. Each selection circuit 530 has one input terminal and three output terminals, selects one of the output terminals, and connects the input terminal to the selected output terminal. The three selection circuits 530 corresponding to one pixel column switch the input wiring of the buffer elements 112a of the corresponding three drive circuits 111.

[0151] The selection circuit 530 to which the drive pulse ΦODG is input selects one of the input lines of the buffer elements 112a of the three drive circuits 111 corresponding to the pixel column, and transmits the drive pulse ΦODG to the selected input line.

[0152] The selection circuit 530 to which the drive pulse ΦTG1 is input selects one of the input lines of the buffer elements 112a of the three drive circuits 111 corresponding to the pixel column, and transmits the drive pulse ΦTG1 to the selected input line.

[0153] Similarly, the selection circuit 530 to which the drive pulse ΦTG2 is input selects one of the input lines of the buffer elements 112a of the three drive circuits 111 corresponding to the pixel column, and transmits the drive pulse ΦTG3 to the selected input line.

[0154] The three selection circuits 530 corresponding to one pixel column exclusively select the destination buffer element 112a.

[0155] The wiring switching unit 510e includes three selection circuits 531 for each pixel column. Each selection circuit 531 has three input terminals and one output terminal, selects one of the input terminals, and connects the selected input terminal to the output terminal. The three selection circuits 531 corresponding to one pixel column switch the output wiring of the buffer elements 112c of the corresponding three drive circuits 111. In the configuration example of FIG. 8, each selection circuit 531 performs a selection operation to restore the switching of wiring by the corresponding selection circuit 530.

[0156] Thereby, the three selection circuits 530 and 531 corresponding to the pixel columns function to replace the drive circuit 111 with the drive circuit 111 of a different column in response to the selection switching signal 540 .

[0157] For example, when the selection switching signal 540 is "0", the driving circuit 111 is connected to the control line 114 of the same column. In this case, the reset control line 114A is connected to the driving circuit 111A, the first readout control line 114B is connected to the driving circuit 111B, and the second readout control line 114C is connected to the driving circuit 111C.

[0158] When the selection switching signal 540 is "1", the driving circuit 111 is connected to a control line that is not in the same column. In this case, the reset control line 114A is connected to the driving circuit 111B, the first readout control line 114B is connected to the driving circuit 111C, and the second readout control line 114C is connected to the driving circuit 111A.

[0159] When the selection switching signal 540 is "2", the drive circuit 111 is connected to another control line not in the same column. In this case, the reset control line 114A is connected to the drive circuit 111C, the first readout control line 114B is connected to the drive circuit 111A, and the second readout control line 114C is connected to the drive circuit 111B.

[0160] Although the selection switching signal 540 has been shown as having three values ​​by way of example, it may have two values ​​or four or more values.

[0161] Next, the exposure operation of the third embodiment will be described with reference to the flowchart of FIG. 9. The flowchart of FIG. 9 is the same as the flowchart of FIG. 5 except that a driving circuit switching step ST05 is added, and the other steps are the same as those of the first embodiment. Normally, when measuring the distance to the object 190, multiple exposures are performed within one frame. In the third embodiment, when exposure is repeated after the reset step ST04, the process proceeds to the driving circuit switching step ST05. In the driving circuit switching step ST05, the selection switching signal 540 is switched to switch the buffer element 112 through which the driving signal passes. When the driving circuit switching step ST05 is completed, the process proceeds again to the light emission accumulation start step ST01. The driving circuit 111 through which the driving signal passes is switched every time exposure is repeated.

[0162] Here, it is assumed that the electrode driving lines 114 include three types of control lines: a reset control line 114A, a first readout control line 114B, and a second readout control line 114C.

[0163] It is assumed that the wiring switching unit 510 switches the three types of control lines for each exposure. It is assumed that a total of (l+m+n) exposures are performed within one frame, and the drive signal applied to the reset control line 114A passes through the drive circuit 111A for l exposures, through the drive circuit 111B for m exposures, and through the drive circuit 111C for n exposures. It is assumed that the drive signal applied to the first readout control line 114B passes through the drive circuit 111B for l exposures, through the drive circuit 111C for m exposures, and through the drive circuit 111A for n exposures. It is assumed that the drive signal applied to the second readout control line 114C passes through the drive circuit 111C for l exposures, through the drive circuit 111A for m exposures, and through the drive circuit 111B for n exposures. If the time shift of driving circuit 111A is Δta, the time shift of driving circuit 111B is Δtb, and the time shift of driving circuit 111C is Δtc, the measured distance difference ΔZ1 of the pixels driven by the reset control line 114A, the measured distance difference ΔZ2 of the pixels driven by the first readout control line 114B, and the measured distance difference ΔZ3 of the pixels driven by the second readout control line 114C are expressed by the following equations (6) to (8).

[0164]

number

[0165] If the number of exposures in which the drive signal passes through drive circuit 111A, the number of exposures in which the drive signal passes through drive circuit 111B, and the number of exposures in which the drive signal passes through drive circuit 111C are the same for the reset control line 114A, the first readout control line 114B, and the second readout control line 114C, then l = m = n, and the measured distance differences ΔZ1, ΔZ2, and ΔZ3 are expressed by the following equation (9).

[0166]

number

[0167] Therefore, the measured distance difference ΔZ1 of the pixel 101 driven by the reset control line 114A, the measured distance difference ΔZ2 of the pixel 101 driven by the first readout control line 114B, and the measured distance difference ΔZ3 of the pixel 101 driven by the second readout control line 114C are all proportional to (Δta+Δtb+Δtc) / 3, which is the average of the time lag Δta of the drive circuit 111A, the time lag Δtb of the drive circuit 111B, and the time lag Δtc of the drive circuit 111C. As a result, the time lags of the reset control line 114A, the first readout control line 114B, and the second readout control line 114C are offset, achieving high distance measurement accuracy.

[0168] 8 shows an example in which wiring interchange units 510d and 510e are inserted on the input side and output side of the driving circuit array 110, and all of the driving circuits 111 are replaced with all of the other driving circuits 111. However, the present invention is not limited to this, and a configuration may be adopted in which some of the buffer elements 112 and some of the wiring of the driving circuits 111 are interchanged. For example, the wiring interchange unit 510d in FIG. 8 may be inserted into the output line of the buffer element 112b instead of the input line of the buffer element 112a.

[0169] 8, the wiring switching unit 510d may be replaced by a circuit identical to that of the wiring switching unit 510e, and the wiring switching unit 510e may be replaced by a circuit identical to that of the wiring switching unit 510d.

[0170] Although an example in which three electrode drive lines 114 for each column are interchanged is shown in FIG. 7 and FIG. 8, the same effect can be obtained even when two or four or more electrode drive lines 114 are interchanged.

[0171] As described above, in the solid-state imaging device 200 according to the third embodiment, the wiring switching section 510 may include the selection circuit 530 or 531 that selects the driving circuit to be switched in response to a selection switching signal.

[0172] (summary) As described above with reference to the drawings, the solid-state imaging device 200 according to the embodiment includes a photoelectric conversion unit 300 that converts received light into electric charge, readout electrodes (first readout electrode 330, second readout electrode 350) that control the reading out of electric charge generated in the photoelectric conversion unit 300, a reset electrode 310 that controls the discharge of electric charge generated in the photoelectric conversion unit 300, a pixel array 100 in which the photoelectric conversion unit 300, the readout electrodes, and the reset electrodes 310 are arranged in a plurality of arrays, readout control lines (first readout control line 114B, second readout control line 114C) that drive the readout electrodes, a reset control line 114A that drives the reset electrode 310, a drive circuit 111 in which at least two or more stages of buffer elements 112 are connected in multiple stages and which applies drive pulses to the readout control line and the reset control line 114A, and a first wiring 113 in which the drive circuit 111 is arranged in a column and which shorts out the outputs of the buffer elements 112 in at least two or more different columns.

[0173] In this configuration, a driving pulse is applied from a driving circuit 111 to electrodes of a plurality of pixels 101 arranged in a matrix form via a read control line and a reset control line 114A, and the transfer of charges accumulated in the photoelectric conversion unit 300 is controlled. The driving circuit 111 has buffer elements 112 connected in multiple stages, and the outputs of the buffer elements 112 between columns are electrically connected with low impedance by a first wiring 113. As a result, the potentials between the columns fluctuate to match, thereby reducing delay differences.

[0174] The first wiring 113 has a wiring length longer than one of the four sides of the effective area of ​​the pixel 101 that is parallel to the first wiring, and the impedance of the first wiring 113 decreases toward the rear. Furthermore, the driving capability of the buffer elements 112 increases toward the rear, and the electrode driving lines 114 are independent for each column.

[0175] By shorting two or more stages of the buffer elements with the first wiring 113, even if there is a delay difference between the columns and a potential difference occurs, the delay difference is small so that the period during which the potential difference occurs is short, and the driving capability of the buffer elements 112 in the front stage is lower so that the through current that flows is small. Therefore, the risk of wiring meltdown and destruction of the buffer elements 112 can be reduced. In addition, the risk of wiring meltdown can be reduced by lowering the impedance of the shorted first wiring 113 in the rear stage of the buffer elements 112. As a result, the first wiring 113 reduces the delay difference between columns of the drive signals caused by the difference in characteristics of the drive buffers and the difference in parasitic components caused by the layout without the need for calibration.

[0176] The drive circuit array 110 also has one or more wiring switching units 510 that switch the wiring of the drive circuit 111 with the wiring of the drive circuit 111 in a different column, and the wiring switching unit 510 has selection circuits 530, 531 that can select the column for which the wiring is to be switched in response to a selection switching signal.

[0177] By connecting two or more stages of buffer elements 112 that are not in the same column in multiple stages, the delay difference can be reduced even when the phases of the drive signals are different and the buffer elements 112 cannot be shorted between columns. By switching the paths through which the drive signals pass, the delay times between different drive signals are averaged to deal with delay differences between columns due to layout differences and manufacturing variations in the drive circuits 111. The selection circuit 530 utilizes multiple exposure of the TOF to change the paths of the drive signals during the exposure period to average the delay times, thereby reducing delay differences between columns or between drive signals with different phases. [Industrial Applicability]

[0178] As described above, the imaging device according to the present disclosure is useful as an imaging device that can reduce the delay difference between each row of drive signals without the need for calibration, while suppressing an increase in circuit size, and can achieve high ranging accuracy. [Explanation of symbols]

[0179] 100 pixel array 101 pixels 102 Vertical signal line 110 Drive circuit array 111 Drive circuit 112, 112a, 112b, 112c buffer elements 113, 113A~113F 1st wiring 114 Electrode drive line (control line) 114A Reset control line 114B First read control line 114C Second read control line 120 Timing Generator Circuit 130 AD conversion section 131 column ADC 132 Memory Array 133 Output circuit 140 Vertical scanning circuit 150 Light Source Driver 160 Light source section 170 Lens 180 Signal Processing Circuit 190 Objects 200 Solid-state imaging device 300 Photoelectric conversion unit 310 Reset electrode 320 Charge discharge section 330 First readout electrode 340 First charge storage section 350 Second readout electrode 360 Second charge storage section 370 First selection transistor 380 Second selection transistor 390 Floating Diffusion Layer 400 Reset Transistor 410 Source Follower 510, 510a~510e Wiring exchange section 530 Selection Circuit 540 Selection Switching Signal 1000 Imaging device

Claims

1. A plurality of pixels arranged in a matrix; a control line provided for each pixel row or each pixel column and connected to the pixels belonging to the corresponding pixel row or pixel column; a driver circuit provided for each of the control lines, the driver circuit having at least two stages of buffer elements connected in series and outputting a control signal to the control line; and a first wiring that shorts output lines of the buffer elements included in the corresponding but different driving circuits in any of the stages in at least two of the driving circuits. Solid-state imaging device.

2. The first wiring is a wiring that averages the delay for each row or column of the control lines.

2. The solid-state imaging device according to claim 1.

3. the plurality of pixels include optical black pixels and normal pixels other than the optical black pixels, The length of the first wiring is longer than one of the four sides of an effective area formed by the normal pixels that is parallel to the first wiring.

3. The solid-state imaging device according to claim 1.

4. The plurality of drive circuits include M drive circuit groups divided into M (M is an integer equal to or greater than 2), The first wiring is provided for each of the M driving circuit groups, and short-circuits output lines of the buffer elements included in the different driving circuits belonging to the driving circuit group.

4. The solid-state imaging device according to claim 1.

5. One of the M driving circuit groups is configured with a driving circuit that is driven in a pixel thinning operation mode. The solid-state imaging device according to claim 4 .

6. The first wiring is provided in each of two or more stages of the at least two stages of the buffer elements.

6. The solid-state imaging device according to claim 1.

7. The impedance of the first wiring is smaller than the impedance of the first wiring corresponding to the buffer element on the upstream side.

7. The solid-state imaging device according to claim 6.

8. The width of the first wiring is larger than the width of the corresponding first wiring on the previous stage side.

7. The solid-state imaging device according to claim 6.

9. The driving capability of the buffer element is higher than that of the preceding buffer element.

9. The solid-state imaging device according to claim 1.

10. The pixel includes a photoelectric conversion unit that converts light into an electric charge, and a readout electrode that reads out the electric charge from the photoelectric conversion unit, The control line is connected to the read electrode.

10. The solid-state imaging device according to claim 1.

11. The pixel has a reset electrode for resetting a charge in the pixel; The control line is connected to the reset electrode. The solid-state imaging device according to any one of claims 1 to 10.

12. The pixel includes a photoelectric conversion unit that converts light into an electric charge, a first readout electrode for reading out the electric charge from the photoelectric conversion unit, and a reset electrode for resetting the electric charge in the pixel; the control lines include a first readout control line connected to the first readout electrode and a reset control line connected to the reset electrode for each pixel column; The solid-state imaging device includes the drive circuit connected to the first readout control line and the drive circuit connected to the reset control line for each pixel column.

10. The solid-state imaging device according to claim 1.

13. The pixel further includes a second readout electrode for reading out charges from the photoelectric conversion unit, the control lines further include a second readout control line connected to the second readout electrode for each pixel column; The solid-state imaging device further includes a drive circuit connected to the second readout control line for each pixel column. The solid-state imaging device according to claim 12.

14. a wiring exchange unit that crosses wiring between the driving circuits so as to substantially exchange the buffer element in the driving circuit with a corresponding buffer element in the same stage in another driving circuit; The solid-state imaging device according to any one of claims 1 to 13.

15. The wiring switching unit includes a selection circuit that selects a drive circuit to be switched in response to a selection switching signal. The solid-state imaging device according to claim 14.

16. A solid-state imaging device according to any one of claims 1 to 15, a signal processing circuit for generating a distance image or a luminance image based on a signal received by the solid-state imaging device; Imaging device.

Images