Interface module, computing device, and communication method

Abstract

To easily address a new communication protocol.SOLUTION: An interface module is connected to a storage controller, and relays communication with a host and the storage controller. The host and the storage controller use different communication protocols, and comprises a plurality of calculation cores and a memory. At least one of the plurality of calculation cores is an IO core which communicates with the host. Each of the IO cores has a virtual queue in the memory. The IO core executes reception processing which converts communication data including a command to the storage controller output by the host into a storage interface command to store it in the virtual queue. The IO core executes transmission processing which takes out the storage interface command from the virtual queue and converts it into communication data to transmit it to the host. In the same session, the same IO core executes the reception processing and the transmission processing.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an interface module, a computing device, and a communication method. [Background technology]

[0002] New communication protocols are being developed every day based on new technologies. Patent Document 1 discloses an interface module including a serial signal transmitting / receiving unit connected to an external transmission line and an interface processing unit connected to the transmitting / receiving unit, the interface processing unit including a serial / parallel conversion unit that converts a serial signal received from the transmitting / receiving unit into a parallel signal and converts a parallel signal to be transmitted to the external transmission line into a serial signal and outputs the serial / parallel conversion unit, a coding / decoding unit connected to the serial / parallel conversion unit, a protocol processing unit connected to the coding / decoding unit and selectively performs at least two types of protocol processing, and a communication mode switching means that switches a basic clock frequency supplied to the serial / parallel conversion unit in conjunction with switching of the protocol processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-339323 A Summary of the Invention [Problem to be solved by the invention]

[0004] The invention described in Patent Document 1 has room for improvement in terms of compatibility with new communication protocols. [Means for solving the problem]

[0005] An interface module according to a first aspect of the present invention is an interface module connected to a storage controller and relaying communication between a host and the storage controller, wherein the host and the storage controller use different communication protocols, the interface module has a plurality of computing cores and a memory, at least one of the plurality of computing cores is an IO core that communicates with the host, each of the IO cores has a virtual queue in the memory, the IO core performs a receiving process of converting communication data including instructions to the storage controller output by the host into a storage interface command and storing it in the virtual queue, the IO core performs a transmitting process of extracting the storage interface command from the virtual queue, converting it into communication data and transmitting it to the host, and in the same session, the receiving process and the transmitting process are performed by the same IO core. A computing device according to a second aspect of the present invention is a computing device comprising an interface module capable of communicating with a host, and a storage controller that communicates with the host via the interface module, wherein the host and the storage controller use different communication protocols, the computing device comprises a plurality of computing cores and a memory, at least one of the plurality of computing cores is an IO core that communicates with the host, each of the IO cores has a virtual queue in the memory, the IO core performs a receiving process to convert communication data including instructions to the storage controller into a storage interface command and store it in the virtual queue, the IO core performs a transmitting process to retrieve the storage interface command from the virtual queue, convert it into communication data and send it to the host, and in the same session, the receiving process and the transmitting process are performed by the same IO core. A communication method according to a third aspect of the present invention is a communication method executed by an interface module that is locally connected to a storage controller, relays communication between a host and the storage controller, and has a plurality of computing cores and a memory, wherein the host and the storage controller use different communication protocols, at least one of the plurality of computing cores is an IO core that communicates with the host, and each of the IO cores has a virtual queue in the memory, and the IO core executes a receive process of converting communication data output by the host, including a command to the storage controller, into a storage interface command and storing the command in the virtual queue, and the IO core executes a transmit process of extracting the storage interface command from the virtual queue, converting it into communication data, and transmitting the command to the host; Including, In the same session, the receiving process and the sending process are executed by the same IO core. 。 Effect of the Invention

[0006] According to the present invention, new communication protocols can be easily accommodated. [Brief description of the drawings]

[0007] [Figure 1] Calculation device configuration diagram [Diagram 2] A diagram showing an example of a session management table, a CPU setting table, and a protocol setting table. [Diagram 3] Figure showing an example of a connection management table, a task management table, and a CPU management table [Figure 4] Figure showing an example of a protocol setting table and a CPU setting table [Diagram 5] A diagram showing the process performed by a Smart NIC [Figure 6] A diagram showing an example of CPU core allocation for communication ports [Figure 7] Overview of the processing of each core of a smart NIC [Figure 8]A diagram explaining the cue operation dedicated mode and the cue operation combined mode [Figure 9] Diagram showing the relationship between the session management table, connection management table, and task management table [Figure 10] Diagram showing the relationship between the session management table, connection management table, and CPU management table [Figure 11] Diagram showing the relationship between the task management table and the CPU management table [Figure 12] Schematic diagram showing data processing in a computing device [Figure 13] Flowchart showing reception processing by the CPU [Figure 14] Flowchart showing queue operation processing by the CPU [Figure 15] Flowchart showing transmission processing by the CPU [Figure 16] A time chart showing the processing of the arithmetic unit [Figure 17] A time chart showing the processing of the arithmetic unit [Figure 18] A diagram showing an example of a setting screen generated by the CHB setting program. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] --First embodiment-- A first embodiment of a smart network interface card (NIC), which is an interface module according to the present invention, will be described below with reference to FIGS.

[0009] Fig. 1 is a configuration diagram of a computing device 1 including a smart NIC 3. The computing device 1 includes a storage controller 2, a smart NIC 3, and an input / output device 4. The computing device 1 can include multiple smart NICs 3, and includes three smart NICs 3 in this embodiment. Since the three smart NICs 3 have the same configuration, Fig. 1 shows only one smart NIC 3.

[0010] The storage controller 2 includes an SSD 21, which is a nonvolatile storage device, a controller CPU 22, and a controller DRAM 23, which is a memory. The SSD 21 is described as merely one example of a nonvolatile storage device, and other nonvolatile storage devices such as a hard disk drive may be used. The SSD 21, the controller CPU 22, and the controller DRAM 23 are connected to each other by a communication bus (not shown) included in the computing device 1, such as a PCI Express (hereinafter also referred to as "PCIe"). The SSD 21 is one or more nonvolatile storage devices. The controller CPU 22 executes a program, which will be described later.

[0011] The controller DRAM 23 stores a session management table 231, a CPU setting list 232, a protocol setting list 233, an IO processing program 234, a network setting program 235, and a CHB setting program 236. The session management table 231 stores information on each session between the processor 1 and the host 99. The CPU setting list 232 stores settings of the CPU 35 mounted in each smart NIC 3. The protocol setting list 233 sets a communication protocol for each port of each smart NIC 3.

[0012] The IO processing program 234, the network setting program 235, and the CHB setting program 236 are executed by the controller CPU 22. The IO processing program 234 writes data to the SSD 21 and reads data from the SSD 21 based on an operation command received from the outside via the smart NIC 3. The storage controller 2 receives a PDU (protocol data unit) according to a predetermined communication protocol from the smart NIC 3, and operates based on the operation command included in this PDU. The predetermined communication protocol is a publicly known or future communication protocol, such as iSCSI, Infini Band, or NVMe over TCP. The PDU is also called a network packet, a network frame, or communication data.

[0013] The network setting program 235 creates a session between the host 99 and the computing device 1, and updates the session management table 231. The CHB setting program 236 provides a setting screen for the operator, and creates or updates the CPU setting list 232 and the protocol setting list 233 based on the operator's input. This setting screen will be described later with reference to FIG.

[0014] The smart NIC 3 includes memories DRAM 31, flash 32, embedded memory 33, ASIC 34, CPU 35, and a communication module 36. The DRAM 31 is a volatile memory. The DRAM 31 stores a connection management table 311, a task management table 312, a CPU management table 313, a protocol setting table 314, a CPU setting table 315, a command processing program 316, a conversion program 317, a queue operation program 318, and a network protocol processing program 319.

[0015] The flash 32 stores firmware for the smart NIC 3. The built-in memory 33 is a non-volatile storage device, and stores program data 331 and setting information 332. The program data 331 becomes a command processing program 316, a conversion program 317, a queue operation program 318, and a network protocol processing program 319 when expanded in the DRAM 31. The setting information 332 is a collection of a connection management table 311, a task management table 312, a CPU management table 313, a protocol setting table 314, and a CPU setting table 315. The data and programs stored in the DRAM 31 will be described later.

[0016] The ASIC 34 is an application specific integrated circuit. The ASIC 34 executes processes to be executed by the smart NIC 3, other than the processes executed by the command processing program 316, the conversion program 317, the queue operation program 318, and the network protocol processing program 319. The CPU 35 is a central processing unit and has multiple arithmetic cores. The CPU 35 may be composed of multiple physical CPUs having one or multiple arithmetic cores, or may be composed of one CPU having multiple arithmetic cores. In this embodiment, a specific example will be described in which the CPU 35 has eight arithmetic cores, but the CPU 35 may have at least one arithmetic core. Hereinafter, the arithmetic core will also be referred to as a "core."

[0017] The communication module 36 is a physical communication module that communicates with a host 99 that exists outside the computing device 1. The communication module 36 has one or more connection ports, for example, SFP ports. The smart NIC 3 in this embodiment has two connection ports, which are referred to as "Port 0" and "Port 1" below to distinguish between the two. However, they may also be referred to as "Port 0" and "Port 1."

[0018] The input / output device 4 is a keyboard, a mouse, and a liquid crystal display. The input / output device 4 outputs screen information generated by the CHB setting program 236 to the liquid crystal display, and transmits inputs to the keyboard or mouse by the operator to the CHB setting program 236.

[0019] The data and programs stored in the DRAM 31 will be described. The connection management table 311 stores connection data for each port. In this embodiment, the communication module 36 has two ports, so there are two connection management tables 311. The task management table 312 stores the state of each task. The CPU management table 313 stores the connection identifiers and task identifiers processed by each core of the CPU 35. The protocol setting table 314 stores the communication protocols used by each port of the communication module 36 to communicate with the host 99. The CPU setting table 315 stores the settings of the CPU 35.

[0020] The command processing program 316 is a program that performs processing that can be processed inside the smart NIC 3. The command processing program 316 performs processing such as starting and ending a connection. For example, if a command included in a PDU received from the host 99 is to read data stored in the SSD 21, the smart NIC 3 cannot process the command, so the PDU is converted into a storage interface command (hereinafter also referred to as a "storage I / F command") and sent to the storage controller 2. However, if the command can be processed by the smart NIC 3, the command is processed by the command processing program 316 without being sent to the storage controller 2.

[0021] The conversion program 317 converts commands contained in the PDU. Specifically, the conversion program 317 rewrites commands contained in the PDU received from the host 99 into generic storage interface commands that can be processed by the storage controller 2. The conversion program 317 also rewrites commands contained in the storage interface commands received from the storage controller 2 into commands of other communications protocols that can be processed by the host 99 that is the destination of the PDU. The conversion program 317 also adds and deletes task IDs and connection IDs to the PDU.

[0022] The queue operation program 318 performs data transfer between a virtual queue and a real queue, which will be described later. The queue operation program 318 will be described in detail later. The network protocol processing program 319 converts the communication protocol in the PDU. In other words, the conversion program 317 converts the communication protocol into a storage interface command by rewriting the PDU.

[0023] FIG. 2 is a diagram showing an example of a session management table 231, a CPU setting list 232, and a protocol setting list 233 stored in the controller DRAM 23 of the storage controller 2. The session management table 231 stores data of each session. Specifically, it includes a session ID, protocol setting information, network setting information, and LUN mapping information. The session ID is an identifier of the session, and is expressed by a combination of "E" and a number in this embodiment. The protocol setting information is setting data related to the communication protocol to be used. Although "iSCSI setting" is written in FIG. 2 for the sake of simplicity, specific setting data is actually stored. The network setting information is setting data related to the network. Although "TCP setting, IP setting" is written in FIG. 2 for the sake of simplicity, specific setting data is actually stored. The LUN mapping information is an identifier of the logical unit number to be used.

[0024] The CPU setting list 232 stores the settings of the CPU 35 mounted on each smart NIC 3. Specifically, it includes CHB ID, queue operation dedicated mode, queue operation dual mode, port 0 CPU resource, and port 1 CPU resource. CHB ID is an identifier of the channel board, that is, the smart NIC 3, and in this embodiment, it is expressed by a combination of "C" and a number.

[0025] The queue operation dedicated mode and queue operation combined mode are settings for whether the CPU 35 operates in queue operation dedicated mode or queue operation combined mode. The queue operation dedicated mode and queue operation combined mode are two sides of the same coin, with one set to "Yes" and the other set to "No." The port 0 CPU resource and port 1 CPU resource are allocation settings for the CPU 35. The sum of the port 0 CPU resource and port 1 CPU resource is less than 100%.

[0026] In the protocol setting list 233, the communication protocol for each port is set for each smart NIC3. Specifically, the applicability for each protocol and port is described for each CHB ID. In the example shown in FIG. 2, it is described that port 0 of the smart NIC3 with CHB ID "C1" only supports "iSCSI Target" and port 1 only supports "NVMe over TCP". The protocol that each port can support is not limited to one; for example, port 1 of the smart NIC3 with CHB ID "C3" supports both "iSCSI Target" and "NVMe over TCP".

[0027] 3 is a diagram showing an example of a connection management table 311, a task management table 312, and a CPU management table 313 stored in the DRAM 31 of a smart NIC 3 whose CHB ID is "C1". The connection management table 311 stores connection data for each port. FIG. 3 shows an example of a connection management table 311 for port 0. That is, although not shown in FIG. 3, there is also a separate connection management table 311 that lists connections created using port 1.

[0028] Specifically, connection management table 311 stores connection IDs, core numbers, connection information, and task IDs. A connection ID is an identifier that identifies a connection, and in this embodiment is expressed as a combination of "N" and a number. A task ID is generated every time an IO is received from host 99. Since it is common to receive multiple PDUs over one connection, there is a 1:many relationship between connection IDs and task IDs.

[0029] The core number is an identifier of a core constituting the CPU 35, and in this embodiment is expressed as a combination of "R" and a number. The connection information is various data related to the connection. In FIG. 3, it is written as "Connection setting" for the sake of simplicity, but in reality, specific connection data is stored. The task ID is a list of identifiers of tasks linked to the corresponding connection, and in this embodiment is expressed as a combination of "T" and a number. Note that the task ID is written in hexadecimal in FIG. 3, but it may be expressed in decimal or other notation.

[0030] The task management table 312 stores the state of each task. Specifically, PDU1 and PDU2 are stored for each task ID. The CPU management table 313 stores the connection identifiers and task identifiers to be processed for each core of the CPU 35. The relationship between the core number and the connection ID, and the relationship between the connection ID and the task ID are described in the connection management table 311. Therefore, the CPU management table 313 can be created based on all the connection management tables 311 that one smart NIC 3 has.

[0031] FIG. 4 is a diagram showing an example of a protocol setting table 314 and a CPU setting table 315 stored in the DRAM 31 of the smart NIC 3 whose CHB ID is "C1". The protocol setting table 314 stores the communication protocol used by each port of the communication module 36 to communicate with the host 99. Since the storage controller 2 sends an operation command when initializing the smart NIC 3 based on the protocol setting list 233, the protocol setting table 314 of the smart NIC 3 records the value of the corresponding CHB ID in the protocol setting list 233 as it is. Specifically, in the protocol setting list 233 shown in FIG. 2, port 0 whose CHB ID is "C1" is set to "iSCSI Target", and port 1 is set to "NVMe over TCP". The protocol setting table 314 in FIG. 4 stores the same data as when the CHB ID is "C1" in the protocol setting list 233.

[0032] The settings of the CPU 35 are stored in the CPU setting table 315. Since the storage controller 2 sends an operation command when initializing the smart NIC 3 based on the CPU setting list 232, the value of the corresponding CHB ID in the CPU setting list 232 is entered as is in the CPU setting table 315 of the smart NIC 3. Specifically, the value of the CHB ID "C1" in the CPU setting list 232 shown in FIG. 2 is entered as is in the CPU setting table 315 of FIG.

[0033] FIG. 5 is a diagram showing an overview of the processing executed by the smart NIC 3. The smart NIC 3 relays bidirectional communication between the host 99 and the storage controller 2. However, FIG. 5 shows the relaying of communication from the host 99 to the storage controller 2. Various communication protocols such as RoCEv2, iSCSI, and NVMe over TCP are used for communication between the host 99 and the smart NIC 3. PCIe is used for communication between the smart NIC 3 and the storage controller 2. The smart NIC 3 supports various communication protocols with the host 9 through software processing.

[0034] When the smart NIC 3 receives communication from the host 99, it first performs protocol analysis, for example, PDU header analysis. Next, the smart NIC 3 distributes commands. Specifically, it determines whether or not the command needs to be sent to the storage controller 2. If the smart NIC 3 can process the command itself, it sends the processing result to the host 9, and if it needs to be sent to the storage controller 2, it continues processing. Next, the smart NIC 3 converts the PDU into a storage interface command. Specifically, it rewrites the received PDU header so that the storage controller 2 can interpret it, and also processes the PDU payload as necessary. Next, the smart NIC 3 stores the storage interface command in a queue, i.e., a waiting queue, to send to the storage controller 2. Queue processing will be described later.

[0035] Next, the smart NIC 3 distributes the interface commands. Finally, the smart NIC 3 transfers the storage interface command to the controller DRAM 23 of the storage controller 2 by DMA. Note that when relaying communication from the storage controller 2 to the host 99, the flow is reversed from that in FIG. 5.

[0036] 6 is a diagram showing an example of allocation of CPU cores in the communication module 36. The allocation of CPU cores in the communication module 36 in the smart NIC 3 is determined based on the entries in the CPU setting table 315 when the smart NIC 3 is initialized, for example, when the power is turned on. However, when the smart NIC 3 is initialized, the CPU setting of the corresponding smart NIC 3 may be copied from the CPU setting list 232 of the storage controller 2 to the CPU setting table 315.

[0037] In the example shown in the upper part of FIG. 6, all eight cores of smart NIC 3 are assigned to port 0. In this case, commands received from host 99-1 connected to port 0 are processed, but commands received from host 99-2 connected to port 1 are not processed. In the example shown in the lower part of FIG. 6, eight cores of smart NIC 3 are evenly assigned to port 0 and port 1. In this case, commands received from host 99-1 and commands received from host 99-2 are processed in the same ratio. This configuration corresponds to CPU setting table 315 shown in FIG. 4.

[0038] FIG. 7 is a schematic diagram showing the processing of each core of the smart NIC 3. However, this diagram shows the operation in the queue operation dual mode. The storage controller 2 has one command reception queue (C-queue) and one response response queue (R-queue). The command reception queue is a queue that stores commands from the host 99. The response response queue is a queue that stores response commands to the host 99. Below, the command reception queue and the response response queue are also referred to as "real queues."

[0039] Each core of the CPU 35 has a virtual command reception queue and a virtual response response queue. The virtual command reception queue and the virtual response response queue are realized by an area reserved in the DRAM 31 of the smart NIC 3. The virtual command reception queue and the virtual response response queue are, for example, a ring buffer. Hereinafter, the virtual command reception queue and the virtual response response queue are also called "virtual queues." That is, there is only one real queue, but there are as many virtual queues as there are cores, so it is necessary to integrate or separate the queues. The real queues and the virtual queues are separated in order to absorb the difference in the current configuration in which the number of queues in the storage controller 2 and the number of cores in the CPU 35 of the smart NIC 3 are different.

[0040] Each core of the CPU 35 performs reception processing, transmission processing, and queue operation. The reception processing is the processing up to storage in a queue, specifically, a virtual command reception queue, among the processing described with reference to FIG. 5 in relaying communication from the host 99 to the storage controller 2. The reception processing is the processing after the processing of acquiring a storage interface command from a virtual response reply queue in relaying communication from the storage controller 2 to the host 99. The queue operation is to extract and integrate storage interface commands from the virtual command reception queues of all cores and send them to the real queue of the storage controller 2 by DMA transfer, and to separate the storage interface commands acquired from the real queue of the storage controller 2 by DMA transfer and store them in the respective virtual response reply queues.

[0041] In smart NIC3, the same connection is handled by the same core. The purpose of this is to save resources, avoid complicated management, and avoid performance degradation due to contention and exclusive waiting between cores. For example, when core R3 receives a data request from host 99, core R3 sends the data obtained from storage controller 2 in response.

[0042] Fig. 8 is a diagram explaining the queue operation dedicated mode and the queue operation dual mode. However, here, as shown in the lower part of Fig. 4, it is assumed that the CPU resource allocation for each port is 50%. The upper part of Fig. 8 shows the queue operation dedicated mode, and the lower part of Fig. 8 shows the queue operation dual mode. The difference between the queue operation dedicated mode and the queue operation dual mode is whether or not roles are shared among cores.

[0043] In the queue operation dedicated mode shown in the upper part of Fig. 8, a dedicated core for performing queue operations is set for each port. In this embodiment, since the communication module 36 has two ports, port 0 and port 1, two cores are engaged in queue operations only. Therefore, in this case, the remaining six cores have virtual queues and perform reception processing and transmission processing. Focusing on one port, one core performs only queue operations, and three cores perform reception processing and transmission processing.

[0044] In the queue operation shared mode shown in the lower part of Figure 8, all cores perform queue operations, receive processing, and send processing. In this case, it is undefined which core performs the queue operations. For example, the same core may perform all of the queue operations, receive processing, and send processing for commands from a host 99. In this case, four cores per port perform the queue operations, receive processing, and send processing.

[0045] In the following, the calculation core that performs reception and transmission processing is called the "IO core", and the calculation core that performs queue operations is called the "queue core". In the queue operation only mode, the IO core and queue core are fixed, but in the queue operation combined mode, the IO core and queue core are fluid. That is, in the queue operation combined mode, one core operates as an IO core at one time, and as a queue core at another time. The same number of virtual queues as the IO cores are prepared, and in the queue operation only mode, the virtual queues shown in the figure below are prepared, which are the number of calculation cores in the CPU35 minus the number of queue cores. In the queue operation combined mode, the number of IO cores varies depending on the timing, but any core can become an IO core, so the same number of virtual queues as the number of calculation cores in the CPU35 are prepared.

[0046] There is no clear superiority or inferiority between the queue operation dedicated mode and the queue operation combined mode, and each has its own advantages and disadvantages. The advantage of the queue operation dedicated mode is that it fixes the core that performs the queue operation, so there is no need for exclusive processing between cores to operate the queue, and there is no overhead for this exclusive processing. On the other hand, it has the disadvantage that the number of cores performing IO processing is reduced. The advantage of the queue operation combined mode is that it increases the number of cores performing IO processing. The disadvantage of the queue operation combined mode is that exclusive processing between cores is required to operate the queue.

[0047] 9 is a diagram showing the relationship between the session management table 231, the connection management table 311, and the task management table 312. The session management table 231 is stored in the storage controller 2, and the connection management table 311 and the task management table 312 are stored in the smart NIC 3. The session management table 231 stores information for each session. The connection management table 311 stores one or more task IDs associated with each session ID, and information for each connection. The task management table 312 stores information for each task. The correspondence between the session ID and the connection ID can be identified from the correspondence between the network setting information associated with the session ID and the connection information associated with the connection ID.

[0048] 10 is a diagram showing the relationship between the session management table 231, the connection management table 311, and the CPU management table 313. The session management table 231 is stored in the storage controller 2, and the connection management table 311 and the CPU management table 313 are stored in the smart NIC 3. The correspondence between the connection ID and the core number can be identified from each of the connection management table 311 and the CPU management table 313.

[0049] 11 is a diagram showing the relationship between the task management table 312 and the CPU management table 313. Information for each task ID is stored in the task management table 312. Information for one or more task IDs corresponding to core numbers is stored in the CPU management table 313.

[0050] 12 is a schematic diagram showing data processing in the computing device 1. First, the host 99 transmits processing request data, which is data requesting processing, to the computing device 1, and the smart NIC 3, which is a network interface of the computing device 1, receives the data. Then, the smart NIC 3 adds a task ID and a connection ID to the storage interface command through command conversion processing by the conversion program 317, and transfers the command to the storage controller 2 by DMA.

[0051] The storage controller 2 identifies the session ID by referring to the session management table 231, performs processing based on the processing request, and obtains the processing result. For example, this processing is reading specified data from the SSD 21, and the processing result is the data read from the SSD 21. The storage controller 2 writes back the task ID and connection ID that were added to the data received from the smart NIC 3 as is to the processing result, and copies it to the smart NIC 3 by DMA transfer. The smart NIC 3 performs command conversion again, and transmits the processing result to the host 99.

[0052] 13 is a flowchart showing reception processing by the CPU 35. The processing of this flowchart is generally executed by the conversion program 317. In step S501, the conversion program 317 receives a protocol command from the host 99. In the following step S502, the conversion program 317 distributes the protocol command, and proceeds to step S506 if it is determined that the command can be processed within the smart NIC 3, and proceeds to step S503 if it is determined that processing by the storage controller 2 is required. In step S503, the command processing program 316 processes the command. In the following step S504, the conversion program 317 performs command conversion, converting the communication protocol used by the host 99 into an interface command that can be interpreted by the storage controller 2.

[0053] In the next step S505, the conversion program 317 adds the generated message to a virtual queue, and ends the process shown in Fig. 13. The virtual queue to which the message is added is the virtual queue of the CPU core that is executing the process shown in Fig. 13. In step S506, the command processing program 316 performs command processing in the smart NIC 3. In the next step S507, the conversion program 317 responds to the host 99 using the result of step S506, and ends the process shown in Fig. 13.

[0054] 14 is a flowchart showing queue operation processing by the CPU 35. In step S511, the queue operation program 318 integrates queues, that is, integrates messages stored in the virtual queues of each CPU core. In the following step S512, the queue operation program 318 transfers the storage interface commands integrated in step S511 to the storage controller 2 by DMA transfer. In response to a request from the storage controller 2, the queue operation program 318 also transfers the processing result of the storage controller 2 from the storage controller 2 to the smart NIC 3 by DMA transfer.

[0055] In the next step S513, the queue operation program 318 receives the command response, and in the next step S514, the queue operation program 318 separates the queue. In the next step S515, the queue operation program 318 adds the separated queue to the virtual response queue of the appropriate core, and ends the process shown in FIG. 14. Here, the method of selecting the appropriate core is as follows. As shown in FIG. 12, a connection ID and a task ID are added to the storage interface command received from the storage controller 2. Therefore, the queue operation program 318 can specify the core number to which the PDU resulting from converting the storage interface command should be transmitted by referring to the connection management table 311 or the CPU management table 313. As described above, a virtual queue is prepared for each core of the CPU 35, and the correspondence between the core and the virtual queue is known, so the queue operation program 318 adds the storage interface command to the virtual queue corresponding to the specified core number.

[0056] Fig. 15 is a flowchart showing a transmission process by the CPU 35. In step S521, the conversion program 317 extracts one storage interface command from the corresponding virtual response reply queue. In the following step S522, the conversion program 317 performs command processing on the extracted storage interface command, and in the following step S523, converts the interface command into a PDU of the communication protocol used by the host 99 by command conversion. In the following step S524, the conversion program 317 responds to the host 99 using the processing result of step S523, and ends the process shown in Fig. 15.

[0057] Figures 16 and 17 are time charts showing the processing of the arithmetic device 1. However, Figures 16 and 17 show a series of processing of the arithmetic device 1 responding to a request from the host 99, and are continuous. Specifically, the response to S551, which is the first processing in Figure 16, is S585 shown at the end of Figure 17. This time chart is intended to illustrate the cores of the CPU 35 that perform the processing.

[0058] First, the host 99 issues a network protocol command to the smart NIC 3 (S551). The core R1 of the smart NIC 3 receives this and performs network protocol analysis (S552) and command distribution (S553), which are protocol processes. Next, command processing (S554) and command conversion (S555) are performed as command processing in the broad sense. Furthermore, the CPU 35 inputs the result of the command conversion into a virtual queue (S556). S552 to S556 are executed by the same core, for example, the core R1.

[0059] Next, the CPU 35 extracts commands from the multiple virtual queues and consolidates them (S561), and transfers the consolidated command to the storage controller 2 by DMA transfer (S562). The transferred commands are input to the real queue of the storage controller 2, and the IO processing program 234 receives the commands in order (S563). S561 to S562 are executed by the same core, for example, core R2. However, S561 to S562 may be executed by the same core as S552 to S556, or may be executed by a different core.

[0060] The description will be continued with reference to FIG. 17. When the IO processing program 234 creates a command response (S564), it requests the smart NIC 3 to perform a DMA transfer (S565). The CPU 35 of the smart NIC 3 that receives this request performs a DMA transfer, copies the storage interface command from the storage controller 2 to the DRAM 31 (S567), and receives the command response (S568). Then, it separates the queue (S569) and adds the separated queue to an appropriate virtual response queue by referring to the connection management table 311 or the CPU management table 313 (S570). S567 to S570 are executed by the same core, for example, the core R3. However, S561 to S562 may be executed by the same core as S552 to S556 and S561 to S562, or may be executed by a different core.

[0061] 17, for example, core R1, dequeues the storage interface command from the virtual response queue of core R3 (S581) and performs command processing (S582). Core R1 then converts the storage interface command into a command that matches the network protocol of host 99 (S583), performs network protocol processing (S584), and transmits a response to host 99 (S585). S581 to S585 are executed by the same core as S552 to S556.

[0062] Fig. 18 is a diagram showing an example of a setting screen generated by the CHB setting program 236. The setting screen may be displayed on the input / output device 4 of the computing device 1, or may be displayed on another device via network communication. A protocol setting screen 910 is shown at the top of Fig. 18, and a CPU setting screen 920 is shown at the bottom of Fig. 18. The protocol setting screen 910 and the CPU setting screen 920 may be displayed simultaneously as shown in Fig. 18, or may be displayed separately.

[0063] The protocol setting screen 910 has a CHB selection button 911, a port 0 setting button 912, and a port 1 setting button 913. The operator uses the CHB selection button 911 to change the channel board to be set. The operator uses the port 0 setting button 912 to set the communication protocol supported by port 0. The operator uses the port 1 setting button 913 to set the communication protocol supported by port 0. The results of the operator's operations on the protocol setting screen 910 are reflected in the protocol setting list 233. Note that in the example shown in FIG. 18, the port 0 setting button 912 and the port 1 setting button 913 are pull-down menus, so only one item can be selected, but two or more items may be selectable.

[0064] The CPU setting screen 920 has a CHB selection button 921, a mode setting button 922, a port 0 ratio setting button 923, and a port 1 ratio setting button 924. The operator uses the CHB selection button 921 to change the channel board to be set. The operator uses the mode setting button 922 to set either the queue operation dedicated mode or the queue operation dual mode. The operator uses the port 0 ratio setting button 923 to set the ratio of CPUs 35 used for port 0. The operator uses the port 1 ratio setting button 924 to set the ratio of CPUs 35 used for port 1. The results of the operator's operations on the protocol setting screen 910 are reflected in the CPU setting list 232.

[0065] According to the above-described first embodiment, the following advantageous effects can be obtained. (1) Smart NIC 3, which can also be called an interface module, is connected to storage controller 2 and relays communication between host 99 and storage controller 2. Host 99 and storage controller 2 use different communication protocols. Smart NIC 3 includes multiple computing cores and DRAM 31. At least one of the multiple computing cores is an IO core that communicates with host 99, and each of the IO cores has a virtual queue in DRAM 31. The IO core performs a receiving process of converting the communication protocol of the PDU output by host 99 and storing it in the virtual queue, and a sending process of extracting a storage interface command from the virtual queue, converting the communication protocol, and sending it to host 99, and in the same session, the same IO core performs the receiving process and the sending process. Therefore, it is easy to support new communication protocols.

[0066] (2) The calculation core performs queuing operations to integrate the storage interface commands stored in each virtual queue by the receiving process and transfer them to the storage controller 2, and to separate the storage interface commands obtained from the storage controller 2 and store them in each virtual queue.

[0067] (3) The smart NIC 3 has multiple external communication ports capable of communicating with the host 99. In this embodiment, the communication module 36 has two communication ports, port 0 and port 1. Using the CPU setting table 315, the number of computing cores to be assigned to each external communication port can be set in advance.

[0068] (4) In the queue operation shared mode, each of the processor cores is set to be able to execute reception processing, transmission processing, and queue operations, allowing the number of cores performing IO processing to be increased.

[0069] (5) In the queue operation-only mode, the IO core, which is part of the computation core, executes receive and transmit processes but does not execute queue operations, and the queue core, which is another part of the computation core, executes queue operations but does not execute receive and transmit processes. Therefore, mutual exclusion between cores for queue operations is not required, and there is no overhead for this mutual exclusion.

[0070] (Variation 1) In the above-described embodiment, the storage controller 3 is provided with only one real queue. However, the storage controller 3 may be provided with two or more real queues.

[0071] In each of the above-mentioned embodiments and modifications, the configuration of the functional blocks is merely an example. Some functional configurations shown as separate functional blocks may be integrated, or a configuration shown in one functional block diagram may be divided into two or more functions. In addition, some of the functions of each functional block may be provided by other functional blocks.

[0072] In each of the above-described embodiments and modifications, the arithmetic device 1 may be provided with an input / output interface (not shown), and a program may be loaded from another device when necessary via the input / output interface and a medium available to the arithmetic device 1. Here, the medium refers to, for example, a storage medium that is detachable from the input / output interface, or a communication medium, i.e., a wired, wireless, optical, or other network, or a carrier wave or digital signal that propagates through the network. In addition, some or all of the functions realized by the program may be realized by a hardware circuit or an FPGA.

[0073] The above-mentioned embodiments and modifications may be combined with each other. Although various embodiments and modifications have been described above, the present invention is not limited to these. Other aspects that are conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. For example, a smart NIC 3 may be used as an interface between one storage and another storage. [Explanation of symbols]

[0074] 1: Arithmetic device 2: Storage controller 3: Smart NIC 35 :CPU 44: Operation mode table 99 : Host 231: Session management table 232: CPU setting list 233: Protocol setting list 234: IO processing program 235: Network configuration program 311: Connection management table 312: Task management table 313 :CPU management table 314: Protocol setting table 315 :CPU setting table 316: Command processing program 317: Command conversion program 318: Queue operation program 319: Network protocol processing program

Claims

1. An interface module connected to a storage controller and relaying communication between a host and the storage controller, the host and the storage controller use different communication protocols; Equipped with multiple computing cores and memory, At least one of the plurality of computing cores is an IO core that communicates with the host; each of the IO cores has a virtual queue in the memory; The IO core executes a receiving process of converting communication data including a command to the storage controller output by the host into a storage interface command and storing the command in the virtual queue; The IO core executes a transmission process to retrieve a storage interface command from the virtual queue, convert it into communication data, and transmit it to the host; An interface module, wherein the receiving process and the transmitting process are executed by the same IO core in the same session.

2. 2. The interface module of claim 1, At least one of the plurality of computing cores is a queue core; the queue core executes a queue operation to integrate the storage interface commands stored in each of the virtual queues by the receiving process and transfer the integrated storage interface commands to the storage controller, and separate the storage interface commands obtained from the storage controller and store the separated commands in each of the virtual queues; An interface module, wherein each of the plurality of computing cores does not simultaneously operate as the IO core and the queue core.

3. 2. The interface module of claim 1, A plurality of external communication ports capable of communicating with the host are provided, an interface module capable of setting in advance the number of calculation cores to be assigned to each of the external communication ports;

4. 3. The interface module of claim 2, an interface module, wherein each of the computing cores is configured to be able to execute all of the receiving process, the transmitting process, and the queue operation;

5. 3. The interface module of claim 2, An interface module, wherein a portion of the computation cores executes the receiving process and the transmitting process but does not execute the queue operation, and another portion of the computation cores executes the queue operation but does not execute the receiving process or the transmitting process.

6. 3. The interface module of claim 2, the IO core assigns an identifier capable of identifying the IO core to the storage interface command stored in the virtual queue; The computing core determines, in the queue operation, the virtual queue in which to store the storage interface command based on the identifier included in the storage interface command, and the interface module.

7. A computing device comprising: an interface module capable of communicating with a host; and a storage controller that communicates with the host via the interface module, the host and the storage controller use different communication protocols; Equipped with multiple computing cores and memory, At least one of the plurality of computing cores is an IO core that communicates with the host; each of the IO cores has a virtual queue in the memory; The IO core executes a receiving process of converting communication data including a command to the storage controller into a storage interface command and storing the command in the virtual queue; The IO core executes a transmission process to retrieve a storage interface command from the virtual queue, convert it into communication data, and transmit it to the host; In the same session, the receiving process and the transmitting process are executed by the same IO core.

8. A communication method executed by an interface module that is locally connected to a storage controller, relays communication between a host and the storage controller, and has a plurality of computing cores and a memory, the method comprising: the host and the storage controller use different communication protocols; At least one of the plurality of computing cores is an IO core that communicates with the host; each of the IO cores has a virtual queue in the memory; The IO core executes a receiving process of converting communication data including a command to the storage controller output by the host into a storage interface command and storing the command in the virtual queue; The IO core executes a transmission process to retrieve a storage interface command from the virtual queue, convert the command into communication data, and transmit the communication data to the host; A communication method, wherein the receiving process and the transmitting process are executed by the same IO core in the same session.

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