Manufacturing method of semiconductor device and semiconductor wafer

Abstract

To provide a manufacturing method of a semiconductor device capable of detecting the occurrence of Hi-K loss.SOLUTION: A manufacturing method of a semiconductor device includes a forming step of forming a test pattern including a reference resistor R_CL and a gate leak resistor GR connected in series with the reference resistor R_CL and through which a gate leak current flows, and a measuring step of measuring a change in voltage at a connection node Cnc between the reference resistor R_CL and the gate leak resistor GR caused by the flow of the gate leak current.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor device and a semiconductor wafer in which a field effect transistor (hereinafter referred to as a transistor or FET) using an insulating film having a higher dielectric constant than a silicon nitride film as a gate insulating film is formed. [Background technology]

[0002] An FET using a high dielectric constant insulating film having a higher dielectric constant than a silicon nitride film as a gate insulating film is described in, for example, Patent Document 1. Patent Document 1 describes a technique related to a manufacturing method for a semiconductor device that can improve reliability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-27096 Summary of the Invention [Problem to be solved by the invention]

[0004] With the advancement of semiconductor devices, FETs are becoming smaller and their gate insulating films are becoming thinner. When the gate insulating film is made thinner, it is thought that the gate leakage current flowing through the gate insulating film increases, and therefore, in order to reduce the gate leakage current, high dielectric constant insulating materials (Hi-K) that have a higher dielectric constant than silicon nitride films, for example, are being used as the gate insulating film.

[0005] The Hi-K gate insulating film is composed of, for example, a hafnium oxide (HfO2) film. In Patent Document 1, a dielectric titanium nitride (TiN) layer that stops etching is formed on top of this. Such a hafnium oxide film and the titanium nitride layer laminated thereon may disappear due to, for example, fluctuations in the process of manufacturing a semiconductor device. Hereinafter, the disappearance of the hafnium oxide film and the titanium nitride layer laminated thereon is referred to as Hi-K disappearance.

[0006] When Hi-K disappearance occurs, for example, gate leakage current increases, the transistor characteristics of the FET do not become as desired, and the circuitry in the semiconductor device may not operate normally.

[0007] The Hi-K loss mentioned above is neither recognized nor described in US Pat. No. 5,399,633. [Means for solving the problem]

[0008] A brief outline of a representative embodiment of the present invention will be described below.

[0009] That is, the manufacturing method of the semiconductor device according to the embodiment includes a formation process of forming a test pattern having a reference resistor and a gate leakage resistor connected in series with the reference resistor and through which a gate leakage current flows, and a measurement process of measuring a change in voltage at a connection node between the reference resistor and the gate leakage resistor caused by the flow of the gate leakage current.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. Effect of the Invention

[0011] According to one embodiment, it is possible to provide a manufacturing method for a semiconductor device capable of detecting the occurrence of Hi-K disappearance. [Brief description of the drawings]

[0012] [Figure 1] 1A and 1B are plan views each showing a schematic configuration of a semiconductor wafer according to a first embodiment. [Diagram 2] FIG. 2 is a flow chart diagrammatically illustrating a method for manufacturing a semiconductor wafer according to the first embodiment. [Diagram 3] 1 is a plan view illustrating a schematic configuration of a semiconductor chip and a TEG circuit according to a first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing a configuration of a memory cell. [Diagram 5] 1A and 1B are cross-sectional views illustrating a semiconductor device according to a first embodiment. [Figure 6] FIG. 2 is a plan view showing a configuration of a test pattern according to the first embodiment. [Figure 7] FIG. 2 is a schematic plan view showing a configuration of a reference resistor according to the first embodiment. [Figure 8] 4 is a schematic cross-sectional view showing a relationship between a reference resistor and a test pattern according to the first embodiment. FIG. [Figure 9] 1A and 1B are diagrams for explaining a TEG circuit according to a first embodiment. [Figure 10] 1A and 1B are diagrams for explaining a TEG circuit according to a first modification of the first embodiment. [Figure 11] FIG. 11 is a block diagram showing a configuration of a TEG circuit according to a second modification of the first embodiment. [Figure 12] FIG. 4 is a diagram for explaining a gate leakage current and a gate leakage resistance according to the first embodiment. [Figure 13] 13(A) and 13(B) are diagrams illustrating the effects of the first embodiment. [Figure 14] 11A to 11C are diagrams for explaining the manufacture of a semiconductor device according to the second embodiment. [Figure 15] 13A to 13C are diagrams for explaining the manufacture of a semiconductor device according to the third embodiment. [Figure 16] 13A to 13C are diagrams for explaining a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those skilled in the art can easily come up with appropriate modifications that maintain the gist of the invention and are naturally included in the scope of the present invention.

[0014] In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0015] In the following, as an example of a semiconductor device, a semiconductor wafer on which multiple semiconductor chips and test patterns (hereinafter also referred to as a TEG (Test Elementary Group) circuit) are arranged will be described, but a semiconductor chip on which a TEG circuit and multiple circuit blocks are arranged may also be used as the semiconductor device.

[0016] (Embodiment 1) <Methods of Manufacturing Semiconductor Wafers and Semiconductor Devices> FIG. 1 is a plan view showing a schematic configuration of a semiconductor wafer according to a first embodiment. Here, FIG. 1(A) is a plan view of the semiconductor wafer, and FIG. 1(B) is a plan view showing the arrangement of semiconductor chips and TEG circuits in the semiconductor wafer. In FIG. 1(A), HW indicates a semiconductor wafer. As shown in FIG. 1(A), a plurality of semiconductor chips CHP are formed on the semiconductor wafer HW. In FIG. 1(B), TG indicates a TEG circuit. The TEG circuit TG is formed on the semiconductor wafer HW, for example, between two semiconductor chips CHP_1 and CHP_2.

[0017] The TEG circuit TG has components similar to those formed on the semiconductor chip CHP, such as FETs. The characteristics of the components in the TEG circuit TG are measured, and the characteristics of the components in the semiconductor chip CHP are estimated. In FIG. 1B, the dashed lines SL indicate scribe lines for cutting the semiconductor chips CHP_1 to CHP_4 out of the semiconductor wafer HW.

[0018] FIG. 2 is a flow chart diagram showing a schematic diagram of a method for manufacturing a semiconductor wafer (semiconductor device) according to the first embodiment. In FIG. 2, S1 indicates a forming process for forming circuit blocks and components of a TEG circuit and wiring layers connecting the components on a semiconductor wafer HW by a semiconductor manufacturing technique. S2 indicates a wafer acceptance test (hereinafter also referred to as WAT) process. In the WAT process (measurement process), the characteristics of components in the TEG circuit formed in the forming process S1, for example, FETs, are measured. In a judgment process S3, it is judged whether or not the measured characteristics of the FETs are within a predetermined standard. In a wafer test process S4, a test of the semiconductor wafer HW is performed on the semiconductor wafer HW when it is judged (Y) that the characteristics of the FETs are within the predetermined standard. Based on the test result in the wafer test process S4, in step S5, it is judged whether or not the semiconductor wafer is a non-defective product.

[0019] If the semiconductor wafer HW is determined to be a non-defective product (Y) in the determination process S5, dicing is performed along the scribe lines SL (FIG. 1(B)) in step S6, and the semiconductor chips CHP are cut out from the semiconductor wafer HW (FIG. 1(A)). The cut-out semiconductor chips CHP are packaged, for example, and a chip test is performed in a chip test process S7. Products selected as non-defective products by the chip test are shipped. That is, multiple semiconductor chips CHP are manufactured from each semiconductor wafer HW.

[0020] On the other hand, if it is determined (N) in the determination step S3 that the characteristics of the FET are not within the predetermined standard (out of standard), or if it is determined (N) in the determination step S5 that the semiconductor wafer HW is not a conforming product, the semiconductor wafer HW is not diced and step S8 is performed. In step S8, an analysis of the characteristics of the components formed on the semiconductor wafer is performed for, for example, a lot including the semiconductor wafer HW determined to be out of standard or an unconformable product.

[0021] As will be described later, in the embodiment, the gate leakage current of the FET is measured with high sensitivity in the WAT process S2. By defining the value of the gate leakage current as a predetermined standard value to be applied in the judgment process S3, it is possible to judge whether the semiconductor wafer HW is good or bad according to the value of the measured gate leakage current.

[0022] In the judgment step S3, instead of judging whether the semiconductor wafer HW is good or bad based on the gate leakage current, if the gate leakage current is large, for example, this may be used as a sign of a defect and notified to the subsequent test steps (for example, wafer test step S4, judgment step S5). In this case, the gate leakage current measured in the WAT step S2 is used as an alarm to call attention in the subsequent test steps performed on the same semiconductor wafer.

[0023] In the first embodiment, as shown in FIG. 1B, the TEG circuit TG is arranged on the scribe line SL, and is therefore removed from the semiconductor chip CHP by dicing in step S6. However, the TEG circuit TG may be arranged at a position away from the scribe line SL. In this case, the TEG circuit TG or a portion of the TEG circuit TG remains on the semiconductor chip CHP.

[0024] <Semiconductor chip> FIG. 3 is a plan view illustrating a schematic configuration of the semiconductor chip and the TEG circuit according to the first embodiment.

[0025] Although a plurality of circuit blocks are formed in the semiconductor chip CHP according to the first embodiment, only the circuit blocks necessary for the explanation are shown in FIG. 3. In FIG. 3, MM_S indicates a static memory (hereinafter also referred to as an SRAM circuit) which is an electrically volatile memory, MM_N indicates an electrically erasable nonvolatile memory, and PR indicates a circuit block formed by combining a plurality of logic circuits. The circuit block PR constitutes, for example, a processor that operates according to a program stored in the nonvolatile memory MM_N. The SRAM circuit MM_S includes a plurality of static memory cells (hereinafter also referred to as memory cells) S_CL, and temporarily stores data when the processor operates. The nonvolatile memory MM_N includes, for example, a plurality of N-channel MONOS (Metal Oxide Nitride Oxide Silicon) transistors with a charge storage layer, and program data is stored in the MONOS transistors.

[0026] The TEG circuit TG is formed with a plurality of test patterns corresponding to a plurality of components and electrodes (pads) to which the probes are abutted during WAT measurement. In Fig. 3, a plurality of test patterns T_CL having a configuration similar to that of the memory cell S_CL and a logic circuit LG connected to the plurality of test patterns T_CL are shown as test patterns. In Fig. 3, the pad to which the logic circuit LG is connected is shown as a pad PAD.

[0027] In the following, an example will be described in which it is detected whether or not Hi-K loss has occurred in the FET constituting the test pattern T_CL of the memory cell. First, the configuration of the memory cell S_CL will be described.

[0028] 4 is a circuit diagram showing the configuration of a memory cell. The memory cell S_CL includes N-channel FETs (hereinafter also referred to as N-FETs) PD1, PD2, PG1, and PG2, and P-channel FETs (hereinafter also referred to as P-FETs) PU1 and PU2. The drain region of the N-FET PD1 is connected to the drain region of the P-FET PU1, the source region is connected to the ground voltage GND, and the gate electrode is connected to the gate electrode of the P-FET PU1. The source region of the P-FET PU1 is connected to the power supply Vdd. Similarly, the drain region of the N-FET PD2 is connected to the drain region of the P-FET PU2, the source region is connected to the ground voltage GND, and the gate electrode is connected to the gate electrode of the P-FET PU2. The source region of the P-FET PU2 is connected to the power supply Vdd.

[0029] The gate electrodes of FETPU1 and PD1 are connected to the drain regions of FETPU2 and PD2. In addition, the gate electrodes of FETPU2 and PD2 are connected to the drain regions of FETPU1 and PD1. That is, a CMOS inverter IV1 formed by FETPU1 and PD1 and a CMOS inverter IV2 formed by FETPU2 and PD2 are cross-connected to form a latch circuit. A path between the drain region and source region of N-FETPG1 is connected in series between the output of CMOS inverter IV1 (input of CMOS inverter IV2) and bit line DL, and a gate electrode of N-FETPG1 is connected to word line WL. In addition, a path between the drain region and source region of N-FETPG2 is connected in series between the output of CMOS inverter IV2 (input of CMOS inverter IV1) and bit line / DL, and a gate electrode of N-FETPG2 is connected to word line WL.

[0030] In FIG. 4, the arrows shown in N-FET PD1, PD2, PG1, and PG2 indicate the gates (back gates) on the substrate side of the N-FET, and the terminal Tn connected to the back gate indicates the electrode on the substrate side. Similarly, the arrows shown in P-FET PU1 and PU2 indicate the back gates of the P-FET, and the terminal Tp connected to the back gate indicates the electrode on the substrate side. When the substrates of N-FET PD1, PD2, PG1, and PG2 are, for example, P-type semiconductor well regions (semiconductor regions), the terminal Tn is constituted by an electrode ohmically connected to the P-type well region. Similarly, when the substrates of P-FET PU1 and PU2 are, for example, N-type semiconductor well regions (semiconductor regions), the terminal Tp is constituted by an electrode ohmically connected to the N-type well region.

[0031] Here, N-FET PD1 and PD2 can be regarded as driver FETS, P-FET PU1 and PU2 can be regarded as load FETS, and N-FET PG1 and PG2 can be regarded as transfer FETS. By setting the word line WL to a high level, the transfer FETS PG1 and PG2 are turned on, and data transmission and reception are performed between the bit lines DL, / DL and the latch circuit in the memory cell S_CL.

[0032] In Embodiment 1, the test pattern T_CL arranged in the TEG circuit TG has a configuration similar to that of the memory cell S_CL as described above. That is, the test pattern T_CL also has the N-FET PD1, PD2, PG1, PG2 and P-FET PU1, PU2 shown in FIG. 4.

[0033] <Hi-K disappearance> FIG. 5 is a schematic cross-sectional view for explaining the semiconductor device according to Embodiment 1. FIG. 5 shows the cross-sections of the drive FET (N-FET PD1) and the load FET (P-FET PU1) shown in FIG. 4. Here, FIG. 5(A) shows the state when Hi-K disappearance does not occur, and FIG. 5(B) shows the state when Hi-K disappearance occurs.

[0034] In Fig. 5, 10 indicates a P-type semiconductor region in which an N-FET PD1 is formed, and 11 indicates an N-type semiconductor region in which a P-FET PU1 is formed. I_ST is an element isolation region for isolating the P-type semiconductor region 10 and the N-type semiconductor region 11. The element isolation region I_ST is formed using a known STI (Shallow Trench Isolation) technique, although there is no particular limitation. The P-type semiconductor region 10 and the N-type semiconductor region 11 correspond to the P-type well region P_W and the N-type well region N_W in Fig. 6 described later.

[0035] In FIG. 5(A), 16 denotes a silicon oxide film of an intermediate layer formed on the P-type semiconductor region 10 and the N-type semiconductor region 11, which are active regions, before forming the hafnium oxide film 12. 13 denotes a titanium nitride layer laminated on the hafnium oxide film 12. Also, 14 and 15 denote metals constituting the gate electrodes of the N-FET PD1 and the P-FET PU1. The metals 14 and 15 are formed of different metals (metal 14 for N-FET and metal 15 for P-FET) so as to be suitable for the N-FET and the P-FET. By using a Hi-K gate insulating film, it is possible to reduce the gate leakage current flowing between the gate electrode (metals 14, 15) and the P-type semiconductor region 10 and the N-type semiconductor region 11 through the gate insulating film.

[0036] When Hi-K disappearance occurs, as shown in FIG. 5(B), the hafnium oxide film 12, the titanium nitride layer 13, and the silicon oxide film 16 disappear, and a new silicon oxide film 16_U is formed on the activation region. Since the hafnium oxide film 12 and the titanium nitride layer 13 disappear, the gate leakage current increases, and circuit blocks such as the memory cell S_CL may not operate properly. Even when Hi-K disappearance occurs, since the silicon oxide film 16_U is formed between the gate electrode and the P-type semiconductor region 10 and the N-type semiconductor region 11, an increase in the gate leakage current is suppressed, and it may operate as a FET. However, in this case, the characteristics of the FET deteriorate, and the characteristics of the circuit block also deteriorate.

[0037] <Detection of Hi-K disappearance> In the first embodiment, a circuit for detecting Hi-K disappearance is arranged in the TEG circuit TG (FIG. 3), and it is possible to detect Hi-K disappearance in the WAT process S2 (FIG. 2).

[0038] As described above, the TEG circuit TG according to the first embodiment includes a test pattern T_CL having a configuration similar to that of the memory cell S_CL, and a logic circuit LG connected to the test pattern T_CL.

[0039] FIG. 6 is a plan view showing the configuration of the test pattern according to the first embodiment. The test pattern T_CL includes FETs corresponding to the FETs constituting the memory cell S_CL (FIG. 4) shown in FIG. 4. In FIG. 6, the same reference numerals as those used in FIG. 4 are attached to the gate electrode portions of the FETs. That is, in FIG. 6, the reference numerals PD1, PD2, PG1, PG2, PU1, and PU2 indicate the gate electrode portions of the corresponding FETs PD1, PD2, PG1, PG2, PU1, and PU2.

[0040] In FIG. 6, P_W indicates a P-type well region (first semiconductor region) formed in a semiconductor substrate, and N_W indicates an N-type well region (semiconductor region) formed in the same semiconductor substrate. In FIG. 6, a region filled with thin diagonal lines (e.g., region A_R) indicates an active semiconductor region formed in the P-type well region P_W and the N-type well region N_W. The active semiconductor region A_R is a semiconductor region separated by an element isolation region I_ST, such as the semiconductor regions 10 and 11 shown in FIG. 5. In FIG. 6, a region GL_R filled with dots indicates a gate wiring layer forming a gate electrode of an FET, and a region G_D filled with thin and thick diagonal lines indicates a cut region dividing the gate wiring layer GL_R. For example, the gate wiring layer GL_R of the gate electrodes constituting the transfer FETs PG1 and PG2 is cut in the cut region G_D. A region C_R marked with an x ​​indicates a contact region.

[0041] 6, the region WV_R surrounded by a dashed line indicates a voltage fixing region that supplies a predetermined voltage to the P-type well region P_W and the N-type well region N_W. That is, the voltage of the P-type well region P_W and the N-type well region N_W is set by supplying a predetermined voltage to the contact region C_R formed in the voltage fixing region WV_R. The contact region C_R formed in the voltage fixing region WV_R can be regarded as the terminals Tn and Tp shown in the memory cell S_CL shown in FIG.

[0042] In Fig. 6, a FET is formed at the intersection of the gate wiring layer GL_R and the active semiconductor region A_R. That is, the overlapping portion of the gate wiring layer GL_R and the active semiconductor region A_R is the configuration shown in Fig. 5(A). A high-k gate insulating film is formed at this overlapping portion. Moreover, the portion of the active semiconductor region adjacent to the overlapping portion becomes the source region and drain region of the FET.

[0043] In the first embodiment, a leakage (gate leakage) current flowing between a well region (P-type well region P_W, N-type well region N_W) and a gate electrode of an FET having a source region and a drain region formed in the well region is measured, and whether or not Hi-K disappearance has occurred is detected. FIG. 6 shows a case where transfer FETs PG1 and PG2 are used as FETs for measuring a gate leakage current. That is, in the example of FIG. 6, a contact region C_R is formed in a gate wiring layer (first electrode) GL_R for the gate electrode of the transfer FET PG2, an electrode (terminal) G_C is connected to the contact region C_R, and the electrode G_C is connected to the gate electrode of the transfer FET PG2. Also, an electrode (terminal) PW_C is connected to the contact region C_R formed in the voltage fixing region WV_R, and the electrode PW_C is connected to the well region. Each of the electrodes G_C and PW_C is connected to a metal wiring for measurement (not shown). When measuring the gate leakage current, for example, a voltage of −1 (V) or more is applied to the gate electrode of the transfer FETPG, and a voltage of 0 (V) is applied to the P-type well region P_W.

[0044] In order to draw out the metal wiring for measurement, three gate wiring layers are set as dummy DMMs from the voltage fixed region WV_R in Fig. 6. That is, the gate wiring layer located at a distance of three gate wiring layers (dummy DMMs) or more from the voltage fixed region WV_R is used to measure the gate leakage current.

[0045] Here, as an example of measuring the gate leakage current, a case where the transfer FET PG2 is used has been described, but the transfer FET PG1 may be used, or both transfer FETs may be used.

[0046] When the memory cell S_CL is configured by the FETs PU1, PU2, PD1, PD2, PG1, and PG2 shown in Fig. 6, the power supply wiring (power supply voltage Vdd, ground voltage GND), the word lines WL, and the bit lines DL and / DL, which are not shown in Fig. 6, are connected to predetermined regions of the FETs by contact regions. For example, the source regions or drain regions of the transfer FETs PG1 and PG2 are connected to the bit lines DL and / DL, which are not shown, by contact regions marked with symbols DL_C and / DL_C. Furthermore, cross-connection (cross-connection of the inverters IV1 and IV2 in Fig. 4) is performed by wiring indicated by the dashed dotted line CR_C.

[0047] In contrast, in the test pattern T_CL for measuring the gate leakage current, the FETs PU1, PU2, PD1, PD2, PG1, and PG2 are not connected to the power supply wiring, the word lines WL, and the bit lines DL and / DL (not shown). Also, no cross-connection is made by the wiring CR_C. Instead, as described above, the electrodes G_C and PW_C are connected to the metal wiring for measurement (not shown).

[0048] <<Reference resistance>> The gate leakage current is a current flowing through a gate leakage resistor (measurement resistor) that exists between a gate electrode and a well region. In the first embodiment, the occurrence of Hi-K vanishing is detected from the resistance value of this gate leakage resistor. In the first embodiment, a reference resistor is used to measure the resistance value of the gate leakage resistor.

[0049] Next, the reference resistor will be described with reference to the drawings. Fig. 7 is a schematic plan view showing the configuration of the reference resistor according to the first embodiment. Fig. 8 is a schematic cross-sectional view showing the relationship between the reference resistor and a test pattern according to the first embodiment.

[0050] In FIG. 7, R_CL denotes a reference resistor. In FIG. 7, the reference resistor R_CL corresponding to the gate leakage resistance of the P-type well region P_W is shown. As shown in FIG. 8, the P-type well region P_W and the P-type well region RP_W for the reference resistor R_CL are formed in the same semiconductor substrate. In FIG. 8, the semiconductor substrate is composed of a common bottom N-type well region BN_W. An isolating N-type well region IN_W is formed between the P-type well region P_W for forming the test pattern T_CL and the P-type well region RP_W for forming the reference resistor R_CL.

[0051] The reference resistor R_CL includes a gate wiring layer R_G formed on a P-type well region RP_W, as shown in Fig. 7 and Fig. 8. The gate wiring layer R_G is formed so as to cover an active region ACT of the P-type well region RP_W, as shown in Fig. 7, and a Hi-K gate insulating film (a hafnium oxide film and a titanium nitride layer laminated thereon) is interposed between the gate wiring layer R_G and the P-type well region RP_W. That is, in the active region ACT, a Hi-K gate insulating film is laminated on the P-type well region RP_W, and the gate wiring layer R_G is further laminated thereon.

[0052] The Hi-K gate insulating film (second insulating film) in the reference resistor R_CL is the same as the gate insulating film (first insulating film) of the transfer FET PG2, but the area of ​​the second insulating film is larger than that of the first insulating film when viewed in a plan view. In other words, the area of ​​the semiconductor region covered by the second insulating film in the second semiconductor region RP_W is larger than the area of ​​the semiconductor region covered by the first insulating film in the first semiconductor region P_W when viewed in a plan view.

[0053] The resistance between the P-type well region RP_W and the gate wiring layer R_G becomes the reference resistance R_CL. When viewed in plan view, the area of the gate wiring layer R_G of the reference resistance R_CL is larger than the gate electrode of the transfer FET PG2 formed by the gate wiring layer GL_R, and since the source region and the drain region are not formed, the occurrence of Hi-K disappearance can be prevented. Since Hi-K disappearance does not occur, the reference resistance R_CL has a stable resistance value that does not depend on Hi-K disappearance. The electrode (terminal) RG_C connected to the gate wiring layer (second electrode) R_G becomes one terminal of the reference resistance R_CL, and the P + type semiconductor region (active region) ACT_V formed in the P-type well region RP_W is connected to the electrode (terminal) RPW_C, which becomes the other terminal of the reference resistance R_CL.

[0054] Although it will be described later with reference to FIG. 9, as shown in FIG. 8, in the P-type well region P_W constituting the test pattern T_CL, P + type active regions ACT_V are formed and are connected to the gate wiring layer R_G by the electrode PW_C shown in FIG. 6. Also, the gate electrode of the transfer FET PG2 is connected to the ground voltage GND by the electrode G_C. Further, in the P-type well region RP_W forming the reference resistance R_CL, P + type active regions ACT_V are formed and are connected to the power supply voltage Vdd by the electrode RPW_C. As a result, the potential of the gate wiring layer R_G of the reference resistance R_CL and the gate electrode of the transfer FET PG2 are made lower than the potentials of the P-type well regions RP_W and P_W. As a result, the P-type well regions RP_W and P_W and the bottom N-type well BN_W and the isolation N-type well region IN_W are in a reverse bias state, and the flow of a forward current is prevented.

[0055] <TEG circuit> FIG. 9 is a diagram for explaining the TEG circuit according to Embodiment 1. Here, FIG. 9(A) is a circuit diagram showing the configuration of the unit circuit included in the TEG circuit TG. Also, FIG. 9(B) is a waveform diagram showing the operation of the unit circuit.

[0056] In the first embodiment, one unit circuit unit is configured by the test pattern T_CL shown in FIGS. 7 and 8, the reference resistor R_CL, and the logic circuit LG shown in FIG.

[0057] In the unit circuit unit, a reference resistor R_CL and a gate leak resistor GR are connected in series between a power supply voltage Vdd and a ground voltage GND. Specifically, a single gate leak resistor (single gate leak resistor) is formed between an electrode PW_C connected to a P-type well region P_W and an electrode G_C connected to a gate wiring layer of a transfer FET (e.g., PG2) shown in Fig. 7 and Fig. 8, and the single gate leak resistors in a plurality of test patterns T_CL are connected in parallel and used as the gate leak resistor GR.

[0058] That is, the electrodes G_C of the gate wiring layer of the transfer FET PG2 in the multiple test patterns T_CL are connected to each other, and the resistance between the electrode G_C and the electrode PW_C of the P-type well region P_W is set as the gate leakage resistance GR. Of course, the electrode G_C of the gate wiring layer of the transfer FET PG1 may also be connected to the electrode G_C of the gate wiring layer of the transfer FET PG2. As a result, the individual gate leakage resistances between the electrode G_C of the gate wiring layer of the transfer FET PG1 and the P-type well region P_W are also connected in parallel.

[0059] An electrode G_C of the gate leakage resistance GR is connected to the ground voltage GND, an electrode PW_C is connected to an electrode RG_C of the reference resistance R_CL, and an electrode RPW_C of the reference resistance R_CL is connected to the power supply voltage Vdd.

[0060] A connection node Cnc between the electrodes PW_C and RG_C is connected to the input of an inverter IV1, and the output of the inverter IV1 becomes the unit output Vunit. Although not particularly limited, the inverter IV corresponds to the logic circuit LG shown in Fig. 3, and the unit output Vunit is supplied to the pad PAD shown in Fig. 3. In Fig. 9, the logic circuit LG is regarded as the first logic circuit.

[0061] In FIG. 9B, the horizontal axis indicates the resistance value of the gate leakage resistor GR, and the vertical axis indicates the voltage. Here, the power supply voltage Vdd is 1 (V), and the resistance value of the reference resistor R_CL is 100 (MΩ). The gate leakage resistor GR is composed of 100 individual gate leakage resistors connected in parallel, and its resistance value is 1 (GΩ) when Hi-K loss has not occurred, as will be described later. In contrast, when Hi-K loss occurs, the resistance value of the gate leakage resistor GR changes from 1 (GΩ) to 10 (MΩ).

[0062] As shown in FIG. 9B, when Hi-K disappearance does not occur, the intermediate potential Vnc at the connection node Cnc rises, and when Hi-K disappearance occurs, the intermediate potential Vnc drops toward 0 (V). When the intermediate potential Vnc exceeds the logical value of the inverter IV1 (about 0.4 (V)), the unit output Vunit changes from 1 (V) to almost 0 (V), and when it falls below the logical value (about 0.4 (V)), the unit output Vunit changes from almost 0 (V) to 1 (V). That is, when Hi-K disappearance occurs, the logical value of the output from the unit circuit unit changes from "0" to "1". In the WAT process S2 (FIG. 2), by measuring the potential of the pad PAD of the TEG circuit, it is possible to easily determine whether Hi-K disappearance has occurred in the determination process S3 (FIG. 2).

[0063] In the first embodiment, the transfer FETs (PG1, PG2) are used to measure the gate leakage current flowing between the gate electrode and the P-type well region P_W. Therefore, it is possible to detect in the WAT process whether or not Hi-K loss has occurred in the driver FETPD using the P-type well region P_W. In addition, for the load FETPU whose gate leakage current is not measured, for example, by connecting the cross-connection wiring (CR_C) shown in FIG. 6 in the test pattern T_CL as well, when an abnormality occurs in the gate leakage current in the load FETPU, the gate leakage current of the cross-connected driver FET also becomes abnormal, so that the abnormality can be detected.

[0064] Here, an example has been described in which the resistance value of the reference resistor R_CL is set to one-tenth the value of the gate leakage resistance GR when Hi-K loss does not occur, but the resistance value of the reference resistor R_CL is not limited to this.

[0065] <Variation 1> Fig. 10 is a diagram for explaining a TEG circuit according to Modification 1 of Embodiment 1. Here, Fig. 10(A) is a block diagram showing the configuration of the TEG circuit TG, and Fig. 10(B) is a logic value table showing the operation of Fig. 10(A).

[0066] The TEG circuit TG according to the first modification includes two unit circuits (unit_1, unit_2) shown in Fig. 9A. The logic circuit LG includes a NOR circuit NR1 to which the outputs from the unit circuits unit_1 and unit_2 are input, and an inverter IV2 to which the output of the NOR circuit NR1 is supplied. The output of the inverter IV2 is supplied to the pad PAD (Fig. 3).

[0067] As shown in FIG. 10(B), when at least one of the unit circuits unit_1 and unit_2 outputs a logical value of “1” indicating Hi-K loss, the output of the NOR circuit NR1 becomes “0”, and the output of the inverter IV2 becomes a logical value of “1” indicating the occurrence of Hi-K loss.

[0068] <Variation 2> 11 is a block diagram showing a configuration of a TEG circuit according to Modification 2 of Embodiment 1. In Modification 2, an example in which the number of unit circuits is further increased will be described.

[0069] In the modified example 2, unit circuits unit_3 and unit_4, NOR circuits NR2 and NR3, and inverters IV3 and IV4 are further added to the modified example 1. When at least one of the unit circuits unit_1 to unit_4 outputs a logical value "1" indicating the occurrence of Hi-K disappearance, at least one of the NOR circuits NR1 and NR2 outputs a logical value "0", and at least one of the inverters IV2 and IV3 outputs a logical value "1". As a result, the output of the NOR circuit NR3 becomes a logical value "0", and the inverter IV4 outputs a logical value "1" indicating the occurrence of Hi-K disappearance to the pad PAD (FIG. 3).

[0070] FIG. 11 shows an example in which a NOR circuit and an inverter are provided for two unit circuits, but the present invention is not limited to this. For example, a NOR circuit and an inverter may be provided for three or more unit circuits. Explaining based on FIG. 11, the NOR circuits NR1 and NR2 and the inverters IV2 and IV3 are removed, and the NOR circuit NR3 has four inputs. The outputs of the unit circuits unit_1 to unit_4 are supplied to the NOR circuit NR3. By providing the NOR circuit 3 with four inputs, the number of NOR circuits and inverters can be reduced.

[0071] In the first and second modifications, a logic circuit configured with an inverter, a NOR circuit, and the like to which a signal from the unit circuit "unit" is supplied is regarded as a second logic circuit.

[0072] According to the first and second modifications, it becomes possible to detect the occurrence of Hi-K vanishing using a larger number of gate leakage resistors, thereby improving the detection accuracy.

[0073] 7 and 8, the conductivity type of the well region constituting the reference resistor R_CL is the same as that of the well region for measuring the gate leakage current, but it may be the opposite conductivity type (N type). In this case, the unit circuit unit is composed of the reference resistor formed in the N-type well region and the gate leakage resistor GR formed in the P-type well region.

[0074] Also, the reference resistor R_CL may use the gate electrode of the FET and a well region in which the source region and drain region of the FET are formed. In this case, the source region and drain region may be fixed to a predetermined voltage.

[0075] FIG. 12 is a diagram for explaining the gate leakage current and the gate leakage resistance according to the first embodiment. In FIG.

[0076] In a normal state where no Hi-K loss has occurred, the gate leakage current of one FET (1Tr) is 1e -11 (A), and the resistance of a single gate leakage resistor at that time is about 100 (GΩ). In contrast, when Hi-K disappearance occurs, the gate leakage current of one FET (1Tr) is about 1e -7 (A), and the resistance value of the single gate leakage resistor at this time is about 10 (MΩ). As described above, by connecting unit gate leakage resistors (unit measurement resistors) in parallel, the resistance value of the gate leakage resistor GR can be changed as shown in Fig. 12, and the number of unit gate leakage resistors connected in parallel can be set so as to obtain an appropriate sensitivity in the WAT process.

[0077] Increasing the number of unit gate leakage resistors connected in parallel will increase the current flowing in the TEG circuit, but this does not pose a problem because the gate leakage current in the normal case when no Hi-K occurs is small.

[0078] <Use of LG logic circuit> As shown in Fig. 12, the gate leakage current varies by four orders of magnitude (1e -7 (A) and 1e -11 (A)) They are different. In order to detect whether Hi-K loss occurs during the WAT process, this four-digit difference must be measured.

[0079] FIG. 13 is a diagram for explaining the effect of the first embodiment.

[0080] In order to measure a four-digit current difference, for example, a configuration as shown in FIG. 13(A) can be considered. That is, a gate leakage resistance GR and pads PAD_T1 and PAD_T2 connected to both ends of the resistance are regarded as one unit, and a plurality of TEG circuits TG (five in FIG. 13(A)) are provided. Here, the gate leakage resistance GR is assumed to be, for example, 100 unit gate leakage resistances connected in parallel. It is possible to measure a four-digit current difference by measuring the current flowing between pads PAD_T1 and PAD_T2. However, even if ten pads PAD_T1 and PAD_T2 are provided in the TEG circuit TG, the number of unit gate leakage resistances that can be measured is about 500 (100×5).

[0081] In contrast, according to the first embodiment, it is possible to configure as shown in Fig. 13(B) In Fig. 13(B), PAD_V indicates a power supply pad to which a power supply voltage Vdd is supplied, PAD_G indicates a ground pad to which a ground voltage GND is supplied, and PAD_O indicates an output pad to which an output of a unit circuit unit is supplied.

[0082] In the example shown in FIG. 13(B), the unit circuit unit includes 20 gate leakage resistors GR, each of which includes 100 unit gate leakage resistors connected in parallel. The unit circuit unit also includes a reference resistor R_CL (FIG. 9) and a logic circuit LG, not shown. The gate leakage resistor GR and the reference resistor R_CL are connected between a power supply pad PAD_V and a ground pad PAD_G, and the output of the logic circuit LG, which changes according to the value of the gate leakage resistor GR, is supplied to an output pad PAD_O. When 10 pads are provided in the TEG circuit TG as in FIG. 13(A), according to the first embodiment, as can be seen from FIG. 13(B), 18,000 (20×9×100) gate leakage resistors GR can be provided in the TEG circuit TG. If an abnormal gate leakage current flows in any of the 18,000 gate leakage resistors, the voltage of the output pad PAD_O changes, and the abnormality can be detected.

[0083] That is, according to the first embodiment, it is possible to improve the detection accuracy while suppressing an increase in the area occupied by the TEG circuit TG.

[0084] Furthermore, in the first embodiment, the gate leakage current is converted into a digital logical value by the logic circuit LG, so that the disappearance of Hi-K can be easily detected in the WAT step S2 and the determination step S3.

[0085] When the gate electrodes of the load FET PU1 (PU2) and the driver FET PD1 (PD2) are connected to the drain regions of the load FET PU2 (PU1) and the driver FET PD2 (PD1) by cross-connection, and the driver FET and / or the load FET are used as gate leakage resistors, it is necessary to take into account the leakage current flowing from the drain region to which the gate electrodes are connected.

[0086] Although an example has been described in which the test pattern T_CL uses a configuration similar to that of the memory cell S_CL, a test pattern with a circuit configuration different from that of the memory cell S_CL (for example, a logic circuit or a FET with a small ratio of the length and width of the gate electrode and connected in parallel) may be used. However, by using a test pattern T_CL similar to that of the memory cell S_CL, it is possible to more accurately detect the Hi-K loss that occurs in the memory cell S_CL.

[0087] In addition, the Hi-K gate insulating film of the reference resistor R_CL is the same as that of the memory cell S_CL and the test pattern T_CL, and is manufactured in the same process. If the thickness of the Hi-K gate insulating film of the memory cell S_CL and the test pattern T_CL fluctuates due to process fluctuations in the manufacturing process, the Hi-K gate insulating film of the reference resistor R_CL will also fluctuate in the same way, and the ratio between the reference resistor R_CL and the gate leakage resistance can be maintained.

[0088] (Embodiment 2) In Embodiment 2 and Embodiment 3 described below, the probability of Hi-K disappearance in the test pattern T_CL is made higher than that in the memory cell S_CL. The gate leakage resistance of the test pattern with the increased probability of Hi-K disappearance is used as the single gate leakage resistance described with reference to FIG. 9. By increasing the probability of Hi-K disappearance in the test pattern T_CL, for example, when there are process variations, the sensitivity for detecting the occurrence of Hi-K disappearance can be increased.

[0089] <Cause of Hi-K disappearance> First, the cause of Hi-K disappearance found by the present inventors will be described with reference to the drawings. Here, two causes will be described. FIGS. 14 and 15 are diagrams for explaining the manufacture of the semiconductor device according to Embodiment 2 and Embodiment 3.

[0090] <<STI - Seam>> FIG. 14 is a schematic perspective view showing a part of the semiconductor device according to Embodiment 2. FIG. 14 is similar to FIG. 5. First, an outline of the manufacturing method of the driver FET PD1 and the load FET PU1 (FIG. 5) will be described.

[0091] A P-type semiconductor region 10, an N-type semiconductor region 11, and an element isolation region I_ST are formed, and on top of them, a hafnium oxide film 12 and a titanium nitride layer 13 are formed. On the hafnium oxide film 12 and the titanium nitride layer 13, a polysilicon layer Pys is formed, and using this polysilicon layer Pys as a mask, impurity implantation (hereinafter referred to as SD implantation) for forming source and drain regions is performed. Thereafter, the polysilicon layer Pys is removed, and a gate wiring layer that becomes a gate electrode is formed.

[0092] When the element isolation region I_ST is formed, a gap (seam) SM as shown in Fig. 14 occurs. In the element isolation region I_ST existing between the N-type semiconductor region 11 and the P-type semiconductor region 10, if a seam SM as shown in Fig. 14 occurs adjacent to the hafnium oxide film 12 and the titanium nitride layer 13, a processing liquid such as hydrofluoric acid used in a later process dissolves the hafnium oxide film 12 in the seam SM portion, and dissolves the hafnium oxide film 12 and titanium nitride layer 13 under the gate electrode connected thereto, causing Hi-K loss.

[0093] <<Side Wall>> 15, SD implantation is performed by implanting impurities into the P-type semiconductor region 10 using the polysilicon layer Pys corresponding to the gate electrode and the sidewall SW (silicon nitride layer or the like) as a mask. The silicon nitride layer of the sidewall SW is oxidized by ashing during SD implantation, and this oxidized portion melts and becomes thinner in a wet process performed later. Therefore, as the number of SD implantations increases, the sidewall SW becomes thinner.

[0094] When the sidewall SW becomes thinner, the distance between the outside of the sidewall SW and the hafnium oxide film 12 and titanium nitride layer 13 under the gate electrode becomes shorter, and if there is a seam SM as shown in Fig. 14, hydrofluoric acid or the like is likely to penetrate through the seam SM. In addition to the seam SM, penetration is also likely to occur due to other causes (for example, defects in the sidewall SW). As a result, the hafnium oxide film 12 and titanium nitride layer 13 under the polysilicon layer Pys are lost due to the permeated solvent, resulting in Hi-K loss.

[0095] In the second embodiment,<STI-シーム> > is utilized. That is, in the second embodiment, the active space in the test pattern T_CL is made narrower than that of the memory cell S_CL. Referring to FIG. 14, in FIG. 14, a space equivalent to the width of the element isolation region I_ST that separates the semiconductor regions is shown as the active space AcD. By narrowing the active space AcD, a seam SM that causes the hafnium oxide film 12 and the titanium nitride layer 13 under the gate electrode to disappear is easily formed. As a result, the occurrence probability of Hi-K disappearance can be increased in the test pattern T_CL, and the detection sensitivity of Hi-K disappearance can be increased.

[0096] (Embodiment 3) In the third embodiment, the cause of the <<sidewall>> is utilized. That is, in the test pattern T_CL, the number of SD injections is increased compared to the memory cell S_CL. Figure 16 is a diagram for explaining the manufacturing method of the semiconductor device according to the third embodiment.

[0097] In Fig. 16, the injection process indicates a process of performing SD injection in the manufacturing process. Logic_P+SD indicates a process of performing SD injection into the source and drain regions of the P-channel FET in the circuit block PR (Fig. 3) and the SRAM circuit MM_S (Fig. 3), and Logic_N+SD indicates a process of performing SD injection into the source and drain regions of the N-channel FET. Also, MONOS_N+SD indicates a process of performing SD injection into the source and drain regions of the N-channel MONOS transistor.

[0098] For example, in the first embodiment, in the Logic_P+SD process, SD injection is performed on the source and drain regions of the load FETPU (PU1, PU2: FIG. 4) of the test pattern T_CL (FIG. 6), and in the Logic_N+SD process, SD injection is performed on the source and drain regions of the driver FETPD and transfer FETPG of the test pattern T_CL. At this time, in the MONOS_N+SD process, SD injection is not performed on the FETs of the test pattern T_CL. That is, one SD injection is performed on each of the load FETPU, driver FETPD, and transfer FETPG of the test pattern T_CL.

[0099] In contrast to this, in the third embodiment, the number of times SD is injected into the FETs that configure the test pattern T_CL is increased. Two examples of increasing the number of times SD is injected are shown in FIG.

[0100] In the first example (embodiment 3-a), SD injection is also performed in the MONOS_N+SD process on the source and drain regions of the driver FETPD and the transfer FETPG in the test pattern T_CL. That is, SD injection is performed twice on the driver FETPD and the transfer FETPG in the test pattern T_CL.

[0101] In the second example (embodiment 3-b), SD injection is performed on the load FETPU, driver FETPD, and transfer FETPG of the test pattern T_CL in the Logic_P+SD process, the Logic_N+SD process, and the MONOS_N+SD process. At this time, impurities suitable for the channel type are injected into the source region and the drain region. In the second example, three SD injections are performed on the load FETPU, driver FETPD, and transfer FETPG of the test pattern T_CL.

[0102] That is, in the third embodiment, the number of times impurities are injected into the source region and / or drain region of the FET formed in the test pattern T_CL is made greater than the number of times impurities are injected into the source region and / or drain region of the FET formed in the semiconductor chip CHP.

[0103] In the test pattern T_CL, by increasing the number of SD injections, over-etching can be caused, the occurrence probability of Hi-K vanishing can be increased, and the detection sensitivity of Hi-K vanishing can be increased.

[0104] Since the detection sensitivity of Hi-K loss can be increased, it is possible to extract semiconductor wafers with minor Hi-K loss that cannot be detected by normal testing. There is concern that semiconductor wafers with minor Hi-K loss may malfunction after being delivered to customers as semiconductor chips. Since semiconductor wafers with minor Hi-K loss can be easily detected in the WAT process, it is possible to prevent semiconductor chips that will become defective at the customer's site from being shipped.

[0105] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the spirit of the present invention. For example, in the first to third embodiments, a configuration is described in which the gate leakage current of a FET having a Hi-K gate insulating film is measured to detect the occurrence of Hi-K disappearance, but the FET for measuring the gate leakage current is not limited to this. The gate leakage current of a FET using a silicon oxide (SiO2) film or a silicon oxynitride (SiON) film as the gate insulating film may be measured. [Explanation of symbols]

[0106] 10 P-type semiconductor region 11 N-type semiconductor region 12 Hafnium oxide film 13 Titanium nitride layer 14, 15 Metal CHP, CHP_1 to CHP_4 Semiconductor chips Cnc Connection Node GR Gate leakage resistance I_ST Element isolation area N_W N-type well region PG transfer FET PD drive FET PU load FET P_W, RP_W P-type well region R_CL Reference resistance S_CL memory cell TG TEG circuit T_CL Test Pattern Vnc intermediate potential Vunit Unit output unit, unit_1~unit_4 unit circuit

Claims

1. forming a test pattern including a reference resistor and a measurement resistor connected in series with the reference resistor and through which a leakage current flows; a measurement step of measuring a change in voltage at a connection node between the reference resistor and the measurement resistor caused by the flow of the leakage current; Equipped with the measurement resistor is a resistor having terminals including a first electrode disposed on a first semiconductor region via a first insulating film and the first semiconductor region; the reference resistor is a resistor having a terminal including a second electrode disposed on a second semiconductor region via a second insulating film and the second semiconductor region; In a plan view, a region of the second semiconductor region covered by the second insulating film is larger than a region of the first semiconductor region covered by the first insulating film, and the second electrode is larger than the first electrode; the first electrode is a gate electrode of a transistor; the first insulating film and the second insulating film contain a material having a higher dielectric constant than a silicon nitride film; The method for manufacturing a semiconductor device, wherein the transistor is a transistor that constitutes a static memory cell provided in the test pattern.

2. 2. The method of manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein an active space between static memory cells in the test pattern is narrower than an active space between static memory cells arranged on a semiconductor chip.

3. 2. The method of manufacturing a semiconductor device according to claim 1, the number of times that impurities are injected into the source region or drain region of the transistor is greater than the number of times that impurities are injected into the source region or drain region of a transistor arranged outside the test pattern.

4. A semiconductor wafer having a plurality of semiconductor chips arranged thereon, the semiconductor wafer includes a test pattern including a reference resistor and a measurement resistor connected in series with the reference resistor and through which a leakage current flows; the test pattern is disposed on a scribe line along which the semiconductor chips are cut out from the semiconductor wafer; A voltage at a connection node between the reference resistor and the measurement resistor is measured.

5. 5. The semiconductor wafer according to claim 4, the measurement resistor is configured by a first semiconductor region and a first electrode disposed on the first semiconductor region via an insulating layer including a material having a higher dielectric constant than a silicon nitride film; The reference resistor is composed of a second semiconductor region and a second electrode disposed on the second semiconductor region via an insulating layer including a material having a higher dielectric constant than a silicon nitride film.

6. 5. The semiconductor wafer according to claim 4, After the voltage at the connection node is measured, the plurality of semiconductor chips are cut from the semiconductor wafer.

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