Display with silicon thin film transistors and semiconductor oxide thin film transistors

Abstract

To provide a display having a silicon thin film transistor and a semiconductor oxide thin film transistor.SOLUTION: An electronic device may include a display having an array of display pixels on a substrate. These display pixels may be an organic light-emitting diode display pixel, or a display pixel in a liquid crystal display. In the organic light-emitting diode display, a hybrid thin film transistor structure, including a semiconductor oxide thin film transistor, a silicon thin film transistor and a capacitor structure, may be formed. The capacitor structure may be superposed on the semiconductor oxide thin film transistor. The organic light-emitting diode display pixel may have a combination of the oxide transistor and the silicon transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This application relates generally to electronic devices, and more particularly to electronic devices with displays having thin film transistors. [Background technology]

[0002] Electronic devices often include a display. For example, cellular telephones and portable computers include displays for presenting information to a user.

[0003] Displays such as liquid crystal displays are formed from a number of layers. A liquid crystal display may have, for example, upper and lower polarizer layers, a color filter layer including an array of color filter elements, a thin film transistor layer including thin film transistors and display pixel electrodes, and a layer of liquid crystal material interposed between the color filter layer and the thin film transistor layer. Each display pixel typically includes a thin film transistor for controlling the application of signals to the display pixel electrode structure within that display pixel.

[0004] Displays such as organic light emitting diode displays have an array of light emitting diode based display pixels. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of a signal to the light emitting diode.

[0005] Thin film display drive circuitry is often included within the display, for example the gate drive circuitry and demultiplexer circuitry on the display can be formed from thin film transistors. Summary of the Invention [Problem to be solved by the invention]

[0006] If care is not taken, thin film transistor circuitry within the display pixels and display drive circuitry of a display can exhibit non-uniformity, excessive leakage current, insufficient drive strength, poor area efficiency, hysteresis, and other problems. It would therefore be desirable to be able to provide improved displays for electronic devices. [Means for solving the problem]

[0007] The electronic device may be provided with a display, which may comprise an array of display pixels on a substrate, which may be organic light emitting diode display pixels or display pixels in a liquid crystal display.

[0008] A hybrid thin film transistor structure can be formed within an organic light emitting diode display, including a semiconductor oxide thin film transistor, a silicon thin film transistor, and a capacitor structure. The capacitor structure can be overlaid on the semiconductor oxide thin film transistor. The capacitor structure can also be formed and used from multiple overlapping electrode layers formed from a source-drain metal layer, a polysilicon layer, and a gate metal layer.

[0009] An organic light emitting diode display pixel may have a combination of oxide and silicon transistors: the transistors, such as the drive transistor coupled to the light emitting diode, may be formed from an oxide transistor structure, and the switching transistor may be formed from a silicon transistor structure.

[0010] In a liquid crystal display, the display driver circuitry may include silicon thin film transistor circuitry and the display pixels may be based on oxide thin film transistors. A single layer or two different layers of gate metal may be used in forming the silicon transistor gates and the oxide transistor gates. The silicon transistors may have gates that overlap a floating gate structure. The oxide transistors may be incorporated into the display driver circuitry.

[0011] The display driver circuitry can be configured to expose the silicon transistor circuitry to lower voltage swings than the oxide transistor circuitry in the array of display pixels. [Brief description of the drawings]

[0012] [Figure 1] 1 is a diagram of an exemplary display, such as an organic light emitting diode display having an array of organic light emitting diode display pixels, or a liquid crystal display having an array of display pixels, according to one embodiment. [Diagram 2] 1 is a diagram of an exemplary organic light emitting diode display pixel of a type that may be used in an organic light emitting diode having a semiconductor oxide thin film transistor and a silicon thin film transistor according to one embodiment. [Diagram 3] FIG. 2 is a cross-sectional side view of an illustrative thin film transistor structure according to an embodiment. [Figure 4] FIG. 2 is a side view of a further exemplary thin film transistor structure according to an embodiment. [Diagram 5] 1 is a diagram of an illustrative organic light emitting diode display pixel of a type that may include oxide thin film transistors and silicon thin film transistors according to one embodiment. [Figure 6] 1 is a cross-sectional side view of exemplary thin film transistor circuitry in a liquid crystal display according to one embodiment. [Figure 7] 1 is a cross-sectional side view of exemplary thin film transistor circuitry in a liquid crystal display according to one embodiment. [Figure 8] 1 is a cross-sectional side view of exemplary thin film transistor circuitry in a liquid crystal display according to one embodiment. [Figure 9] FIG. 2 is a diagram of an exemplary complementary metal oxide semiconductor transistor inverter of a type that can be formed from a hybrid silicon-oxide transistor structure according to one embodiment. [Figure 10] FIG. 2 is a cross-sectional side view of an exemplary thin film transistor structure of a type that may be used to form a hybrid complementary metal oxide semiconductor transistor inverter according to one embodiment. [Figure 11] FIG. 2 is a circuit diagram of gate drive circuitry within a thin-film display drive circuitry according to one embodiment. [Figure 12] 12 is a diagram of a level shifter of a type that can be used in the gate drive circuitry of FIG. 11 within the display drive circuitry on a display according to one embodiment. [Figure 13] FIG. 2 is a schematic diagram of an exemplary circuit that may be used to prevent transistors within display driver circuitry on a display from experiencing excessive voltage, according to one embodiment. [Figure 14] 1 is a cross-sectional side view of exemplary thin film transistor circuitry in a liquid crystal display according to one embodiment. [Figure 15] FIG. 2 is a cross-sectional side view of an exemplary thin film transistor circuitry including a top-gate semiconductor oxide transistor in a liquid crystal display according to one embodiment. [Figure 16] FIG. 2 is a cross-sectional side view of an exemplary thin film transistor circuitry including a top-gate semiconductor oxide transistor with a light shield in a liquid crystal display according to one embodiment. [Figure 17] FIG. 2 is a cross-sectional side view of an exemplary thin film transistor circuitry including a top-gate semiconductor oxide transistor in a liquid crystal display according to one embodiment. [Figure 18]FIG. 2 is a cross-sectional side view of an exemplary thin film transistor circuitry including a top-gate semiconductor oxide transistor in an organic light emitting diode display according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] A display in an electronic device may be provided with drive circuitry for displaying images on an array of display pixels. An exemplary display is shown in FIG. 1. As shown in FIG. 1, the display 14 may have one or more layers, such as a substrate 24. A layer, such as the substrate 24, may be formed from a flat rectangular layer of material, such as a flat layer of glass. The display 14 may have an array of display pixels 22 for displaying images to a user. The array of display pixels 22 may be formed from rows and columns of display pixel structures on the substrate 24. There may be any suitable number of rows and columns in the array of display pixels 22 (e.g., 10 or more, 100 or more, or 1000 or more).

[0014] Display driver circuitry, such as a display driver integrated circuit 16, may be coupled to conductive paths, such as metal traces, on the substrate 24 using solder or conductive adhesive. The display driver integrated circuit 16 (sometimes referred to as a timing controller chip) may include communication circuitry for communicating with system control circuitry via paths 25. The paths 25 may be formed from traces on a flexible printed circuit or other cable. The control circuitry may be located on a main logic board within an electronic device in which the display 14 is used, such as a cellular phone, computer, set-top box, media player, portable electronic device, or other electronic device. During operation, the control circuitry may provide information to the display driver integrated circuit 16 about an image to be displayed on the display 14. To display an image on the display pixels 22, the display driver integrated circuit 16 may provide corresponding image data to the data lines D while issuing clock and other control signals to supporting thin film transistor display driver circuitry, such as gate driver circuitry 18 and demultiplexing circuitry 20.

[0015] The gate drive circuitry 18 may be formed on a substrate 24 (e.g., on the right and left edges of the display 14, on only a single edge of the display 14, or elsewhere within the display 14). Using demultiplexer circuitry 20, data signals from the display driver integrated circuits 16 may be distributed onto a number of corresponding data lines D. In this exemplary arrangement of FIG. 1, the data lines D extend vertically through the display 14. Each data line D is associated with a corresponding column of display pixels 22. Gate lines G extend horizontally through the display 14. Each gate line G is associated with a corresponding row of display pixels 22. The gate drive circuitry 18 may be located on the left side of the display 14, on the right side of the display 14, or on both the right and left sides of the display 14 as shown in FIG. 1.

[0016] The gate drive circuitry 18 may assert gate signals (sometimes referred to as scan signals) on gate lines G in the display 14. For example, the gate drive circuitry 18 may receive clock and other control signals from the display driver integrated circuit 16 and, in response to those received signals, may assert gate signals on gate lines G in sequence, starting with gate line signal G in a first row of display pixels 22. As each gate line is asserted, the corresponding display pixel in the row whose gate line is asserted displays display data appearing on data lines D.

[0017] Display driver circuitry, such as demultiplexer circuitry 20 and gate line driver circuitry 18, may be formed from thin film transistors on a substrate 24. Thin film transistors may also be used in forming circuitry within display pixels 22. To improve display performance, thin film transistor structures within display 14 that meet desired criteria, such as leakage current, switching speed, drive strength, uniformity, etc., may be used. The thin film transistors within display 14 may generally be formed using any suitable type of thin film transistor technology (e.g., silicon-based, semiconductor oxide-based, etc.).

[0018] In one suitable arrangement, which may be described by way of example herein, the channel regions (active areas) in some thin film transistors on display 14 are formed from silicon (e.g., silicon such as polysilicon deposited using a low temperature process, which may be referred to as LTPS or low temperature polysilicon), and the channel regions in other thin film transistors on display 14 are formed from a semiconductor oxide material (e.g., amorphous indium gallium zinc oxide, which may be referred to as IGZO). If desired, other types of semiconductors, such as amorphous silicon, semiconductor oxides other than IGZO, may be used in forming these thin film transistors. In this type of hybrid display configuration, silicon transistors (e.g., LTPS transistors) can be used where attributes such as switching speed and good drive current are desired (e.g., for gate drivers in a liquid crystal diode display, or within the portion of an organic light emitting diode display pixel where switching speed is a consideration), while oxide transistors (e.g., IGZO transistors) can be used where low leakage current is desired (e.g., within the liquid crystal diode display pixel and display drive circuitry) or where high pixel-to-pixel uniformity is desired (e.g., within an array of organic light emitting diode display pixels). Other considerations (e.g., related to power consumption, resource consumption, hysteresis, etc.) can also be taken into account.

[0019] Oxide transistors, such as IGZO thin film transistors, are typically n-channel devices (i.e., NMOS transistors). Silicon transistors can be fabricated using p-channel or n-channel designs (i.e., LTPS devices can be either PMOS or NMOS). A combination of these thin film transistor structures can provide optimal performance.

[0020] In an organic light emitting diode display, each display pixel includes a corresponding organic light emitting diode. A schematic diagram of an exemplary organic light emitting diode display pixel 22-1 is shown in FIG. 2. As shown in FIG. 2, display pixel 22-1 may include a light emitting diode 26. A positive power supply voltage ELVDD may be provided at a positive power supply terminal 34, and a ground power supply voltage ELVSS may be provided at a ground power supply terminal 36. The state of drive transistor 28 controls the amount of current that flows through diode 26, and therefore the amount of emitted light 40 from display pixel 22-1.

[0021] To ensure that the transistor 28 is held in a desired state between successive frames of data, the display pixel 22-1 may include a storage capacitor, such as a storage capacitor Cst. The voltage on the storage capacitor Cst is applied to the gate of the transistor 28 at node A to control the transistor 28. One or more switching transistors, such as a switching transistor 30, may be used to load data into the storage capacitor Cst. When the switching transistor 30 is off, the data line D is isolated from the storage capacitor Cst and the gate voltage on terminal A is equal to the data value stored in the storage capacitor Cst (i.e., the data value from the previous frame of display data is displayed on the display 14). When a gate line G (sometimes referred to as a scan line) in the row associated with the display pixel 22-1 is asserted, the switching transistor 30 is turned on and a new data signal on the data line D is loaded into the storage capacitor Cst. This new signal on the capacitor Cst is applied to the gate of the transistor 28 at node A to adjust the state of the transistor 28 and the corresponding amount of light 40 emitted by the light emitting diode 26.

[0022] An organic light emitting diode display pixel, such as pixel 22-1 of FIG. 2, can use a thin film transistor structure of the type shown in FIG. 3. In this type of structure, two different types of semiconductors are used. As shown in FIG. 3, circuitry 72 can include a display pixel structure, such as a light emitting diode cathode terminal 42 and a light emitting diode anode terminal 44. An organic light emitting diode emissive material 47 can be interposed between the cathode 42 and the anode 44. A dielectric layer 46 can help define the layout of the display pixel and is sometimes referred to as a pixel defining layer. A planarization layer 50 can be formed on top of the thin film transistor structure 52. The thin film transistor structure 52 can be formed on a buffer layer 54 on the substrate 24.

[0023] The thin film transistor structure 52 may include a silicon transistor 58. The transistor 58 may be an LTPS transistor formed using a "top gate" design and may function as a switching transistor in an organic light emitting diode display pixel (see, for example, transistor 30 in pixel 22-1 of FIG. 2). The transistor 58 may have a polysilicon channel 62 covered by a gate insulation layer 64 (e.g., a layer of silicon oxide). The gate 66 may be formed from a patterned metal (e.g., molybdenum, as an example). The gate 66 may be covered by a layer of interlevel dielectric (e.g., a silicon nitride layer 68 and a silicon oxide layer 70). Source-drain contacts 74 and 76 may contact opposing sides of the polysilicon layer 62 to form the silicon thin film transistor 58.

[0024] The thin film transistor structure 52 may also include a thin film transistor and capacitor structure 60. The structure 60 may include a storage capacitor (i.e., storage capacitor Cst in FIG. 2) and an oxide thin film transistor structure. The storage capacitor may have a first terminal (sometimes referred to as a plate, electrode, or electrode layer) formed from a polysilicon layer 62' (patterned as part of the same layer as layer 62). The terminal 62' may be covered by a gate insulating layer 64', which may be an extension of the gate insulating layer 64. The capacitor may have a second terminal formed from a metal layer 66'. The metal layer 66' may be patterned from the same metal layer used to form the gate 66 of the transistor 58. The metal layer 66' may be covered by a dielectric layer 68 and a dielectric layer 70. The thin film transistor in the structure 60 may be a "bottom gate" oxide transistor. The layer 66', which serves as the second terminal of the capacitor Cst (i.e., node A in FIG. 2), may also serve as the gate of the oxide transistor. This oxide transistor may function as the drive transistor 28 of FIG. 2. The "gate insulator" of this oxide transistor may be formed from a layer of interlevel dielectric (i.e., layers 68 and 70). The channel semiconductor of this oxide transistor may be formed from an oxide layer 80 (e.g., IGZO). Space can be saved by overlaying the oxide layer 80 on a polysilicon capacitor electrode layer 62' (i.e., overlaying the oxide transistor on the capacitor). Source-drain terminals 82 and 84 may be formed from metal contacting opposite ends of the semiconducting oxide layer 80.

[0025] Transistors such as LTPS transistors and oxide transistors can be formed in a variety of layouts. For example, LTPS transistors tend to have high carrier mobility. As a result, LTPS transistors may have a relatively long gate length L and a relatively short gate width to ensure an appropriately low W / L ratio, offsetting their relatively high mobility. This can make LTPS transistors relatively inefficient with respect to pixel layout. Oxide transistors can be constructed with a W / L ratio that has a smaller aspect ratio (e.g., 4 / 4 for oxide versus 3 / 30 for LTPS). These layout efficiency considerations may make it preferable to use oxide transistors as drive transistors in display pixel 22-1. The relatively fast switching speeds offered by LTPS transistors may make it preferable to use LTPS transistors with respect to switching transistors such as transistor 30 of FIG. 2.

[0026] In display pixels having more transistors (e.g., three or more, four or more, five or more, six or more, seven or more, or eight or more), the choice of which transistors to implement using LTPS technology and which transistors to implement using oxide technology can be made to balance transistor performance considerations between the two types of transistors.

[0027] When implementing drive transistors, LTPS transistors tend to exhibit larger sizes (longer channel lengths) than oxide transistors, tend to exhibit larger dark currents than oxide transistors, and may exhibit poorer uniformity than oxide transistors. LTPS drive transistors may also exhibit larger hysteresis than oxide drive transistors. As a result of these factors, it may often be advantageous to form the drive transistors in organic light emitting diode display pixels from oxide transistors. Oxide drive transistors may exhibit low leakage currents and minimal hysteresis.

[0028] When implementing switching transistors, LTPS transistors can be smaller than oxide transistors, can exhibit less parasitic capacitance than oxide transistors, and can exhibit lower power consumption than oxide transistors. As a result of factors such as these, it can often be advantageous to form the switching transistors in organic light emitting diode display pixels from LTPS transistors. LTPS switching transistors can exhibit high switching speeds and low parasitic capacitance.

[0029] An exemplary hybrid thin film transistor structure that can be used to implement both LTPS and oxide transistors in a single organic light emitting diode display pixel (e.g., to implement a circuit such as the display pixel circuit 22-1 of FIG. 2) is shown in FIG. 4. The hybrid thin film transistor structure 114 of FIG. 4 includes a silicon thin film transistor 108, a capacitor (Cst) 110, and an oxide transistor 112. The silicon transistor 108 is formed from a polysilicon layer 90. A gate insulating layer 92 covers the polysilicon layer 90. On top of the gate insulating layer 92, a layer of gate metal is patterned to form a gate 94, a capacitor electrode 96, and a gate electrode 98. The patterned gate metal structure can be covered by layers of interlayer dielectric material such as a silicon nitride layer 116 and a silicon oxide layer 118. The source-drain contacts 100 and 94 for the silicon transistor 108 can contact (i.e., short) the polysilicon layer 90 near the channel region 106. The gate 94 of transistor 108 may act as an implant mask to enable a low density drain implant to be formed in polysilicon layer 90 in region 104 adjacent to the polysilicon channel region 106 of transistor 108.

[0030] The source-drains 100 and 102 of silicon transistor 108 and the source-drains 122 and 124 of oxide transistor 112 may be formed from patterned portions of a common metal layer over interlevel dielectric 116 and interlevel dielectric 118 .

[0031] Capacitor 110 may have a first terminal formed from metal electrode 120 and portion 126 of polysilicon layer 90. Capacitor 110 may have a second terminal formed from metal electrode 96.

[0032] Oxide transistor 112 may have a semiconducting oxide layer, such as an IGZO layer 128, source-drain contacts 122 and 124, and a gate 98. Gate 98 is separated from semiconducting oxide 128, which serves as a channel region for transistor 112, by dielectric 116 and dielectric 118. Dielectric 116 and dielectric 118 therefore serve as a gate insulator for oxide transistor 112.

[0033] 5 is a circuit diagram of another exemplary organic light emitting diode pixel circuit that can be used in display 14. Pixel 22-2 includes a drive transistor 28 for driving current into light emitting diode 26. A storage capacitor Cst is used to store the signal on the gate of transistor 28 between frames. A sense line SENSING is used to implement a compensation scheme to adjust for variations in transistor performance between pixels. Gate lines SCAN and SCAN2 are used to apply control signals to switching transistors 30-1 and 30-2.

[0034] To optimize performance within display pixel 22-2, it may be desirable to use hybrid structures of the type shown in Figures 3 and 4, or other configurations for forming silicon and / or oxide thin film transistors and capacitors. For example, it may be desirable to form drive transistor 28 from oxide transistors (e.g., NMOS oxide transistors), while forming switching transistors such as transistors 30-1 and 30-2 from silicon transistors or from a mixture of silicon (NMOS and / or PMOS) and oxide (NMOS) transistors.

[0035] In the first exemplary configuration, the transistor 30-1 is an oxide transistor, the transistor 30-2 is an oxide transistor, and the transistor 28 is an oxide transistor. In the second exemplary configuration, the transistor 30-1 is a silicon transistor, the transistor 30-2 is a silicon transistor, and the transistor 28 is an oxide transistor. A hybrid transistor structure, such as the structure of FIG. 3 or the structure of FIG. 4, can be used in this scenario (e.g., to implement the transistors 30-1 and 28 and the capacitor Cst). In the third exemplary configuration, the transistor 30-1 is a silicon transistor, the transistor 30-2 is an oxide transistor, and the transistor 28 is an oxide transistor. As in the second exemplary configuration, a hybrid transistor structure, such as the structure of FIG. 3 or the structure of FIG. 4, can be used to implement the transistors 30-1 and 28 and the capacitor Cst.

[0036] Optionally, the display 14 may be a liquid crystal display. In this type of scenario, each pixel of the display 14 may include an electrode structure for applying an electric field to an associated portion of a liquid crystal layer in the display, a capacitor for storing charge on the electrode between frames of image data, and a thin film transistor for controlling the application of the electric field to the electrode. In one preferred arrangement, the gate drive circuitry 18 and demultiplexer circuitry 20 (FIG. 1) in the liquid crystal display may be formed from silicon transistors, and the thin film transistors in the display pixels 22 may be formed from oxide transistors. Silicon transistors have high mobility channel regions, suitable for fast switching speeds and high drive currents, while operating at low voltages and low power. The oxide thin film transistors in the display pixels 22 exhibit low leakage currents.

[0037] A type of thin film transistor structure that can be used in forming a liquid crystal display having both silicon and oxide transistors is shown in Figure 6. As shown in Figure 6, thin film transistor structure 242 can include a silicon thin film transistor structure 216 (e.g., for forming portions of peripheral circuitry such as display driver circuitry 18 and demultiplexer circuitry 20) and an oxide thin film transistor structure 240 (e.g., for forming display pixels 22 in a liquid crystal display having a layout of the type shown by display 14 in Figure 1).

[0038] Structure 216 and structure 240 may be formed on a buffer layer 202 on substrate 24. A polysilicon layer 204 may be deposited on buffer 202. A gate insulating layer 206 may be formed on polysilicon layer 204. A common layer of metal may be patterned to form metal structures 218, 220, and metal structure 228. Structure 218 may serve as a gate for a silicon transistor including source-drain contacts 212 and 214 and a channel formed from polysilicon 204. Metal structure 228 may serve as a gate for an oxide transistor formed from a semiconductor oxide layer 224 (e.g., IGZO) and source-drain terminals 222 and 226. Metal structure 228 may also serve as a light shield to help block backlight in display 14 from reaching oxide layer 224, eliminating the need to incorporate a separate light shielding structure in structure 240. An interlayer dielectric, such as silicon nitride layer 208 and silicon nitride layer 210, may cover gate 218 in structure 216 and may act as a gate insulator for gate 228 in the oxide transistor of structure 240.

[0039] The metal 230 contacts the source-drain 226 of the display pixel thin-film oxide transistor formed from the oxide layer 224. The metal 230 can be supported by an organic layer 232. On the surface of the organic layer 232, the metal 230 can form an electrode having multiple fingers. A dielectric layer 236 can insulate the electrode 230 from a common electrode (Vcom) 234. During operation, electric fields are generated between the electrodes 230 and 234. These electric fields pass through the liquid crystal material in the display. If desired, the display 14 can incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, optional metal lines, such as lines 238, can be used to help reduce the resistance of the material used in forming the electrode 234, which can be a somewhat resistive conductive material, such as indium tin oxide.

[0040] The thickness of layers 208 and 210 may be approximately 6000 angstroms. This relatively large thickness may help minimize capacitance between gate 218 and nearby metal structures such as source-drain 214, but may limit the switching speed in the oxide transistor. To address this concern, a design of the type used by structure 242' in FIG. 7 may be used. In the arrangement of FIG. 7, an additional semiconductor fabrication mask may be used to create a gate for the oxide transistor formed from a layer of metal separate from the metal layer used in forming gate 218. In this approach, only a single 3000 angstrom dielectric layer 210' (e.g., formed from silicon nitride and silicon oxide sublayers) may be used to separate oxide transistor gate 228' from oxide layer 224, improving the switching speed of the oxide transistor. The arrangement of structure 242' in FIG. 7 allows gate 218 and gate 228' to be formed from different metals. For example, gate 218 may be formed from a heat-resistant metal such as Mo to accommodate the elevated temperatures associated with activation of silicon transistors, while gate 228' may be formed from a less resistive metal such as copper.

[0041] In some applications, it may be necessary to consider handling high drive voltages (between the gate and the source and drain). The transistor structure 242" of FIG. 8 can be used in scenarios where it is desired to handle a relatively large (e.g., 20 volt) swing on a silicon transistor gate. In this situation, the gate insulation layer 206 may be insufficiently thin to withstand damage from a 20 volt signal. For example, the gate insulator 206 may be approximately 800 Angstroms thick, which may not be thick enough to reliably handle a 20 volt drive voltage. To ensure that the gate insulation layer 206 is not overly stressed, the gate structure 218 may be floating. The silicon transistor gate 218' may be converted to a gate (electrically insulating) metal structure, and an additional metal layer (i.e., a portion of the same metal layer that is patterned to form gate 228' of oxide transistor 240) may be used in forming the silicon transistor gate 218'. The floating gate 218 may be maintained to act as a mask for low density drain (LDD) implants made in the source and drain contact portions of polysilicon layer 204, even when the floating gate 218 is not driven with a control signal during operation of the silicon transistor 216.

[0042] In a hybrid silicon / oxide liquid crystal display, the display driver circuitry, such as the gate driver circuitry 18 and the demultiplexer circuitry 20, need not be formed from silicon transistors. Portions of the display driver circuitry can be formed from oxide transistors, if desired. For example, low drive current CMOS type circuits in the peripheral circuitry of the display 14, such as the exemplary CMOS inverter 300 of FIG. 9, may include oxide transistors. Because PMOS oxide transistors can be difficult to form, circuits such as the inverter 300 can be formed using NMOS oxide transistors and PMOS silicon transistors (by way of example) if desired.

[0043] A hybrid oxide-silicon thin film transistor structure, such as the exemplary thin film transistor structure 302 of FIG. 10, can be used in forming CMOS type circuitry in display driver circuitry, such as the gate driver circuitry 18 and the demultiplexer circuitry 20. As shown in FIG. 10, the structure 302 can have a polysilicon layer 308 formed on a substrate 24. A P-channel active area 310 can be formed under a gate 312. A gate insulating layer 306 (e.g., silicon oxide) can separate the gate 312 from a silicon channel region 310 in the silicon layer 308. A dielectric layer 302 (e.g., silicon oxide and silicon nitride sublayers) can cover the gate 312. The dielectric layer 306 can separate the gate 312 from an overlying oxide layer 312. The oxide layer 312 can be a semiconducting oxide, such as an IGZO material. The gate 312 can be formed from a first patterned metal layer. A second patterned metal layer may be used in forming the output terminal 322, the source terminal 316, and the drain terminal 318. A passivation layer 320 may cover the terminal 316 and the terminal 312. The gate 312 may be formed from materials such as molybdenum, molybdenum tungsten, tungsten, or other metals. Metals for forming structures such as metal structures 322, 316, and metal structure 318 may be formed from metals such as aluminum, molybdenum, etc.

[0044] In the arrangement of Figure 10, gate 314 serves as a common (shared) gate for two transistors. Specifically, gate 314 (see, e.g., terminal Vin in Figure 9) serves as both the gate for a PMOS silicon transistor (transistor TP in Figure 9) formed from silicon layer 308 and the gate for an NMOS oxide transistor (transistor TN in Figure 9) formed from oxide layer 312. Oxide layer 312 is disposed above gate 314 and silicon layer 310 is disposed below gate 314. The shared gate arrangement of Figure 10 allows for a compact implementation of a CMOS inverter of the type shown in Figure 9.

[0045] 11 shows an exemplary gate drive circuitry 18 that may be used on a liquid crystal display. The circuitry 18 uses signals having a relatively small voltage swing (e.g., 15 or 16 volts amplitude) for silicon transistors, while generating gate signals G having a larger voltage swing (e.g., 20 volts or more amplitude) to ensure good operation of oxide thin film transistors in display pixels 22 being driven by those gate signals.

[0046] As shown in FIG. 11, the circuitry 18 may include a shift register formed from serially connected SR latches 400 or other register circuits. Each row of the circuitry in FIG. 11 is associated with a separate row of display pixels 22 in the liquid crystal display and provides a corresponding gate signal G to that row of display pixels. During operation, a trigger signal TRIGGER may be applied to the latches in the first row of the shift registers in the circuitry 18 while a clock signal LOAD CLOCK is applied to the shift register. This trigger signal causes a cascade signal to ripple down through the shift register. In response, each latch 400 in turn asserts its output OUT. Each row of the gate drive circuitry 18 has a corresponding level shifter 404 and buffer 404 that receives the output signal OUT.

[0047] The output signal OUT ranges from a high voltage of 15V (or other suitable voltage) to 0V (or other suitable voltage). While the 15V swing associated with this type of configuration can be tolerated by the silicon thin film transistors in the latch 400, a larger voltage swing, such as a 20V swing, may overly stress the silicon thin film transistors. The level shifter 402 shifts the 15V to 0V signal OUT from the latch 400 such that the output on path 406 from the level shifter 402 ranges from 5V to -11V (i.e., a 16V swing that can be tolerated by the silicon transistors in the level shifter 402). The buffer 404 receives the 15V to 0V signal OUT from the latch 400 as an input signal IN_H and receives the 5V to -11V signal as an input signal IN_L. The buffer 404 preferably includes silicon thin film transistors. This design of buffer 404 enables it to generate an output signal (gate line signal G) having a large voltage swing (e.g., 15 volts to -11 volts) of a type suitable for controlling oxide transistors in an array of display pixels 22 on a liquid crystal display.

[0048] 12 is a circuit diagram of an exemplary circuit of a type that can be used to implement a level shifter 402. A signal from an output OUT of the latch 400 can be received at an input 410 of the level shifter 402, and a corresponding level-shifted output signal (signal IN_L) for the buffer 404 can be provided at an output 412 of the level shifter 402. Other level shifter designs can be used for the level shifter 402, as desired. The configuration of FIG. 12 is merely exemplary. Silicon thin film transistors can be used in forming the level shifter 402.

[0049] The circuitry 404 of FIG. 13 is one example of a design that may be used to implement the buffer 404 of FIG. 11. In this design, the signals IN_H and IN_L are identical square wave pulses with different corresponding voltage amplitudes. The signal IN_H ranges from 15 to 0 volts. The signal IN_L ranges from 5 to -11 volts. The corresponding output signal (gate line signal) G in this example is a square wave pulse that ranges from 15 volts to -11 volts, and therefore has an amplitude of over 20 volts.

[0050] A ground voltage GND is applied to the gates of transistors T2 and T3. This limits the maximum voltage experienced by the transistors of circuit 414 to less than about 16 volts, even if the output swing of circuit 414 exceeds 20 volts. The ground voltage GND on the gates of transistors T2 and T3 turns off these transistors whenever an excessive source terminal voltage swing is detected, protecting transistors T1 and T4. As an example, consider transistors T1 and T2. Transistor T2 can be characterized by a threshold voltage Vth. When the source S of transistor T1 begins to fall below the voltage GND-Vth, transistor T2 turns off, isolating transistor T1. Transistors T3 and T4 operate in the same manner. Using this arrangement, none of the transistors in buffer 414 are exposed to excessive voltage swings, and transistors T1, T2, T3, and T4 can be made from silicon thin film transistors.

[0051] If desired, other circuit configurations can be used to enable the gate drive circuitry 18 to operate in environments where the gate line signal G has a large voltage swing to accommodate oxide transistors in the display pixels 22. As an example, in addition to using silicon thin film transistor structures, oxide thin film transistor structures can be used to implement a subset of the level shifter transistors, and a subset of the output buffer transistors.

[0052] Figure 14 is a cross-sectional side view of further thin film transistor circuitry of a type that can be used in a liquid crystal display. As shown in Figure 14, thin film transistor structure 242 can include silicon thin film transistor structure 216 (e.g., for forming portions of peripheral circuitry such as display driver circuitry 18 and demultiplexer circuitry 20) and oxide thin film transistor structure 240 (e.g., for forming display pixels 22 in a liquid crystal display having a layout of the type shown by display 14 of Figure 1).

[0053] Structure 216 and structure 240 may be formed on a buffer layer 202 on substrate 24. A polysilicon layer 204 may be deposited on buffer 202. A gate insulating layer 206 may be formed on polysilicon layer 204. A common layer of metal may be patterned to form metal structures 218, 220, and metal structure 228. Structure 218 may serve as a gate for a silicon transistor including source-drain contacts 212 and 214 and a channel formed from polysilicon 204. Metal structure 228 may serve as a gate for an oxide transistor formed from a semiconductor oxide layer 224 (e.g., IGZO) and source-drain terminals 222 and 226. Metal structure 228 may also serve as a light shield to help block backlight in display 14 from reaching oxide layer 224, eliminating the need to incorporate a separate light shielding structure in structure 240. An interlevel dielectric, such as silicon nitride layer 208 and silicon nitride layer 210 , may cover gate 218 in structure 216 and may act as a gate insulator for gate 228 in the oxide transistor of structure 240 .

[0054] Metal structures 218, 220, and 228, as well as routing lines such as interconnect line 502, may be formed from a first metal layer (sometimes referred to as an M1 layer). Metal 222 and metal 226, which form source-drain contacts for the oxide transistors of structure 240, as well as routing lines such as interconnect line 500, may be formed from a second metal layer (sometimes referred to as an SD1 layer). Metal structures 212, 214, as well as routing lines such as interconnect line 506, may be formed from a third metal layer (sometimes referred to as an SD2 layer). Dielectric layer 232B may separate the second metal layer from the third metal layer. Dielectric layer 232A may separate the third metal layer from metal structures such as metal layer 234.

[0055] The metal 230 is coupled to the source-drain 226 of the display pixel thin-film oxide transistor formed from the oxide layer 224 by contacting the metal layer 504. The metal 230 may be supported by the organic layer 232B. On the surface of the organic layer 232B, the metal 230 may form an electrode having multiple fingers. The electrode 230 may be insulated from the common electrode (Vcom) 234 by the dielectric layer 236. During operation, electric fields are generated between the electrodes 230 and 234. These electric fields pass through the liquid crystal material in the display. If desired, the display 14 may incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, optional metal lines, such as lines 238, may be used to help reduce the resistance of the material used in forming the electrode 234, which may be a somewhat resistive conductive material, such as indium tin oxide.

[0056] Capacitive coupling between routing lines in the display 14 can result in switching losses. As an example, the source-drain structure 222 can be coupled to a data line in the display 14. The voltage on this line can switch with respect to Vcom (electrode 234), resulting in power losses. The presence of the dielectric layers 232A and 232B can help reduce capacitive coupling between this data line and the Vcom electrode, thereby reducing power losses. The presence of these dielectric layers can also reduce capacitive coupling between the routing lines in the display 14 (e.g., capacitive coupling between the routing lines and other structures, such as the first and second metal layers, the first and third metal layers, etc.). The layers 232A and 232B can be formed from organic dielectrics or other dielectric materials with low dielectric constants. As an example, the layers 232A and 232B can be acrylic polymers, other polymers, types of dielectrics sometimes referred to as spin-on glass (e.g., spin-on glass polymers deposited via a slit coating tool), siloxane-based materials, etc.

[0057] FIG. 15 is a cross-sectional side view of an exemplary thin film transistor circuitry for a liquid crystal display including a top-gate semiconductor oxide transistor. As shown in FIG. 15, a thin film transistor structure 242 can include a silicon thin film transistor structure 216 and a semiconductor oxide thin film transistor structure 240. The silicon thin film transistor structure 216 can be used in peripheral circuits, such as the display driver circuitry 18 and the demultiplexer circuitry 20, and / or can be used in forming circuits for display pixels 22 in a liquid crystal display. The semiconductor oxide thin film transistor structure 240 can be used in peripheral circuits, such as the display driver circuitry 18 and the demultiplexer circuitry 20, and / or can be used in forming circuits for display pixels 22 in a liquid crystal display. A transistor such as the silicon (polysilicon) transistor 216 can be an n-channel device or a p-channel device. A transistor such as the semiconductor oxide transistor 240 can be an n-channel device or a p-channel device.

[0058] Structure 216 and structure 240 may be formed on a buffer layer 202 on substrate 24. Buffer layer 202 may be formed from a dielectric material, such as an inorganic dielectric material. Buffer layer 202 may help prevent ions in substrate 24 from migrating into structure 216 and structure 240.

[0059] A polysilicon layer 204 may be deposited on the buffer 202. A gate insulating layer 206 may be formed on the polysilicon layer 204. The gate insulating layer 206 may be formed from a dielectric such as silicon oxide (e.g., a 100 nm silicon oxide layer). The common layer of metal may be patterned to form metal structures 218, 220, and metal structure 228. Structure 218 may serve as a gate for a silicon transistor including source-drain contacts 212 and 214 and a channel formed from polysilicon 204. Metal structure 228 may serve as a gate for a top-gate oxide transistor (i.e., a semiconductor oxide transistor) formed from a semiconductor oxide layer 224 (e.g., IGZO) and source-drain terminals 222 and 226. One or more layers of interlayer dielectric (ILD) may cover the metal structures 218, 220, and metal structure 228. For example, a first dielectric layer, such as layer 208, and a second dielectric layer, such as layer 210, may cover the metal structures 218, 220, and metal structures 228. (By way of example) layer 208 may be a silicon nitride layer, and layer 210 may be a silicon oxide layer. Because there is no lateral overlap between the gate 228 and the source-drain electrodes 222 and 226, parasitic capacitance between the gate 228 and the source-drain structures 222 and 226 may be minimized. Furthermore, layers 208 and 210 of the oxide transistor of FIG. 15 may be thicker than layers 208 and 210 in the bottom gate oxide transistor of FIG. 14, further reducing parasitic capacitance.

[0060] Metal structures 218, 220, and metal structure 228 can be formed from a first metal layer (sometimes referred to as an M1 layer). Metal 222 and metal 226, which form the source-drain contacts for the oxide transistor of structure 240, and metal 212 and metal 214, which form the source-drain contacts for the silicon transistor of structure 216, can be formed from a second metal layer (sometimes referred to as an SD1 or M2 layer). Metal structures such as metal line 238 can be formed from a third metal layer (sometimes referred to as an M3 layer). The second metal layer can be separated from the third metal layer by a dielectric 232 (e.g., an organic dielectric layer such as a polymer layer).

[0061] The metal 230 contacts the source-drain 226 of a display pixel thin-film oxide transistor formed from the oxide layer 224. The metal 230 can be supported by an organic layer 232. On the surface of the organic layer 232, the metal 230 can form an electrode having multiple fingers (e.g., a pixel electrode for a display pixel in a display). The electrode 230 can be insulated from a common electrode (Vcom) 234 by a dielectric layer 236. During operation, electric fields are generated between the electrodes 230 and 234. These electric fields pass through the liquid crystal material in the display, which is formed on top of the structure of FIG. 15. If desired, the display 14 can incorporate a capacitive touch sensor formed from portions of the Vcom electrode 234. In this type of configuration, optional metal lines, such as lines 238, can be used to help reduce the resistance of the material used in forming the electrode 234 (which can be a slightly resistive conductive material, such as indium tin oxide).

[0062] 16, an optional light blocking structure, such as a light shield 520, may be formed under the semiconductor oxide transistor 240 or elsewhere in the display. The light shield 520 may be formed from an opaque material, such as a metal, a metal oxide, a dark polymer, or other light blocking material. The presence of the light shield 520 may help prevent stray light from interfering with the operation of the semiconductor oxide transistor structure 240 or other overlapping structures.

[0063] In the embodiment of FIG. 17, the dielectric layer 232 of FIG. 15 is split into two dielectric layers 232A and 232B. Layer 232A can overlay the source-drain electrodes of transistor 216 and transistor 240. Layer 232B can be interposed between the source-drain electrodes and other metal structures formed from the source-drain metal layer and layers 208 and 210. As described in connection with FIG. 14, this type of two-layer approach can reduce capacitive coupling between the metal structures of device 216 and device 240. A side cross-sectional view of an exemplary thin film transistor circuitry including a top-gate semiconductor oxide transistor in an organic light emitting diode display is shown in FIG. 18. As shown in FIG. 18, the circuitry 72 can include display pixel structures such as a light emitting diode cathode terminal 42 and a light emitting diode anode terminal 44. An organic light emitting diode emitting material 47 can be interposed between the cathode 42 and the anode 44. The pixel defining layer 46 may be a dielectric layer 46 that helps to define the layout of the display pixels. Layer 46 may be formed from a polymer, such as a black polymer, to help block stray light.

[0064] A planarization layer 50 may be formed on top of the thin film transistor structure 52. The thin film transistor structure 52 may be formed on a buffer layer 54 on a substrate 24. The substrate 24 may be formed of metal, glass, polymer, other materials, or combinations of these materials. The buffer layer 54 may be formed of an inorganic dielectric layer that helps prevent ions in the substrate 24 from interfering with the operation of the structure 52. An optional functional layer 522 may be interposed between the buffer layer 54 and the substrate 24. The functional layer 522 may be a stress relief layer, a light blocking layer, a layer used in forming components such as capacitors (e.g., capacitor electrodes for pixel circuits and / or peripheral circuits), and the like.

[0065] The thin film transistor structure 52 may include a silicon transistor 58. The transistor 58 may be an LTPS transistor formed using a top-gate design and may serve as a switching transistor in an organic light emitting diode display pixel (see, for example, transistor 30 in pixel 22-1 of FIG. 2). The transistor 58 may also be used in peripheral circuits (e.g., the driver circuitry 18 and the demultiplexer circuitry 20).

[0066] The transistor 58 may have a polysilicon channel 62 covered by a gate insulation layer 64 (e.g., a layer of silicon oxide having a thickness of 100 nm or other suitable thickness). The gate 66 may be formed from a patterned metal (e.g., molybdenum, by way of example). The gate 66 may be covered by a layer of interlevel dielectric (e.g., a silicon nitride layer 68 and a silicon oxide layer 70). Source-drain contacts 74 and 76 may contact opposing sides of the polysilicon layer 62 to form the silicon thin film transistor 58.

[0067] A dielectric layer 526 may cover the source-drain structures 74 and 76. An optional metal layer 524 may be formed on layer 526 and may contact underlying metal structures through vias (see, e.g., via 528) if necessary. Structure 66 may be formed in a first ("M1") metal layer. Source-drain electrodes 74 and 76 may be formed in a second metal layer. Metal layer 524 may be formed as part of a third ("M3") metal layer. Layer 524 may overlay portions of transistor 58 and / or transistor 60 and may be used to form capacitors or signal interconnects (i.e., routing). Layer 524 may be overlaid with emissive material layer 47, which may form a light blocking structure that prevents stray light from emissive material 47 from reaching underlying transistor structures, etc.

[0068] Thin film transistor structures, such as semiconductor oxide thin film transistor structure 60 and silicon thin film transistor structure 58, may be used in forming part of pixel circuitry in an organic light emitting diode display and / or may be used in forming part of peripheral circuitry 18 and peripheral circuitry 20. Thin film transistor 60 of Figure 18 may be a top-gate semiconductor oxide transistor. Gate insulation layer 64, which serves as the gate insulator for silicon transistor 58, also serves as the gate insulator for oxide transistor 60.

[0069] Metal gate 532 forms the gate of oxide transistor 60. The channel semiconductor of this oxide transistor may be formed from semiconductor oxide layer 128 (e.g., IGZO). Source-drain terminals 534 and 536 may be formed from metal contacting opposite ends of semiconductor oxide layer 128. Metal structure 530 and metal structure 538 may be used for routing and may be formed from the same layer of metal that is patterned to form gate 66 and gate 532. Source-drain structures 534 and 536 may be formed from the same layer of metal used in forming source-drain structures 74 and 76.

[0070] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixels on the substrate, display driver circuitry formed from thin film transistors on the substrate, the display driver circuitry comprising silicon thin film transistors and the array of display pixels comprising semiconductor oxide thin film transistors, and a layer of gate metal patterned to form a common gate which serves as a gate for the silicon thin film transistors and as a gate for the semiconductor oxide thin film transistors.

[0071] According to another embodiment, a semiconductor oxide thin film transistor has a semiconductor oxide layer and a common gate below the semiconductor oxide layer.

[0072] According to another embodiment, a layer of polysilicon on a substrate forms a silicon channel for a silicon thin film transistor, and a common gate resides above the layer of polysilicon.

[0073] According to another embodiment, the liquid crystal display includes a layer of silicon nitride and a layer of silicon oxide interposed between a gate of a semiconductor oxide thin film transistor and a semiconductor oxide layer.

[0074] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixels on the substrate, display driver circuitry formed from thin film transistors on the substrate, the display driver circuitry including silicon thin film transistors and the array of display pixels including semiconductor oxide thin film transistors, a layer of polysilicon on the substrate forming a silicon channel for the silicon thin film transistors, a layer of a first gate metal forming a gate for the silicon thin film transistors, and a layer of a second gate metal different from the first gate metal layer and forming the gate for the semiconductor oxide thin film transistor.

[0075] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixels on the substrate, and display driver circuitry formed from thin film transistors on the substrate, the display driver circuitry including silicon thin film transistors and the array of display pixels including semiconductor oxide thin film transistors; a layer of polysilicon on the substrate forming a silicon channel for the silicon thin film transistor; a layer of a first gate metal forming a floating gate for the silicon thin film transistor; and a layer of a second gate metal forming a gate for the silicon thin film transistor overlying the floating gate and separated from the floating gate by a layer of dielectric, a portion of the layer of second gate metal forming the gate for the semiconductor oxide thin film transistor.

[0076] According to one embodiment, there is provided a liquid crystal display including a substrate, an array of display pixel circuits on the substrate, and display driver circuitry for driving signals into the array of display pixel circuits, the display driver circuitry being formed from thin film transistors on the substrate, the display driver circuitry including silicon thin film transistors and including semiconductor oxide thin film transistors.

[0077] According to another embodiment, the liquid crystal display includes a metal layer that forms a shared gate for both the silicon thin film transistors and the semiconductor oxide thin film transistors.

[0078] According to another embodiment, a semiconductor oxide thin film transistor has a semiconductor oxide layer above its shared gate.

[0079] According to another embodiment, a silicon thin film transistor has a polysilicon layer beneath its shared gate.

[0080] According to another embodiment, a silicon thin film transistor and a semiconductor oxide thin film transistor form an inverter.

[0081] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixels on the substrate, display driver circuitry formed from thin film transistors on the substrate, the display driver circuitry comprising silicon thin film transistors and the array of display pixels comprising semiconductor oxide thin film transistors, a first patterned metal layer comprising a gate for the silicon thin film transistor and a gate for the semiconductor oxide thin film transistor, a second patterned metal layer comprising source-drain contacts for the semiconductor oxide thin film transistor, a third patterned metal layer comprising a structure coupled to at least one of the source-drain contacts, and a dielectric layer between the second patterned metal layer and the third patterned metal layer.

[0082] According to another embodiment, the liquid crystal display includes a fourth patterned metal layer that includes display pixel electrodes.

[0083] According to another embodiment, the liquid crystal display includes an additional dielectric layer between the third patterned metal layer and the fourth patterned metal layer.

[0084] According to another embodiment, the dielectric layer between the second patterned metal layer and the third patterned metal layer is an organic dielectric layer.

[0085] According to another embodiment, the dielectric layer between the third patterned metal layer and the fourth patterned metal layer is an organic dielectric layer.

[0086] According to another embodiment, the liquid crystal display includes an inorganic dielectric layer between the first patterned metal layer and the second patterned metal layer.

[0087] According to another embodiment, the first patterned metal layer includes routing lines.

[0088] According to another embodiment, the second patterned metal layer includes routing lines.

[0089] According to another embodiment, the third patterned metal layer includes routing lines.

[0090] According to one embodiment, there is provided a display pixel circuit in a display pixel in an organic light emitting diode display, the display pixel circuit including a light emitting diode, a semiconductor oxide thin film transistor coupled to the light emitting diode, and a silicon thin film transistor.

[0091] According to another embodiment, the semiconductor oxide thin film transistor includes a drive transistor having a gate, and the display pixel includes a capacitor coupled between the gate and the light emitting diode.

[0092] According to another embodiment, a silicon thin film transistor has a polysilicon channel and is coupled to the capacitor.

[0093] According to another embodiment, the display pixel circuitry includes a layer of metal, the capacitor has a first electrode and a second electrode, the first electrode and a gate formed from a portion of the layer of metal, and the silicon thin film transistor has a gate formed from another portion of the layer of metal.

[0094] According to another embodiment, the silicon thin film transistor has a channel formed from a portion of the layer of polysilicon and the second electrode is formed from a further portion of the layer of polysilicon, and the oxide transistor has a channel formed from a layer of semiconductor oxide that overlaps the further portion of the layer of polysilicon.

[0095] According to one embodiment, a hybrid thin film transistor structure is provided that includes a silicon layer for a silicon thin film transistor, a semiconductor oxide layer for an oxide transistor, and a layer of metal patterned to form a first gate for the silicon thin film transistor and patterned to form a second gate for the oxide transistor.

[0096] According to another embodiment, the hybrid thin film transistor structure includes a capacitor having an electrode layer formed from a portion of the metal layer.

[0097] According to another embodiment, the hybrid thin film transistor structure includes a layer of a further metal having portions forming source-drain contacts for the silicon thin film transistor, portions forming source-drain contacts for the oxide transistor, and portions forming an electrode layer in a capacitor.

[0098] According to another embodiment, the capacitor has a further electrode layer formed from a portion of the layer of metal that is patterned to form the first gate.

[0099] According to another embodiment, the silicon layer includes a polysilicon layer, portions of which form an electrode layer for the capacitor that are shorted to portions of a layer of further metal that forms the electrode layer in the capacitor.

[0100] According to one embodiment, an organic light emitting diode display is provided that includes a light emitting diode and thin film transistors coupled to the light emitting diode, the thin film transistors including at least one semiconductor oxide channel region and at least one silicon channel region.

[0101] According to another embodiment, the thin film transistor includes a semiconductor oxide thin film transistor formed from a semiconductor oxide channel region and coupled to a light emitting diode.

[0102] According to another embodiment, the thin film transistor comprises a silicon thin film transistor formed from a silicon channel region.

[0103] According to another embodiment, the thin film transistor includes a semiconductor oxide thin film transistor formed from a semiconductor oxide channel region and coupled to a light emitting diode, and a silicon thin film transistor formed from a silicon channel region.

[0104] According to another embodiment, a semiconductor oxide thin film transistor includes a drive transistor having a gate.

[0105] According to another embodiment, the organic light emitting diode display includes a capacitor coupled between the gate and the light emitting diode.

[0106] According to another embodiment, the silicon channel region includes a polysilicon channel region coupled to the capacitor.

[0107] According to another embodiment, the organic light emitting diode display includes a layer of metal, the capacitor has a first electrode and a second electrode, the first electrode and a gate formed from a portion of the layer of metal, and the silicon thin film transistor has a gate formed from another portion of the layer of metal.

[0108] According to another embodiment, the thin film transistor comprises a silicon thin film transistor and a semiconductor oxide thin film transistor, wherein the silicon channel region is formed from a portion of the layer of polysilicon to form part of the silicon thin film transistor, and the second electrode is formed from a further portion of the layer of polysilicon.

[0109] According to another embodiment, the semiconductor oxide channel region forms part of a semiconductor oxide thin film transistor, the semiconductor oxide channel region overlapping a further portion of the layer of polysilicon.

[0110] According to one embodiment, there is provided a liquid crystal display including a substrate, an array of display pixel circuits on the substrate, and display driver circuitry for driving gate line signals into the array of display pixel circuits, the display driver circuitry including level shifter circuitry.

[0111] According to another embodiment, the array of display pixel circuits includes semiconductor oxide thin film transistor circuitry.

[0112] According to another embodiment, the display driver circuitry includes silicon thin film transistors formed on a substrate.

[0113] According to another embodiment, the display drive circuitry includes gate drive circuitry, and the level shifter circuitry forms part of the gate drive circuitry.

[0114] According to another embodiment, the gate drive circuitry further includes a shift register.

[0115] According to another embodiment, the level shifter circuitry is coupled to a shift register.

[0116] According to another embodiment, the gate drive circuitry includes buffer circuitry.

[0117] According to another embodiment, buffer circuitry is coupled to the level shifter circuitry to generate the gate line signals.

[0118] According to another embodiment, the shift register provides a signal having a first voltage amplitude, the level shifter adjusts the first voltage amplitude to a second voltage amplitude, and the buffer circuitry receives the signal from the shift register having the first voltage amplitude and receives the signal from the level shifter having the second voltage amplitude.

[0119] According to another embodiment, a shift register provides a signal having a first voltage amplitude and a level shifter adjusts the first voltage amplitude to a second voltage amplitude.

[0120] According to another embodiment, the gate drive circuitry includes buffer circuitry that receives a signal from the shift register having a first voltage swing.

[0121] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixel circuits on the substrate, the display pixel circuits comprising semiconductor oxide thin film transistors, and display drive circuitry formed from silicon thin film transistors on the substrate, the display drive circuitry including gate drive circuitry including level shifter circuitry receiving a signal having a first voltage amplitude and adjusting the first voltage amplitude to a second voltage amplitude.

[0122] According to another embodiment, gate drive circuitry drives gate line signals into an array of display pixel circuits.

[0123] According to another embodiment, the semiconductor oxide thin film transistors each have a semiconductor oxide channel region and the silicon thin film transistors each have a polysilicon channel region.

[0124] According to another embodiment, the gate drive circuitry further includes a shift register, and the level shifter circuitry is coupled to the shift register.

[0125] According to another embodiment, the gate drive circuitry includes buffer circuitry that receives a signal from the shift register having a first voltage swing and receives a signal from the level shifter having a second voltage swing.

[0126] According to one embodiment, there is provided a liquid crystal display comprising an array of semiconductor oxide thin film transistor display pixel circuits on a substrate; and silicon thin film transistor gate drive circuitry on the substrate including a level shifter that receives a signal having a first voltage amplitude and adjusts the first voltage amplitude to a second voltage amplitude, the silicon thin film transistor gate drive circuitry controlling the array of semiconductor oxide thin film transistor display pixel circuits.

[0127] According to another embodiment, the silicon thin film transistor circuitry includes silicon thin film transistors, each having a polysilicon channel region, and the silicon thin film transistor gate drive circuitry includes a shift register.

[0128] According to another embodiment, the silicon thin film transistor gate drive circuitry includes buffer circuitry.

[0129] According to another embodiment, the liquid crystal display includes shift register circuitry coupled to the level shifter, and buffer circuitry receives signals from the level shifter and signals from the shift register and provides gate line signals to an array of semiconductor oxide thin film transistor display pixel circuits.

[0130] According to one embodiment, there is provided a liquid crystal display comprising a substrate, an array of display pixel circuits on the substrate, and display driver circuitry on the substrate, the display driver circuitry and the display pixels comprising thin film transistors, the thin film transistors comprising at least one top-gate semiconductor oxide transistor and at least one silicon transistor.

[0131] According to another embodiment, the liquid crystal display includes a layer of gate metal patterned to form a first gate for a silicon transistor and a second gate for a top-gate semiconductor oxide transistor.

[0132] According to another embodiment, the liquid crystal display includes a layer of polysilicon on a substrate forming a silicon channel for a silicon transistor, and a first gate above the layer of polysilicon.

[0133] According to another embodiment, the liquid crystal display includes a semiconductor oxide layer on a substrate forming a semiconductor oxide channel for a top-gate semiconductor oxide transistor, and a second gate above the semiconductor oxide layer.

[0134] According to another embodiment, the liquid crystal display includes a gate insulating layer.

[0135] According to another embodiment, a first portion of a gate insulation layer is interposed between the first gate and the polysilicon layer.

[0136] According to another embodiment, a second portion of the gate insulating layer is interposed between the second gate and the semiconductor oxide layer.

[0137] According to another embodiment, the liquid crystal display includes source-drain electrodes for thin film transistors, the source-drain electrodes being formed from a patterned layer of metal.

[0138] According to another embodiment, the liquid crystal display includes a silicon oxide layer interposed between a layer of metal on which the source-drain electrodes are formed and the first and second gates.

[0139] According to another embodiment, the liquid crystal display includes a silicon nitride layer interposed between a layer of metal on which source-drain electrodes are formed and the first and second gates.

[0140] According to another embodiment, the liquid crystal display includes a display pixel electrode and an organic layer interposed between the display pixel electrode and a source-drain electrode.

[0141] According to another embodiment, the liquid crystal display includes a display pixel electrode, a first organic layer interposed between the display pixel electrode and a source-drain electrode, and a second organic layer interposed between the source-drain electrode and a silicon oxide layer.

[0142] According to one embodiment, the liquid crystal display includes a light shield below the semiconductor oxide layer.

[0143] According to one embodiment, an organic light emitting diode display is provided that includes a light emitting diode, a top gate semiconductor oxide thin film transistor coupled to the light emitting diode, and a silicon thin film transistor.

[0144] According to one embodiment, the organic light emitting diode display includes a layer of gate metal patterned to form a first gate for a silicon thin film transistor and a second gate for a top gate semiconductor oxide transistor.

[0145] According to another embodiment, the organic light emitting diode display includes a layer of polysilicon forming a silicon channel for a silicon transistor and a semiconductor oxide layer forming a semiconductor oxide channel for a top-gate semiconductor oxide transistor, a first gate above the layer of polysilicon and a second gate above the semiconductor oxide layer.

[0146] According to another embodiment, a light emitting diode includes a cathode, an anode, and an organic emissive layer between the anode and the cathode, and the organic light emitting diode display includes a gate insulator having a first portion interposed between a first gate and the layer of polysilicon and a second portion interposed between a second gate and the layer of semiconducting oxide, and source-drain electrodes in a semiconducting oxide thin film transistor coupled to the anode.

[0147] According to one embodiment, there is provided an organic light emitting diode display including a light emitting diode, a silicon thin film transistor, a semiconductor oxide thin film transistor having source-drain electrodes and a semiconductor oxide layer coupled to the source-drain electrodes, the semiconductor oxide thin film transistor having a gate, and a light blocking layer overlying at least a portion of the silicon thin film transistor and at least a portion of the semiconductor oxide thin film transistor.

[0148] According to another embodiment, a light emitting diode includes a cathode, an anode, and an organic emissive layer between the anode and the cathode, the organic emissive layer overlying a light blocking layer, and the organic light emitting diode display includes a gate insulating layer having a first portion that serves as a gate insulator for a silicon thin film transistor and having a second portion that serves as a gate insulator for a semiconductor oxide thin film transistor.

[0149] According to another embodiment, the organic light emitting diode display includes source-drain electrodes in a semiconducting oxide thin film transistor coupled to an anode.

[0150] The above is merely illustrative, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. 1. A display having an array of pixels, the display comprising: A substrate; a buffer layer formed on the substrate; a thin film transistor structure for the array of pixels, the buffer layer being disposed between the substrate and the thin film transistor structure, the thin film transistor structure including a silicon transistor and an oxide transistor, the silicon transistor including a polysilicon channel and a first gate, the polysilicon channel being disposed between the buffer layer and the first gate, the oxide transistor including a semiconductor oxide layer and a second gate, the second gate being disposed between the buffer layer and the semiconductor oxide layer; a first metal layer patterned to form the first gate; a second metal layer patterned to form the second gate; a light shield disposed between the substrate and at least one of the silicon transistor and the oxide transistor.

2. The display of claim 1 , wherein the buffer layer is disposed between the light shield and the silicon transistor.

3. 10. The display of claim 1, further comprising a gate insulation layer disposed between said polysilicon channel and said first gate.

4. 10. The display of claim 1, further comprising a dielectric layer, said first gate being disposed between said dielectric layer and said polysilicon channel.

5. The display of claim 1 , wherein the buffer layer is formed of an inorganic material.

6. The display of claim 1 , wherein the substrate is a polymer substrate.

7. The display of claim 1 , wherein the light shield is disposed between the substrate and the silicon transistor.

8. further comprising an electrode for one of the pixels; The display of claim 1 , wherein the electrode is electrically connected to the semiconductor oxide layer.

9. 10. The display of claim 8, further comprising at least one dielectric layer disposed between the electrode and the semiconductor oxide layer.

10. 10. The display of claim 9, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer, with a metal layer disposed between the first dielectric layer and the second dielectric layer.

11. 11. The display of claim 10, wherein a first metal via portion electrically connects the metal layer to the semiconductor oxide layer and a second metal via portion electrically connects the metal layer to the electrode.

12. 12. The display of claim 11, wherein the first and second dielectric layers are first and second organic dielectric layers.

13. 1. A display having an array of pixels, the display comprising: A substrate; a buffer layer formed on the substrate; a thin film transistor structure for the array of pixels, the buffer layer being disposed between the substrate and the thin film transistor structure, the thin film transistor structure including a silicon transistor and an oxide transistor, the silicon transistor including a polysilicon channel and a first gate, the polysilicon channel being disposed between the buffer layer and the first gate, the oxide transistor including a semiconductor oxide layer and a second gate, the second gate being disposed between the buffer layer and the semiconductor oxide layer; a dielectric layer disposed between the first gate and the second gate; a light shield disposed between the substrate and the buffer layer, the light shield overlapping at least one of the silicon transistor and the oxide transistor.

14. The display of claim 13 , wherein the light shield overlaps the silicon transistor.

15. The display of claim 13 , wherein the buffer layer is formed of an inorganic dielectric material.

16. 14. The display of claim 13, further comprising a planarization layer formed over the thin film transistor structure.

17. an anode formed on the planarization layer; a cathode formed on the anode; 17. The display of claim 16, further comprising an organic light emitting diode emissive material disposed between the anode and the cathode.

18. 20. The display of claim 17, wherein the anode is electrically connected to the semiconductor oxide layer through the planarization layer.

19. 1. A display having an array of pixels, the display comprising: A substrate; a buffer layer formed on the substrate; a thin film transistor structure for the array of pixels, the buffer layer being disposed between the substrate and the thin film transistor structure, the thin film transistor structure including a silicon transistor and an oxide transistor, the silicon transistor including a polysilicon channel and a first gate, the polysilicon channel being disposed between the buffer layer and the first gate, the oxide transistor including a semiconductor oxide layer and a second gate, the second gate being disposed between the buffer layer and the semiconductor oxide layer; a light shield disposed between the substrate and the silicon transistor, the light shield being disposed between the substrate and the buffer layer.

20. a gate insulating layer having a first portion disposed between the first gate and the polysilicon channel and a second portion disposed between the second gate and the buffer layer; a first dielectric layer having a third portion and a fourth portion, the first gate being disposed between the polysilicon channel and the third portion, and the fourth portion being disposed between the second gate and the semiconductor oxide layer; an electrode for one of said pixels; 20. The display of claim 19, further comprising second and third dielectric layers disposed between the semiconductor oxide layer and the electrodes.

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