Semiconductor Device

Abstract

To provide a semiconductor device suitable for high reliability and high speed operation.SOLUTION: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron capture layer. The semiconductor has a channel formation region, the electron capture layer has a region mutually overlapped to the channel formation region through the second insulator, the first conductor has a region mutually overlapped to the channel formation region through the first insulator, the second conductor has a region mutually overlapped to the electron capture layer through the third insulator; and the second conductor does not have a region overlapped to the channel formation region.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, or a memory device. In particular, one aspect of the present invention relates to an acid The present invention relates to a semiconductor device, a display device, or a light-emitting device having a compound semiconductor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices The vessel may include a semiconductor device. [Background technology]

[0003] Silicon used as a semiconductor in transistors is classified into amorphous silicon and polycrystalline silicon depending on the application. For example, transistors that make up large display devices are It is preferable to use amorphous silicon, for which a film formation technique for a large-area substrate has been established. The transistors constituting a high-performance display device in which a driver circuit and a pixel portion are integrally formed include: It is preferable to use polycrystalline silicon, which allows the fabrication of transistors with high field effect mobility. Polycrystalline silicon is produced by subjecting amorphous silicon to high-temperature heat treatment or laser light treatment. This is how the method of forming the sintered body is known.

[0004] In recent years, the development of transistors using oxide semiconductors (typically In-Ga-Zn oxide) has become The development of oxide semiconductor transistors is becoming more and more active. It has different characteristics from transistors using polycrystalline silicon. For example, a display device including a transistor including an oxide semiconductor has low power consumption. It is known.

[0005] In addition, a transistor including an oxide semiconductor has an extremely low leakage current in an off-state. For example, it is known that the leakage current of a transistor using an oxide semiconductor is low. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). .

[0006] In order to reduce power consumption by power gating, a transistor using an oxide semiconductor is required. It is preferable that the transistor has normally-off electrical characteristics. One method for controlling the threshold voltage of a transistor to achieve normally-off electrical characteristics is to A floating gate is disposed in a region overlapping with the oxide semiconductor. A method for injecting negative fixed charges has been disclosed (see Patent Document 2).

[0007] Since oxide semiconductors can be deposited by sputtering or the like, they can be used to form large display devices. In addition, a transistor using an oxide semiconductor can be Because it has high field effect mobility, it is suitable for use in high-performance displays in which the driver circuit and pixel section are integrated. In addition, a transistor using amorphous silicon or a transistor using polycrystalline silicon can be realized. It is possible to improve and use some of the production equipment for transistors using Another benefit is reduced investment.

[0008] The history of oxide semiconductors is long, and in 1985, the synthesis of crystalline In-Ga-Zn oxide was reported. (See Non-Patent Document 1.) In 1995, In-Ga-Zn oxide was Homologous structure, InGaO3(ZnO) m (m is a natural number.) It has been reported that this is the case (see Non-Patent Document 2).

[0009] In 1995, a transistor using an oxide semiconductor was invented, and its electrical properties Its characteristics are disclosed (see Patent Document 3).

[0010] In 2014, a transistor using a crystalline oxide semiconductor was reported. (See Non-Patent Documents 3 and 4.) Here, the CAAC-OS (C-Axis Aligned C) with excellent electrical characteristics and reliability Transistor using Rystalline Oxide Semiconductor It has been reported that [Prior art documents] [Patent documents]

[0011] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2013-247143 A [Patent Document 3] Special Publication No. 11-505377 [Non-patent literature]

[0012] [Non-Patent Document 1] N. Kimizuka, and T. Mohri: Journal of Solid State Chemistry, 1985, volume 60, p.382-384 [Non-Patent Document 2] N. Kimizuka, M. Isobe, and M. Nakamura: Journal of Solid State Chemistry, 1995, volume 116, p.170-178 [Non-Patent Document 3] S. Yamazaki, T. Hirohashi, M. Takahashi, S. Adachi, M. Tsubuku, J. Koezuka, K. Okazaki, Y. Kanzaki, H. Matsukizono, S. Kaneko, S. Mori, and T. Matsuo: Journal of the Society for Information Display,2014, volume 22, Issue 1, p.55-p.67 [Non-Patent Document 4] S. Yamazaki, T. Atsumi, K. Dairiki, K. Okazaki, and N. Kimizuka: ECS Journal of Solid State Science and Technology, 2014, volume 3, Issue 9, p.Q3012-p.Q3022 Summary of the Invention [Problem to be solved by the invention]

[0013] One embodiment of the present invention is to provide a semiconductor device including a transistor with low off-state current. Another embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another embodiment of the present invention is to provide a semiconductor device having a high writing speed. Another object of one embodiment of the present invention is to provide a semiconductor device having a high read speed. Another object of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a display device that is easy on the eyes. Another object of one embodiment of the present invention is to provide a semiconductor device having a transparent semiconductor. One of the objectives of the project is to provide a place where

[0014] The description of these problems does not preclude the existence of other problems. The embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the description. The above will become apparent from the description, drawings, claims, etc. From descriptions such as these, it is possible to extract other issues. [Means for solving the problem]

[0015] (1) In one embodiment of the present invention, a transistor includes a first conductor, a second conductor, and a first insulator. a second insulator, a third insulator, a semiconductor, and an electron capture layer, The electron trap layer is connected to the channel forming region through a second insulator. The first conductor and the channel forming region overlap each other via the first insulator. The second conductor overlaps with the electron capture layer via a third insulator. a second conductor having no region overlapping with a channel formation region, do. (2) Alternatively, in one embodiment of the present invention, a transistor includes a first conductor, a second conductor, and a third conductor, a fourth conductor, a first insulator, a second insulator, and a third insulator; a semiconductor and an electron capture layer, the semiconductor having a first region in contact with the third conductor and a fourth region in contact with the third conductor; a second region in contact with the conductor; and a third region disposed between the first region and the second region. and the electron capture layer has a region overlapping with the third region via the second insulator. The first conductor has a region overlapping with the third region via the first insulator, and the second The conductor has an area overlapping the electron capture layer with the third insulator interposed therebetween, and the second conductor , the semiconductor device does not have a region overlapping with the third region. (3) Alternatively, in one embodiment of the present invention, a transistor includes a first conductor, a second conductor, and a third conductor, a fourth conductor, a first insulator, a second insulator, and a third insulator; a semiconductor and an electron capture layer, the semiconductor having a first region in contact with the third conductor and a fourth region in contact with the third conductor; a second region in contact with the conductor; and a third region disposed between the first region and the second region. and the electron capture layer is connected to the first region and the third region through the second insulator. The first conductor has an overlapping region with the third region via the first insulator. The second conductor has an overlapping region with the electron capture layer via a third insulator. The second conductor is a semiconductor device having a region overlapping with the first region. (4) Alternatively, one aspect of the present invention is characterized in that the electron capture layer contains a conductor or a semiconductor. The semiconductor device according to any one of (1) to (3) has the following characteristics. Effect of the Invention

[0016] It is possible to provide a semiconductor device or the like that includes a transistor with low off-state current. It is possible to provide a semiconductor device with low power consumption. Alternatively, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device with a high writing speed. It is possible to provide a semiconductor device capable of reading out data at a high speed. Alternatively, a novel semiconductor device can be provided. can provide a display device that is easy on the eyes. An apparatus can be provided.

[0017] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the specification, drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0018] [Figure 1] 1A to 1C are diagrams illustrating examples of a semiconductor device according to an embodiment; [Diagram 2] 1A to 1C are diagrams illustrating examples of a semiconductor device according to an embodiment; [Diagram 3] 1 is a diagram illustrating an example of a band diagram of a semiconductor device according to an embodiment; [Figure 4] 1A to 1C are a diagram illustrating characteristics of a semiconductor device according to an embodiment and a diagram illustrating an example of a circuit to which the semiconductor device is applied. [Diagram 5] 1A and 1B are a top view and a cross-sectional view of a transistor according to the present invention; [Figure 6] 1A and 1B are a top view and a cross-sectional view of a transistor according to the present invention; [Figure 7]1 is a cross-sectional view of a transistor according to the present invention. [Figure 8] 1 is a cross-sectional view of a transistor according to the present invention. [Figure 9] 1A and 1B are a cross-sectional view and a band diagram of a transistor according to the present invention; [Figure 10] 1 is a cross-sectional view of a transistor according to the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view of a transistor according to the present invention; [Figure 12] 1A and 1B are a top view and a cross-sectional view of a transistor according to the present invention; [Figure 13] 1A and 1B are a top view and a cross-sectional view of a transistor according to the present invention; [Figure 14] 1A to 1C illustrate a method for manufacturing a transistor according to the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a transistor according to the present invention. [Figure 16] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 17] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 18] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 19] Electron diffraction pattern of CAAC-OS. [Figure 20] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 21] 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to the present invention. [Figure 22] 1 is a cross-sectional view of a semiconductor device according to the present invention. [Figure 23] 1 is a top view showing a semiconductor device according to the present invention; [Figure 24] 1A and 1B are a top view and a block diagram showing a semiconductor device according to the present invention; [Diagram 25] 1 is a cross-sectional view showing a semiconductor device according to the present invention. [Figure 26] 1 is a cross-sectional view showing a semiconductor device according to the present invention. [Figure 27] 1 is a cross-sectional view showing a semiconductor device according to the present invention. [Figure 28] 1A and 1B are a perspective view and a cross-sectional view showing a semiconductor device according to the present invention; [Figure 29] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to the present invention. [Diagram 30] 1A and 1B are a circuit diagram and a cross-sectional view showing a semiconductor device according to the present invention; [Diagram 31] 1 shows an example of the configuration of an RF tag according to the present invention. [Diagram 32] 1 is a block diagram of a semiconductor device according to the present invention; [Diagram 33] FIG. 1 is a circuit diagram illustrating a memory device according to the present invention. [Diagram 34] 1A and 1B are a top view and a circuit diagram of a display device according to the present invention. [Diagram 35] 1A and 1B are diagrams illustrating examples of electronic devices according to the present invention. [Diagram 36] 1 shows an example of the use of an RF tag according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not to be construed as being limited to the description in the form of the above.

[0020] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals may be used in common between different drawings, and repeated explanations may be omitted. In addition, when referring to similar functions, the hatch pattern will be the same and no particular symbol will be added. There is.

[0021] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it in a variety of ways.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0023] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0024] A transistor is a type of semiconductor device that amplifies current and voltage and controls conduction or non-conduction. In this specification, the transistor can realize a switching operation such as IGFET(Insulated Gate Field Effect Transi) stor) and thin film transistor (TFT) Includes.

[0025] The terms "film" and "layer" can be used interchangeably. For example, if it is possible to change the term "conductive layer" to the term "conductive film" Alternatively, for example, the term "insulating film" may be changed to the term "insulating layer." It may be possible to do so.

[0026] Unless otherwise specified, in this specification, the off-state current refers to the current that flows when a transistor is in an off state. (also called non-conducting or cut-off state). The off state is Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, Vgs is lower than the threshold voltage Vth. In a p-channel transistor, the gate and source This refers to a state in which the voltage Vgs between the gates is higher than the threshold voltage Vth. For example, The off-state current of a transistor is the time when the voltage between the gate and source, Vgs, is lower than the threshold voltage, Vth. It may refer to the drain current when it is lower than the

[0027] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the off-state current at a given Vgs. Off-state at Vgs within a given range or sufficiently reduced off-current is obtained It may refer to the off-state current at Vgs, etc.

[0028] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs of -0.5 V is 1×10 -19 A and Vgs The drain current at -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 A or below Therefore, the off-state current of the transistor is 1×10-19 There are cases where it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 There are cases where it is A or lower.

[0029] In this specification, the off-state current of a transistor having a channel width W is expressed as It may be expressed as the current value that flows. It may also be expressed as the current that flows per a given channel width (for example, 1 μm). In the latter case, the unit of the off-state current is a unit with the dimensions of current / length. It is sometimes expressed in units (e.g., A / μm).

[0030] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off-state current is measured at room temperature, 60℃, 85℃, 95℃, or 125℃. Or, the reliability of the semiconductor device that contains the transistor may be in doubt. or the temperature at which a semiconductor device or the like that includes the transistor is used (for example, For example, the off-state current at any one of temperatures from 5°C to 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor is The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I. There are cases where it is pointed out.

[0031] The off-state current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may represent the off-state current at 20 V. Or, the semiconductor including the transistor Vds that guarantees the reliability of devices, etc., or semiconductor devices that include the transistor The off-state current of a transistor may be expressed as the off-state current at the Vds used in the The current is less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2 .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is included, or Vds used in the device, etc., Vg at which the off-state current of the transistor is I or less It may refer to the existence of a value of s.

[0032] In this specification, the term "leakage current" may be used to mean the same thing as the off-state current.

[0033] In this specification, the off-state current is, for example, the current that flows through a source when a transistor is in an off state. It can also refer to the current that flows between the source and drain.

[0034] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0035] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0036] (Embodiment 1) In this embodiment, the configuration and operation of a semiconductor device having a semiconductor, an electron capture layer, and a gate electrode are described. The principle and the circuit that applies it are explained. Figure 1 (A) shows a semiconductor 101 and an electron capture A semiconductor having a gate electrode 103, a gate insulator 104, and a gate electrode 105. It is a body device.

[0037] Here, the electron capture layer 102 may be, for example, an insulator 102 as shown in FIG. Alternatively, the insulating layer 102 may be a laminate of the insulating layer 102a and the insulating layer 102b, as shown in FIG. Alternatively, the insulating layer 102 may be a laminate of the insulating layer 102a, the insulating layer 102b and the insulating layer 102c. Alternatively, as shown in FIG. 2, the electron capture layer 102 may be a stack of insulators 102. The insulator 102 may have an electrically isolated conductor 102d in the insulator 102e. 02e may be formed from a plurality of insulators.

[0038] For example, an example of a band diagram from point A to point B of the semiconductor device shown in FIG. 1(B) is shown in FIG. In the figure, Ec is the energy at the bottom of the conduction band, and Ev is the energy at the top of the valence band. In FIG. 3(A), the potential of the gate electrode 103 is the source electrode or the drain electrode (either (not shown).

[0039] In this example, the energy gap of insulator 102a is equal to the energy gap of insulator 102b. The electron affinity of the insulator 102a is larger than that of the insulator 102b. It is assumed to be smaller than, but not limited to,

[0040] The interface between the insulator 102a and the insulator 102b and / or the inside of the insulator 102b may be electrically connected. The potential of the gate electrode 103 is set to the potential of the source electrode or the drain electrode. If the potential of the gate electrode 103 is set higher than that of the electrode, the potential becomes as shown in FIG. The source electrode or drain electrode may be set to a potential of 1 V or more. It may be lower than the highest potential subsequently applied to the gate electrode 105. Typically, it is less than 4V. It would be better to write it as follows.

[0041] At this time, the potential of the gate electrode 105 is the same as that of the source electrode or the drain electrode. The electrons 107 present in the semiconductor 101 move in the direction of the gate electrode 103 having a higher potential. Then, the electrons that move from the semiconductor 101 toward the gate electrode 103 Some of the electrons 107 are captured by the electron capture level 106 .

[0042] It takes several The first process is the tunnel effect. The tunnel effect occurs when an insulator However, in this case, the electrons trapped in the electron trap level 106 are The child may be lost again due to the tunnel effect.

[0043] By applying an appropriate voltage to the gate electrode 103, the insulator 102a becomes relatively Even if the material is relatively thick, the tunnel effect (Fowler-Nordheim tunnel effect) is observed. In the case of the Fowler-Nordheim tunneling effect, the gate When the electric field between the electrode 103 and the semiconductor 101 becomes stronger, the tunnel current increases rapidly.

[0044] Second, the electron 107 enters a trap level in the energy gap, such as a defect level in the insulator 102a. The electrons hop from one position to another and reach the insulator 102b. This is a conduction mechanism called Frenkel conduction. The higher the absolute temperature, the shallower the capture level. As a result, electrical conductivity increases.

[0045] The third is that electrons 107 cross the barrier of the insulator 102a due to thermal excitation. The distribution of electrons in the semiconductor 101 follows the Fermi-Dirac distribution, generally The ratio of high energy electrons increases with increasing temperature. For example, When the density of electrons with energy 3 eV higher than the At 450K (177℃), it is 6×10 16 At 600K (327℃), it is 1.5×10 25 At 750K (477℃), it is 1.6×10 30 It becomes.

[0046] The process in which electrons 107 cross the barrier of the insulator 102a and move toward the gate electrode 103 It is believed that the above three processes and their combinations are responsible for the above. In the first and third processes, the current increases exponentially with increasing temperature.

[0047] The Fowler-Nordheim tunneling effect in the first process also occurs in the insulator 10 This is more likely to occur when the concentration of electrons in the thin part of the barrier layer (the part with high energy) is high. Therefore, the higher the temperature, the more advantageous it is.

[0048] In addition, the current flowing in the above process is particularly large when the potential of the gate electrode 103 is low (5 V or less). Although the electrons are often very weak, they can be used for a long period of time to produce the required amount of electrons. As a result, the electron trapping layer 102 becomes negatively charged. do.

[0049] That is, at higher temperatures (higher than the operating or storage temperatures of the semiconductor device, or 125°C to 450°C, typically 150°C to 300°C) The potential of the electrode 103 is kept higher than the potential of the source or drain for 5 milliseconds or more and for less than 10 seconds. By maintaining the current for a period of time, typically for 3 seconds or more, the current is transferred from the semiconductor 101 to the gate electrode 103. Then, the required electrons are transferred, some of which are captured by the electron capture level 106. The temperature for such a process of capturing electrons is hereinafter referred to as the process temperature.

[0050] At this time, the amount of electrons captured by the electron capture level 106 is controlled by the potential of the gate electrode 103. When a certain amount of electrons are captured in the electron capture level 106, the gate The electric field of the gate electrode 103 is blocked, and the channel formed in the semiconductor 101 disappears.

[0051] The total amount of electrons captured by the electron capture level 106 increases linearly at first, but gradually The rate of increase decreases and eventually converges to a constant value. The higher the potential, the more electrons are captured. The total number of the numbers cannot exceed 6.

[0052] It is required that the electrons trapped in the electron trap level 106 do not flow out of the electron trap layer 102. To this end, first, the thickness of the insulator 102a and the insulator 102b is set to be equal to or larger than the thickness of the tunnel. It is preferable that the thickness is such that the holing effect is not a problem. For example, the physical thickness is 1n It is preferable that it is greater than m.

[0053] Typically, the thickness of the insulator 102a is 10 nm or more and 20 nm or less, and the thickness of the insulator 102b is The thickness in terms of silicon oxide is set to 10 nm or more and 25 nm or less.

[0054] In addition, by sufficiently lowering the operating temperature or storage temperature of the semiconductor device, the electron capture level 10 For example, the processing temperature can be increased to 300 °C, and if the semiconductor device is stored at 120°C, what is the probability that an electron will overcome the 3 eV barrier? The latter is less than one hundred thousandth of the former.

[0055] In addition, in the semiconductor 101, the effective mass of the holes is extremely large or substantially localized. In this case, the semiconductor 101 is effectively covered with the insulator 102a and the insulator 102b. There is no hole injection into electron trap level 102b, and therefore the electrons trapped in electron trap level 106 are It also does not disappear by combining with the ionizing radiation.

[0056] Alternatively, the insulator 102b may be a material that exhibits Poole-Frenkel conduction. As mentioned above, Poole-Frenkel conduction is a phenomenon in which electrons hop between defect levels in a material. Materials with many or deep defect levels do not conduct electricity well. It has low conductivity and can hold the electrons captured in the electron capture level 106 for a long period of time.

[0057] In addition, the insulator 102a and / or the insulator 102b may be configured to emit electrons trapped therein. The circuit design and / or material selection may be performed so that excessive voltage is not applied. For example, , the effective mass of holes is extremely large, such as in In-Ga-Zn oxide semiconductors, or In the case of a material that is substantially localized, the potential of the gate electrode 103 is When the potential is higher than the drain electrode, a channel is formed. When the potential is lower, the insulator In this case, the electric field between the gate electrode 103 and the semiconductor 101 is extremely This causes the Fowler-Nordheim tunneling effect, or Poole-F Electronic conduction due to Renkel conduction is significantly reduced.

[0058] As shown in FIG. 1C, the electron capture layer 102 is formed of three layers of insulators. The electron affinity of the insulator 102c is set to be smaller than the electron affinity of the insulator 102b. If the energy gap of the insulator 102b is made larger than the energy gap of the insulator 102b, The electrons trapped in the electron trap level in 2b or at the interface with other insulators are held It is effective in

[0059] In this case, even if the insulator 102b is thin, as long as the insulator 102c is physically thick enough, The insulator 102c can hold the electrons captured in the electron capture level 106. The same material as that of the insulator 102a can be used. However, it is also possible to use a material with a sufficiently small number of electron capture levels. varies depending on the formation method.

[0060] In addition, in the case of having an electrically insulated conductor 102d in an insulator 102e as shown in FIG. In this case, electrons are captured by the conductor 102d by the same principle as above. Although the trap layer is a conductor, a semiconductor may be used. The potential is the same as that of the source or drain electrode.

[0061] When the potential of the gate electrode 103 is made higher than that of the source electrode or the drain electrode, as shown in FIG. The electrons 107 present in the semiconductor 101 are attracted to the gate electrode 102, which has a higher potential. 103. Then, the electron moves from the semiconductor 101 toward the gate electrode 103. Some of the transferred electrons 107 are captured by the conductor 102d. In the semiconductor device, the conductor 102d is the electron trap quasi-electron ... It has the same function as position 106.

[0062] If the work function of the conductor 102d is large, an energy barrier between the conductor 102d and the insulator 102e is large. Therefore, the electrons trapped in the electron trap level 106 can be prevented from flowing out.

[0063] In the above, the insulators 102a, 102b, and 102c are each a plurality of insulators. Alternatively, the insulating layer may be made of multiple insulating materials that are made of the same constituent elements but formed by different methods. The insulating layer 20 may be made of a metal.

[0064] For example, the insulators 102a and 102b may be made of insulators made of the same constituent elements (e.g., oxides). When the insulator 102a is made of hafnium oxide, the insulator 102a is formed by CVD or ALD (atomic deposition). The insulator 102b is formed by sputtering. Alternatively, the insulating layer 14 may be formed by a bonding method.

[0065] As the CVD method, various methods can be used. Methods such as plasma CVD, MOCVD, and LPCVD can be used. Even if different CVD methods are used to form one insulator and another insulator, good.

[0066] Insulators formed by sputtering are generally made by CVD or ALD. For the same reason, the insulator 102b has more defects and is more likely to capture electrons than the insulator 102b. When the insulator 102b and the insulator 102c are made of insulators made of the same constituent elements, the insulator 102b is The insulating layer 102c may be formed by a CVD or ALD method. .

[0067] In addition, when the insulator 102b is composed of a plurality of insulators made of the same constituent elements, One is formed by sputtering, and the other is formed by CVD or ALD. good.

[0068] When the electron trap layer 102 traps electrons in this manner, the semiconductor device is The threshold voltage becomes higher. In particular, the semiconductor 101 is a material with a large energy gap ( When the gate electrode 103 and the gate electrode 105 are a low energy gap semiconductor, The current between the source and drain when the potential is set to 0 V can be significantly reduced. .

[0069] For example, in the case of an In-Ga-Zn oxide semiconductor with an energy gap of 3.2 eV, When the potential of the gate electrode 103 and the gate electrode 105 is set to 0V, The current density (current value per 1 μm of channel width) is 1 zA / μm (1 × 10-21 A / μ m) or less, typically 1yA / μm (1×10 -24 A / μm or less.

[0070] FIG. 4A shows the state before and after electron capture in the electron capture layer 102. The current per 1 μm of channel width (Id / μm) between the source and drain electrodes at room temperature 1 is a schematic diagram showing the potential (Vg) dependence of the source electrode 105. The potential of the gate electrode 103 is set to 0 V, and the potential of the drain electrode is set to +1 V. Although it is difficult to measure the current directly, the value measured by other methods and the SS value ( Subthreshold Swing value) can be used as a basis for estimation.

[0071] Initially, as shown by curve 108, the threshold voltage of the semiconductor device is Vth1. After the trapping, the threshold voltage increases (shifts in the positive direction) and Vth2 As a result, the current density at Vg = 0 is 1aA / μm (1×10 -18 A / μ m) or less, for example, 1 yA / μm or more and 1 zA / μm or less.

[0072] For example, as shown in FIG. 4B, the charge stored in the capacitor 111 is transferred to the transistor 110. Consider the control circuit. Here, the leakage current between the electrodes of the capacitance element 111 is ignored. The capacitance of the element 111 is 1 fF, and the potential of the capacitance element 111 on the transistor 110 side is +1 Assume that the potentials of V and Vd are 0V.

[0073] The Id-Vg characteristic of the transistor 110 is shown by the curve 108 in FIG. When the channel width is 0.1 μm, the potential of the gate electrode 103 and the gate electrode 105 is set to 0 V. The current density between the source and drain of the transistor 110 is about 1 fA. The resistance at this time is about 1×10 15 Ω. Therefore, the transistor 110 and the capacitance element The time constant of the circuit including the capacitor 111 is about 1 second. This means that much of the stored charge is lost.

[0074] The Id-Vg characteristic of the transistor 110 is shown by the curve 109 in FIG. When the channel width is 0.1 μm, the potential of the gate electrode 103 and the gate electrode 105 is set to 0 V. The current density between the source and drain of the transistor 110 is about 1 yA. The resistance at this time is about 1×10 24 Ω. Therefore, the transistor 110 and the capacitance element The time constant of the circuit consisting of the resistor 111 is about 1 × 10 9 seconds (= about 31 years). That is, 10 This means that even after years have passed, 1 / 3 of the charge stored in the capacitance element 111 remains. do.

[0075] In other words, a simple circuit consisting of a transistor and a capacitor can hold a charge for 10 years. This can be used in a variety of storage devices.

[0076] (Embodiment 2) In this embodiment, a structure of a transistor according to one embodiment of the present invention will be described with reference to drawings. .

[0077] 5A to 5C are top views and cross-sectional views of a transistor of one embodiment of the present invention. FIG. 5(A) is a top view, and FIG. 5(B) is a cross section taken along the dashed line AB shown in FIG. 5(A). The cross section of the dashed line CD corresponds to FIG. 5(C). For clarity, some elements are omitted. The direction of the dashed line AB is the channel length. The direction indicated by the dashed dotted line CD may be referred to as the channel width direction.

[0078] The transistors shown in FIGS. 5A to 5C are formed by forming an insulator 602 on a substrate 600 and insulating An insulator 604 is disposed on the substrate 602, a gate electrode 606 is embedded in the insulator 604, and An insulator 608 is formed on the gate electrode 604 and the gate electrode 606, and an electron trapping layer 610 is formed on the insulator 608. An insulator 612 is formed on the insulator 608 and the electron capture layer 610, and an oxide layer is formed on the insulator 612. A source electrode 616a and a drain electrode 616b are formed on the oxide semiconductor 614. 6b, on the oxide semiconductor 614, on the source electrode 616a, and on the drain electrode 616b. The gate insulator 618 is in contact with the top surface of the oxide semiconductor 614 and the A gate electrode 620 facing the side, a gate electrode 620 on the insulator 612, a source electrode 616a on the drain electrode 616b, and a gate electrode 620 on the insulator 612. and an insulator 622 on the electrode 616b and on the gate electrode 620.

[0079] The oxide semiconductor 614 has a channel formation region 650. The channel formation region 650 is an insulating The gate electrode 606 has an area overlapping the electron capture layer 610 via an insulating layer 612. The gate electrode 606 has an area overlapping the electron capture layer 610 through the body 608. There is no region overlapping with the channel forming region 650 .

[0080] As explained in the first embodiment, this transistor operates by applying a current to the gate electrode 606. By applying a voltage, electrons are injected into the electron trap layer 610, thereby lowering the threshold voltage of the transistor. By applying a voltage to the gate electrode 606, a channel is formed. Region 650 and the gate insulator 618 that overlaps channel forming region 650 are not degraded.

[0081] When the gate electrode 606 and the channel forming region 650 overlap each other, the gate electrode 60 Applying a voltage to 6 causes the Fowler-Nordheim tunnel effect. The Fowler-Nordheim tunneling effect occurs when the gate electrode 606 and the channel forming region When the electric field between the regions 650 becomes stronger, the tunnel current increases rapidly. The number of defects in the growth region 650 may increase, resulting in an increase in electron traps. Similarly, in the gate insulator 618 overlapping the formation region 650, the number of electron traps due to the increase in defects is increased. This may cause instability in transistor characteristics and reduced reliability. There is a gender.

[0082] According to the present invention, as shown in FIG. 5B, a gate electrode 606, a channel forming region 650, However, by arranging them so that they do not overlap each other, the above problems can be avoided. This is explained below.

[0083] The gate electrode 606 and the electron capture layer 610 overlap each other, forming a gate A voltage can be applied to the electrode 606 to inject electrons into the electron trapping layer 610. The electron trapping layer 610 and the channel forming region 650 overlap each other, so that the electron trapping layer 610 and the channel forming region 650 overlap each other. It is possible to control the threshold voltage of the transistor according to the amount of electrons injected into the capture layer 610. Therefore, the gate electrode 606 and the channel forming region 650 do not overlap each other. By doing so, it is possible to avoid the above-mentioned problems and control the threshold voltage of the transistor. It becomes Noh.

[0084] In the present invention, the electron trapping layer 610 is formed by using an electron trapping Conductors capable of moving through layer 610 and the interface between electron capture layer 610 and insulator 608 The threshold voltage of a transistor can be controlled by using a conductive material or a semiconductor. The conductive materials are tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum. In addition, a tungsten-butanol alloy or the like can be used. It is used as a multilayer film by appropriately combining it with tantalum nitride, tungsten nitride, titanium nitride, etc. The semiconductor may be polycrystalline silicon, microcrystalline silicon, amorphous silicon, or oxide semiconductor. For example, the oxide semiconductor 614 used in this transistor can be used. When an oxide semiconductor is used as the electron trap layer 610, If the insulator 612 has excess oxygen, excess oxygen may be transferred from the insulator 612 to the electron trapping layer 610. This is preferable since it can prevent the diffusion of oxygen.

[0085] As shown in FIGS. 6A and 6B, the electron capture layer 610 is alternately connected to the drain electrode 616b. Alternatively, the gate electrode 606b may be newly disposed so as to extend to the region where the gate electrode 606b overlaps the gate electrode 606b. The electron capture layer 610 may be disposed in an overlapping region with the drain electrode 616b. As shown in FIG. 6C, the gate electrode 606 is connected to the drain electrode 616b and the electron capture layer 616c. 610 and 611 may be placed only in the area where they overlap.

[0086] As shown in FIGS. 7A and 7C, a gate electrode 606 and a channel forming region 650 The non-overlapping regions may occupy approximately half of the channel formation region.

[0087] Also, in FIG. 5, the gate electrode 606 and the electron trapping layer 610 are mutually connected to the source electrode 616a. Although an example having overlapping regions is shown, the gate electrode 606 and the electron trapping layer 610 are The pole 616b may have an overlapping area with the pole 616b (see Figs. 7(B) and (C)).

[0088] As shown in FIGS. 8A and 8B, the gate electrode 606 is It may not have an area overlapping with the source electrode 616a or the drain electrode 616b.

[0089] Next, transistors in which the oxide semiconductor 614 has a different structure will be described. Please refer to the above for the configuration.

[0090] FIG. 9A is a cross-sectional view in the channel length direction, similar to the transistor shown in FIG. 5B. FIG. 9B shows a cross-sectional view in the channel width direction of the transistor shown in FIG. FIG.

[0091] In the transistor structure shown in FIG. 9(A) and FIG. 9(B), an insulator 612 and an oxide semiconductor An oxide semiconductor 614a is disposed between the insulator 612 and the conductor 614. The electrode 616a or the drain electrode 616b, the oxide semiconductor 614a and the oxide semiconductor An oxide semiconductor 614 c is disposed between the gate insulator 614 and the gate insulator 618 .

[0092] The oxide semiconductor 614 is, for example, an oxide semiconductor containing indium. For example, when 14 contains indium, the carrier mobility (electron mobility) is increased. The oxide semiconductor 614 preferably contains an element M. The element M is preferably aluminum. Other elements that can be used for element M include boron, gallium, and tin. silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum Lithium, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. However, there are cases where the element M may be a combination of multiple elements. The element M is, for example, an element that has a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M is, for example, an oxide semiconductor. The oxide semiconductor 614 is an element having a function of increasing the energy gap. It is preferable that the oxide semiconductor contains zinc. When the oxide semiconductor contains zinc, it may be easily crystallized. .

[0093] However, the oxide semiconductor 614 is not limited to an oxide semiconductor containing indium. The semiconductor 614 may be, for example, an indium-containing material such as zinc tin oxide or gallium tin oxide. First, oxide semiconductors containing zinc, oxide semiconductors containing gallium, and oxide semiconductors containing tin etc. are also acceptable.

[0094] The oxide semiconductor 614 is, for example, an oxide having a wide energy gap. The energy gap of the conductor 614 is, for example, 2.5 eV or more and 4.2 eV or less, preferably is set to 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0095] For example, the oxide semiconductor 614a and the oxide semiconductor 614c constitute the oxide semiconductor 614. It is an oxide semiconductor composed of one or more elements other than oxygen. The oxide semiconductor 614 is made of one or more elements other than oxygen. Since the oxide semiconductor 614a and the oxide semiconductor 614c are formed, At the interface with the oxide semiconductor 614 and the interface between the oxide semiconductor 614 and the oxide semiconductor 614c, Therefore, defect levels are unlikely to be formed.

[0096] The oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor 614c are at least It is preferable that the oxide semiconductor 614a contains indium. When the sum of In and M is 100 atomic %, In is preferably 50 atomic %. mic%, M is higher than 50 atomic %, and more preferably In is 25 atomic %. % or less, and M is higher than 75 atomic %. In the case of M-Zn oxide, when the sum of In and M is 100 atomic %, it is preferable Preferably, In is greater than 25 atomic % and M is less than 75 atomic %, and more preferably In is higher than 34 atomic % and M is less than 66 atomic %. When the compound semiconductor 614c is an In-M-Zn oxide, the sum of In and M is 100 atoms. c%, it is preferable that In is less than 50 atomic % and M is more than 50 atomic %. More preferably, In is less than 25 atomic % and M is more than 75 atomic %. Note that the oxide semiconductor 614c is made of the same oxide as the oxide semiconductor 614a. However, the oxide semiconductor 614a and / or the oxide semiconductor 614c may be an indium tin oxide. For example, the oxide semiconductor 614a and / or The oxide semiconductor 614c may be gallium oxide. 4a, the number of atoms of each element contained in the oxide semiconductor 614 and the oxide semiconductor 614c is It does not have to be a simple integer ratio.

[0097] The oxide semiconductor 614 has a higher electron affinity than the oxide semiconductor 614a and the oxide semiconductor 614c. For example, the oxide semiconductor 614 is an oxide having a large sum of the electrons. and the oxide semiconductor 614c, the oxide semiconductor 614c has an electron affinity of 0.07 eV or more and 1.3 eV or less. Preferably, the value is 0.1 eV or more and 0.7 eV or less, and more preferably, the value is 0.15 eV or more and 0.4 eV or less. The electron affinity is calculated by the relationship between the vacuum level and the energy at the bottom of the conduction band. This is the difference.

[0098] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the oxide semiconductor 614c preferably contains indium gallium oxide. The atomic ratio of In atoms [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. , and more preferably 90% or more.

[0099] At this time, when a gate voltage is applied, the oxide semiconductor 614a, the oxide semiconductor 614, and the oxide A channel is formed in the oxide semiconductor 614 having a large electron affinity among the oxide semiconductors 614c. do.

[0100] Here, the oxide semiconductor 614a is provided between the oxide semiconductor 614a and the oxide semiconductor 614. In some cases, the oxide semiconductor 614 and the oxide semiconductor 615 are mixed. A mixed region of the oxide semiconductor 614 and the oxide semiconductor 614c is formed between the oxide semiconductor 614 and the oxide semiconductor 614c. The mixed region has a low density of defect states. The stack of the oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor 614c is In the vicinity of the junction, the energy changes continuously (also called a continuous junction). Note that the oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor In the conductors 614c, it may be difficult to clearly distinguish the boundaries between them.

[0101] At this time, the electrons are transferred to the oxide semiconductor 614a and the oxide semiconductor 614c, but not to the oxide semiconductor 614b. As described above, the electrons move mainly through the oxide semiconductor 614a and the oxide semiconductor 614b. The defect state density at the interface of the oxide semiconductor 614 and the oxide semiconductor 614 By reducing the defect state density at the interface with 14c, The movement of electrons is not hindered much, which makes it possible to increase the on-state current of the transistor. .

[0102] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. For example, if there are no factors that impede the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel formation region is large. will be done.

[0103] In order to increase the on-state current of the transistor, for example, The lower surface (the surface to be formed, here the oxide semiconductor 614a) is Root Mean Square (RMS) roughness is less than 1 nm, preferably Preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the range of 1 μm × 1 μm is 1 nm or less, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably The maximum height difference (P- V) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm; More preferably, it is less than 7 nm. RMS roughness, Ra and PV are Scanning probe microscope system SPA-500 manufactured by Lee Nano Technology Co., Ltd. It can be measured by

[0104] Alternatively, for example, when the density of defect states in the region where the channel is formed is high, the electron transfer Movement is hindered.

[0105] For example, if the oxide semiconductor 614 has an oxygen vacancy (V O If the sample has an oxygen deficiency, Hydrogen can enter the nucleus and form a donor level. The state in which hydrogen has entered the O It may be written as H. V O H scatters electrons This causes a decrease in the on-state current of the transistor. Therefore, the oxygen vacancies in the oxide semiconductor 614 are reduced. By reducing the gate insulating film, the on-state current of a transistor can be increased in some cases.

[0106] In addition, if the density of defect states in the region where the channel is formed is high, the electrical characteristics of the transistor are adversely affected. For example, when a defect level is a carrier generation source, The threshold voltage may be varied.

[0107] In order to reduce oxygen vacancies in the oxide semiconductor 614, for example, the excess oxygen in the insulator 612 is For example, oxygen may be transferred to the oxide semiconductor 614 via the oxide semiconductor 614a. In this case, the oxide semiconductor 614a is a layer having oxygen permeability (a layer that passes or transmits oxygen). It is preferable that the layer is a layer in which the light is reflected.

[0108] In order to increase the on-state current of the transistor, the thickness of the oxide semiconductor 614c is small. For example, it is preferably less than 10 nm, more preferably 5 nm or less, and even more preferably 3 nm or less. On the other hand, the oxide semiconductor 614c may have a region having a thickness of 100 nm or less. The oxide semiconductor 614 in which the channel is formed is formed by introducing oxygen other than oxygen constituting the adjacent insulator. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. The oxide semiconductor 614c preferably has a certain thickness. For example, the oxide semiconductor 614c has a thickness of 0.3 nm. or more, preferably 1 nm or more, and more preferably 2 nm or more. The oxide semiconductor 614c may be a semiconductor 614c. In order to suppress the outward diffusion of oxygen, it is preferable that the material has an oxygen blocking property. .

[0109] In order to increase reliability, the oxide semiconductor 614a is thick and the oxide semiconductor 614c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably The oxide semiconductor 61 has a region having a thickness of at least 40 nm, more preferably at least 60 nm. By increasing the thickness of the oxide semiconductor 614a, Distance from the interface with the oxide semiconductor 614a to the oxide semiconductor 614 where a channel is formed However, the productivity of the semiconductor device may decrease. A region having a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The oxide semiconductor 614a may have a SiO 2 region.

[0110] For example, a secondary ion mass spectrometry is performed between the oxide semiconductor 614 and the oxide semiconductor 614a. Analysis method (SIMS: Secondary Ion Mass Spectrometry) ) at 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 below , and more preferably 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The oxide semiconductor 614 and the oxide semiconductor 6 Between 14c and 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 2×1 or more 0 18 atoms / cm 3 The silicon concentration in the region is as follows:

[0111] In order to reduce the hydrogen concentration in the oxide semiconductor 614, It is preferable to reduce the hydrogen concentration in the oxide semiconductor 614a and the oxide semiconductor 614c. The compound semiconductor 614c has a SIMS resolution of 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 1x or more 10 19 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 Below top 5×10 18 atoms / cm 3 The hydrogen concentration in the oxide semiconductor layer is as follows: In order to reduce the nitrogen concentration in the conductor 614, the oxide semiconductor 614a and the oxide semiconductor 61 It is preferable to reduce the nitrogen concentration in the oxide semiconductor 614a and the oxide semiconductor 614c. c is 1×10 15 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than or equal to 1×10 15atoms / cm 3 More than 1×10 18 ato ms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0112] The above-described three-layer structure is an example. For example, the oxide semiconductor 614 and the oxide semiconductor 614a Alternatively, a two-layer structure of an oxide semiconductor 614 and an oxide semiconductor 614c may be used. Alternatively, the oxide semiconductor 614a may be formed on or under the oxide semiconductor 614c. The oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor 614c are shown in FIG. Alternatively, the semiconductor layer may have a four-layer structure having any one of the semiconductors exemplified above. The oxide semiconductor 614c is disposed on the oxide semiconductor 614a. The oxide semiconductor 614c is disposed on the oxide semiconductor 614a. The oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor 614c are disposed in two or more locations below the oxide semiconductor 614a, the oxide semiconductor 614, and the oxide semiconductor 614c. and an n-layer structure (n is 5 or more) having any one of the semiconductors exemplified as the oxide semiconductor 614c. It is also acceptable to use the integer above.

[0113] Here, a transistor having a different structure from that shown in FIG. 9(A)(B) is described. The following description will be given using B) for other configurations.

[0114] As shown in FIGS. 10(A) and 10(B), the insulator 612 is etched to thin areas. The structure of the transistor in FIG. 6 differs from that of the transistor in FIG. 9A and FIG. 9B in that the oxide semiconductor 6 By leaving the oxide semiconductor 614 in the region not overlapping the oxide semiconductor 614, the insulator 61 By applying a voltage to the gate electrode 606, the electron trap layer 610 However, if the thickness of the insulator 612 becomes thin, the electrostatic breakdown of the insulator 612 may occur. This may cause defects such as breakdown and electron trapping. The remaining oxide semiconductor 614a is Although not shown in the figure, after the gate electrode 620 is formed, the gate insulator 618 and the oxide semiconductor 61 4c, and the unnecessary parts are removed. In this way, the same characteristics as those of a transistor using an oxide semiconductor layer can be obtained.

[0115] Next, a configuration different from that of the transistor shown in FIG. 5 will be described with reference to FIG. For other configurations, please refer to the above.

[0116] FIG. 11(A) is a top view, and FIG. 11(B) is a cross section taken along a dashed line AB shown in FIG. 11(A). , the cross section of the dashed line CD corresponds to FIG. 11(C). Note that in the top view of FIG. 11(A), In order to clarify the figure, some elements have been omitted. The direction indicated by the dashed dotted line CD may be referred to as the channel length direction, and the direction indicated by the dashed dotted line CD may be referred to as the channel width direction.

[0117] As shown in FIG. 11(A) and (B), a gate electrode 620 and a source electrode 616a or The transistor shown in FIG. 5 has no overlapping area with the drain electrode 616b. This is different from the structure of the stadium.

[0118] The gate electrode 620 and the source electrode 616a or the drain electrode 616b overlap each other. By not having an overlapping area, the gate electrode 620 and the source electrode 616a or the drain electrode Since there is no parasitic capacitance between the electrodes of the pole 616b, this is favorable for high speed operation of the transistor. In addition, between the gate electrode 620 and the source electrode 616a or the drain electrode 616b This can prevent current leakage.

[0119] Next, regarding a transistor having a different arrangement of the electron capture layer 610 from that of the transistor in FIG. The following description will be given with reference to FIG. 12. FIG. 12(A) is a top view, and the dashed line A in FIG. The cross section of -B corresponds to FIG. 12(B), and the cross section of the dashed line CD corresponds to FIG. 12(C). In the top view of FIG. 12(A), some elements are omitted for clarity. The direction of the dashed dotted line AB is called the channel length direction, and the direction of the dashed dotted line CD is called the channel width direction. There are cases.

[0120] As shown in FIGS. 12A and 12B, the electron trap layer 610 is in contact with the gate electrode 620. 11 in that they have overlapping regions, but the end of the gate electrode 620 and , the end of the electron trap layer 610 and the position of the electron trap layer 610 coincide with each other.

[0121] Similar to the transistor shown in FIG. 11, a gate electrode 620 and a source electrode 616a or The drain electrode 616b and the gate electrode 620 do not overlap each other. Since there is no parasitic capacitance between the source electrode 616a or the drain electrode 616b, This is preferable for high speed operation of the transistor. Alternatively, current leakage between the drain electrodes 616b can be prevented.

[0122] Next, a configuration different from that of the transistor shown in FIG. 5 will be described with reference to FIG. 13(A) is a top view, and FIG. 13(B) is a cross section taken along the dashed line AB shown in FIG. 13(A). The cross section of the dashed line CD corresponds to FIG. 13(C). For clarity, some elements are omitted. The direction of the dashed line AB is the channel The longitudinal direction, or the direction of the dashed dotted line CD, may be referred to as the channel width direction.

[0123] The transistors shown in FIGS. 13A to 13C include an insulator 602 and a An insulator 604 is disposed on the insulator 602, a gate electrode 606 is embedded in the insulator 604, and an insulating film 605 is disposed on the insulator 602. An insulator 612 is formed on the insulator 604 and the gate electrode 606, and an oxide semiconductor is formed on the insulator 612. 614, a source electrode 616a and a drain electrode 616b on the oxide semiconductor 614, On the insulator 612, on the oxide semiconductor 614, on the source electrode 616a and on the drain electrode 61 6b, a gate insulator 618, an electron trapping layer 610 on the gate insulator 618, and an electron trapping An insulator 608 on layer 610 and on gate insulator 618, and a gate electrode on insulator 608. 620 and an insulator 622 on the gate electrode 620 and on the insulator 608 .

[0124] The oxide semiconductor 614 has a channel formation region 650. The gate electrode 620 has a region overlapping the electron trap layer 610 via the gate insulator 618. 608 and the electron trap layer 610 overlap each other. 0 does not have an area overlapping with the channel forming region 650.

[0125] The transistor shown in FIG. 13 has a gate electrode 62 for injecting electrons into the electron trap layer 610. 5 in that a voltage is applied to the gate electrode 620. By adding the above, the threshold voltage of the transistor is controlled by injecting electrons into the electron trap layer 610. By applying a voltage to the gate electrode 620, the channel forming region 6 50 and does not degrade the gate insulator 618 that overlaps the channel forming region 650 .

[0126] The operating principle of this transistor is described in the first embodiment and the transistor shown in FIG. I will take part.

[0127] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. For example, a channel formation region of a transistor may include an oxide semiconductor. Although an example in which the transistor includes an oxide semiconductor such as the oxide semiconductor 614 has been described, One embodiment of the present invention is not limited thereto. Various transistors in one embodiment of the present invention are The various transistors in one aspect of the present invention may include, for example, For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, Aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors For example, various transistors according to an embodiment of the present invention may have at least one of the following: The transistor does not necessarily have to include an oxide semiconductor.

[0128] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0129] (Embodiment 3) In this embodiment, the method for manufacturing the transistor in FIG. 5 described in Embodiment 2 will be described. This will be explained with reference to FIG. 14 and FIG.

[0130] The cross section of the dashed line AB shown in FIG. 5(A) is shown on the left side of FIG. 14 and FIG. 15, and the cross section of the dashed line CD is shown on the right side of FIG. The cross section is shown on the right side of FIGS.

[0131] An insulator 602 is formed on a substrate 600. The substrate 600 is made of, for example, silicon or germanium. A single semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, Compound semiconductor substrates made of indium phosphide, zinc oxide, gallium oxide, etc. are used. Alternatively, an insulating substrate such as quartz or glass may be used. The body 602 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or a silicon nitride film. Silicon film, aluminum oxide film, aluminum nitride film, hafnium oxide film, etc. The film formation method can be thermal oxidation, CVD, sputtering, ALD, or plasma oxidation. , plasma nitridation, etc. can be used.

[0132] An insulator 604 is formed on the insulator 602, and an opening is formed in a part of the insulator 604. The opening of the insulator 604 is filled with a gate electrode 606 (see FIG. 14(A)). The structure is formed by forming a resist mask by photolithography and then etching the The insulator 604 is formed by removing unnecessary portions of the insulator. The gate electrode 606 is formed by sputtering. The film can be formed by using a method such as the CVD method, MBE method, PLD method, ALD method, plating method, etc. The gate electrode 606 is made of tantalum, tungsten, titanium, molybdenum, aluminum, etc. Aluminum, copper, molybdenum tungsten alloy, etc. can be used. It may be combined with titanium, tungsten nitride, titanium nitride, etc. to form a multilayer film. The method of embedding the electrode 606 in the opening is chemical mechanical polishing (CME). The best way to achieve this is to use Mechanical Polishing (CMP).

[0133] Next, an insulator 608 is formed on the gate electrode 606 and the insulator 604. The insulating layer 08 can be formed by the same film and deposition method as the insulating layer 602. A conductive or semiconductor film that will become an electron capture layer 610 is formed on the insulator 608. Using photolithography, a gate electrode is formed on a conductor or semiconductor that will become the electron capture layer 610. A resist mask is formed so as to have an area overlapping the electrode 606, and then dry etched. The unnecessary parts of the conductor or semiconductor are removed using a etching method to form the electron capture layer 610. Next, an insulator 612 is formed on the electron trap layer 610 and the insulator 608 (FIG. 14( See B). ).

[0134] The electron capture layer 610 can be made of a conductor or a semiconductor. The film may be formed by using a method such as the ring method, the CVD method, the MBE method, the PLD method, or the ALD method. The conductors are tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum, Ribbon tungsten alloys can be used. In addition, they have the function of being difficult for oxygen to permeate. It is combined with tantalum nitride, tungsten nitride, titanium nitride, etc. to form a multilayer film. The semiconductor may be formed by sputtering, CVD, MBE, PLD, or ALD. The semiconductor may be formed using polycrystalline silicon, microcrystalline silicon, or amorphous silicon. For example, crystalline silicon, an oxide semiconductor, or the like can be used.

[0135] The insulator 612 can be formed using a film similar to that of the insulator 602 described above and a film formation method similar to that of the insulator 602 described above. Alternatively, an insulator with excess oxygen may be used.

[0136] Next, an oxide semiconductor 613 is formed over the insulator 612 and subjected to heat treatment (see FIG. 14C). The oxide semiconductor 613 is formed by sputtering, CVD, MBE or PLD. The film may be formed by using an ALD method or the like. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The heat treatment may be performed at a temperature of 300° C. or higher and 500° C. or lower. The treatment is carried out in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under an inert gas atmosphere followed by To compensate for the oxygen that has been removed, the gas contains 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment can be performed in an atmosphere containing 100% oxygen. It is possible to increase the purity of the electrolyte and remove impurities such as hydrogen and water.

[0137] A conductor is formed over the oxide semiconductor 613 to form a channel formation region over the oxide semiconductor 613. A resist pattern is formed by photolithography on the part to be processed, and then the part is etched by dry etching. The conductor is then removed to form a conductor 615 (see FIG. 15(A)). The conductor 615 is The same film and film formation method as those for the gate electrode 606 can be used.

[0138] Next, a resist pattern is formed on the conductor 615 and the oxide semiconductor 613 by photolithography. A turn is formed, and unnecessary portions of the oxide semiconductor 613 are removed by dry etching. The semiconductor 614 is formed in an island shape. At the same time, a source electrode 616a and a drain electrode 6 16b is formed (see FIG. 15(B)).

[0139] Next, on the insulator 612, the source electrode 616a, the drain electrode 616b, and the oxide semiconductor A gate insulator 618 is deposited on the conductor 614. The gate insulator 618 may be any of the insulators described above. The same film and film formation method as those for 602 can be used.

[0140] A gate electrode 620 is formed on the gate insulator 618. The gate electrode 620 is The gate electrode 620 may be formed by the same film and film forming method as the gate electrode 606. The formation is performed by depositing a conductor that will become a gate electrode 620 on a gate insulator 618. A resist mask is formed on the surface by photolithography, and unnecessary parts are removed by dry etching. The conductor is removed to form a gate electrode 620 and a gate insulator 618. A resist mask is formed by photolithography, and non-contact etching is performed by dry etching. Remove the gate insulator 618 if necessary. Alternatively, the gate insulator 618 may not be removed. .

[0141] Next, on the insulator 612, the source electrode 616a, the drain electrode 616b, the gate insulator 6 An insulator 622 is formed on the semiconductor layer 18 and the gate electrode 620 (see FIG. 15(C)). The insulator 622 can be formed using a film similar to that of the insulator 602 described above and a film formation method similar to that of the insulator 602 described above. However, it is particularly preferable to use an aluminum oxide film or the like which is difficult for oxygen and hydrogen to permeate.

[0142] Through the above manufacturing method, the transistor in Embodiment 1 can be manufactured.

[0143] (Embodiment 4) In this embodiment, a structure of an oxide semiconductor will be described.

[0144] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0145] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0146] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0147] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0148] First, let me explain about CAAC-OS.

[0149] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0150] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0151] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0152] FIG. 16(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 16(A). From FIG. 16(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0153] As shown in Figure 16(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 16(B) and Figure 16(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the CA can also be called nanocrystal (nc). AC-OS, CANC (C-Axis Aligned nanocrystals) The oxide semiconductor may also be referred to as an oxide semiconductor having the above structure.

[0154] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 16(D)). The inclination between the pellets observed in FIG. 16(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0155] FIG. 17(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 17(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 17(B), Fig. 17(C), and Fig. 17(D), respectively. 17(D). From Fig. 17(B), Fig. 17(C) and Fig. 17(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0156] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 18(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0157] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0158] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 18(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When the scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0159] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in FIG. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 19(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) surface and other factors. The second ring in Figure 19(B) This is thought to be due to the (110) plane, etc.

[0160] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0161] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0162] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0163] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0164] Next, we will explain nc-OS.

[0165] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where it is difficult to confirm the crystal structure. The size is often between nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor whose crystal size is greater than 10 nm and less than 100 nm is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are clearly visible. It may be difficult to confirm the exact structure of nanocrystals. Therefore, in the following, we consider the crystalline part of nc-OS as pellets. It is sometimes called a “to.”

[0166] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0167] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0168] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0169] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0170] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is difficult to

[0171] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0172] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0173] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0174] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0175] Figure 20 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 20, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 20, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0176] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that it has a more unstable structure than S.

[0177] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0178] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0179] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0180] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0181] (Embodiment 5) In this embodiment, a semiconductor device using the transistor described in the first embodiment will be described. An example will be described.

[0182] FIG. 21A shows an example of a circuit of a memory device, and FIG. 21B shows a cross-sectional view thereof.

[0183] The substrate 350 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide. Substrates made of silicon germanium and other materials, and compound semiconductor substrates made of silicon on insulator (SOI) It is also possible to use a substrate such as a GaN-GaN on Insulator (GaN-GaN on Insulator) substrate.

[0184] The transistor 300 is formed on a substrate 350. The transistor 300 is shown in FIG. As shown, a planar transistor having sidewalls 355 can be used. The transistor is made of STI (Shallow Trench Isolation) The transistor 300 is a fin type transistor. Alternatively, the transistor 300 may be a p-channel transistor. Alternatively, n-channel transistors may be used, or both may be used.

[0185] In this embodiment, the transistor 300 uses single crystal silicon for the channel formation region. However, for example, an oxide semiconductor may be used for the channel formation region, and a silicon single crystal may be used. In addition, the insulator 354 having the function of a gate insulator may be For example, silicon oxide obtained by thermally oxidizing silicon single crystal may be used. Silicon film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, aluminum oxide The film may be an aluminum film, an aluminum nitride film, a hafnium oxide film, or the like. , thermal oxidation method, CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. Alternatively, a laminated film can be formed by appropriately selecting the above-mentioned films. .

[0186] An insulator 360 is formed on the transistor 300, the STI 351, and the diffusion layer 353. CMP is performed to flatten the surface of the insulator 360. The insulator 360 is a silicon oxide film. , silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, nitrogen The film may be formed by thermal oxidation. , CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. Planarization can be achieved by other processes. Alternatively, CMP and etching (dry It is also possible to combine the above-mentioned processes with other processes such as etching, wet etching, plasma treatment, etc.

[0187] A contact hole is formed in the insulator 360, the contact hole reaching the top surface of the gate electrode 330 of the transistor 300. Then, a contact hole is formed to reach the upper surface of the diffusion layer 353, and a conductor is inserted through the contact hole. Then, CMP is performed until the top surface of the insulator 360 is exposed. The plug 370, the plug 371, and the plug 372 are formed. For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum Tungsten alloy, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film may be formed by appropriately selecting a plurality of the above methods. The deposition method, CVD method, ALD method, plating method, etc. can be used. A plurality of forming methods may be used.

[0188] Next, a conductor is formed on the insulator 360 to form wiring layers 373, 374, and 375. The wiring layer 373, the wiring layer 374, and the wiring layer 375 are formed by the above-mentioned plug 370, the plug The same film and film formation method as those for the gap 371 and the plug 372 can be used.

[0189] An insulator 361 is formed on the insulator 360 and on the wiring layer 373, the wiring layer 374, and the wiring layer 375. The surface of the insulator 361 is planarized by CMP. The same film and film formation method as those in 360 can be used.

[0190] The insulator 361 is provided with a wiring layer 373, a wiring layer 374, and a wiring layer 375. A contact hole and a groove are formed, and a conductor is embedded in the contact hole and the groove. Then, CMP is performed until the top surface of the insulator 361 is exposed, and a wiring layer serving as both a plug and a wiring layer is formed. 376, a wiring layer 377, and a wiring layer 378 are formed. The plug 378 is a film formed by the same method as the plugs 370, 371, and 372 described above. can be used.

[0191] Next, an insulator 362 is formed on the insulator 361, the wiring layer 376, the wiring layer 377, and the wiring layer 378. A wiring layer 37 serving as both a plug and a wiring layer is formed in the same manner as the insulator 361 described above. 9, wiring layer 380 and wiring layer 381 are formed. The insulator 362 is the same as the insulator 360 described above. The same films and film forming methods can be used. 1 uses the same film and film formation method as the plugs 370, 371, and 372 described above. The formation of the wiring layer, which also serves as the plug, can be performed by a method such as the above-mentioned. The above-described method can be repeated to fabricate a highly integrated semiconductor device. .

[0192] Next, an insulator 363 is formed on the insulator 362, the wiring layer 379, the wiring layer 380, and the wiring layer 381. The insulator 363 is formed by using the same film and film formation method as the insulator 360 described above. The insulator 363 preferably has a function of being difficult to permeate by hydrogen. Alternatively, the insulator 363 does not need to be formed.

[0193] The insulator 302 is deposited on the insulator 363. The insulator 302 has the same structure as the insulator 360 described above. The insulator 302 is preferably impermeable to oxygen. For example, aluminum oxide may be used.

[0194] Next, the transistor 310 is formed by the method described in the third embodiment. An insulator 303 is deposited on the substrate 310. The insulator 303 is the same as the insulator 360 described above. The insulator 303 is preferably impermeable to oxygen. For example, aluminum oxide may be used.

[0195] The hydrogen in the insulator provided near the channel forming region of the transistor 300 is converted into silicon diaphragm. This has the effect of terminating the ring bonds and improving the reliability of the transistor 300. In this case, hydrogen in an insulator provided near the transistor 310 or the like is trapped in the oxide semiconductor. This is one of the factors that cause the generation of rears, which reduces the reliability of the transistor 310. Therefore, the oxide layer on the upper layer of a transistor using a silicon semiconductor is When transistors using nitride semiconductors are stacked, a layer that blocks hydrogen between the transistors is provided. It is preferable to provide an insulator 302 having a function of trapping hydrogen below the insulator 302. By confining the transistor 300, the reliability of the transistor 300 can be improved. This suppresses hydrogen diffusion from the layer below the insulator 302 to the layer above the insulator 302. This can improve the reliability of the transistor 310. The insulator 303 is preferably provided because it can prevent oxygen from diffusing into the oxide semiconductor. As shown in FIG. 21B, a transistor 310 is formed by dividing an insulator 302 and an insulator 303. , and the insulator 302 and the insulator 303 are wrapped in the contact hole 3. It is more preferable to connect and seal with 04.

[0196] Next, an insulator 308 is formed, and a plug 382, ​​a plug 383, and a plug 384 are formed. A wiring layer 385 is formed on the plug 382, ​​the plug 383, and the plug 384, respectively. A wiring layer 386 and a wiring layer 387 are formed. A plug 382, ​​a plug 383, a plug 384, The wiring layers 385, 386, and 387 are the plugs 370 and 371 described above. The same film and film formation method as for the plug 372 can be used. The plug 383, the plug 384, the wiring layer 385, the wiring layer 386, and the wiring layer 387 are formed by absorbing hydrogen. For example, tungsten or the like is formed on titanium nitride. A two-layer structure may also be used.

[0197] Next, an insulating layer is formed on the insulator 308, the wiring layer 385, the wiring layer 386, and the wiring layer 387. The insulator 364 is formed, and the surface of the insulator 364 is planarized by CMP. The same film and film formation method as those for the insulator 360 described above can be used.

[0198] Contact holes are formed in the insulator 364, reaching the upper surfaces of the wiring layers 386 and 387. Then, the conductor is embedded in the contact hole, and CMP is performed until the top surface of the insulator 364 is exposed. The plugs 388 and 389 are formed by: The same films and film formation methods as those for the plugs 370, 371, and 372 described above are used. This can be done.

[0199] Next, a conductor is formed on the insulator 364, and one electrode 341 of the capacitor element 315 and a wiring layer The electrode 341 and the wiring layer 390 are connected to the plug 370 and the plug 3 The same film and film formation method as those for the plug 372 can be used. The other electrode 342 is formed so as to overlap the electrode 341 via an insulator. Then, an insulator 365 is formed, and the surface of the insulator 365 is planarized by CMP. For the insulator 5, the same film and film formation method as those for the insulator 360 described above can be used.

[0200] A contact hole is formed in the insulator 365 to reach the top surface of the other electrode 342 of the capacitor element 315. On the other hand, a contact hole is formed to reach the upper surface of the wiring layer 390, and a conductor is inserted into the contact hole. The plug 391 is embedded in the hole and CMP is performed until the top surface of the insulator 365 is exposed. The plug 391 and the plug 392 are the same as the plug 37 described above. 0, the plug 371, and the plug 372 can be formed using the same film and film formation method.

[0201] Next, a conductor is deposited on the insulator 365 to form a wiring layer 393 and a wiring layer 394. The line layer 393 and the wiring layer 394 are formed by the above-mentioned plugs 370, 371, and 372. The same films and film formation methods can be used.

[0202] 21B is replaced with a cylinder type capacitor element 315 shown in FIG. The cylinder-shaped capacitive element 320 may be formed as a plate-shaped capacitive element. This is more preferable because the capacitance element can be fabricated in a smaller area than the thin-film capacitance element 315. stomach.

[0203] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0204] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0205] (Embodiment 6) <Imaging device> An imaging device according to an aspect of the present invention will be described below.

[0206] FIG. 23A is a top view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0207] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0208] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 210. Also, a semiconductor device such as an IC may be used for part or all of the peripheral circuit. The circuit is any one of the peripheral circuits 260, 270, 280, and 290. One or more of them may be omitted.

[0209] As shown in FIG. 23B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0210] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0211] FIG. 24A is a top view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 24(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A subpixel 212 (hereinafter, also referred to as “subpixel 212G”) is provided with a color filter that transmits A subpixel 212 is provided with a color filter that transmits light in the blue (B) and blue (C) wavelength bands. (hereinafter, also referred to as "subpixel 212B"). The subpixel 212 has a photo sensor. It can be made to function.

[0212] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 24A, the sub-pixel 212R of the pixel 211 in the m-th column is written as The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0213] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light of the same wavelength band. The sub-pixels 212 provided with filters are electrically connected to each other via switches. In Figure 24(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). A sub-pixel 212 of the pixel 211 arranged in the pixel 211 and a sub-pixel 212 of the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 212 ... 24B shows an example of a connection of the sub-pixels 212 of the arranged pixel 211. In FIG. The sub-pixel 212R arranged in row m and column m and the sub-pixel 212R arranged in row (n+1) and column m are switched. The sub-pixels 212A and 212B are connected to each other via a switch 201. The sub-pixel 212G arranged in the +1 row and the m column is connected via the switch 202. , the sub-pixel 212B arranged in the nth row and the mth column, and the sub-pixel 212B arranged in the n+1th row and the mth column They are connected via a switch 203 .

[0214] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0215] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0216] Also, for example, in FIG. 24A, a sub-pixel 212 detects the red wavelength band, The ratio of the number of sub-pixels 212 that detect the blue wavelength band and the number of sub-pixels 212 that detect the blue wavelength band ( or light receiving area ratio) does not have to be 1:1:1. For example, The Bayer array may be used with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0217] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0218] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0219] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0220] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 25A, a lens 255 and a filter 25 are formed in a pixel 211. 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0221] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Fig. 25(B), the light is blocked by a part of the A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0222] As the photoelectric conversion element 220 shown in FIG. 25, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0223] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0224] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0225] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0226] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor according to the present invention will be described. An example of forming a pixel using a register will be described.

[0227] 26 and 27 are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. A transistor 551 using silicon provided on a silicon substrate 500; A transistor 552 using an oxide semiconductor and a transistor A photodiode 560 provided on the silicon substrate 500 and a microlens 553 are provided. The transistors include a lens array layer 590, a color filter layer 592, and a light-shielding layer 594. The cathodes 562 of the transistors and photodiodes 560 are connected to various plugs 570 and The photodiode 560 has an anode 561 electrically connected to a wiring 571. , and has electrical connection with plug 570 via low resistance region 563 .

[0228] The imaging device includes a transistor 551 and a photodiode 552 provided on a silicon substrate 500. A layer 510 having an electrode 560 and a layer 571 having wiring 571 provided in contact with the layer 510. 20 and a layer 520, and includes a transistor 552 and a transistor 553. A layer 530 is provided in contact with the layer 530 and has wiring 572 and wiring 573. It has 40.

[0229] In the example of the cross-sectional view of FIG. 26, a transistor 551 is formed on a silicon substrate 500. The light receiving surface of the photodiode 560 is disposed on the opposite side to the surface on which the light receiving surface is formed. This makes it possible to ensure an optical path without being affected by various transistors and wiring. Therefore, a pixel with a high aperture ratio can be formed. Alternatively, the light receiving surface of the transistor 551 may be the same as the surface on which the transistor 551 is formed.

[0230] In the case where a pixel is formed using a transistor including an oxide semiconductor, the layer 530 Alternatively, the layer 510 may be omitted and an oxide semiconductor may be used. A pixel may be formed by only the transistor.

[0231] When a pixel is constructed using a silicon transistor, the layer 530 is omitted. An example of a cross-sectional view in which layer 530 is omitted is shown in FIG.

[0232] The silicon substrate 500 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, and aluminum arsenide The substrate has a gallium nitride, indium phosphide, gallium nitride or organic semiconductor. You can also be there.

[0233] Here, a layer 510 having a transistor 551 and a photodiode 560, An insulator 580 is provided between the layer 530 having the resistor 552 and the transistor 553. However, the position of the insulator 580 is not limited.

[0234] The hydrogen in the insulator provided near the channel formation region of the transistor 551 is converted into silicon diaphragm. This has the effect of terminating the ring bond and improving the reliability of the transistor 551. , hydrogen in an insulator provided near the transistor 552 and the transistor 553, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 553. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 580 having a function of blocking hydrogen is provided between them. It is preferable to provide the insulator 580. By confining hydrogen below the insulator 580, the transistor The reliability of the insulator 551 can be improved. Since hydrogen diffusion to layers above 580 can be suppressed, the transistors 552 and The reliability of the transistor 552 and the transistor 553 can be improved. By providing an insulator 581 over the transistor 553, oxygen diffusion in the oxide semiconductor can be prevented. As shown in FIG. 26, the transistor 552 and the transistor The capacitor 553 is wrapped in an insulator 580 and an insulator 581. It is more preferable to connect and seal the insulating material 581 through a contact hole 583. .

[0235] For the insulator 580, for example, the description of the insulator 363 can be referred to.

[0236] In the cross-sectional view of FIG. 26, a photodiode 560 is provided in the layer 510, and a layer 530 is provided in the layer 530. The transistors can be formed so as to overlap with the transistors provided in the pixel. In other words, the resolution of the imaging device can be increased.

[0237] As shown in FIG. 28(A1) and FIG. 28(B1), a part or the whole of the imaging device may be 28(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. FIG. 28(A2) shows the curved state. FIG. 28(A3) is a cross-sectional view of the portion indicated by the dashed line Y1-2 in FIG. This is a cross-sectional view of the portion indicated by Y2.

[0238] FIG. 28(B1) shows a case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and FIG. 28(B2) shows a state where the wire is bent in the direction of the dashed line Y3-Y4 in the figure. FIG. 28(B3) is a cross-sectional view of a portion indicated by a dashed line X3-X4 in FIG. 28(B1). 28(B1) is a cross-sectional view of a portion indicated by dashed dotted line Y3-Y4 in FIG. 28(B1).

[0239] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, which contributes to the miniaturization of electronic devices that use imaging devices. It is possible to realize a lighter weight and a smaller camera. It is also possible to improve the quality of the captured image. .

[0240] (Embodiment 7) A display device according to an embodiment of the present invention will be described below with reference to FIGS. 29 and 30. do.

[0241] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, etc. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose luminance can be controlled, specifically inorganic EL (Electroluminescent) The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0242] The display device described below is a panel in which a display element is sealed, and a control circuit is attached to the panel. This includes modules in which ICs including controllers are mounted.

[0243] The display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and TCP with printers A module or display element with a printed wiring board has an IC (integrated circuit) mounted on it by the COG method. The display device also includes all modules mounted on the display device.

[0244] 29A and 29B are diagrams illustrating an example of an EL display device according to one embodiment of the present invention. FIG. 29(B) is a top view showing the entire EL display device. FIG. 29(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 29(B). .

[0245] FIG. 29A is an example of a circuit diagram of a pixel used in an EL display device.

[0246] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple When multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements) By specifying the connection destinations of only some of the terminals on It may be possible to configure a clear embodiment.

[0247] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if the function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0248] The EL display device shown in FIG. 29(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitance element 742 and a light emitting element 719 .

[0249] Note that FIG. 29(A) is an example of a circuit configuration, and therefore, if a transistor is further added, Conversely, at each node in FIG. 29(A), it is possible to It is also possible to avoid adding passive elements.

[0250] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0251] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switch element 743 is a transistor manufactured through the same process as the transistor 741. By using the transistor 74, the productivity of the EL display device can be improved. As the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0252] FIG. 29B is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 includes the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively / and the driving circuit 736 may be disposed outside the sealing material 734 .

[0253] FIG. 29(C) is a cross-sectional view of an EL display device corresponding to a part of the dashed line MN in FIG. 29(B). It is.

[0254] FIG. 29C shows a transistor 741 including an insulator 708 and an insulator 708, and a conductor 704a embedded in the insulator 708 and the conductor 704a an insulator 712a on the top of the semiconductor substrate 712; an electron trapping layer 715 on the insulator 712a; An insulator 712b on the electron capture layer 715 and a conductor 704a on the insulator 712b overlapping the conductor 704a A semiconductor 706 having a region, a conductor 716a and a conductor 716b in contact with the semiconductor 706, b, an insulator 718a on the semiconductor 706, the conductor 716a, and the conductor 716b; Insulator 718b on insulator 718a, insulator 718c on insulator 718b, and insulator 7 18c and a conductor 714a overlapping the semiconductor 706. The structure of the transistor 741 is just an example, and a structure different from that shown in FIG. That's fine.

[0255] Therefore, in the transistor 741 shown in FIG. The insulator 71 has a function as an electrode, the electron capture layer 715 has a function of capturing electrons, 2a and insulator 712b function as gate insulators, and conductor 716a is the source The conductor 716b functions as a drain electrode, and the insulator 7 18a, insulator 718b and insulator 718c function as gate insulators and are conductive. The body 714a functions as a gate electrode. Therefore, the electrical characteristics of the conductor 704a, the conductor 716a, the conductor It is preferable that at least one of the conductor 716b and the conductor 714a has a light-shielding property.

[0256] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, insulators 718a and 718b may not be clearly defined. Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method.

[0257] In FIG. 29C, an insulator 708 and an insulator 70 conductor 704b embedded in insulator 708 and insulator 704b on insulator 708 12a, an insulator 712b on the insulator 712a, and a conductor 704 on the insulator 712b. A conductor 716a overlapping with b, an insulator 718a on the conductor 716a, and an insulator 718a on the insulator an insulator 718b on the insulator 718b; an insulator 718c on the insulator 718b; and a conductive layer on the insulator 718c. and a conductor 714b overlapping the conductor 716a. 7 shows a structure in which a portion of the insulator 718a and the insulator 718b are removed in the overlapping region. vinegar.

[0258] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a serves as the other electrode.

[0259] Therefore, the capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0260] A capacitor 742 shown in FIG. 29C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 29(C) has high display quality. The illustrated capacitive element 742 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b are partially removed. The capacitive element according to one embodiment is not limited to this. For example, the conductors 716a and A structure in which a part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b. It is okay to have one.

[0261] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to a conductor 716a which serves as the source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. The conductor 78 1 may be electrically connected to transistor 741 through an opening in insulator 720.

[0262] A partition 784 having an opening reaching the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 so as to be in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0263] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0264] FIG. 30(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel shown in FIG. A transistor 751, a capacitor element 752, and an element in which liquid crystal is filled between a pair of electrodes (liquid crystal The liquid crystal element 753 is also included.

[0265] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. The gate is electrically connected to a scan line 754 .

[0266] In the capacitor 752, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0267] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. A common potential applied to a wiring to which the other electrode of the capacitor 752 is electrically connected, The common potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0268] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dotted-chain line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 3a is a conductor or a semiconductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0269] For the transistor 751, refer to the description of the transistor 741. For 752, refer to the description of the capacitor 742. Although the structure of the capacitor 752 corresponding to the capacitor 742 in (C) is shown, the present invention is not limited to this. stomach.

[0270] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be Therefore, the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. This eliminates the need for power to operate the transistor 751, and the liquid crystal display has low power consumption. In addition, the area occupied by the capacitor 752 can be reduced; It is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device.

[0271] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. The conductor 791 is disposed on the insulator 721. The conductor 791 is connected to the transistor Electrically connect to 751.

[0272] An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulator 794 that functions as an alignment film is disposed on the liquid crystal layer 793. 94 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the insulator 794. The substrate 79 7 is placed.

[0273] By using the above-mentioned structure, it is possible to provide a display device having a capacitance element with a small occupancy area. Alternatively, a display device with high display quality can be provided. It is possible to provide a display device.

[0274] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various A display element, a display device, a light-emitting element, or a light-emitting device may include, for example, For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene rating light valve (GLV), plasma display (PDP), MEMS Display element using microelectromechanical system, digital micromirror DMD (Digital Micro Shutter), DMS (Digital Micro Shutter), IMOD (Interface Modulation Device) Optical interference, optical shutter-type MEMS display element MEMS display element, electrowetting element, piezoelectric ceramic display , a display element using carbon nanotubes, etc. In addition, contrast, brightness, reflectance, transmittance, etc. can change due to electrical or magnetic effects. The display device may have a display medium that changes the display mode.

[0275] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E LCD displays are used in the following applications: An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). play, reflective LCD, direct-view LCD, projection LCD) Display devices using electronic ink, electronic liquid powder, or electrophoretic elements An example of such a display is electronic paper. When realizing a liquid crystal display, a part or the whole of the pixel electrode is used as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum. In this case, the reflective electrode may have a thickness of 100 nm or less, and the reflective electrode may have a thickness of 100 nm or less. This can further reduce power consumption. can be done.

[0276] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride on the graphene or graphite. Semiconductors, such as n-type GaN semiconductors having crystals, can be easily formed into films. Furthermore, a p-type GaN semiconductor having crystals can be placed on top of it to form an LED. It is possible to fabricate a crystalline n-type GaN semiconductor using graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by a tar deposition method.

[0277] (Embodiment 8) In this embodiment, an RF device including the transistor or memory device described in the above embodiment will be The tag will be explained with reference to FIG.

[0278] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems, etc. High reliability is required.

[0279] The structure of an RF tag will be described with reference to FIG. 31. FIG. 31 is a block diagram showing an example of the structure of an RF tag. FIG.

[0280] As shown in FIG. 31, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the 04. The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of suppressing the electric field, for example, an oxide semiconductor, may be used. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these methods. It is also possible to use it for.

[0281] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0282] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0283] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0284] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0285] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0286] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance during reading and writing. To prevent malfunction or erroneous writing caused by a power shortage when writing data can be done.

[0287] In addition, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must input the data to ROM811. A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0288] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0289] (Embodiment 9) In this embodiment, at least the transistors described in the embodiment can be used. A CPU including the storage device described in the above embodiment will be described.

[0290] FIG. 32 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0291] The CPU shown in FIG. 32 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, A plate, a glass substrate, etc. are used. The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 32 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, A configuration including the CPU or arithmetic circuit shown in FIG. 32 is considered as one core, and a configuration including multiple such cores is Alternatively, each core may be configured to operate in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be, for example, a .

[0292] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0293] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0294] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0295] In the CPU shown in FIG. 32, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0296] In the CPU shown in FIG. 32, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0297] FIG. 33 is an example of a circuit diagram of a memory circuit that can be used as the register 1196. The memory circuit 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory circuit 1200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0298] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory circuit 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0299] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0300] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0301] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0302] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0303] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 33, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0304] In FIG. 33, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0305] In addition, in FIG. 33, among the transistors used in the memory circuit 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory circuit may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the circuit 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory circuit 1200 may include a transistor other than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may be a transistor that is connected to the gate of the transistor.

[0306] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0307] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory circuit 1200. During this period, data stored in the circuit 1201 is transferred to the capacitor 12 in the circuit 1202. It can be retained by 08.

[0308] Further, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of a transistor in which the channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when power supply voltage is not supplied to 00, the signal held in the capacitance element 1208 is retained for a long period of time. In this way, the memory circuit 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0309] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory circuit that performs the above-mentioned operation after the power supply voltage is resumed, This shortens the time it takes to restore the original data.

[0310] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory circuit 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0311] Such a memory circuit 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0312] In the present embodiment, the memory circuit 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, It can also be applied to RF tags.

[0313] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0314] (Embodiment 10) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0315] [Configuration example] FIG. 34A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 34C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0316] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0317] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 400, a pixel section 401, a first scanning line driving circuit 402, a second scanning line driving circuit 403, and a third scanning line driving circuit 404 are provided. The pixel portion 401 includes a signal line driver circuit 403 and a signal line driver circuit 404. A first scanning line driving circuit 402 and a second scanning line driving circuit 404 are arranged to extend from the first scanning line driving circuit 402 and a second scanning line driving circuit 404. The second scanning line driving circuit 403 is extended from the second scanning line driving circuit 403. In each region, pixels each having a display element are arranged in a matrix. The substrate 400 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0318] In FIG. 34A, a first scanning line driver circuit 402, a second scanning line driver circuit 403, a signal The line driver circuit 404 is formed on the same substrate 400 as the pixel portion 401. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 400 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 400, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0319] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 34(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0320] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0321] A gate wiring 412 of a transistor 416 and a gate wiring 413 of a transistor 417 The data lines are separated so that different gate signals can be applied. The source or drain electrode 414 functions as a transistor 416 and a transistor The transistors 416 and 417 are used in common. The transistor described in the embodiment can be appropriately used. A display panel can be provided.

[0322] The transistor 416 is electrically connected to a first pixel electrode, and the transistor 417 is The first pixel electrode and the second pixel electrode are electrically connected to each other. The shapes of the first pixel electrode and the second pixel electrode are not particularly limited. For example, the first pixel electrode may be V-shaped.

[0323] The gate electrode of the transistor 416 is connected to the gate wiring 412, and the transistor 417 The gate electrode of the gate electrode 412 is connected to the gate wiring 413. 3, different gate signals are applied to transistors 416 and 417. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0324] In addition, the capacitance wiring 410, the gate insulator acting as a dielectric, and the first pixel electrode or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0325] The multi-domain structure has a first liquid crystal element 418 and a second liquid crystal element 419 in one pixel. The first liquid crystal element 418 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 419 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0326] Note that the pixel circuit shown in FIG. 34(B) is not limited to this. The pixel circuit shown in FIG. 1 may be newly configured with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic A logic circuit or the like may be added.

[0327] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0328] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which then When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0329] FIG. 34C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0330] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0331] The pixel 420 includes a switching transistor 421, a driving transistor 422, and a light emitting The switching transistor 421 has a gate element 424 and a capacitor element 423. The gate electrode is connected to the scanning line 426, and the first electrode (one of the source electrode and the drain electrode) is The second electrode (the other of the source electrode and the drain electrode) is connected to the signal line 425. The driving transistor 422 is connected to a gate electrode of the driving transistor 422. The first electrode is connected to the power supply line 427 via the capacitance element 423, and the second electrode is connected to the power supply line 427. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 424. The second electrode of 4 corresponds to a common electrode 428. The common electrode 428 is formed on the same substrate. It is electrically connected to a common potential line.

[0332] The switching transistor 421 and the driving transistor 422 are the same as those in the above embodiment. The transistors described below can be used appropriately. This makes it possible to realize a highly reliable organic EL display. A display panel can be provided.

[0333] The potential of the second electrode (common electrode 428) of the light-emitting element 424 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 427. For example, D, 0V, etc. can be set as a low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 424, a current flows through the light emitting element 424, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0334] The capacitance element 423 is substituted for the gate capacitance of the driving transistor 422. The gate capacitance of the driving transistor 422 can be omitted. A capacitance may be formed between the gate electrode and the gate electrode.

[0335] Next, a description will be given of the signal input to the driving transistor 422. In the case of the above method, the driving transistor 422 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 422. In order to operate the actuator 422 in a linear region, a voltage higher than the voltage of the power supply line 427 is applied to the driving A gate electrode of the transistor 422 is connected to a signal line 425. A voltage equal to or greater than the threshold voltage Vth of the input transistor 422 is applied.

[0336] When analog gradation driving is performed, the gate electrode of the driving transistor 422 is connected to the light emitting element 42 A voltage equal to or greater than the sum of the forward voltage of the transistor 421 and the threshold voltage Vth of the driving transistor 422 is applied. In addition, a video signal is input so that the driving transistor 422 operates in the saturation region. A current flows through the light emitting element 424. In addition, the driving transistor 422 is operated in a saturation region. In order to achieve this, the potential of the power supply line 427 is set higher than the gate potential of the driving transistor 422. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 424. , analog gray scale driving can be performed.

[0337] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. A switch, a resistor, a capacitor, a sensor, a transistor or A logic circuit or the like may be added.

[0338] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0339] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0340] (Embodiment 11) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0341] FIG. 35A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 35A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0342] FIG. 35B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and A display device in which a function as a position input device is added to at least one of the second display units 914 The function as a position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photo It can also be added by providing a photoelectric conversion element, also called a sensor, in the pixel section of the display device. can.

[0343] FIG. 35C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0344] FIG. 35(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. Holds 3rd place.

[0345] FIG. 35E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 45 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. The angle may be switched according to the angle between the above and the above.

[0346] FIG. 35(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and lights. 954 etc.

[0347] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0348] (Embodiment 12) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including bills, coins, securities, and unregistered securities. Bonds, certificates (driver's licenses, resident cards, etc., see Figure 36 (A)), recording media (DVDs, videos, etc.) Deotape, etc., see Figure 36(B), packaging containers (wrapping paper, bottles, etc., see Figure 36(C) (See Figure 36(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( Liquid crystal display devices, EL display devices, television sets, or mobile phones) or other articles, It can be used by attaching it to tags (see Figure 36 (E) and Figure 36 (F)) to each item. can.

[0349] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0350] As described above, the RF tag according to one aspect of the present invention is used for each of the applications described in this embodiment. This reduces the power required for operations, including writing and reading information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even if the power is cut off. Since the data can be retained for a long time, it can be used for applications where the frequency of writing and reading is low. Cut.

[0351] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together. [Explanation of symbols]

[0352] 101 Semiconductors 102 Electron capture layer 102a Insulator 102b Insulator 102c Insulator 102d Conductor 102e Insulator 103 Gate electrode 104 Gate Insulator 105 Gate electrode 106 Electron capture level 107 Electronic 108 Curve 109 Curve 110 Transistor 111 Capacitive element 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Transistors 302 Insulators 303 Insulators 304 Contact Hole 308 Insulators 310 Transistor 315 Capacitive element 320 Capacitive element 330 Gate electrode 341 Electrode 342 Electrode 350 Substrate 351 STI 353 Diffusion Layer 354 Insulators 355 Sidewall 360 Insulator 361 Insulators 362 Insulators 363 Insulators 364 Insulators 365 Insulator 370 Plug 371 Plug 372 Plug 373 Wiring layer 374 Wiring layer 375 Wiring layer 376 wiring layer 377 Wiring layer 378 Wiring layer 379 Wiring layer 380 wiring layer 381 Wiring layer 382 Plug 383 Plug 384 Plug 385 wiring layer 386 wiring layer 387 Wiring layer 388 Plug 389 Plug 390 wiring layer 391 Plug 392 Plug 393 Wiring layer 394 Wiring layer 400 Substrates 401 Pixel section 402 Scanning line driver circuit 403 Scanning line driver circuit 404 Signal line driver circuit 410 Capacitance wiring 412 Gate wiring 413 Gate wiring 414 Drain electrode 416 Transistor 417 Transistor 418 Liquid crystal element 419 Liquid crystal element 420 pixels 421 Switching Transistors 422 Drive transistor 423 Capacitive element 424 Light emitting element 425 Signal Line 426 scan lines 427 Power line 428 Common electrode 500 Silicon substrate 510 layers 520 layers 530 layers 540 layers 551 Transistor 552 Transistor 553 Transistor 560 Photodiode 561 Anode 562 Cathode 563 Low resistance region 570 Plug 571 Wiring 572 Wiring 573 Wiring 580 Insulator 581 Insulators 583 Contact Hole 590 Microlens Array Layer 592 Color filter layer 594 Light blocking layer 600 Substrates 602 Insulators 604 Insulators 606 Gate electrode 606b Gate electrode 608 Insulators 610 Electron capture layer 612 Insulators 613 Oxide Semiconductors 614 Oxide Semiconductors 614a Oxide Semiconductor 614c Oxide Semiconductor 615 Conductors 616a Source electrode 616b Drain electrode 618 Gate Insulator 620 Gate electrode 622 Insulators 650 Channel formation region 700 Substrates 704a Conductor 704b Conductor 706 Semiconductors 708 Insulator 712a Insulator 712b Insulator 714a Conductor 714b Conductor 715 Electron capture layer 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light emitting element 720 Insulator 721 Insulators 731 Terminal 732 FPC 733a Wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitive element 743 Switching element 744 Signal Line 750 Board 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 scan lines 755 Signal Line 781 Conductors 782 Light-emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid crystal layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory circuit 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 4000 RF tags 5100 pellets 5120 PCB 5161 area

Claims

1. A semiconductor device comprising: a first transistor having a first channel formation region; and a second transistor having a second channel formation region; one of a source electrode or a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; the first channel formation region includes an oxide semiconductor; The second channel formation region is a semiconductor device having silicon, an oxide semiconductor layer having the first channel formation region; a first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer with the first insulating layer interposed therebetween and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a lower surface of the oxide semiconductor layer; a second conductive layer having a region located below the oxide semiconductor layer with the second insulating layer interposed therebetween; a third insulating layer having a region in contact with a lower surface of the second conductive layer; a third conductive layer located below the third insulating layer and overlapping the second conductive layer; a fourth insulating layer having a region underlying the first transistor; a fourth conductive layer having a region located below the fourth insulating layer and above the second channel formation region, and having a function as a gate electrode of the second transistor; the second conductive layer overlaps with the first channel formation region; the third conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween but does not overlap with the first channel formation region.

2. A semiconductor device comprising: a first transistor having a first channel formation region; and a second transistor having a second channel formation region; one of a source electrode or a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; the first channel formation region includes an oxide semiconductor; The second channel formation region is a semiconductor device having silicon, an oxide semiconductor layer having the first channel formation region; a first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer with the first insulating layer interposed therebetween and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a lower surface of the oxide semiconductor layer; a second conductive layer having a region located below the oxide semiconductor layer with the second insulating layer interposed therebetween; a third insulating layer having a region underlying the second conductive layer; a third conductive layer having a region in contact with a lower surface of the third insulating layer and overlapping with the second conductive layer; a fourth insulating layer having a region underlying the first transistor; a fourth conductive layer having a region located below the fourth insulating layer and above the second channel formation region and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor, the second conductive layer overlaps with the first channel formation region; the third conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween but does not overlap with the first channel formation region; the fifth conductive layer has a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, and a region overlapping with the fourth conductive layer.

3. A semiconductor memory device comprising: a first transistor having a first channel formation region; a second transistor having a second channel formation region; and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one of the electrodes of the capacitance element, the first channel formation region includes an oxide semiconductor; The second channel formation region is a semiconductor device having silicon, an oxide semiconductor layer having the first channel formation region; a first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer with the first insulating layer interposed therebetween and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a lower surface of the oxide semiconductor layer; a second conductive layer having a region located below the oxide semiconductor layer with the second insulating layer interposed therebetween; a third insulating layer having a region in contact with a lower surface of the second conductive layer; a third conductive layer located below the third insulating layer and overlapping the second conductive layer; a fourth insulating layer having a region underlying the first transistor; a fourth conductive layer having a region located below the fourth insulating layer and above the second channel formation region, and having a function as a gate electrode of the second transistor; the second conductive layer overlaps with the first channel formation region; the third conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween but does not overlap with the first channel formation region.

4. A semiconductor memory device comprising: a first transistor having a first channel formation region; a second transistor having a second channel formation region; and a capacitor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one of the electrodes of the capacitance element, the first channel formation region includes an oxide semiconductor; The second channel formation region is a semiconductor device having silicon, an oxide semiconductor layer having the first channel formation region; a first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer with the first insulating layer interposed therebetween and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a lower surface of the oxide semiconductor layer; a second conductive layer having a region located below the oxide semiconductor layer with the second insulating layer interposed therebetween; a third insulating layer having a region underlying the second conductive layer; a third conductive layer having a region in contact with a lower surface of the third insulating layer and overlapping with the second conductive layer; a fourth insulating layer having a region underlying the first transistor; a fourth conductive layer having a region located below the fourth insulating layer and above the second channel formation region and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor, the second conductive layer overlaps with the first channel formation region; the third conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween but does not overlap with the first channel formation region; the fifth conductive layer has a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, and a region overlapping with the fourth conductive layer.

5. In any one of claims 1 to 4, the first transistor is an n-channel transistor, The second transistor is a p-channel transistor.

6. In any one of claims 1 to 5, The second conductive layer comprises molybdenum.

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