Semiconductor device, electronic device, pH sensor, biosensor, method for manufacturing semiconductor device, and method for manufacturing electronic device

Abstract

This semiconductor apparatus has a first electrode, a second electrode, and a semiconductor layer in contact with the first electrode and the second electrode, wherein the semiconductor layer includes a 5–20 nm first oxide layer including spinel-type ZnGa2O4 and a 5–50 nm second oxide layer including In, Ga, and Zn.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, an electronic device, a pH sensor, a biosensor, a method for manufacturing a semiconductor device, and a method for manufacturing an electronic device. The present invention claims priority to Japanese Patent Application No. 2021-088679 filed on May 26, 2021, and the contents of that application are incorporated by reference into this application in designated countries where incorporation by reference to literature is permitted. [Background technology]

[0002] Semiconductor materials used in semiconductor devices such as thin film transistors (TFTs) include amorphous oxides such as oxides of In, Ga, and Zn (IGZO; In-Ga-Zn-O) (see Patent Document 1). Since such conventional semiconductor materials do not have sufficient chemical durability, when manufacturing semiconductor devices, etching steps and other processes are performed with a structure that protects the semiconductor materials from chemical damage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 3013-051421 A Summary of the Invention

[0004] A first aspect of the present invention is a semiconductor device having a first electrode, a second electrode, and a semiconductor layer in contact with the first electrode and the second electrode, the semiconductor layer including a first oxide layer of 5 to 20 nm containing spinel-type ZnGa2O4, and a second oxide layer of 5 to 50 nm containing In, Ga, and Zn.

[0005] A second aspect of the present invention is an electronic device comprising the semiconductor device of the first aspect.

[0006] A third aspect of the present invention is a pH sensor including the semiconductor device of the first aspect.

[0007] A fourth aspect of the present invention is a biosensor including the semiconductor device of the first aspect.

[0008] A fifth aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a semiconductor layer, forming a conductive layer on the semiconductor layer, and etching the conductive layer according to a predetermined pattern to form a first electrode and a second electrode.

[0009] A sixth aspect of the present invention is a method for producing an electronic device, comprising the step of forming a semiconductor device by the method for producing a semiconductor device according to the fifth aspect. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor device A according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a semiconductor device B according to the second embodiment. [Diagram 3] FIG. 3 is a schematic diagram of a pH sensor C including the semiconductor device according to this embodiment. [Figure 4] FIG. 4 is a diagram showing an example of a method for manufacturing the semiconductor device A according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing an example of a method for manufacturing the semiconductor device B according to the second embodiment. [Figure 6] FIG. 6 is a graph showing the measurement results of the characteristics of the semiconductor device A according to the first embodiment. [Figure 7] FIG. 7 is a graph showing the measurement results of the characteristics of semiconductor devices having semiconductor layers of various thicknesses that were post-treated at an annealing temperature of 120° C. [Figure 8] FIG. 8 is a graph showing the measurement results of the characteristics of semiconductor devices having semiconductor layers of various thicknesses that were post-treated at an annealing temperature of 150° C. [Figure 9] FIG. 9 is a graph showing the measurement results of the characteristics of semiconductor devices including IGZTO semiconductor layers of various thicknesses that were post-treated at an annealing temperature of 120° C. [Figure 10] FIG. 10 is a graph showing the measurement results of the characteristics of a semiconductor device including an IGZTO semiconductor layer post-treated at an annealing temperature of 150° C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, a mode for carrying out the present invention (hereinafter simply referred to as "the present embodiment") will be described in detail. The present embodiment described below is an example for explaining the present invention, and is not intended to limit the present invention to the following content. In addition, positional relationships such as up, down, left, and right in the drawings are based on the positional relationships shown in the drawings, unless otherwise specified. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0012] FIG. 1 is a schematic diagram of a semiconductor device A according to the first embodiment.

[0013] FIG. 2 is a schematic diagram of a semiconductor device B according to the second embodiment.

[0014] The semiconductor device A according to the first embodiment is a bottom-gate top-contact (BGTC) type semiconductor device. The semiconductor device A has a first electrode 71, a second electrode 72, and a semiconductor layer 60 in contact with the first electrode and the second electrode. The semiconductor layer 60 includes a spinel-type ZnGa2O4 layer 50 (first oxide layer) and an IGZO layer 40 (second oxide layer). The first electrode 71 and the second electrode 72 are disposed on the insulating layer 30, and a part of them covers the spinel-type ZnGa2O4 layer 50. The IGZO layer 40 is an inorganic semiconductor of an oxide containing In, Ga, and Zn.

[0015] The semiconductor device B according to the second embodiment is a bottom-gate top-contact (BGTC) type semiconductor device. The semiconductor device B has a first electrode 71, a second electrode 72, and a semiconductor layer 60 in contact with the first electrode and the second electrode. The semiconductor layer 60 includes a spinel-type ZnGa2O4 layer 50 (first oxide layer) and an IGZTO layer 41 (second oxide layer). The first electrode 71 and the second electrode 72 are disposed on the insulating layer 30, and a part of them covers the spinel-type ZnGa2O4 layer 50. The IGZTO layer 41 is an inorganic semiconductor of an oxide containing In, Ga, Zn, and Sn.

[0016] The semiconductor devices A and B each have a substrate 10, a third electrode 20 formed on the substrate 10, and an insulating layer 30 formed on the third electrode 20. The third electrode 20 is provided opposite the semiconductor layer 60 via the insulating layer 30. The first electrode 71 is a source electrode, the second electrode 72 is a drain electrode, and the third electrode 20 is a gate electrode.

[0017] The semiconductor devices A and B have the advantages of a low film-forming temperature, a high film-forming speed, and less inclusion of impurities by using the spinel-type ZnGa2O4 layer 50. In addition, they have the advantage of being easily manufactured even when a flexible substrate is used.

[0018] Conventionally, metal oxide films such as silicon oxide and aluminum oxide have been widely used as protective layers (passivation layers) for semiconductor layers, but these have many problems such as high film formation temperatures and slow film formation speeds. For example, when these metal oxide films are formed by chemical vapor deposition (CVD), problems include high film formation temperatures, the need for large-scale CVD film formation equipment, and the introduction of large amounts of impurities such as hydrogen and carbon derived from the material gas. Alternatively, when these metal oxide films are formed by radio frequency (RF) sputtering, oxygen vacancies occur in the protective layer, which reduces the insulating properties and causes optical absorption.

[0019] In this regard, the semiconductor devices A and B can solve these problems at once by using the spinel-type ZnGa2O4 layer 50 as the protective layer. The spinel-type ZnGa2O4 layer can be formed relatively easily and efficiently compared to the above-mentioned metal oxide films and the like.

[0020] Furthermore, the spinel-type ZnGa2O4 layer 50 of the semiconductor devices A and B has semiconductor properties and is extremely stable against acids and bases, etc. Therefore, it exhibits a passivation effect that is equal to or better than that of a conventional protective layer using a metal oxide film, and the semiconductor devices A and B are also excellent in terms of semiconductor properties.

[0021] Furthermore, by using the spinel-type ZnGa2O4 layer 50, an electrode can be placed directly on the semiconductor layer without an ESL (etch stop layer) or the like. When an ESL is used, it is necessary to provide holes in the ESL to connect the electrode and the semiconductor layer, and furthermore, a high-temperature heat treatment of 250°C or more is required. By using the spinel-type ZnGa2O4 layer 50, such a treatment becomes unnecessary. The configurations of the semiconductor devices A and B are described below.

[0022] The material of the substrate 10 is not particularly limited, and known materials can be used. Specific examples include glass, resin, silicon, metal, alloy, foils of these, etc. Among these, it is preferable to use one selected from the group consisting of glass, resin, silicon, and combinations of these.

[0023] Examples of the resin that can be used include polyacrylate, polycarbonate, polyurethane, polystyrene, cellulose polymer, polyolefin, polyamide, polyimide, polyester, polyphenylene, polyethylene, polyethylene terephthalate, polypropylene, ethylene-vinyl copolymer, and polyvinyl chloride.

[0024] The CVD method with a high film formation temperature does not need to be used to form the spinel-type ZnGa2O4 layer 50. Therefore, even if a resin material with a low heat resistance temperature is used for the substrate 10, the spinel-type ZnGa2O4 layer 50 can be suitably formed.

[0025] Furthermore, the substrate 10 may be flexible. If the substrate 10 is a flexible film substrate (sometimes called a "sheet substrate"), a roll-to-roll method or a roll-to-sheet method in which a film is continuously formed in a roll shape can be adopted, which is expected to increase the efficiency and simplification of the manufacturing process and improve the yield.

[0026] The roll-to-roll method is a method in which a rolled film substrate is unwound, a film is continuously formed, and then wound up into a roll again.The roll-to-sheet method is a method in which a rolled film substrate is unwound, a film is continuously formed, and then cut into sheets.

[0027] The third electrode 20 is a gate electrode. The third electrode 20 is not particularly limited, and a known electrode can be used. Specific examples include a single layer of Mo, W, Al, Cu, Au, a Cu-Al alloy, an Al-Si alloy, a Mo-W alloy, a Ni-P alloy, and the like, and a laminate thereof. The method of manufacturing the third electrode 20, which is a gate electrode, is not particularly limited, and a suitable method can be appropriately adopted in consideration of the materials of the substrate 10 and the gate electrode.

[0028] The third electrode 20 which is the gate electrode may be made of conductive silicon and may also serve as the substrate 10 .

[0029] The insulating layer 30 is not particularly limited and may be made of any known material, such as inorganic materials such as SiO, SiN, SiON, AlO, TaO, and HfO, photocurable resins, and thermosetting resins.

[0030] The semiconductor layer 60 is formed in contact with a first electrode 71 and a second electrode 72. The first electrode 71 and the second electrode 72 are disposed on the insulating layer 30, and a part of them covers a spinel type ZnGa2O4 layer 50 (first oxide layer). The semiconductor layer 60 includes the ZnGa2O4 layer 50 (first oxide layer) and an IGZO layer 40 or an IGZTO layer 41 (second oxide layer).

[0031] The IGZO layer 40 is an inorganic semiconductor made of an oxide containing In, Ga, and Zn. The IGZTO layer 41 is an inorganic semiconductor made of an oxide containing In, Ga, Zn, and Sn.

[0032] The IGZO layer 40 or the IGZTO layer 41 (second oxide layer) may be doped with a carrier element from the viewpoint of further improving the semiconductor characteristics. The carrier element is not particularly limited, and any known element in the doping process can be used. Specific examples include hydrogen, monovalent metals, divalent metals, and trivalent metals. Among these, in this embodiment, it is more preferable that the semiconductor layer 60 is doped with hydrogen.

[0033] The thickness of the IGZO layer is 5 to 50 nm, preferably 10 to 40 nm, and more preferably 10 to 30 nm.The thickness of the IGZTO layer is 5 to 50 nm, preferably 10 to 40 nm, and more preferably 10 to 30 nm.

[0034] ZnGa2O4 constituting the spinel-type ZnGa2O4 layer 50 (first oxide layer) crystallizes at a relatively low temperature. In this embodiment, the spinel-type ZnGa2O4 can be hydrogen-free. That is, the protective layer can be preferably one that is not doped with hydrogen or does not substantially contain hydrogen. Here, "substantially does not contain" means that the component is not actively added, and does not exclude the inevitable inclusion or mixing.

[0035] If excessive hydrogen exists in the spinel-type ZnGa2O4 layer 50 (first oxide layer), it may cause a problem that the hydrogen may enter the semiconductor layer 60 as an impurity. For example, if there are impurities such as hydrogen, they may diffuse into the semiconductor and cause the V TH In this regard, for example, when a metal oxide film such as silicon oxide is used as a protective layer by a conventional method, hydrogen is used as a raw material, and excessive hydrogen may be present in the protective layer, causing deterioration of the semiconductor layer 60. However, in this embodiment, hydrogen is not required. From this viewpoint, the hydrogen content of the spinel-type ZnGa2O4 layer 50 (first oxide layer) is set to 1×10 21 atm / cc or less, and 1×10 18 It is more preferable that the hydrogen content is equal to or less than atm / cc. The hydrogen content can be measured by secondary ion mass spectrometry (SIMS).

[0036] The spinel-type ZnGa2O4 layer 50 (first oxide layer) can also function as a passivation film. The passivation film isolates the IGZO layer 40 or the IGZTO layer 41 (second oxide layer) from the outside environment, and can protect the IGZO layer 40 or the IGZTO layer 41 (second oxide layer) from moisture, metal ions, and the like.

[0037] The thickness of the spinel-type ZnGa2O4 layer 50 (first oxide layer) is 5 to 20 nm, preferably 5 to 15 nm, and more preferably 5 to 10 nm.

[0038] A conductive layer 70 is formed on the semiconductor layer 60, and the conductive layer 70 is etched in accordance with a predetermined pattern to form a first electrode 71 and a second electrode 72. For example, the first electrode 71 and the second electrode 72 are formed by a normal photolithography process.

[0039] When the first electrode 71 is used as a source electrode, the source electrode is not particularly limited and any known electrode can be used. Specific examples include a single layer of Mo, W, Al, Cu, Au, a Cu-Al alloy, an Al-Si alloy, a Mo-W alloy, a Ni-P alloy, or the like, or a laminate thereof.

[0040] When the second electrode 72 is used as a drain electrode, the drain electrode is not particularly limited and any known electrode can be used. Specific examples include a single layer of Mo, W, Al, Cu, Au, a Cu-Al alloy, an Al-Si alloy, a Mo-W alloy, a Ni-P alloy, or the like, or a laminate thereof.

[0041] In this embodiment, a transistor may be configured in which the first electrode 71, the second electrode 72, and the third electrode 20 serve as a source electrode, a drain electrode, and a gate electrode, respectively, as in the semiconductor devices A and B. In this way, the semiconductor device according to this embodiment is not limited to the configurations shown in Figures 1 and 2, and various configurations can be adopted.

[0042] The semiconductor devices A and B described so far not only have excellent semiconductor properties such as electronic conductivity, but also have chemical resistance such as acid resistance and base resistance by having the spinel-type ZnGa2O4 layer 50 (first oxide layer).

[0043] Therefore, the semiconductor device according to this embodiment can be suitably used in various sensors such as pH sensors and biosensors, as well as electronic devices such as TFT liquid crystal displays and organic EL displays. Examples of such devices will be described below.

[0044] <pHセンサ> FIG. 3 is a schematic diagram of a pH sensor C including the semiconductor device according to this embodiment.

[0045] The pH sensor C is, for example, a pH sensor (Ion-Sensitive-FET; ion-sensitive field effect transistor) using the semiconductor device according to this embodiment.

[0046] The pH sensor C has the semiconductor device according to this embodiment, a pool wall 80 made of silicone rubber provided on the semiconductor device, and a reference electrode 90. A solution S to be measured (for example, hydrochloric acid in the case of an acidic solution, or a sodium hydroxide solution in the case of an alkaline solution) is filled into a pool defined by the pool wall 80, and the potential difference with the reference electrode 90 is measured. Since the pH of the solution S depends on the amount of protons in the solution, the measurement principle of the pH sensor is to electrically measure the amount of protons in the solution and calculate the pH value based on the measured amount of protons.

[0047] The semiconductor device according to this embodiment can be provided with high stability against strong acids and strong bases, and therefore a pH sensor using the same exhibits high stability over a wide pH range, such as pH 1 to 14, and can perform rapid and accurate measurement even when the target sample is a strong acid or strong base.

[0048] <Biosensor> Although not shown, the semiconductor device according to this embodiment can also be used as a biosensor (sometimes called a biosensor chip). A biosensor is a chemical sensor that utilizes a molecular recognition mechanism originating from a living organism, and is used as a chemical recognition element for pH changes, oxidation-reduction reactions, etc. in a living organism.

[0049] In this regard, the semiconductor device according to the present embodiment has high stability over a wide pH range, and therefore can be used as a biosensor capable of accurate sensing even when the measurement target is strongly acidic or strongly alkaline. For example, a specific antibody can be modified on the semiconductor surface, and a biosensor can be used to measure the amount of protons when a detection target such as specific DNA is adsorbed thereon.

[0050] <Manufacturing method> Fig. 4 is a diagram showing an example of a method for manufacturing the semiconductor device A according to the first embodiment, and Fig. 5 is a diagram showing an example of a method for manufacturing the semiconductor device B according to the second embodiment.

[0051] 4 is a method for manufacturing a bottom-gate top-contact type semiconductor device A. This manufacturing method includes the steps of forming a semiconductor layer 60 including a spinel-type ZnGa2O4 layer 50 (first oxide layer) and an IGZO layer 40 (second oxide layer) on a substrate 10, forming a conductive layer 70 on the substrate 10, and etching the conductive layer 70 according to a predetermined pattern to form a first electrode 71 and a second electrode 72.

[0052] The manufacturing method shown in FIG. 5 is a method for manufacturing a bottom-gate-top-contact type semiconductor device B, and involves the same steps as in the manufacturing method shown in FIG. 4 except that the IGZO layer 40 of the semiconductor device A is replaced with an IGZTO layer 41.

[0053] Each step will be described in detail below.

[0054] (1st step) First, the third electrode 20 is formed on the surface of the substrate 10. The third electrode 20 corresponds to the above-mentioned gate electrode. The method of forming the third electrode 20 on the surface of the substrate 10 is not particularly limited, and a suitable method can be adopted as appropriate, taking into consideration the materials of the substrate 10 and the electrodes, etc.

[0055] (2nd process) Next, an insulating layer 30 is formed on the surface of the substrate 10 on the side where the third electrode 20 is formed, and the third electrode 20 is covered with the insulating layer 30. The method for forming the insulating layer 30 is not particularly limited, and a suitable method can be adopted as appropriate, taking into consideration the materials of the substrate 10, the third electrode 20, and the insulating layer 30, etc.

[0056] (3rd step) Then, a semiconductor layer 60 is formed on the surface of the insulating layer 30. When manufacturing the semiconductor device A, the semiconductor layer 60 is formed by covering the IGZO layer 40 with a spinel type ZnGa2O4 layer 50. When manufacturing the semiconductor device B, the semiconductor layer 60 is formed by covering the IGZTO layer 41 with a spinel type ZnGa2O4 layer 50. The spinel type ZnGa2O4 layer 50 can protect the inside of the device from moisture, metal ions, and the like in the external environment.

[0057] Conventionally, it has been considered desirable to use a metal oxide film such as silicon oxide or aluminum oxide as a protective layer (passivation layer), and therefore the deposition temperature has been required to be 400°C or higher. However, in the manufacturing method according to the present embodiment, the deposition temperature of the spinel-type ZnGa2O4 layer 50 used as the protective layer is low, and the deposition rate is also high, so that a semiconductor device can be manufactured simply and efficiently. For example, when a resin substrate is used as the substrate 10, the usable temperature is relatively low, so that the deposition temperature is preferably low. From this viewpoint, the deposition temperature of the spinel-type ZnGa2O4 layer 50 is 190 to 250°C, and preferably 190 to 210°C.

[0058] It is preferable that all layers constituting the semiconductor layer 60 are formed by a sputtering method. In this case, they can be formed using a sputtering device, and multiple cathodes may be used. For sputtering, a single-target simultaneous sputtering using one type of material as a target may be adopted, or a co-sputtering using multiple types of materials as targets may be adopted. For example, if the target used in forming the IGZO layer 40 or the IGZTO layer 41 is the same as the target used in the spinel type ZnGa2O4 layer 50, the target of the sputtering method can be commonly used, and thus the layers can be continuously formed in the same device.

[0059] The IGZO layer 40 included in the semiconductor device A may be formed using an oxide sintered body of InGaZnO4 as a target (single-target simultaneous sputtering). Alternatively, the three types of In2O3, Ga2O3, and ZnO may be simultaneously used to gradient the composition ratio and control the IGZO layer to have a desired composition (multiple-target simultaneous sputtering, co-sputtering).

[0060] The IGZTO layer 41 included in the semiconductor device B may be formed using KOS-B02 (manufactured by Kobelco Research Institute, Ltd.) as a target (single-target simultaneous sputtering). In addition, by simultaneously using four types of In2O3, Ga2O3, SnO2, and ZnO, the composition ratio may be gradient to control the IGZTO layer to have a desired composition (multiple-target simultaneous sputtering, co-sputtering).

[0061] For example, in the case of n-type semiconductor materials, it is possible to produce them by element doping or oxygen vacancies in the film. The elements from which n-type semiconductors can be obtained are not particularly limited, but include, for example, Al, In, Sn, Sb, and Ta. The method of generating oxygen vacancies is not particularly limited, and any known method can be adopted. Specifically, it is preferable to perform heat treatment in an oxygen-averse atmosphere or in a reducing gas atmosphere such as hydrogen or water vapor. For example, a method of forming a film in a state where hydrogen is mixed into the sputtering gas and performing n-type carrier doping with interstitial hydrogen can be mentioned. These treatments may be performed in a chamber after film formation, or may be sintered as a post-process.

[0062] The spinel-type ZnGa2O4 layer 50 can be formed by co-sputtering using gallium zinc oxide and zinc oxide as targets. Alternatively, a method of co-sputtering using gallium oxide and zinc oxide as targets, or a method of co-sputtering using gallium and zinc as targets and oxidizing with a reactive gas during film formation may be used. Furthermore, in addition to co-sputtering, a method of sputtering using a mixture of zinc oxide and gallium oxide as a target and oxidizing with a reactive gas during film formation may be used.

[0063] By using the spinel-type ZnGa2O4 layer 50, the semiconductor layer 60 exhibits strong resistance to strong acids and strong bases, so that the manufacturing process can omit a step of protecting the semiconductor layer.

[0064] From the viewpoint of improving the crystallinity of the film, the lower limit of the deposition temperature of the spinel-type ZnGa2O4 layer 50 is 190° C. or more, preferably 200° C. or more, and the upper limit is 250° C. or less, preferably 210° C. or less. Note that excessive heating may promote evaporation of Zn particles flying to the surface of the substrate 10, resulting in deviation from the stoichiometric ratio of Ga and Zn (composition deviation); however, by simultaneously discharging a sintered compact target containing Zn or ZnO, the Zn concentration in the film can be increased, and the composition deviation can be effectively prevented.

[0065] (4th step) A conductive layer 70 is formed on the semiconductor layer 60, and the conductive layer 70 is etched in accordance with a predetermined pattern to form a first electrode 71 and a second electrode 72. The first electrode 71 is a source electrode, and the second electrode 72 is a drain electrode. A normal photolithography process can be used as a method for forming the first and second electrodes. In this case, after the conductive layer 70 is formed on the semiconductor layer 60, a resist layer is formed on the conductive layer 70, and the resist layer is exposed to a predetermined pattern of light and developed. Next, the conductive layer exposed from the opening of the resist layer is etched to form the first electrode 71 and the second electrode 72. Note that a positive type material or a negative type material may be used as the resist layer.

[0066] In this case, the etching solution is preferably an acidic solution, since resist materials used in normal photolithography processes are often soluble in alkali, by using an acidic solution, the conductive layer can be suitably etched without dissolving the resist layer.

[0067] By the above steps, semiconductor devices A and B can be obtained. The semiconductor device thus obtained may be subjected to other steps as necessary to obtain a desired device configuration. For example, a pretreatment step before forming each part, a surface polishing step after forming each part, a dicing step, a mounting step on a lead frame, an assembly step of packaging after forming a circuit, a wire bonding step, a mold encapsulation step, etc. can be appropriately adopted. EXAMPLES

[0068] The present invention will be described in more detail with reference to the following examples and comparative examples, but the present invention is not limited to the following examples in any way.

[0069] <Example 1> Semiconductor device A with ZnGa2O4 (10 nm) / IGZO (15 nm) semiconductor layers

[0070] (IGZO layer formation) A highly conductive n-type silicon substrate was prepared, consisting of a silicon wafer with an n-type resistivity of less than 0.0017 Ω·cm and a 200 nm thermal oxide film (SiO2) formed on it. A 15 nm IGZO layer was formed on this substrate. The IGZO layer was formed by RF sputtering using a sintered IGZO target with an In:Ga:Zn atomic concentration of 2:2:1. The substrate temperature during film formation was set to 105°C, and Ar was used as the sputtering gas. At the same time, oxygen was introduced as a reactive gas at a volume ratio of 10% relative to Ar.

[0071] (Formation of a spinel-type ZnGa2O4 layer) Next, a 10 nm spinel-type ZnGa2O4 layer was formed to cover the above-mentioned IGZO layer, obtaining a ZnGa2O4 / IGZO semiconductor layer. The spinel-type ZnGa2O4 layer was formed using a sintered ZnGa2O4 target in the same sputtering device as that used for forming the IGZO layer. It was known from the results of a previous experiment that the optimum temperature for ZnGa2O4 to crystallize into a spinel type is 190°C or higher. Therefore, the target output was controlled so that the composition ratio of Zn to Ga was 8:1, and the substrate was heated to 230°C to form a ZnGa2O4 layer with a spinel-type crystal structure. Ar gas containing no hydrogen was used as the sputtering gas. At the same time, oxygen was introduced as a reactive gas at a volume ratio of 10% to Ar. This controlled the amount of hydrogen and oxygen deficiency to be prevented. The back pressure was 1×10 -4 The film was formed under the conditions of a film formation pressure of 0.22 Pa or less.

[0072] A resist material was applied onto the obtained ZnGa2O4 / IGZO semiconductor layer, and the resist material was patterned using a typical photolithography process. The semiconductor layer was then patterned by etching for approximately 120 seconds using an etching solution (ITO-07: manufactured by Kanto Chemical) heated to 40°C.

[0073] (Formation of source and drain electrodes) Then, an Al film (thickness 100 nm) serving as source and drain electrodes was formed by vacuum deposition so as to cover the semiconductor layer. The vacuum deposition was performed using a resistance heating type vacuum deposition apparatus.

[0074] Then, a resist material was applied onto the Al film and patterned using a typical photolithography process. The Al film was then immersed in an etching solution (KSMF-100: manufactured by Kanto Chemical) at 40°C for approximately 40 seconds to etch the Al film, forming source and drain electrodes.

[0075] Next, the semiconductor layer was annealed in an atmospheric environment at 105° C. for 3 hours (annealing furnace: thermostatic machine with safety door manufactured by ESPEC Corporation), to produce a semiconductor device A having the structure shown in FIG.

[0076] For the semiconductor device A, the transfer characteristics were measured using a semiconductor parameter analyzer (Keithley: 4300A-SCS), and the film thickness was measured using KLA-Tencor P16+. The results are shown in FIG.

[0077] <Example 2> Semiconductor device B with a semiconductor layer of ZnGa2O4 (10 nm) / IGZTO (10 nm)

[0078] (Formation of IGZTO layer) A highly conductive n-type silicon substrate was prepared, consisting of a silicon wafer with an n-type resistivity of 0.0017 Ω·cm or less and a 200 nm thermal oxide film (SiO2) formed on it. A 10 nm IGZTO layer was formed on this substrate. The IGZTO layer was formed by RF sputtering using an IGZTO target (KOS-B02: Kobelco Research Institute, Inc.) and a sintered target of ZnGa2O4 with an atomic concentration of Zn:Ga of 8:1. The substrate temperature during film formation was set to 105°C, and Ar was used as the sputtering gas. At the same time, oxygen was introduced as a reactive gas at a volume ratio of 10% to Ar.

[0079] (Formation of a spinel-type ZnGa2O4 layer) Next, a 10 nm spinel-type ZnGa2O4 layer was formed to cover the above-mentioned IGZTO layer, obtaining a ZnGa2O4 / IGZTO semiconductor layer. The ZnGa2O4 layer was formed using a sintered ZnGa2O4 target in the same sputtering device as that used for forming the IGZO layer. The target output was controlled so that the composition ratio of Zn to Ga was 8:1, and the substrate was heated to 230°C to form a ZnGa2O4 layer with a spinel-type crystal structure. Ar gas containing no hydrogen was used as the sputtering gas. At the same time, oxygen was introduced as a reactive gas at a volume ratio of 10% relative to Ar. This controlled the absence of hydrogen or oxygen deficiency. The back pressure was 1×10 -4 The film was formed under the conditions of a film formation pressure of 0.22 Pa or less.

[0080] A resist material was applied to the obtained ZnGa2O4 / IGZTO semiconductor layer, and the resist material was patterned using a typical photolithography process. The semiconductor layer was then patterned by etching for approximately 3 minutes with an etching solution (ITO-07: manufactured by Kanto Chemical) heated to 40°C.

[0081] (Formation of source and drain electrodes) Then, Mo electrodes (thickness: 100 nm) serving as source and drain electrodes were formed by vacuum deposition so as to cover the semiconductor layer. The vacuum deposition was performed using a resistance heating type vacuum deposition apparatus.

[0082] Then, a resist material was applied onto the Mo film and patterned using a typical photolithography process. The Mo film was then immersed in an etching solution (KSMF-100: manufactured by Kanto Chemical) heated to 40°C for approximately 40 seconds for etching to form source and drain electrodes.

[0083] Next, the semiconductor layer was annealed in an atmospheric environment at 120° C. for 3 hours (annealing furnace: thermostatic machine with safety door manufactured by ESPEC Corporation), to produce a semiconductor device B having the structure shown in FIG.

[0084] For the semiconductor device B, the transfer characteristics were measured using a semiconductor parameter analyzer (Keithley: 4300A-SCS), and the film thickness was measured using KLA-Tencor P16+. The results are shown in FIG.

[0085] <Examples 3 to 6 and Comparative Examples 1 to 3> Evaluation of semiconductor devices with semiconductor layers of different thicknesses

[0086] Semiconductor devices having semiconductor layers with different thicknesses were fabricated, and the transfer characteristics were evaluated. Comparative Examples 1 to 3 did not have a ZnGa2O4 layer. The semiconductor devices were fabricated under the same conditions as in Example 2, except for the semiconductor layer formation conditions (thickness, presence or absence of a ZnGa2O4 layer), etching conditions, and post-treatment. The designed film thickness was controlled by the sputtering time. The etching conditions were immersion at room temperature for 1 minute. Post-treatment was performed at an annealing temperature of 120°C or 150°C for 3 hours. The film thickness was measured using P16+ manufactured by KLA-Tencor. The transfer characteristics were measured using a semiconductor parameter analyzer (manufactured by Keithley: 4300A-SCS). The results are shown in Figures 7 to 10.

[0087] Example 3 Semiconductor layer: Spinel-type ZnGa2O4 (10 nm) / IGZTO (20 nm) Annealing temperature: 120℃ Measurement results: Figure 7

[0088] Example 4 Semiconductor layer: Spinel-type ZnGa2O4 (10 nm) / IGZTO (30 nm) Annealing temperature: 120℃ Measurement results: Figure 7

[0089] Example 5 Semiconductor layer: Spinel-type ZnGa2O4 (10 nm) / IGZTO (10 nm) Annealing temperature: 150℃ Measurement results: Figure 8

[0090] Example 6 Semiconductor layer: Spinel-type ZnGa2O4 (10 nm) / IGZTO (20 nm) Annealing temperature: 150℃ Measurement results: Figure 8

[0091] Comparative Example 1 Semiconductor layer: IGZTO (10 nm) Annealing temperature: 120℃ Measurement results: Figure 9

[0092] Comparative Example 2 Semiconductor layer: IGZTO (30 nm) Annealing temperature: 120℃ Measurement results: Figure 9

[0093] Comparative Example 3 Semiconductor layer: IGZTO (10 nm) Annealing temperature: 150℃ Measurement results: Figure 10

[0094] As shown in Figures 6 to 8, it was found that the semiconductor devices of Examples 1 to 6 had good semiconductor characteristics. On the other hand, as shown in Figures 9 and 10, it was found that Comparative Examples 1 and 3 were not suitable as semiconductor devices because of the large hysteresis, and Comparative Example 2 was electrically conductive regardless of the voltage applied to the gate electrode and did not function as a semiconductor device. [Explanation of symbols]

[0095] REFERENCE SIGNS LIST 10 substrate, 20 third electrode, 30 insulating layer, 40 IGZO layer, 41 IGZTO layer, 50 spinel-type ZnGa2O4 layer, 60 semiconductor layer, 70 conductive layer, 71 first electrode, 72 second electrode, 80 pool wall, 90 reference electrode, A first semiconductor device, B second semiconductor device, C pH sensor, S solution

Claims

1. A first electrode; A second electrode; and a semiconductor layer in contact with the first electrode and the second electrode; having The semiconductor layer is a 5 to 20 nm spinel type ZnGa ２ O ４ and a second oxide layer of 5 to 50 nm containing In, Ga, and Zn.

2. 2. The semiconductor device according to claim 1, The second oxide layer comprises Sn.

3. 3. The semiconductor device according to claim 1, an insulating layer in contact with the semiconductor layer; a third electrode provided opposite the semiconductor layer with the insulating layer interposed therebetween; Further comprising: A semiconductor device in which the first electrode, the second electrode, and the third electrode function as a source electrode, a drain electrode, and a gate electrode, respectively, to form a transistor.

4. 3. The semiconductor device according to claim 1, The first electrode and the second electrode are on the first oxide layer.

5. An electronic device comprising the semiconductor device according to claim 1 or 2.

6. A pH sensor comprising the semiconductor device according to claim 1 .

7. A biosensor comprising the semiconductor device according to claim 1 .

8. 2. The method of manufacturing a semiconductor device according to claim 1, forming the semiconductor layer; forming a conductive layer on the semiconductor layer; Etching the conductive layer in accordance with a predetermined pattern to form the first electrode and the second electrode; A method for manufacturing a semiconductor device comprising the steps of:

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the step of forming the first oxide layer is performed at 190° C. or higher.

10. A method for manufacturing an electronic device, comprising the step of forming a semiconductor device by the method for manufacturing a semiconductor device according to claim 8 or 9.

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