Memory die with unique storage capacity

Abstract

To provide a memory die capable of operating in a QLC (4 bits per data cell) mode and a TLC (3 bits per memory cell) mode.SOLUTION: A plurality of memory cells that store 3 bits of data in each memory cell when a memory die is in a TCL operation mode is included. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is in the TCL operation mode. A plurality of memory cells that store 4 bits of data in each memory cell when the memory die is in a QLC operation mode is included. The memory die has a binary data capacity, which is a multiple of 1 Tb, when the memory die is operating in the QLC operation mode.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present disclosure relates generally to memory devices, and more particularly to memory devices configured to operate in a multi-bit per memory cell mode. [Background technology]

[0002] Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, electronic medical devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows the non-volatile memory to store and retain information even when it is not connected to a power source (e.g., a battery).

[0003] Such non-volatile memory devices generally include one or more memory dies, including an array wafer having a plurality of memory cells, and a CMOS wafer containing electrical components for programming, reading, and erasing the memory cells in the memory blocks. As technology improves, array wafer sizes are decreasing more rapidly than CMOS wafer sizes.

[0004] Memory products traditionally have binary capacities, e.g., 256GB, 512GB, 1TB, 2TB, etc. In other words, the capacity of many memory products, as measured in either gigabytes, terabytes, etc., is traditionally expressed in binary units. n where n is 0 or a positive integer. Similarly, the memory dies found in these memory products traditionally have binary capacities, although they are measured in gigabits, terabits, etc. (e.g., 256 Gb, 512 Gb, 1 Tb, 2 Tb, etc.). Summary of the Invention

[0005] One aspect of the disclosure relates to a memory die including a plurality of memory blocks, each memory block including a plurality of memory cells configured to store three bits of data in each memory cell when the memory die is in a TLC mode of operation, the memory die having a non-binary data capacity when operating in the TLC mode of operation.

[0006] According to another aspect of the present disclosure, the non-binary data capacity of the memory die when operating in the TLC mode of operation is a multiple of six hundred eighty-three gigabits (683 Gb).

[0007] According to yet another aspect of the present disclosure, the non-binary data capacity of the memory die when operating in the TLC mode of operation is six hundred eighty-three gigabits (683 Gb).

[0008] According to yet another aspect of the present disclosure, the plurality of memory blocks includes a main block that contributes to the non-binary data capacity of the memory die when operating in a TLC mode of operation and an extension block that does not contribute to the non-binary data capacity of the memory die when operating in the TLC mode of operation.

[0009] According to a further aspect of the present disclosure, the memory die can be configured to operate in a QLC mode of operation, the memory die having a binary data capacity when operating in the QLC mode of operation.

[0010] According to a further aspect of the present disclosure, when the memory die is in a TLC mode of operation, the plurality of memory blocks includes a first plurality of main blocks that contribute to the non-binary data capacity and a plurality of extended blocks that do not contribute to the non-binary data capacity, and when the memory die is in a QLC mode of operation, the plurality of memory blocks includes a second plurality of main blocks that contribute to the binary data capacity, the second plurality of main blocks being larger than the first plurality of main blocks.

[0011] According to still further aspects of the present disclosure, the first plurality of main blocks is less than or equal to 80 percent of the plurality of memory blocks.

[0012] According to another aspect of the present disclosure, the memory die further includes a CMOS layer overlying the array layer including the plurality of memory blocks.

[0013] Another aspect of the disclosure relates to a memory device including a plurality of memory dies each including a plurality of memory blocks having memory cells configured to store three bits of data in each memory cell when the memory device is operating in a TLC mode of operation, wherein each of the memory dies has a non-binary data capacity and the memory dies combine to provide a memory device having a binary data capacity when operating in the TLC mode of operation.

[0014] According to another aspect of the present disclosure, the non-binary data capacity of the memory die when operating in the TLC mode of operation is a multiple of six hundred eighty-three gigabits (683 Gb).

[0015] According to yet another aspect of the present disclosure, the non-binary data capacity of the memory die when operating in the TLC mode of operation is six hundred eighty-three gigabits (683 Gb).

[0016] According to yet another aspect of the present disclosure, the plurality of memory blocks in each of the memory die includes a main block that contributes to the non-binary data capacity of the memory die when operating in a TLC mode of operation and an extension block that does not contribute to the non-binary data capacity of the memory die when operating in the TLC mode of operation.

[0017] According to a further aspect of the present disclosure, the memory die can be configured to operate in a QLC mode of operation, the memory die having a binary data capacity when operating in the QLC mode of operation.

[0018] According to yet a further aspect of the present disclosure, when the memory die is in a TLC mode of operation, the plurality of memory blocks includes a first set of main blocks that contribute to a non-binary data capacity, and when the memory die is in a QLC mode of operation, the plurality of memory blocks includes a second set of main blocks that contribute to a binary data capacity, the second plurality of main blocks being larger than the first plurality of main blocks.

[0019] According to still further aspects of the present disclosure, the first plurality of main blocks is less than or equal to 80 percent of the plurality of memory blocks.

[0020] According to another aspect of the disclosure, each of the memory dies includes an array layer having a plurality of memory blocks and a CMOS layer overlying the array layer.

[0021] Yet another aspect of the disclosure relates to a method of fabricating a plurality of memory devices. The method includes forming a plurality of array layers. Each of the array layers includes a plurality of memory cells arranged in a plurality of memory blocks. The method continues with bonding the array layers with a plurality of CMOS layers including electrical components for programming, reading, and erasing the plurality of memory cells to form a plurality of memory dies. The method continues with configuring a first set of the plurality of memory dies to operate in a TLC mode of operation with a non-binary data capacity. The method continues with configuring a second set of the plurality of memory dies to operate in a QLC mode of operation with a binary data capacity.

[0022] According to another aspect of the disclosure, the non-binary data capacity of each memory die of the first set of memory dies is a multiple of 683 Gb.

[0023] According to yet another aspect of the present disclosure, the non-binary data capacity of each memory die of the first set of memory dies is 683 Gb.

[0024] According to yet another aspect of the present disclosure, the binary data capacity of each memory die of the second set of memory dies is 1 Tb.

[0025] According to a further aspect of the present disclosure, the method further includes combining a plurality of memory dies of the first set of memory dies into a single memory device having a binary data capacity.

[0026] A further aspect of the present disclosure relates to a memory die including a plurality of memory blocks, each of which includes a plurality of memory cells, the plurality of memory blocks including a plurality of main memory blocks that contribute to a data capacity of the memory die and a plurality of extension blocks that do not contribute to the data capacity of the memory blocks, the data capacity of the memory die being a non-binary quantity.

[0027] According to another aspect of the disclosure, the plurality of memory cells are configured to store three bits of data per memory cell.

[0028] According to yet another aspect of the present disclosure, the non-binary data capacity of the memory die is a multiple of 683 Gb.

[0029] According to yet another aspect of the present disclosure, the non-binary data capacity of the memory die is 683 Gb.

[0030] Yet another aspect of the present disclosure relates to a method of operating a memory device, the method including providing a memory device including at least one memory die, the memory die including a plurality of memory blocks and having a maximum data capacity that is a non-binary quantity, the method further including programming memory cells of the memory die to the maximum data capacity.

[0031] According to another aspect of the disclosure, the plurality of memory cells are configured to store three bits of data per memory cell.

[0032] According to yet another aspect of the present disclosure, the maximum data capacity is a multiple of 683 Gb.

[0033] According to yet another aspect of the present disclosure, the maximum data capacity is 683 Gb.

[0034] Yet another aspect of the present disclosure relates to a memory die including a plurality of memory blocks, each memory block including a plurality of memory cells configured to store three bits of data in each memory cell when the memory die is in a TLC mode of operation, the memory die having a data capacity of 683 Gb when operating in the TLC mode of operation. [Brief description of the drawings]

[0035] A more detailed description is provided below with reference to exemplary embodiments illustrated in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure. The present disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings. [Figure 1A] FIG. 1 is a block diagram of an exemplary memory device. [Figure 1B] FIG. 2 is a block diagram of an exemplary control circuit. [Diagram 2] 1B illustrates blocks of memory cells in an exemplary two-dimensional configuration of the memory array of FIG. 1A. [Figure 3A] 1 illustrates a cross-sectional view of an exemplary floating gate memory cell in a NAND string. [Figure 3B] 1 illustrates a cross-sectional view of an exemplary floating gate memory cell in a NAND string. [Figure 4A] 1 illustrates a cross-sectional view of an exemplary charge trapping memory cell in a NAND string. [Figure 4B] 1 illustrates a cross-sectional view of an exemplary charge trapping memory cell in a NAND string. [Diagram 5] 2 shows an exemplary block diagram of the sensing block SB1 of FIG. 1; [Figure 6A] 2 is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1. [Figure 6B] 6B shows an exemplary cross-sectional view of a portion of one of the blocks of FIG. 6A. [Figure 6C] 6C shows a plot of memory hole diameter for the stack of FIG. 6B. [Figure 6D] 6C shows an enlarged view of region 622 of the stack of FIG. 6B. [Figure 7A] FIG. 6C is a top view of an example word line layer WLL0 of the stack of FIG. 6B. [Figure 7B] FIG. 6C is a top view of an exemplary upper dielectric layer DL116 of the stack of FIG. 6B. [Figure 8] 1 is a perspective view of an example memory die having a CMOS layer and an array layer. [Figure 9] 1 is a cross-sectional view of an exemplary memory die having a chip under array (CUA) structure. [Figure 10] 1 shows threshold voltage distributions for a group of memory cells programmed with one bit per memory cell (SLC). [Figure 11] 1 shows the threshold voltage distribution of a group of memory cells programmed with 3 bits per memory cell (TLC). [Figure 12] 1 shows the threshold voltage distribution of a group of memory cells programmed with 4 bits per memory cell (QLC). [Figure 13A] 1 is a schematic diagram of a first memory device having a data capacity of 256 GB and including three memory dies each having a data capacity of 683 Gb. [Figure 13B] 1 is a schematic diagram of a first memory device having a data capacity of 512 GB and including six memory dies each having a data capacity of 683 Gb. [Figure 14] 1 is a plot showing which memory blocks in an example memory die are main blocks and which memory blocks are extended blocks when the memory die is operating in a QLC (4 bits per memory cell) operating mode. [Figure 15] 1 is a plot showing which memory blocks in an exemplary memory die are main blocks and which memory blocks are extended blocks when the memory die is operating in a TLC (three bits per memory cell) operating mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The present disclosure relates to a low-cost memory device having a non-conventional (non-binary) data capacity, but can be joined with other such memory dies to form a memory device having a conventional (binary) data capacity. More specifically, the memory die has a data capacity of six hundred and eighty-three gigabits (683 Gb) while operating in a TLC (three bits per memory cell) storage scheme. In one exemplary embodiment, three such memory dies are packaged together in a single memory device having a storage capacity of two hundred and fifty-six gigabytes (256 GB). In other embodiments, different numbers of memory dies can be packaged together to form other memory devices having binary data capacities, such as, for example, 512 GB, 1 TB, 2 TB, 4 TB, etc.

[0037] The memory die may also be configured to operate in a QLC (4 bits per data cell) storage scheme and to have a binary data capacity when operating in the QLC storage scheme.

[0038] 1A is a block diagram of an exemplary memory device 100 including one or more memory dies 108 with non-binary capacity. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuit 128 includes multiple sense blocks SB1, SB2, ... SBp (sense circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0039] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include one or more arrays of memory cells that include a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not within) a single substrate, such as a wafer, with no intervening substrates. The memory structure 126 may include any type of non-volatile memory formed monolithically at one or more physical levels of an array of memory cells having active areas disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0040] Control circuitry 110, in cooperation with read / write circuitry 128, performs memory operations in memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations.

[0041] The storage area 113 may be provided for programming parameters, for example. The programming parameters may include a program voltage, a program voltage bias, a position parameter indicating a position of the memory cell, a thickness parameter of the contact line connector, a verify voltage, etc. The position parameter may indicate a position of the memory cell within an entire array of NAND strings, a position of the memory cell in a particular group of NAND strings, a position of the memory cell on a particular plane, etc. The thickness parameter of the contact line connector may indicate a thickness of the contact line connector, a substrate, or a material of which the contact line connector is made, etc.

[0042] An on-chip address decoder 114 provides an address interface between those used by the host or memory controller and the hardware addresses used by decoders 124 and 132. A power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. This can include drivers for the word lines, SGS and SGD transistors, and source lines. The sense block, in one approach, can include bit line drivers. The SGS transistors are the select gate transistors at the source end of the NAND strings, and the SGD transistors are the select gate transistors at the drain end of the NAND strings.

[0043] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the activities described herein. For example, the control circuit may include any one or combination of the control circuit 110, the state machine 112, the decoders 114 / 132, the power control module 116, the sense blocks SBb, SB2, ..., SBp, the read / write circuit 128, the controller 122, etc.

[0044] The control circuitry may include a programming circuit configured to perform program and verify operations on a set of memory cells, the set of memory cells including memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states, the program and verify operations including a plurality of program and verify iterations, in each program and verify iteration the programming circuit performs programming of one selected word line, and thereafter the programming circuit applies a verify signal to the selected word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells passing a verify test of one data state. The control circuitry may also include a decision circuit configured to determine whether the programming operation is complete based on the amount by which the count exceeds a threshold.

[0045] For example, FIG. 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a decision circuit 153.

[0046] The off-chip controller 122 may include a processor 122c, storage devices (memories) such as ROM 122a and RAM 122b, and an error-correction code (ECC) engine 245. The ECC engine may correct a number of read errors that occur when the upper tail of the Vth distribution becomes too high. However, in some cases, there may be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors occurring.

[0047] The storage devices 122a, 122b include code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor 122c may access code from the storage device 126a of the memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. For example, the code may be used by the controller 122 to access the memory structure 126, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 during a boot or start-up process and allows the controller 122 to access the memory structure 126. The code may be used by the controller 122 to control one or more memory structures 126. Upon power-up, the processor 122c fetches the boot code from the ROM 122a or the storage device 126a for execution, which initializes system components and loads the control code into the RAM 122b. Once loaded into RAM 122b, the control code is executed by processor 122c. The control code includes drivers for performing basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0048] In general, the control code can include instructions to perform the functions described herein, including the steps of the flow diagrams further discussed below, and can provide voltage waveforms, including those further discussed below.

[0049] In one embodiment, the host is a computing device (e.g., notebook, desktop, smartphone, tablet, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0050] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0051] Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and non-volatile memory devices such as magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0052] A memory device may be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or a phase change material, and optionally a steering element, such as a diode or a transistor. By way of further non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0053] The memory elements may be configured such that the memory elements are connected in series or each element is individually accessible. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically include memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and SG transistors.

[0054] A NAND memory array may be configured such that the array is made up of multiple memory strings, where a string is made up of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be configured in alternative ways. Semiconductor memory elements located within and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure, or a three-dimensional memory structure.

[0055] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., an xy-directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on or within which layers of memory elements are formed, or may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0056] The memory elements may be arranged in an ordered array, such as multiple rows and / or columns, in a single memory device level. However, the memory elements may be arranged in a non-regular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0057] A three-dimensional memory array is one in which memory elements are arranged to occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional (i.e., x, y, and z directions, where the z direction is substantially perpendicular to the major surface of the substrate and the x and y directions are substantially parallel to the major surface of the substrate) structure.

[0058] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in the xy plane, resulting in a three-dimensional arrangement of memory elements with elements in multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also make up a three-dimensional memory array.

[0059] As a non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned in which some NAND strings contain memory elements at a single memory level and other strings contain memory elements across multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0060] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the memory device level below the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intervening layers between the memory device levels.

[0061] From another perspective, two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. Although the substrate may be thinned or removed from the memory device levels before stacking, the resulting memory array is not a monolithic three-dimensional memory array because the memory device levels are first formed across separate substrates. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0062] FIG. 2 illustrates blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1. The memory array 126 may include many such blocks 200, 210. Each exemplary block 200, 210 includes a number of NAND strings and corresponding bit lines, e.g., BL0, BL1, ..., that are shared between the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), whose control gates are connected via a common SGD line. The NAND strings are connected at their other ends to a source-side select gate (SGS), which is in turn connected to a common source line 220. 112 word lines, e.g., WL0-WL111, extend between SGS and SGD. In some embodiments, the memory block may include more or less than 112 word lines. For example, in some embodiments, the memory block includes 164 word lines. In some cases, dummy word lines containing no user data may also be used in the memory array adjacent to the select gate transistors. Such dummy word lines may shield the edge data word lines from certain edge effects.

[0063] One type of non-volatile memory that may be provided in the memory array is a floating gate memory, such as the type shown in Figures 3A and 3B. However, other types of non-volatile memory may be used. In another embodiment shown in Figures 4A and 4B, discussed in more detail below, a charge trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed from silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, which are captured and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. Similar cells may be provided in a split gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0064] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending across the channel between the source and drain diffusions. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multistate data storage is obtained by separately reading the binary states of spatially separated charge storage regions in the insulator. Other types of non-volatile memories are also known.

[0065] FIG. 3A illustrates a cross-sectional view of exemplary floating gate memory cells 300, 310, 320 in a NAND string. In this view, the bit line or NAND string direction is into the page and the word line direction runs from left to right. As an example, a word line 324 extends across a NAND string including corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, 320 is in a different corresponding NAND string. An inter-poly dielectric (IPD) layer 328 is also shown. Control gates 302, 312, 322 are part of the word lines. A cross-sectional view along contact line connector 329 is shown in Figure 3B.

[0066] The control gates 302, 312, 322 wrap around the floating gates 304, 314, 321, increasing the surface contact area between the control gates 302, 312, 322 and the floating gates 304, 314, 321. This results in higher IPD capacitance, leading to a higher coupling ratio and facilitating programming and erasing. However, as NAND memory devices are scaled down, the spacing between adjacent cells 300, 310, 320 becomes smaller, so there is little space for the control gates 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 302, 312, 322.

[0067] Alternatively, flat or planar memory cells 400, 410, 420 have been developed in which the control gate 402, 412, 422 is flat or planar, as shown in Figures 4A and 4B. That is, the control gate does not wrap around the floating gate, and its contact with the charge storage layer 428 is only from above. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate becomes quite thin. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic conduction of electrons, which may move through the floating gate after tunneling through the tunnel oxide during programming.

[0068] FIG. 4A shows a cross-sectional view of an exemplary charge trapping memory cell 400, 410, 420 in a NAND string. The view is in the word line direction of the memory cell 400, 410, 420 including a planar control gate and a charge trapping region as a two-dimensional example of the memory cell 400, 410, 420 in the memory cell array 126 of FIG. 1. Charge trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, as opposed to floating gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. As an example, a word line 424 extends across the NAND string including the corresponding channel regions 406, 416, 426. Portions of the word line provide the control gates 402, 412, 422. Below the word lines are an IPD layer 428, charge trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge trapping layer 404, 414, 421 extends continuously within the corresponding NAND string. The planar configuration of the control gate allows it to be thinner than the floating gate. In addition, the memory cells can be closer together.

[0069] FIG. 4B shows a cross-sectional view of the structure of FIG. 4A along the contact wire connector 429. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Vias in the IPD layer 428 in the SGS and SGD transistors 431, 436 allow the control gate layer 402 and the floating gate layer to communicate. For example, the control gate 402 and the floating gate layer may be polysilicon and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O) as in the NONON configuration.

[0070] The NAND string may be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be applied directly to the channel region of the substrate.

[0071] FIG. 5 illustrates an exemplary block diagram of the sense block SB1 of FIG. 1. In one approach, the sense block includes multiple sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subsets of bit lines may be sensed using different corresponding sense blocks. This allows the processing load associated with the sense circuits to be divided and handled by corresponding processors in each sense block. For example, a sense circuit controller 560 of SB1 may communicate with a set of sense circuits and latches. The sense circuit controller 560 may include a recharge circuit 561 that provides a voltage to each sense circuit for setting a recharge voltage. In one possible approach, a voltage is provided independently to each sense circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided simultaneously to each sense circuit. The sense circuit controller 560 may also include a recharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with the sense circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing voltages to set recharge levels to the sense nodes of the sense circuits 550a, 551a, 552a, 553a. Further exemplary details of the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, 553a are provided below.

[0072] In some embodiments, the memory cells may include a flag register that includes a set of latches that store flag bits. In some embodiments, the amount of flag registers may correspond to an amount of data states. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying the memory cells. In some embodiments, the output of the flag bits may modify associated logic of the device, such as address decoding circuitry, such that a particular block of cells is selected. Bulk operations (such as, for example, erase operations) may be performed using flags set in the flag register, or using a combination of the flag register and the address register, such as in implicit addressing, or alternatively by straight addressing using only the address register.

[0073] 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. 1. On the substrate are blocks of memory cells (storage elements) BLK0, BLK1, BLK2, and BLK3, as well as a peripheral region 604 having circuitry used by the blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 605 that may be connected to the control gate layers of the blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in the blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry circuitry beneath the blocks BLK0, BLK1, BLK2, and BLK3, with one or more lower metal layers patterned in conductive paths to carry the signals of the circuitry. The blocks BLK0, BLK1, BLK2, and BLK3 are formed in an intermediate region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry the circuit signals. Each block BLK0, BLK1, BLK2, and BLK3 includes a stacked region of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each block BLK0, BLK1, BLK2, and BLK3 has opposing layered sides with vertical contacts extending up to the upper metal layer to form connections to the conductive paths. Although four blocks BLK0, BLK1, BLK2, and BLK3 are shown as examples, two or more blocks extending in the x-direction and / or y-direction can be used.

[0074] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal paths to the wordlines extend through one or more upper metal layers (wordline or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal paths to the bitlines extend through one or more upper metal layers (bitline direction), and the z-direction represents the height of the memory device.

[0075] FIG. 6B illustrates an exemplary cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3 of FIG. 6A. The block includes a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include data word line layers (word lines) WL0-WL111, as well as two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0-DL116. Additionally, a region of the stack 610 is shown that includes NAND strings NS1 and NS2. Each NAND string includes memory holes 618, 619 filled with material that forms the memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in more detail in FIG. 6D and will be discussed in more detail below.

[0076] The stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits such as metal-filled slits) 617, 620 may be provided periodically across the stack 610 as interconnects extending through the stack 610 to connect the source lines to specific contact lines above the stack 610. The contact line connectors 617, 620 may be used during the formation of the word lines and subsequently filled with metal. A portion of a bit line BL0 is also shown. A conductive via 621 connects the drain end 615 to BL0.

[0077] FIG. 6C shows a plot of memory hole diameters for the stack of FIG. 6B. The vertical axis is aligned with the stack of FIG. 6B and shows the width (wMH), e.g., diameter, of memory holes 618 and 619. The word line layers WL0-WL111 of FIG. 6A are repeated as an example, at corresponding heights z0-z111 in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25-30 is typical. The memory holes may have a circular cross section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, which causes the diameter to be slightly wider and then gradually narrower from the top to the bottom of the memory hole.

[0078] Due to the non-uniformity of the memory hole width, the programming speed, including the program ramp and erase speed, of the memory cells may vary based on their position along the memory hole, e.g., based on their height in the stack. The smaller the diameter of the memory hole, the stronger the electric field across the tunnel oxide, and therefore the higher the programming and erase speed. One approach is to define groups of adjacent word lines with similar memory hole diameters, e.g., within a defined diameter range, and apply an optimized verify scheme for each word line in the group. Different groups may have different optimized verify schemes.

[0079] FIG. 6D shows an expanded view of region 622 of stack 610 of FIG. 6B. Memory cells are formed at the intersections of word line layers and memory holes at different levels of the stack. In this embodiment, SGD transistors 680, 681 are provided above dummy memory cells 682, 683 and data memory cells MC. Several layers may be deposited along the sidewalls (SW) of memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., pillar formed by material within memory hole 630) may include a charge trapping layer or film 663, such as SiN or other nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / blocking high-k material 660 as a control gate, a metal barrier 661, and a conductive metal 662, such as tungsten. For example, control gates 690, 691, 692, 693, and 694 are provided. In this embodiment, all layers except metal are provided in the memory hole 630. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars can form the columnar active areas (AA) of the NAND strings.

[0080] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are drawn from the channel through the tunnel layer into the charge trapping layer. The Vth of the memory cell increases in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0081] Each of the memory holes 630 may be filled with multiple annular layers including a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. A core region of each of the memory holes 630 is filled with a body material, and the multiple annular layers are between the core region of each of the memory holes 630 and the word lines.

[0082] The NAND strings can be considered to have floating body channels because the length of the channel is not formed above the substrate, and further, the NAND strings are provided by multiple wordline layers above each other in a stack and are separated from each other by dielectric layers.

[0083] FIG. 7A shows a top view of an exemplary word line layer WL0 of the stack 610 of FIG. 6B. As described above, a three-dimensional memory device can include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates of the SG transistors and memory cells. The layers used for the SG transistors are the SG layers, and the layers used for the memory cells are the word line layers. Furthermore, memory holes are formed in the stack and filled with charge trapping material and channel material. This forms a vertical NAND string. A source line is connected to the NAND string below the stack, and a bit line is connected to the NAND string above the stack.

[0084] A block BLK in a three-dimensional memory device can be divided into sub-blocks, each of which includes a NAND string group with a common SGD control line. For example, see SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, a word line layer in a block can be divided into regions. Each region can be in a respective sub-block and extend between contact line connectors (e.g., slits) periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The processing can include replacing sacrificial material of the word line layer with metal. In general, the distance between the contact line connectors needs to be relatively small, considering the limit of the distance that the etchant can move laterally to remove the sacrificial material and the metal can move to fill the void created by the removal of the sacrificial material. For example, the distance between the contact line connectors can allow several rows of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors must also consider the limit of the number of bit lines that can extend across the region while each bit line is connected to a different memory cell. After processing the wordline layers, the contact line connectors can optionally be filled with metal to provide interconnections through the stack.

[0085] In this example, there are four rows of memory holes between adjacent contact line connectors. Here, a row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are in a staggered pattern to increase the density of memory holes. The word line layer or word lines are divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by a contact line 713. The last region of the word line layer in a block may be connected to the first region of the word line layer in the next block, in one approach. The contact line 713 is then connected to a voltage driver for the word line layer. Region WL0a has exemplary memory holes 710, 711 along contact line 712. Region WL0b has exemplary memory holes 714, 715. Region WL0c has exemplary memory holes 716, 717. Region WL0d has exemplary memory holes 718, 719. The memory holes are also shown in FIG. 7B. Each memory hole may be part of a respective NAND string. For example, memory holes 710, 714, 716, and 718 may be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0086] Each circle represents a cross section of a memory hole in a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and by adjacent word line layers. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0087] Contact line connectors (e.g., slits such as metal filled slits) 701, 702, 703, 704 may be disposed adjacent between the edges of regions WL0a-WL0d. The contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, which is connected to a voltage driver in a peripheral region of the memory device.

[0088] FIG. 7B shows a top view of an exemplary upper dielectric layer DL116 of the stack of FIG. 6B. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a respective voltage driver. This allows a set of memory cells in one region of the word line layer to be programmed simultaneously, with each memory cell in a respective NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or inhibit programming during each program voltage.

[0089] Region DL116a has exemplary memory holes 710, 711 along with contact line 712 that coincides with bit line BL0. A number of bit lines extend above and connect to the memory holes, as indicated by the "X" symbols. BL0 connects to a set of memory holes including memory holes 711, 715, 717, 719. Another exemplary bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, 718. Contact line connectors (e.g., slits such as metal filled slits) 701, 702, 703, 704 from FIG. 7A are also shown extending vertically through the stack. The bit lines may be numbered in the sequence BL0-BL23 across the DL116 layers in the x-direction.

[0090] Different subsets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells on the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in an adjacent row of cells adjacent to the first row on the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells on the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in an adjacent row of memory cells adjacent to the first row on the left edge.

[0091] 8, some memory dies have a CMOS under array ("CUA") architecture whereby peripheral circuitry (e.g., page buffers, sense amplifiers [S / A], charge pumps, etc.) are located in a CMOS wafer 800 that is located below an array wafer 802 that contains a vertical stack of memory cells. The array wafer 802 in this example includes four planes 804, 806, 808, 810, and the CMOS wafer includes four sense amplifier regions, one in each of the planes 804, 806, 808, 810. In some embodiments, the array wafer may include more or less than four planes, and the number of sense amplifier regions may be equal to or less than the number of planes.

[0092] 9 illustrates a cross section of an exemplary memory die having a CUA architecture. In this embodiment, peripheral semiconductor devices 900 of the memory device are located below the memory array area 902 such that wordlines 904W and memory aperture fill structures 906 are located above the peripheral semiconductor devices 900.

[0093] The peripheral semiconductor device 900 includes a driver circuit transistor 908 that includes a gate electrode structure 910, an active area 912 (i.e., source and drain regions), and a semiconducting channel 914 underlying the gate electrode structure 908. The peripheral semiconductor device 900 also includes a lower level dielectric material layer 916 and a lower level metal interconnect structure 918 electrically connected to a node (e.g., gate electrode structure 910 and / or active area 912) of the driver circuit transistor (e.g., a CMOS type transistor) 908.

[0094] A peripheral region contact via structure 920 in region 922 and / or a memory region through-via structure 924 in region 902 are formed in electrical contact with the lower level metal interconnect structure 918. An interconnect line structure 926 and a bit line 928 are formed in an interconnect level dielectric layer 930. The interconnect line structure 926 electrically connects the contact via structure 932 to the peripheral region contact via structure 920 and / or the memory region through-via structure 924. A horizontal source line 934 may include one or more doped polysilicon layers. An optional conductive plate 936, such as a metal or metal silicide plate, may be placed in contact with the horizontal source line 934 to improve electrical conductivity. Another memory die architecture is known as CMOS bonded to array (CBA), which is similar to the CUA array architecture, but has a CMOS wafer placed vertically above rather than below the vertical stack. In memory dies having both the CUA and CBA architectures, the CMOS layer overlaps the array layer.

[0095] The memory cells of a memory block can be programmed to store one or more bits of data in multiple data states. Each data state is associated with a respective threshold voltage Vt. For example, FIG. 10 shows the threshold voltage Vt distribution of a group of memory cells programmed according to a one bit per cell (SLC) storage scheme. In the SLC storage scheme, there are two total data states, including an erased state (Er) and a single programmed data state (S1). FIG. 11 shows the threshold voltage Vt distribution of a three bits per cell (TLC) storage scheme, which includes eight total data states, namely an erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with a verify voltage (Vv1-Vv7) that is used during the verify portion of the programming operation. 12 shows the threshold voltage Vt distribution for a 4-bits-per-cell (QLC) storage scheme with 16 total data states, namely the erased state (Er) and 15 programmed data states (S1-S15). Other storage schemes are also available, such as 2-bits-per-cell (MLC) with 4 data states or 5-bits-per-cell (PLC) with 32 data states.

[0096] In some memory dies, the memory blocks may be configured to operate in multiple storage modes, for example, SLC and TLC, or SLC and QLC. The memory device may then be configured to first write data to the memory blocks operating in the SLC mode, which provides high performance. Then, in background operations when performance is not critical, the memory device may program that data into a multi-bit per memory cell format for long-term storage.

[0097] According to one aspect of the present disclosure, a memory die is provided that can be configured to operate in either a QLC mode with a binary data capacity of 1 Tb, or a TLC mode with a non-binary capacity of 683 Gb, with zero or minimal difference between memory dies that can operate in QLC and TLC modes. Thus, being useful in both QLC and TLC modes of operation, memory blocks can be used in different products with different purposes and can be manufactured in higher volumes and at lower costs per memory die through economies of scale. As used herein, the term binary capacity refers to a capacity of 2 n It means a data capacity equal to Gb, Tb, etc., or GB, TB, etc., where n is 0 or a positive integer.

[0098] Although 683 Gb is a non-binary data capacity, multiple memory blocks with this particular non-binary capacity can be packaged together into a single memory product with a binary capacity. For example, in the embodiment of FIG. 13A, three memory dies 1300 configured to operate in TLC mode and each having a capacity of 683 Gb are packaged together to form a TLC memory product 1302 with a capacity of 256 GB. In the embodiment of FIG. 13B, six memory dies 1300 each having a capacity of 683 Gb are packaged together to form a TLC memory product 1304 with a capacity of 512 GB. This pattern can be scaled up. For example, a memory product with a capacity of 2 Tb can be made by packaging together 24 memory dies of 683 Gb, or a memory product with a capacity of 4 TB can be made by packaging together 48 memory dies of 683 Gb.

[0099] 14, when the memory die 1400 is operating in QLC mode, approximately ninety percent (90%) of the memory blocks are main blocks 1402 and ten percent (10%) of the memory blocks are extended blocks 1404 to provide the memory die 1400 with a data capacity of 1 Tb. In an example where the memory die 1400 includes 507 memory blocks, when operating in QLC mode, 456 memory blocks are main blocks 1402 and 51 memory blocks are extended blocks 1404. Now referring to FIG. 15, when the memory die 1400 is in TLC mode with a data capacity of 683 Gb, approximately eighty percent (80%) of the memory blocks are main blocks 1402 and approximately twenty percent (20%) of the memory blocks are extended blocks 1404. In an exemplary embodiment, 406 memory blocks are main blocks 1402 and 101 memory blocks are extended blocks 1404. The extension blocks 1404 may be used to store data by replacing any of the main blocks 1402 that may become defective and cannot be repaired. The extension blocks 1404 may also be used to temporarily store data (without counting the data against the data capacity) during certain operations of the memory die 1400. By having such a large number of extension blocks 1404 within the memory die 1400 when the memory die 1400 is operating in TLC mode, the performance of the memory die 1400 is and remains high over its operational life.

[0100] In some embodiments, when operating in TLC mode, the memory die can have a capacity equal to or approximately equal to any multiple of 683 Gb, for example, 1.33 Tb, 2.67 Tb, 3.33 Tb, 4.67 Tb, 5.34 Tb, etc.

[0101] Various terms are used herein to refer to specific system components. Different companies may refer to the same or similar components by different names, and this description is not intended to distinguish between components that differ in name but not function. To the extent that various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly limit the range of potential implementation mechanisms. For example, a "module" may be implemented as a hardware circuit including custom very-large-scale integration (VLSI) circuits or gate arrays, or off-the-shelf semiconductors including logic chips, transistors, or other discrete components. In further embodiments, a module may also be implemented in a programmable hardware device, such as a field programmable gate array (FPGA), programmable array logic, programmable logic device, or the like. Furthermore, a module may also be implemented, at least in part, by software executed by various types of processors. For example, a module may include segments of executable code that make up one or more physical or logical blocks of computer instructions that translate into an object, process, or function. Also, executable portions of such modules need not be physically located together, but rather comprise separate instructions stored in different locations that, when executed together, comprise the identified module and achieve the stated purpose of that module. Executable code may comprise only a single instruction or a set of multiple instructions, and may similarly be distributed across different code segments, or among different programs, or among several memory devices, etc. In a software or partial software modular implementation, the software portions may be stored in one or more computer-readable and / or executable storage media, including, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, apparatus, or device, or any suitable combination thereof.Generally, for purposes of this disclosure, a computer-readable and / or executable storage medium may comprise any tangible and / or non-transitory medium that can contain and / or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

[0102] Similarly, for purposes of this disclosure, the term "component" may be comprised of any tangible, physical, and non-transitory device. For example, a component may be in the form of a hardware logic circuit comprised of custom VLSI circuits, gate arrays, or other integrated circuits, or may be in the form of a hardware logic circuit comprised of off-the-shelf semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic devices. In addition, a component may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, programmable logic device, or the like. Furthermore, a component may be comprised of one or more silicon-based integrated circuit devices such as chips, dies, die planes, and packages, or other discrete electrical devices, in electrical communication with one or more other components via electrical conductors, such as a printed circuit board (PCB). Thus, as defined above, a module may be embodied by or implemented as a component in certain embodiments, and in some cases, the terms module and component may be used interchangeably.

[0103] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow an electric current to flow. A circuit may be in the form of a closed loop or an open loop configuration. In a closed loop configuration, the circuit components may provide a return path for the electric current. In contrast, in an open loop configuration, the circuit components therein may still be considered to form a circuit, even though they do not include a return path for the electric current. For example, an integrated circuit is referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for the electric current). In certain exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other types of integrated circuits, as well as commercially available semiconductors such as logic chips, transistors, or other discrete devices. In further examples, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, in electrical communication with one or more other components, for example, via electrical conductors of a printed circuit board (PCB). A circuit may also be implemented as a composite circuit in terms of programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, a circuit may include a network of non-integrated electric and / or electronic components (with or without integrated circuit devices). Thus, as defined above, a module may, in certain embodiments, be embodied by or implemented as a circuit.

[0104] It will be understood that the exemplary embodiments disclosed herein may be configured with one or more microprocessors and certain stored computer program instructions that control the one or more microprocessors to implement some, most, or all of the functions disclosed herein, along with certain non-processor circuitry and other elements. Alternatively, some or all of the functions may be implemented by state machines without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), with each function or some combination of specific functions being implemented as custom logic. A combination of these approaches may also be used. Furthermore, references below to a "controller" should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or processors with control software, or combinations thereof.

[0105] Additionally, the terms "coupled," "coupled," or "couple" as may be used herein are intended to mean either a direct or indirect connection. Thus, when a first device couples or is coupled to a second device, the connection may be by a direct connection or through an indirect connection via other devices (or components) and connections.

[0106] With respect to the use herein of terms such as "an embodiment," "one embodiment," "exemplary embodiment," "particular embodiment," or other similar terminology, these terms are intended to indicate that a particular feature, structure, function, operation, or characteristic described in connection with an embodiment is found in at least one embodiment of the present disclosure. Thus, expressions such as "in one embodiment," "in an embodiment," "in an exemplary embodiment," and the like do not necessarily all refer to the same embodiment, but rather may mean "one or more, but not all, embodiments," unless otherwise expressly stated. Furthermore, the terms "comprising," "having," and "including," as well as variations thereof, are used in an open-ended manner and thus should be interpreted to mean "including, but not limited to," unless otherwise expressly stated. Furthermore, an element preceded by "comprising" does not exclude, without further constraint, the presence of additional identical elements in the subject process, method, system, article, or apparatus that includes the element.

[0107] "a," ​​"an," and "the" also refer to "one or more," unless expressly stated otherwise. Additionally, the phrase "at least one of A and B," where A and B are variables indicating particular objects or attributes, as may be used herein and / or in the claims that follow, indicates a choice of A or B, or both A and B, similar to the word "and / or." When more than two variables are present in such a phrase, the phrase is defined herein to include only one of the variables, any one of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0108] Additionally, as used herein, the terms "about" or "approximately" apply to all numerical values, whether or not expressly stated. These terms generally refer to a range of numerical values ​​that one of ordinary skill in the art would consider equivalent to the recited value (e.g., having the same function or result). In certain cases, these terms may include numerical values ​​that are rounded to the nearest significant figure.

[0109] Additionally, the listing of any enumerated items described herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. Furthermore, as used herein, the term "set" should be interpreted to mean "one or more," and in the case of "sets," unless otherwise stated, should be interpreted to mean multiples (or pluralities) of "one or more," in accordance with set theory.

[0110] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above description. The described embodiments have been selected to best explain the principles of the technology and its practical application, thereby enabling those skilled in the art to best utilize the technology in various embodiments, with various modifications as appropriate for the particular use contemplated. The scope of the technology is defined by the claims appended hereto.

Claims

1. 1. A memory die comprising: a plurality of memory blocks, each memory block including a plurality of memory cells configured to store three bits of data in each memory cell when the memory die is in a TLC mode of operation; the memory die has a non-binary data capacity when operated in the TLC mode of operation; when the memory die is in the TLC mode of operation, the plurality of memory blocks includes a first plurality of main blocks that contribute to the non-binary data capacity and a plurality of extended blocks that do not contribute to the non-binary data capacity; when the memory die is in a QLC mode of operation, the plurality of memory blocks includes a second plurality of main blocks that contribute to a binary data capacity; The memory die, wherein the second plurality of main blocks are larger than the first plurality of main blocks.

2. 10. The memory die of claim 1, wherein the non-binary data capacity of the memory die when operating in the TLC mode of operation is a multiple of six hundred eighty-three gigabits (683 Gb).

3. 3. The memory die of claim 2, wherein the non-binary data capacity of the memory die when operating in the TLC mode of operation is six hundred eighty-three gigabits (683 Gb).

4. The memory die of claim 1 , wherein said first plurality of main blocks is less than or equal to 80 percent of said plurality of memory blocks.

5. The memory die of claim 1 further comprising a CMOS layer overlying an array layer containing the plurality of memory blocks.

6. 1. A memory device comprising: a plurality of memory dies, the memory dies including a plurality of memory blocks, the memory blocks including a plurality of memory cells configured to store three bits of data in each memory cell when the memory dies are operating in a TLC mode of operation; A memory device, wherein each of the memory dies has a non-binary data capacity, and the memory dies combine to provide the memory device having a binary data capacity when the memory dies are operating in the TLC mode of operation.

7. 7. The memory device of claim 6, wherein the non-binary data capacity of the memory die when operated in the TLC mode of operation is a multiple of six hundred eighty-three gigabits (683 Gb).

8. 8. The memory device of claim 7, wherein the non-binary data capacity of the memory die when operated in the TLC mode of operation is six hundred eighty-three gigabits (683 Gb).

9. 8. The memory device of claim 7, wherein the plurality of memory blocks in each of the memory dies includes a main block that contributes to the non-binary data capacity of the memory die when operating in the TLC mode of operation, and an extension block that does not contribute to the non-binary data capacity of the memory die when operating in the TLC mode of operation.

10. 8. The memory device of claim 7, wherein the memory die is configurable to operate in a QLC mode of operation, the memory die having a binary data capacity when operating in the QLC mode of operation.

11. when the memory die is in the TLC mode of operation, the plurality of memory blocks includes a first set of main blocks that contribute to the non-binary data capacity; when the memory die is in a QLC mode of operation, the plurality of memory blocks includes a second set of main blocks that contribute to the binary data capacity; The memory device of claim 7 , wherein the second plurality of main blocks are larger than the first plurality of main blocks.

12. 12. The memory device of claim 11, wherein the first plurality of main blocks is less than or equal to 80 percent of the plurality of memory blocks.

13. 7. The memory device of claim 6, wherein each of the memory dies includes an array layer having the plurality of memory blocks and a CMOS layer overlying the array layer.

14. 1. A method of fabricating a plurality of memory devices, comprising: forming a plurality of array layers, each array layer including a plurality of memory cells arranged in a plurality of memory blocks; bonding the array layer with a plurality of CMOS layers containing electrical components for programming, reading, and erasing the plurality of memory cells to form a plurality of memory dies; configuring a first set of the plurality of memory dies to operate in a TLC mode of operation with a non-binary data capacity; and configuring a second set of the plurality of memory dies to operate at a binary data capacity in a QLC mode of operation.

15. 15. The method of claim 14, wherein the non-binary data capacity of each memory die of the first set of memory dies is a multiple of 683 Gb.

16. 16. The method of claim 15, wherein the non-binary data capacity of each memory die of the first set of memory dies is 683 Gb.

17. 16. The method of claim 15, wherein the binary data capacity of each memory die of the second set of memory die is 1 Tb.

18. 15. The method of claim 14, further comprising combining a plurality of memory dies of the first set of memory dies into a single memory device having a binary data capacity.

19. 1. A memory die comprising: A plurality of memory blocks each including a plurality of memory cells; when the memory die is in a TLC mode of operation, the plurality of memory blocks includes a first plurality of main memory blocks that contribute to a non-binary data capacity of the memory die and a plurality of extension blocks that do not contribute to the non-binary data capacity of the memory blocks; the plurality of memory blocks includes a second plurality of main memory blocks contributing a binary data capacity when the memory die is in a QLC mode of operation; The second plurality of main memory blocks is larger than the first plurality of main memory blocks.

20. 20. The memory die of claim 19, wherein the plurality of memory cells are configured to store three bits of data per memory cell.

21. 21. The memory die of claim 20, wherein the non-binary data capacity of the memory die is a multiple of 683 Gb.

22. 22. The memory die of claim 21, wherein the non-binary data capacity of the memory die is 683 Gb.

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