Electronic equipment

Abstract

To provide an electronic apparatus capable of efficiently recognizing handwritten characters.SOLUTION: An electronic apparatus includes a first circuit, display, and a touch sensor. The first circuit has a neural network. The display has a flexible display. The touch sensor has a function for outputting input handwritten characters to the first circuit as image information. The first circuit has: a function for analyzing the image information and converting it into character information; and a function for displaying an image including the character information. Analysis is performed by reasoning with the neural network.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a touch panel system and an electronic device using the same.

[0002] Another embodiment of the present invention relates to a semiconductor device.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, memory devices, electro-optical devices, power storage devices, semiconductor circuits, and An electronic device may include a semiconductor device.

[0004] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a method of manufacture. Alternatively, one aspect of the present invention is , process, machine, manufacture, or composition of matter (-) [Background technology]

[0005] In recent years, machines such as artificial neural networks (hereafter referred to as neural networks) have There has been active development of learning technologies, with successful examples being reported mainly in the field of image recognition.

[0006] Patent Document 1 describes a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) and other processors An example of machine learning using neural networks to recognize handwritten characters has been disclosed. .

[0007] In recent years, transistors using oxide semiconductors or metal oxides in their channel formation regions ( Oxide Semiconductor transistor, hereafter referred to as OS transistor ) has been attracting attention. OS transistors have an extremely small off-state current. Applications using OS transistors have been proposed. discloses an example in which OS transistors are used for training a neural network. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2005-182785 A [Patent Document 2] JP 2016-219011 A Summary of the Invention [Problem to be solved by the invention]

[0009] Machine learning using neural networks requires a huge amount of calculations. When building a neural network using digital circuits such as U or GPU, This results in a huge number of transistors, which makes the design inefficient and consumes a lot of power.

[0010] One aspect of the present invention provides a touch panel system capable of efficiently recognizing handwritten characters. Another object of the present invention is to provide a method for efficiently generating a neural network. Another object of the present invention is to provide a semiconductor device capable of forming a network. An object of one embodiment of the present invention is to provide a semiconductor device capable of efficiently executing a multiply-and-accumulate operation. Another aspect of the present invention is a semiconductor device capable of performing a multiply-and-accumulate operation with high accuracy. Another object of the present invention is to provide a novel semiconductor device. One of our goals is to provide

[0011] Another embodiment of the present invention provides an electronic device capable of efficiently recognizing handwritten characters. Another object of the present invention is to provide a display device that can recognize handwritten characters and has a flexible display unit. It is an object of the present invention to provide an electronic device that can recognize handwritten characters and is portable. One object of the present invention is to provide an electronic device that can achieve both ease of use and excellent viewability.

[0012] In addition, the description of a plurality of problems does not preclude the existence of each problem. The embodiment does not necessarily have to solve all of these problems. Also, problems other than those listed may not be solved by the specification. These problems will become apparent from the description of the present invention, drawings, claims, etc. This could be a form of challenge for the Ming. [Means for solving the problem]

[0013] One embodiment of the present invention is an electronic device including a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display unit includes a flexible display. The touch sensor outputs input handwritten characters as image information to a first circuit. The first circuit has the function of analyzing image information and converting it into text information. and a function of displaying an image including text information on a display unit, and the analysis is performed using a neural network. This is done by inference using the work.

[0014] In the above, the electronic device includes a first housing, a second housing, a third housing, and a plurality of housings. In this case, the flexible display preferably has a first housing, a second housing, It is preferable that the first housing and the third housing each have a portion that is held by the first housing and the third housing. The first housing, the second housing, and the third housing are in a state where the flexible display is open, It is hinged so that it can be reversibly transformed between the three folded states. It is preferable that

[0015] In the above, the first circuit has a memory capable of holding analog data. It is preferable to do so.

[0016] In the above, the first circuit is a transistor having a metal oxide in a channel forming region. It is preferable that the sensor further includes a sensor. Effect of the Invention

[0017] According to one aspect of the present invention, there is provided a touch panel system capable of efficiently recognizing handwritten characters. According to one embodiment of the present invention, it is possible to provide a neural network that can efficiently In addition, according to one embodiment of the present invention, a semiconductor device that can be constructed can be provided. It is possible to provide a semiconductor device capable of efficiently executing product-sum operations. According to one embodiment of the present invention, there is provided a semiconductor device capable of performing a multiply-and-accumulate operation with high accuracy. According to one embodiment of the present invention, a novel semiconductor device can be provided. do.

[0018] According to another aspect of the present invention, there is provided an electronic device capable of efficiently recognizing handwritten characters. Alternatively, an electronic device having a flexible display unit capable of recognizing handwritten characters can be provided. Or, a portable electronic device that can recognize handwritten characters and has excellent readability can be provided. Child devices can be provided.

[0019] The description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the specification, drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0020] [Figure 1] An example of an information terminal that uses a touch panel system. [Diagram 2] An example of an information terminal that uses a touch panel system. [Diagram 3] FIG. 1 is a block diagram showing an example of the configuration of a touch panel system. [Figure 4] 4 is a flowchart showing a data flow of the touch panel system. [Diagram 5] A conceptual diagram showing the flow of data in a neural network. [Figure 6] An example of disassembling an information terminal module. [Figure 7] External view of the information terminal and server. [Figure 8] An example of an image receiving device using a touch panel system. [Figure 9] FIG. 1 is a block diagram showing an example of the configuration of a touch panel system. [Figure 10] Schematic diagram of a neural network. [Figure 11] An example of neural network configuration. [Figure 12] FIG. 1 is a circuit diagram showing an example of a product-sum calculation circuit. [Figure 13] 4 is a timing chart showing an example of the operation of the product-sum calculation circuit. [Figure 14] FIG. 13 is a diagram showing the configuration of another example of a product-sum calculation circuit. [Figure 15] FIG. 2 is a circuit diagram showing an example of a memory cell array of a product-sum operation circuit. [Figure 16]FIG. 4 is a circuit diagram showing an example of a current source circuit of a product-sum operation circuit. [Figure 17] FIG. 13 is a circuit diagram showing another example of a current source circuit of the product-sum calculation circuit. [Figure 18] 4 is a timing chart showing an example of the operation of the product-sum calculation circuit. [Figure 19] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel. [Figure 20] FIG. 2 is a cross-sectional view showing a configuration example of a display panel. [Figure 21] FIG. 2 is a cross-sectional view showing a configuration example of a display panel. [Figure 22] 3 is an optical microscope photograph of the OS-APS chip fabricated in Example 1. [Diagram 23] 4 shows the multiplication characteristics of the OS-APS chip prototyped in Example 1. [Figure 24] 4 shows the multiplication characteristics of the OS-APS chip prototyped in Example 1. [Diagram 25] 13 shows the results of a simulation in which a neural network is configured using the OS-APS prototyped in Example 1. [Figure 26] 3 is a photograph of a display device prototyped in Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be implemented in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0022] Also, in the drawings, sizes, layer thicknesses, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0023] In addition, the present specification can be appropriately combined with the following embodiments. In the case where a plurality of configuration examples are shown in the embodiment, the configuration examples may be appropriately combined with each other. It is possible.

[0024] In this specification, the term "neural network" refers to a network that mimics the neural circuitry of living organisms and is used for learning. Therefore, it refers to a general model that determines the strength of connections between neurons and provides problem-solving capabilities. A neural network has an input layer, an intermediate layer (also called a hidden layer), and an output layer.

[0025] In addition, when we discuss neural networks in this specification, we will use existing information to The process of determining the connection strengths (also called weighting coefficients) between neurons from the neural network is called "learning". There is a chance to call.

[0026] In this specification, the neural network is constructed using the connection weights obtained by learning. The process of constructing a theory and deriving a new conclusion from it is sometimes called "inference."

[0027] (Embodiment 1) The present embodiment relates to a touch panel system according to one embodiment of the present invention and an electronic device using the touch panel system. In the present embodiment, an information terminal will be described as an example of an electronic device. conduct.

[0028] 1 is an external view showing an example of use of an information terminal 1. The information terminal 1 includes a display unit 2. The display unit 2 also functions as an input unit.

[0029] The information terminal 1 can recognize characters entered on the display unit 2 and display the recognition results. 1, the user types the alphabet "a" with his / her finger, and the information terminal 1 recognizes the typed character. 13 shows an example in which the character is recognized and the recognition result is displayed in the upper left corner of the display unit 2 (for example, the "a" in Neura). In addition, characters can be input on the display unit 2 not only with a finger but also with a stylus or the like. can.

[0030] In addition, a flexible display can be used as a display unit provided in an information terminal. Figure 2 (A), (B), and (C) show an information terminal 1 using a flexible display. It shows a.

[0031] The information terminal 1a has three housings (a housing 3a, a housing 3b, and a housing 3c) and a display unit 2a. The display unit 2a has a flexible display and is supported by three housings. The housings 3a and 3b, and the housings 3b and 3c are connected by hinges 4. The shaft 14 is rotatably connected to the shaft 14.

[0032] The information terminal 1a is configured to change the display unit 2a from an open state as shown in FIG. 2(A) to an open state as shown in FIG. 2(C). As shown in FIG. 2(a), the display unit 2a can be folded in three reversibly. Figure B) shows a state between these two states.

[0033] When the display unit 2a of the information terminal 1a is open, handwritten text can be displayed on a large, seamless display area. You can input and display characters (in the figure, "Flexible Display"). In addition, when the display unit 2a is folded into three, the information terminal can be made smaller. This makes it possible to carry the device around easily.

[0034] In FIG. 2B, handwritten characters (Flexible Display) are displayed on the curved display unit 1a. In this case, if you enter characters beyond the curved part, However, the characters may be distorted when using the touch panel system described later. By doing so, even if the characters are distorted like this, they can be recognized efficiently. can.

[0035] In addition, when inputting handwritten characters, the speed at which you slide your finger or stylus depends on the individual user. This individual difference is not limited to when inputting handwritten characters, but also applies to touch operations. However, by using the touch panel system described later, Even if there are individual differences in the slide speed, efficient recognition is possible.

[0036] FIG. 3 shows an example of the configuration of a touch panel system 10 used in the information terminal 1 and the information terminal 1a. The touch panel system 10 includes a display panel 20 and a touch sensor. 15 and host 25.

[0037] The display panel 20 includes a pixel section 11, a gate driver 12, a source driver 13, and a gate A power line 21, a source line 22, an I / F (interface) 18, and a neural network (NN) The pixel section 11 has a gate line 21 and a source line 22. It has a number of pixels 14 connected together.

[0038] The touch sensor 15 includes a sensing circuit 16 and an I / F 17 .

[0039] The host 25 has a CPU (Central Processing Unit) and F18 to the source driver 13. The 25 has a GPU (Graphics Processing Unit) Good too.

[0040] The NN circuit 19 is capable of performing learning or inference using a neural network. More specifically, deep neural networks, convolutional neural networks, recurrent neural network, autoencoder, deep Boltzmann machine, or deep belief network. It is possible to perform learning or inference using the network.

[0041] Next, the process flow of the touch panel system 10 will be explained with reference to the flowchart shown in FIG. Reveal.

[0042] First, a user inputs handwritten characters into the touch sensor 15 (Input by hand writing, Step S1).

[0043] The sensing circuit 16 detects handwritten characters (image information) input to the touch sensor 15. , the NN circuit 19. Also, the sensing circuit 16 detects that a touch has been performed by / F17 to notify the host 25 (Touch sensing, step S 2).

[0044] The NN circuit 19 analyzes the pattern of the image information. The image information is then analyzed and converted into text information (Character recognition) n, step S3). The above analysis is carried out by inference using a neural network. do.

[0045] The NN circuit 19 sorts the character information. The source driver 13 outputs the image data received from the host 25 to the The character information received from the NN circuit 19 is synthesized and displayed on the pixel section 11 (Display of input characters, step S4).

[0046] FIG. 5 is a conceptual diagram showing the data flow in the neural network circuit 19. The neural network shown in Figure 5 is composed of an input layer 31 and a hidden layer The input layer 31 has neurons 41_1 to 41_3, and the output layer 33. The intermediate layer 32 has neurons 42_1 to 42_3, and the output layer 33 has neurons 43_1 to For convenience, the number of intermediate layers in FIG. 5 is 1, and the number of intermediate layers in each layer is The number of neurons is three, but is not limited to this. The NN circuit 19 may be any number depending on the problem to be solved. , it is possible to provide as many hidden layers and neurons as necessary.

[0047] The computation in each layer is a multiplication and addition operation between the output of the neurons in the previous layer and the weight coefficients. For example, the output of the i-th neuron in the input layer is x i Then, the output is x i and The connection strength (weight coefficient) with the jth neuron in the intermediate layer is w ji Then, the jth new Ron's output is y j =f(Σw ji x i ) where i and j are integers of 1 or greater. Here, f(x) is an activation function, and a sigmoid function, a threshold function, etc. can be used. Similarly, the output of each layer is the sum of the products of the output of the previous layer neuron and the weighting coefficient. The activation function is applied to the result of the calculation. The connections between layers are It can be a full connection where all neurons are connected to each other, or a partial connection where some neurons are connected to each other. Good too.

[0048] In FIG. 5, image information representing the number "2" is input to the input layer 31, and "2" is output from the output layer 33. 13 shows an example in which a classification result representing

[0049] The NN circuit 19 uses technology such as TFT (Thin Film Transistor). It is preferable to form the pixel section 11 on the same substrate as the NN circuit. The manufacturing cost of the display panel 19 can be reduced. The substrate will be described in detail in the fifth embodiment below.

[0050] In addition, the NN circuit 19 is formed with an IC chip, and COG (Chip On Glass), OF (Chip On Film) or TAB (Tape Automated Board) The IC may be mounted on the display panel 20 using a mounting technique such as 3D printing. A source driver 13 may be included in the chip.

[0051] The NN circuit 19 may be included in the host 25 outside the display panel 20. In that case, A delay occurs between the display panel 20 and the host 25, and the touch sensor 15 receives the input. Then, a time lag occurs before the input result is displayed on the pixel unit 11 via the host 25. Put away.

[0052] By forming the NN circuit 19 on the display panel 20, delay due to wiring resistance is improved, and the input This improves the responsiveness from input to display. In addition, the number of wires is reduced, so the touch panel system The power consumption of the system 10 is also reduced.

[0053] FIG. 6 shows an example of disassembly of the information terminal 1. The information terminal 1 is made up of an upper cover 81 and a lower cover. Between the touch sensor 15, the display panel 20, the backlight unit 87, the frame 92, The device has a frame 89, a printed circuit board 90, and a battery 91.

[0054] The upper cover 81 and the lower cover 92 are formed to fit the size of the touch sensor 15 and the display panel 20. In addition, the shape and dimensions can be changed appropriately.

[0055] The backlight unit 87 includes a light source 88. The LED (Light Emitting Diode) may be installed at the end of the light source and a light diffusion plate may be used. Display panels 2, such as OLED (light emitting diode) and organic EL (electroluminescence) When the display device 80 uses a self-luminous display element, the backlight unit 87 may be omitted.

[0056] The frame 89 has a function of protecting the display panel 20 and also a function of preventing damage caused by the operation of the printed circuit board 90. The frame 89 also functions as an electromagnetic shield to block electromagnetic waves. It may also have a function as a hot plate.

[0057] The information terminal 1 may be provided with additional components such as a polarizing plate, a retardation plate, and a prism sheet. good.

[0058] The printed circuit board 90 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The host 25 shown in FIG. 3 is mounted on a printed circuit board 90. The power source for supplying power to the circuit may be an external commercial power source or a battery 91 The battery 91 can be omitted if a commercial power source is used. be.

[0059] The touch sensor 15 can be used by being superimposed on the display panel 20. For example, a resistive, capacitive or optical touch panel may be used. can.

[0060] In addition, by providing the display panel 20 with a touch sensor function, the touch sensor shown in FIG. 15 can be included in the display panel 20. For example, the opposing substrate (sealing By providing a touch panel function to the substrate, the touch sensor 15 is included in the display panel 20. For example, a touch sensor electrode can be provided in each pixel of the display panel 20. Thus, the touch sensor 15 can be included in the display panel 20. For example, the display panel 2 By providing a light sensor in each pixel of the display panel 20, the touch sensor 15 can be included in the display panel 20. This can be done.

[0061] In addition, the information terminal 1 has a light emitting section, a light guiding section, and a light receiving section disposed around the display panel 20. In this case, the light passing through the light guide is blocked by a finger, and the information is transmitted to the touch panel. The information terminal 1 detects the touch.

[0062] In FIG. 6, the touch sensor 15 is a flexible printed circuit (FPC). The display panel 20 is connected to the FPC 82 and the FPC 84 is connected to the printed circuit board 90. The FPC 82 enables electrical connection between the touch sensor 15 and the display panel 20. C83 enables electrical connection between the touch sensor 15 and the printed circuit board 90, and FPC84 It enables electrical connection between the display panel 20 and the printed circuit board 90. 5 is included in the display panel 20, the FPC 82 is not required.

[0063] Neural networks like the one shown in Figure 5 are implemented using a huge number of multiply-and-accumulate operations. If these calculations were to be performed using digital circuits, the number of transistors required would be enormous. It is inefficient and consumes a lot of power. Therefore, the above multiply-and-accumulate circuit is implemented using an analog multiply-and-accumulate circuit (hereafter, What is done with APS (Analog Product-Sum circuit) It is preferable that the APS has an analog memory. By storing the coefficients in the analog memory, the APS can perform multiplication and addition operations using analog data. As a result, APS can efficiently perform neural network calculations using fewer transistors. It is possible to build a network.

[0064] In this specification, an analog memory is a storage device capable of storing analog data. In this specification, analog data refers to data with 3 bits (8 values) or more. It refers to data with a certain resolution. Multi-value data is sometimes called analog data. do.

[0065] The analog memory mentioned above includes multi-level flash memory, ReRAM (Resistive Random Access Memory), MRAM (Magnetoresis tive Random Access Memory (OS transistor) The memory (hereinafter, referred to as OS memory) can be used.

[0066] As the analog memory, it is particularly preferable to use an OS memory. Compared with other non-volatile memories such as flash memory, ReRAM or MRAM, The power consumption when writing data is small. Also, unlike flash memory and ReRAM, The elements do not deteriorate when writing data, and there is no limit to the number of times data can be written. .

[0067] In this specification, an analog multiply-accumulate circuit having an OS memory is referred to as an OS-APS. Details of the OS-APS will be described later in the third and fourth embodiments.

[0068] The learning by the neural network may be performed on the information terminal 1 or on a dedicated server. It can be done on a large computer like a cloud, or on a group of computers connected by a network. In particular, learning using neural networks requires a large amount of calculations. Therefore, it is preferable to use a large-scale computer. Figure 7 shows an example of learning on the server 5. When a request is sent from the information terminal 1 to the server 5, the server 5 determines The weighting coefficient thus calculated can be transmitted to the information terminal 1. The information terminal 1 receives the weighting coefficient from the server 5. Using the received weighting coefficients, we can perform inference and display, for example, Neura's a Cut.

[0069] The server 5 is a software capable of constructing a neural network similar to the NN circuit 19. It is preferable to have a processor with excellent computing power. In this way, the information terminal 1 can receive the learning results of the server 5 more efficiently. It can be obtained.

[0070] As described above, by using the touch panel system described in this embodiment, it is possible to efficiently input handwritten characters. It is possible to provide a touch panel system capable of recognizing the touch of a finger. It is possible to provide an information terminal capable of recognizing handwritten characters.

[0071] (Embodiment 2) The present embodiment relates to a touch panel system according to one embodiment of the present invention and an electronic device using the touch panel system. In the present embodiment, an image receiving device will be described as an example of an electronic device. conduct.

[0072] FIG. 8 is an external view showing an example of the specifications of the image receiving device 60. The image receiving device 60 is a television. The antenna 64 has a function of generating image data from the broadcast signal received and displaying the image. The receiver 60 also communicates with a server 66 of a broadcasting station via an Internet line 65. It is possible.

[0073] The antenna 64 may be, for example, a UHF (Ultra High Frequency) antenna. Examples include BS / 110°CS antennas, CS antennas, etc.

[0074] Also, communication with the server 66 may be performed using a telephone line instead of an internet line. stomach.

[0075] The image receiving device 60 includes a display unit 61, and all or a part of the display unit 61 functions as an input unit. The user can input information to the image receiving device 60 by touching the display unit 61. do.

[0076] FIG. 8 shows a television receiver 60 displaying a quiz show currently being broadcast. The question is displayed on the left side of the display 61, and the time limit and an input area 62 are displayed on the right side of the display 61. The user is required to handwrite the answer in the input area 62 within a time limit. In FIG. 8, the subject answers the word that comes before "flower" from a flower image. The image receiving device 60 The handwritten characters entered by the user (here, "sun") are recognized, and the recognition result (here, "sun") is stored in area 63. When the time limit is over, the answer will be sent via the Internet It is transmitted to the broadcasting station's server 66.

[0077] FIG. 9 is a block diagram showing an example of the configuration of a touch panel system 70 used in the image receiving device 60. The touch panel system 70 includes a display panel 20, a touch sensor 15, and a receiving circuit 7. 6, a network I / F 71, and an antenna 64.

[0078] The receiving circuit 76 includes an encoder 72, an image processing circuit 73, a decoder 74, and an analog frame. It has a front end 75.

[0079] The analog front end 75 has a function of receiving a broadcast signal input from the antenna 64. Yes.

[0080] The decoder 74 expands the broadcast signal in accordance with the broadcast standard to generate image data. Examples of the above standards include H.264 and H.265.

[0081] The image processing circuit 73 has a function of performing image processing on the decompressed image data. For example, , noise reduction, correction of seams when splitting the screen, correction of image color and detail, dynamic Image processing such as correction of the optical range, image sharpening, and filtering is also performed. The image processing is preferably performed using a neural network. By using neural network image processing, the image appears more natural to the user. The image can be displayed.

[0082] The encoder 72 extracts features from the image data that has been subjected to the image processing, and converts the image data into It has a compression function.

[0083] The display panel 20 includes a decoder 77. The decoder 77 is a decoder corresponding to the encoder 72. It has a function of restoring image data compressed by the encoder 72.

[0084] The encoder 72 and the decoder 77 preferably constitute an autoencoder. Da72 uses a neural network to extract features from image data and The decoder 77 uses a neural network to compress the compressed data. It has the ability to restore image data from the data.

[0085] The image data restored by the decoder 77 is input to the source driver 13 .

[0086] The display panel 20 and the receiving circuit 76 are electrically connected using a cable such as an FPC. For example, in the case of 8K (7680 x 4320) broadcasting, the receiving device 60 is large. When handling large amounts of data, FPCs capable of high-speed transmission are required, but the transmission speed of FPCs In addition, as the size of the display panel increases, the number of circuits connected to the receiving circuit 76 and the display The physical distance of the cable connecting the panels 20 becomes longer, and the transmission loss of the image data increases.

[0087] The image receiving device 60 includes an encoder 72 and a decoder 77, and receives the compressed image ( The image data is transmitted from the receiving circuit 76 to the display panel 20 (when the data size is small). Therefore, the image receiving device 60 can efficiently receive image data with a high resolution such as 8K. Image data can be efficiently transmitted to the display panel 20. In addition, the data size is small. Since the power required for transmission is small, the image receiving device 60 can reduce its power consumption. can.

[0088] The network I / F 71 is an I / F that connects the image receiving device 60 to the Internet. It has functions.

[0089] As in the touch panel system 10 shown in the first embodiment, the NN circuit 19 in FIG. It can perform learning or inference using a neural network. The pattern of the image information is analyzed and the image information is converted into text information. This is done by inference using neural networks.

[0090] The character information (the answer to the quiz in FIG. 8) is input to the pixel section 11 via the source driver 13. and is sent to the broadcasting station's server via the network I / F.

[0091] As in the touch panel system 10 shown in the first embodiment, the NN circuit 19 in FIG. It is preferable to have an analog multiplier / accumulator (APS) circuit. It is preferable to have an OR circuit (OS-APS). In addition, it is possible to efficiently perform multiply-and-accumulate operations with a small amount of power consumption. The theory can be carried out.

[0092] The decoder 77, the encoder 72 and the image processing circuit 73 also use the OS-APS. Neural networks can be built.

[0093] In addition, the decoder 74 performs multiplication and accumulation operations such as discrete cosine transformation when expanding image data. The multiplication and accumulation process may be performed using OS-APS.

[0094] The details of the other components of the touch panel system 70 are the same as those of the touch panel shown in the first embodiment. For more information, please refer to the description of the system 10.

[0095] As described above, by using the touch panel system described in this embodiment, it is possible to efficiently input handwritten characters. It is possible to provide a touch panel system capable of recognizing the touch of a finger. It is possible to provide an image receiving device capable of recognizing handwritten characters.

[0096] (Embodiment 3) In this embodiment, an analog multiply-and-accumulate circuit that can be used for neural network calculations is provided. The arithmetic circuit will now be described.

[0097] As mentioned above, neural network operations involve the output of neurons and the inputs stored in synapses. The weighting coefficients are multiplied and accumulated. Figure 10 shows a schematic diagram of the neural network. do.

[0098] The neural network NN shown in Figure 10 is composed of multiple neurons. The neural network has neuron groups N1 and N2, and synapse SNPs in which weight coefficients between neurons are stored. The neuron group N1 corresponds to the input layer or the hidden layer, and the neuron group N2 corresponds to the hidden layer or the output layer. The signal output from neuron group N1 is transmitted to neuron group N2 via synapse SNP. Entered into group N2.

[0099] FIG. 11 shows a specific example of the configuration of the neural network NN. Multiple neurons N 1 The output of each is fed to a neuron group N via a synapse SNP. 2 has multiple neurons N 2 In Figure 11, the white circles between the neurons are Represents synaptic SNP. Synaptic SNP between neuron group N1 and neuron group N2 is Neuron N 1 The output of neuron N is multiplied by the weight coefficient. 2 Equipped with the function to output to do.

[0100] As shown in FIG. 10, the signal output from the neuron group N1 includes the synaptic SNPs. In other words, Synapse SNP has the function of multiplication (MUL). The weight coefficients are stored in the synapse SNP beforehand. The signal output from the neuron SNP is input to the neuron group N2.

[0101] Each neuron in the neuron group N2 receives inputs from multiple synaptic SNPs. In other words, neurons have the function of adding (ADD). In this way, multiply-accumulate (MAD) operations are performed by synapses and neurons. The signal obtained by the multiplication and addition operation is transformed based on the activation function and then used as a is output to the neuron.

[0102] As mentioned above, the synapse SNP is an arithmetic circuit that multiplies the output of a neuron by a weighting factor. (arithmetic circuit) and memory for storing weighting coefficients Therefore, the neural network NN is When using hardware, the synapse is constructed using an arithmetic circuit and memory. However, if the arithmetic circuit and the memory are formed separately, the circuit scale increases. In addition, memory access is required for each multiplication, which increases power consumption. do.

[0103] In one embodiment of the present invention, the synapse is formed by forming a channel in a silicon (e.g. Transistors using silicon (such as single crystal silicon) (hereafter referred to as Si transistors) and transistors using O It is composed of a circuit combining S transistors. Specifically, as shown in Figure 10, As shown in the figure, the OS and the layer having the Si transistor (indicated by "Si" in the figure) are A layer having a Si transistor (in the figure, marked with "OS") is provided. The function of multiplication and the function of storing weight coefficients are integrated by using a multiplier and an OS transistor. This allows the circuit scale to be reduced and the power consumption to be reduced. It is possible to reduce

[0104] Below, we will introduce an analog multiply-and-accumulate circuit ( We will explain a specific example of OS-APS.

[0105] The APS (analog product-sum operation circuit) 50 shown in FIG. 12, VDD is a high power supply potential, VS S represents the low power supply potential.

[0106] The memory cell array 51 is arranged in a matrix of i rows and j columns (i and j are integers equal to or greater than 1). The memory cells MC[1, 1] to MC[i, j] arranged in one column and the memory cells MC_ The memory cells MC and MC_R have analog The memory cells MC_R[1] to MC_R[i ] functions as a reference memory cell.

[0107] In this specification, when the parentheses of the code representing a sequence are omitted, The symbol represents an unspecified one of the array elements. For example, memory cell MC is a memory cell M It represents an unspecified memory cell among C[1, 1] to MC[i, j].

[0108] As described later, the memory cell MC has a function of performing multiplication, a function of storing weight coefficients, and That is, the memory cell MC has a function as a synapse.

[0109] The memory cell MC and the memory cell MC_R each include a transistor M01 and a transistor M0 2 and a capacitance element C0. In addition, in the memory cell MC, The gate of the transistor M01 in the memory cell MC_R is called a node NM. The node is called node NM_R.

[0110] In the memory cell MC[i, j], the on / off state of the transistor M02 is determined by the signal WW[i] The signal BW[j] is connected to the node NM[i , j], and the signal VX[i] is written to the node NM[i, j] via the capacitive element C0. The transistor M01 outputs a current IM Stream [i, j].

[0111] In the memory cell MC_R[i], the on / off state of the transistor M02 is determined by the signal WW[i] The signal BW_R is coupled to the node NM_R[ The signal VX[i] is written to node NM_R[i] via the capacitance element C0. The transistor M01 outputs a current IM_ Flow R[i].

[0112] In the memory cell MC, the transistor M02 is preferably an OS transistor. Since the off-state current of the OS transistor is extremely low, turning off the transistor M02 Thus, the memory cell MC can hold the potential (analog data) of the node NM.

[0113] Similarly, in the memory cell MC_R, the transistor M02 is an OS transistor. By turning off the transistor M02, the memory cell MC_R is It is possible to hold the potential (analog data) of NM_R.

[0114] There is no particular limitation on the type of transistor that can be used as the transistor M01. For example, a Si transistor can be used as the transistor M01. , the transistor M02 can be stacked above the transistor M01, as shown in FIG. Such a synapse can be constructed.

[0115] The circuit 54 includes circuits CSC[1] to CSC[j] and a circuit CSC_R. C and CSC_R represent the transistor M11, the transistor M12, and the capacitive element C1. Yes.

[0116] In the circuit CSC, the on / off state of the transistor M12 is controlled by the signal CSCS. The signal BCSC is coupled to the gate of the transistor M11 and the capacitor C1 through the transistor M12. The circuit CSC[j] has memory cells MC[1, j]. 1 through MC[i, j] and causes a current ICSC[j] to flow.

[0117] In the circuit CSC_R, the on / off state of the transistor M12 is controlled by the signal CSCS. The signal BCSC_R is supplied to the gate of the transistor M11 via the transistor M12. and one terminal of the capacitance element C1 is written. It functions as a current source for the circuits [1] to MC_R[i] and causes the current ICSC_R to flow.

[0118] In the circuit CSC, the transistor M12 is preferably an OS transistor. Since the off-state current of the OS transistor is extremely low, by turning off the transistor M12, The circuit CSC can hold the potential (analog data) of the gate of the transistor M11. can.

[0119] Similarly, in the circuit CSC_R, the transistor M12 is an OS transistor. By turning off the transistor M12, the circuit CSC_R is It is possible to hold the potential (analog data) of 11 gates.

[0120] The circuit 52 includes circuits CSK[1] to CSK[j]. The circuit CSK is a current sink circuit. The circuit CSK includes transistors M21, M22, and The transistor M22 is turned on and off by a signal C The on / off state of transistor M23 is controlled by signal CSKR. will be done.

[0121] In the circuit CSK, the transistors M22 and M23 are OS transistors. Since the off-state current of an OS transistor is extremely low, By turning off M22 and transistor M23, the circuit CSK is connected to transistor M21 The potential (analog data) of the gate can be held.

[0122] The wiring BL_R is connected to the memory cells MC_R[1] to MC_R[i] and the circuit CSC_R. The wiring BL[j] is electrically connected to the memory cells MC[1, j] to MC[i, j]. ], the circuit CSC[j] and the circuit CSK[j].

[0123] The circuit 53 has a function as a current mirror circuit, and directs the current flowing through the wiring BL_R to the wiring It has the function of copying to lines BL[1] to BL[j].

[0124] The memory cell MC has a function of holding a potential corresponding to a weighting factor (W). By applying a potential corresponding to the multiplicand (X) to [i], the transistor M01 The APS50 detects the sum of the currents IM (current IWX). Thus, an analog multiply-and-accumulate operation is performed.

[0125] The memory cell MC can be configured with a small number of elements as shown in FIG. Therefore, the multiplication circuit and memory can be realized with a relatively simple configuration, and the neural network This makes it possible to reduce the circuit scale of the network NN.

[0126] The timing chart shown in FIG. 13 shows an example of the operation of the APS 50. The time series is divided into periods P1 to P4 to represent timing.

[0127] In a period P1, a charge is written to the circuit CSC. In a period P2, the memory cell M During period P3, data corresponding to the weighting coefficient is written to the offset counter CSK. After the period P4, a charge that can cause a bit current to flow is written according to the potential of the signal VX[i]. The result of the analog multiply-and-accumulate operation is output as current IWX[j].

[0128] All the transistors used in the APS50 are n-channel transistors. The APS50 eliminates the need to separately manufacture n-channel and p-channel types, greatly reducing manufacturing costs. The APS50 can also be constructed using only OS transistors. For example, in the case where pixel portion 11 in FIG. 3 and FIG. 9 is configured with OS transistors, In this case, the NN circuit 19 and the pixel section 11 can be manufactured in the same manufacturing process. The pixel section 11 and the NN circuit 19 can be fabricated simultaneously on the substrate. In addition, the OS transistor can be used on large glass substrates. Since it can be fabricated on a silicon substrate, it is possible to fabricate a large-scale product-sum operation circuit.

[0129] As described above, by using the analog multiply-and-accumulate circuit shown in this embodiment, it is possible to efficiently perform multiply-and-accumulate. In addition, it is possible to provide a semiconductor device capable of efficiently implementing neural network. It is possible to provide a semiconductor device capable of constructing a network.

[0130] (Embodiment 4) This embodiment is directed to an analog multiply-and-accumulate circuit (OS A specific example of the APS will be described with reference to FIGS. 14 to 18. An example different from the analog sum-of-products arithmetic circuit shown in the third embodiment will be described. In terms of form, gate refers to the front gate unless otherwise specified.

[0131] <Configuration of multiply-and-accumulate circuit> FIG. 14 is a diagram showing an example of the configuration of an APS (analog multiply-accumulate circuit) 100. 00 includes a current source circuit 130, a memory cell array 120, and an offset circuit 110. do.

[0132] The current source circuit 130 has n column output circuits OUT in the row direction and a reference column output circuit CREF. The memory cell array 120 is arranged in a matrix of m memory cells in the column direction and n memory cells in the row direction. The memory cell array has m×n memory cells MEM arranged in a row direction and m reference memory cells REF arranged in a column direction. The offset circuit 110 has n column input circuits OM in the row direction, where n is greater than 1. m is an integer greater than 1, and i is an integer greater than 1 and less than or equal to m-1. For example, the memory location in the i-th row and j-th column is A cell will be written as MEM[i,j].

[0133] A part of the column output circuit OUT can function as a constant current circuit 131a, and the reference column output circuit A part of the circuit can function as a constant current circuit 131b. The other part of the reference column output circuit CREF can function as a current mirror. Cut.

[0134] A signal line B[j] and a signal The line B[j+1] corresponds to the memory cell MEM in the [j]th column and the memory cell MEM in the [j+1]th column. The constant current circuit 131b of the reference column output circuit CREF is electrically connected to the The electrically connected signal line BREF is electrically connected to the reference memory cell REF.

[0135] The column input circuit OM[j] and the column input circuit OM[j+1] of the offset circuit 110 are The transistor 111, the transistor 112, the transistor 113, and the capacitance element 1 14, a resistive element 115, and a holding node O[j] or a holding node O[j+1]. do.

[0136] The offset circuit 110 also includes signal lines ORP, OR, OB, and OREF. , and a signal line VO serving as an output terminal. [j+1] is connected to the signal line B[j] and the signal line B[j+1], respectively, The memory cell MEM and the memory cell MEM in the column [j+1] are electrically connected.

[0137] In the column input circuit OM[j], the first terminal of the transistor 111 is electrically connected to OPR[j]. The gate of the transistor 111 is electrically connected to the signal line OR, and the gate of the transistor 112 is electrically connected to the signal line OR. The second terminal of the transistor 111 is electrically connected to the gate of the transistor 112 and the first terminal of the capacitance element 114. The first terminal of the transistor 112 is connected to VDD (high power supply potential, the first A potential (which may be referred to as a potential or the like) is applied to the second terminal of the transistor 112. 13 and the signal line VO[j] serving as the output terminal. The gate of the transistor 113 is electrically connected to the signal line OB, and the second terminal of the transistor 113 is The capacitor is supplied with VSS (which may be called the low power supply potential or the second power supply potential). A second terminal of the resistor element 114 is electrically connected to the signal line B[j] and a first terminal of the resistor element 115. A second terminal of the resistance element 115 is electrically connected to the signal line OREF.

[0138] As shown in FIG. 14, the second terminal of the transistor 111 and the gate of the transistor 112 are The node electrically connected to the first terminal of the capacitance element 114 and the second terminal of the capacitance element 114 is referred to as a retention node O[ j] may be used.

[0139] Similarly, in the column input circuit OM[j+1], the first terminal of the transistor 111 is OPR[j+ 1], and the gate of the transistor 111 is electrically connected to a signal line OR. The second terminal of the transistor 111 is connected to the gate of the transistor 112 and the gate of the capacitor 114. The first terminal of the transistor 112 is electrically connected to VDD (high power supply A potential, which may be a first potential of a power supply, etc., is applied to the second terminal of the transistor 112. , and electrically connected to the signal line VO[j+1] which is the first terminal and the output terminal of the transistor 113. The gate of the transistor 113 is electrically connected to the signal line OB. The second terminal of the resistor 113 is connected to VSS (low power supply potential, which may be called the second power supply potential, etc.). The second terminal of the capacitance element 114 is connected to the signal line B[j+1] and the first terminal of the resistance element 115. The second terminal of the resistor element 115 is electrically connected to the signal line OREF. Connected.

[0140] In addition, the second terminal of the transistor 111, the gate of the transistor 112, and the capacitance element 11 The node electrically connected to the first terminal of 4 is called the holding node O[j+1]. be.

[0141] A control signal can be supplied from the signal line OR. Also, the signal line OPR[j] and the signal line From OPR[j+1], the processes of the retention nodes O[j] and O[j+1] are A reset potential can be supplied from the signal line OB to the transistor 113. A bias potential can be supplied from the signal line OREF to operate the device as a power source. Therefore, a reference potential for current-voltage conversion can be supplied by the resistor element 115. Also, the signal lines VO[j] and VO[j+1] are connected to columns [j] and [j+ 1] can output a potential that represents the result of the multiplication and accumulation operation.

[0142] <Example of memory cell array> Next, an example of the configuration of the memory cell array 120 of the APS 100 will be described with reference to FIG. The memory cell array 120 can function as an analog memory. The cell array 120 is not limited to the configuration shown in Fig. 15. Circuit configuration capable of functioning as an analog memory As long as it is, other configurations may be used.

[0143] As described above, the memory cell array 120 shown in FIG. Memory cell MEM[i,j+1], memory cell MEM[i+1,j], memory cell MEM [i+1, j+1]. The memory cell array 120 also has reference memory cells REF[i ], and a reference memory cell REF[i+1].

[0144] Furthermore, the memory cells MEM[i,j] to MEM[i+1,j+1] are connected to the power supply line VR, signal line WD[j] or signal line WD[j+1], signal line RW[i] or signal line R W[i+1], signal line WW[i] or signal line WW[i+1]. Also, signal line B [j] and signal line B[j+1]. i] and REF[i+1] are the power supply line VR, the reference signal line WDREF, and the signal line R W[i] or signal line RW[i+1], signal line WW[i] or signal line WW[i+1] Also, it is electrically connected to the signal line BREF.

[0145] Memory cells MEM[i,j] to MEM[i+1,j+1] and a reference memory cell R EF[i] and REF[i+1] are the transistors 123 and 12 4, and has a capacitance element 125.

[0146] In the memory cell MEM[i,j], the first terminal of the transistor 123 is connected to the signal line WD[j] The gate of the transistor 123 is electrically connected to the signal line WW[j]. The second terminal of the transistor 123 is connected to the first terminal of the capacitance element 125 and the transistor 12 The first terminal of the transistor 124 is electrically connected to the gate of the power supply line VR. The second terminal of the transistor 124 is electrically connected to the signal line B[j]. A second terminal of the quantum element 125 is electrically connected to the signal line RW[i].

[0147] As shown in FIG. 15, the second terminal of the transistor 123 and the first terminal of the capacitance element 125 and a node electrically connected to the gate of transistor 124 is referred to as a charge storage node. It may be written as N[i,j].

[0148] A potential (here, a low potential) can be supplied from the power supply line VR. Also, the signal line WW [i], signal line WW[i+1], signal line RW[i] and signal line RW[i+1] In addition, the signal line WD[j] and the signal line WD[j+1 ] can supply data signals from signal line B[j] and signal line B It is possible to output a current corresponding to the data of the memory cell of each column to [j+1]. A current corresponding to the data of the reference memory cell can be output to the line BREF.

[0149] In addition, the charge storage node N[i,j], the charge storage node N[i,j+1], the charge storage node N[i+1,j], charge retention node N[i+1,j+1], charge retention node NREF[i ], and the charge retention node NREF[i+1] can store a charge corresponding to the data. Cut.

[0150] Note that the current flowing through the transistor 124 of the memory cell MEM[i,j] (the current drawn Similarly, the current (i,j) of memory cell MEM[i,j+1] is The current flowing through the transistor 124 is I[i,j+1], and the memory cell MEM[i+1, The current flowing through the transistor 124 in the memory cell MEM[i+1,j] is I[i+1,j]. i+1,j+1] is the current flowing through the transistor 124 of The current flowing through the transistor 124 of the reference memory cell REF[i] is expressed as IRE F[i], the current flowing through the transistor 124 of the reference memory cell REF[i+1] is Let IREF[i+1].

[0151] The electrical connections, functions, etc. of the other memory cells are shown in FIG. 15 and the memory cells MEM[i, j] may be taken into consideration.

[0152] <Current source circuit example 1> Next, an example of the configuration of the current source circuit 130 included in the APS 100 will be shown with reference to FIG.

[0153] As described above, the current source circuit 130 includes the column output circuit OUT[j] and the column output circuit OUT[j+ 1], and a reference column output circuit CREF. The current source circuit 130 includes a constant current circuit 13 1a, a constant current circuit 131b and a current mirror.

[0154] The column output circuit OUT[j] and the column output circuit OUT[j+1] are transistors 1 32, transistor 133, transistor 134, capacitance element 135 and node NG[j ] or node NG[j+1]. The transistor 132 has a dual gate structure. In the case of a dual-gate transistor, one of the gates is connected to the first The gate is sometimes called the front gate, or simply the gate, and the other gate is called the second gate. This is sometimes called a back gate.

[0155] The reference column output circuit CREF includes a transistor 136, a transistor 137, and a transistor The transistor 136 has a dual-gate structure. It is a transistor.

[0156] The column output circuit OUT[j] and the column output circuit OUT[j+1] are connected to a signal line GW and a signal line FG[j] and signal line FG[j+1] and signal line B[j] and signal line B[j+1] has.

[0157] The reference column output circuit CREF includes a signal line GW, a signal line FGREF, and a signal line BREF. Yes.

[0158] In the column output circuit OUT[j], the front gate of the transistor 132 is connected to the front gate of the transistor 13 3 and the first terminal of the capacitance element 135. The back gate of the second transistor 132 is connected to a first terminal of the transistor 132, a second terminal of the capacitance element 135, The first terminal of the transistor 134 is electrically connected to the signal line B[j]. The second terminal of the transistor 132 is connected to the signal line GW. The second terminal of the transistor 133 is electrically connected to the signal line FG[j]. The gate of the transistor 134 is connected to the transistor 134 of the column output circuit OUT[j+1]. the gate of the transistor 138 of the reference column output circuit CREF, the signal line BREF, a first terminal of the transistor 138, a back gate of the transistor 136, and a second terminal of the transistor 136 The second terminal of the transistor 134 is electrically connected to the second terminal of the capacitor 139. VSS is applied to terminal 2.

[0159] As shown in FIG. 16, the front gate of the transistor 132 and the front gate of the transistor 133 The node electrically connected to the first terminal of the capacitive element 135 is referred to as a node NG[ j] may be used.

[0160] Similarly, in the column output circuit OUT[j+1], the front gate of the transistor 132 is The first terminal of the transistor 133 and the first terminal of the capacitance element 135 are electrically connected to each other. The back gate of the transistor 132 is connected to the first terminal of the transistor 132 and the second terminal of the capacitance element 135. The second terminal is electrically connected to the first terminal of the transistor 134 and the signal line B[j+1]. The second terminal of the transistor 132 is supplied with VDD. The gate of the transistor 133 is The second terminal of the transistor 133 is electrically connected to the signal line GW, and the second terminal of the transistor 133 is electrically connected to the signal line FG[j+1] A second terminal of the transistor 134 is electrically connected to VSS.

[0161] The front gate of the transistor 132, the first terminal of the transistor 133, and the capacitance element 1 The node electrically connected to the first terminal of 35 is called node NG[j+1]. be.

[0162] In the reference column output circuit CREF, the front gate of transistor 136 is connected to the front gate of transistor 13 7 and the first terminal of the capacitor 139. The back gate of the transistor 136 and the capacitor 139 are connected to each other as described above. a second terminal of the transistor 138, a gate of the transistor 138, a first terminal of the column output circuit O UT[j] and the gate of the transistor 134 of the column output circuit OUT[j+1], the signal line B A second terminal of the transistor 136 is electrically connected to REF. The gate of the transistor 137 is electrically connected to the signal line GW. The second terminal of the transistor 138 is electrically connected to the signal line FGREF. SS is given.

[0163] As shown in FIG. 16, the front gate of the transistor 136 and the front gate of the transistor 137 The node electrically connected to the first terminal of the capacitance element 139 is designated as NGREF. There are cases where this is said.

[0164] A control signal can be supplied from the signal line GW. When the signal line of the signal line GW is set to “H”, , the transistor 133 of the column output circuit OUT[j], the transistor 134 of the column output circuit OUT[j+1] At this time, the transistor 133 of the reference column output circuit CREF and the transistor 137 of the reference column output circuit CREF are turned on. The signal lines FG[j], FG[j+1], and FGREF are connected to the column output circuits O The front gate of transistor 132 of UT[j] (i.e., node NG[j]), the column output The front gate of the transistor 132 of the circuit OUT[j+1] (i.e., the node NG[j+ 1]), the front gate of transistor 136 of the reference column output circuit CREF (i.e., node Any voltage can be written to the NGREF pin. This allows transistors 132 and and transistor 136 can be normally on.

[0165] In addition, the signal line B[j] and the signal line B[j+1] are connected to the currents IREF'[j] and IR This is because the column output circuit OUT[j] and the column output circuit EF'[j+1] can be The current ICM flowing through the transistor 134 of the circuit OUT[j+1] (the current it sinks) is The sum of the currents IC[j] and IC[j+1] flowing through the transistor 132 (the currents being output) is equivalent to.

[0166] Similarly, the signal line BREF is connected to a current ICM flowing through the transistor 138 (current to be sunk). , a current flowing through the transistor 136 (current output) ICREF, and a current equivalent to the sum of IREF can be passed.

[0167] Here, the current IREF flows through the transistor 124 of the reference memory cell REF. The current that is drawn (sink current) IREF[i] and IREF[i+1] must be equal to the sum of these two. The source potential of the transistor 136 is determined. The transistor size (channel length and channel width) is set equal to the transistor size of the transistor 138. By adjusting the current flowing through the transistor 134 (current to be sunk), the current flowing through the transistor 134 becomes ICM. can be done.

[0168] That is, the transistors 1 of the column output circuit OUT[j] and the column output circuit OUT[j+1] 34 and the transistor 138 of the reference column output circuit CREF form a current mirror. Therefore, the same current is applied to the signal line B[j], the signal line B[j+1], and the signal line FGREF. It can be flushed.

[0169] All the transistors used in the APS100 shown so far are n-channel transistors. Therefore, the APS100 does not require separate production of n-channel and p-channel types. This allows for a significant reduction in manufacturing costs. For example, the pixel section 11 in FIG. 3 and FIG. 9 can be configured with only an OS transistor. When the transistor is used, the NN circuit 19 and the pixel section 11 can be manufactured in the same manufacturing process. In other words, the pixel section 11 and the NN circuit 19 can be fabricated simultaneously on the same substrate. As a result, the manufacturing cost of the display panel can be significantly reduced. Since the transistor can be fabricated on a large glass substrate, it is possible to create a large-scale multiply-accumulate circuit. It can be manufactured.

[0170] <Current source circuit example 2> The current source circuit 130 of the APS 100 is not limited to the configuration shown in FIG. The current source circuit 130 may be configured using a p-channel transistor. 2 shows an example of the configuration of a current source circuit 130 using transistors.

[0171] The column output circuit OUT[j] and the column output circuit OUT[j+1] are p-channel transistors. The reference column output circuit CREF has a p-channel transistor 141. has.

[0172] The column output circuit OUT[j] and the column output circuit OUT[j+1] are connected to the signal line B[j] and and a signal line B[j+1]. The reference column output circuit CREF has a signal line BREF.

[0173] In the column output circuit OUT[j], the gate of the transistor 140 is connected to the column output circuit OUT[j+ 1], the gate of transistor 140 of the reference column output circuit CREF, The first terminal of the transistor 141 is electrically connected to the signal line BREF. The first terminal of the transistor 140 is electrically connected to the signal line B[j]. The second terminal is supplied with VDD. The transistor 140 functions as a constant current circuit. can be done.

[0174] Similarly, in the column output circuit OUT[j+1], the first terminal of the transistor 140 is connected to the signal line B[j The second terminal of the transistor 140 is electrically connected to the first terminal of the transistor 140. .

[0175] In the reference column output circuit CREF, the gate of transistor 141 is connected to the transistor The first terminal of the first column of the first input of the second input ... The gate of the transistor 141 is electrically connected to the gate of the transistor 140 of the [j+1] position. The second terminal is supplied with VDD. The transistor 141 functions as a constant current circuit. It is possible.

[0176] The transistors 140 and 141 of the column output circuit OUT[j] and the column output circuit OUT[j+1] The transistor 141 of the reference column output circuit CREF forms a current mirror, and To function as a constant current circuit, signal line B[j], signal line B[j+1], and signal line The same current can be applied to BREF.

[0177] The configuration of the current source circuit 130 is not limited to that shown in FIG. 16 and FIG. 17, and may be any other circuit that can function as a constant current circuit. Other configurations may be used as long as they are possible.

[0178] <Timing chart> Next, the configuration of FIG. 15 is adopted for the memory cell array 120, and the configuration of FIG. 16 is adopted for the current source circuit 130. The operation of the APS100 shown in FIG. 14 when the APS100 is in the above-mentioned case is illustrated using the timing chart in FIG. He explains.

[0179] The period from time T01 to time T02 shown in FIG. In order to operate the transistor 132 and the transistor 136 as a current source, Voltage is applied to nodes NG[j], NG[j+1], and NGREF, which are electrically connected to the port. This corresponds to the act of applying a voltage.

[0180] The period from time T03 to time T06 corresponds to an operation of storing the first analog data in each memory cell. do.

[0181] The period from time T07 to time T08 is an operation for setting a preset potential to the column input circuit of the offset circuit. This corresponds to the work.

[0182] From time T09 to time T14, the first analog data stored in the memory cells of each row and A second analog data corresponding to a selection signal to be supplied to the memory cell, and an output corresponding to the product of This corresponds to the operation of acquiring force data.

[0183] Here, the power supply line VR is at low potential, the power supply line VDD is at high potential, and the power supply line VSS is at low potential. Also, transistor 112, transistor 113, transistor 124, transistor 13 2. Transistor 134, transistor 136, and transistor 138 are In this case, the transistor operates in the saturation region. The source and drain voltages are appropriately biased to a voltage range that operates in the saturation region. In addition, the operation of the transistor may deviate from the ideal operation in the saturation region. However, if the accuracy of the output data is within a desired range, the gate of the transistor may be The gate, source and drain voltages are assumed to be appropriately biased.

[0184] In addition, the other transistors, namely, transistor 111, transistor 123, The transistor 133 and the transistor 137 are preferably OS transistors. The extremely low off-state current of OS transistors makes them ideal switching transistors. Therefore, the capacitance element 114, the capacitance element 125, and the capacitance element The potential stored in the capacitor 135 and the capacitor 139 can be held for a long period of time.

[0185] The current I, the current IREF, and the current ICM at times T03 to T08 are respectively The currents are expressed as I0, IREF0, and ICM0. The current flowing through signal line B is represented as current IOF.

[0186] First, from time T01 to time T02, the potential of the signal line GW is set to “H” and the potential of the signal line FG[j] The potential of the signal line FG[j+1] is VG[j+1], and the potential of the signal line FGREF If the potential of is VGREF, the potentials of nodes NG[j], NG[j+1], and NGREF are These are VG[j], VG[j+1], and VGREF, respectively. j+1], VGREF operates transistor 132 and transistor 136 in normally on mode. This is the potential for making

[0187] Between time T03 and time T04, the signal line WW[i] is set to “H” and the signal line WW[i+1] is set to “L”, the potential of the signal line WD[j] is set to VPR-VX[i,j], and the potential of the signal line WD[j+1] is set to The potential of the signal line WDREF is VPR, the potential of the signal line RW[i ] is the reference potential, and the potential of the signal line RW[i+1] is the reference potential. The potential of node N[i,j] is VPR-VX[i,j], and the charge retention node N[i,j+1] The potential of the charge storage node NREF[i] is VPR-VX[i,j+1]. Here, VX[i,j] and VX[i,j+1] are a plurality of first analog data are potentials corresponding to the respective capacitors.

[0188] Between time T05 and time T06, the signal line WW[i] is set to “L” and the signal line WW[i+1] is set to “H”, the potential of the signal line WD[j] is set to VPR-VX[i+1,j], and the potential of the signal line WD[j+1 ] is VPR-VX[i+1,j+1], the potential of the signal line WDREF is VPR, and the potential of the signal line The potential of RW[i] is the reference potential, and the potential of the signal line RW[i+1] is the reference potential. The potential of the charge storage node N[i+1,j] is VPR-VX[i+1,j]. The potential of N[i+1,j+1] is VPR-VX[i+1,j+1], the charge retention node NRE The potential of F[i+1] is set to VPR, where VX[i+1,j], VX[i+1 , j+1] are potentials corresponding to the multiple first analog data, respectively.

[0189] Here, the current flowing through the transistor 124 in the memory cell MEM[i,j] (sink The current I0[i,j] is I0[i,j]=k(VPR-VX[i,j]-Vth) 2 Formula (1) In addition, the current flowing through the transistor 124 in the reference memory cell REF[i] ( The sink current IREF0[i] is IREF0[i] = k (VPR - Vth) 2 Formula (2) where k is a coefficient and Vth is the threshold voltage of the transistor 124.

[0190] In the reference column output circuit CREF, the reference memory cell REF[i] is connected to the signal line BREF. The sum of the currents IREF0[i] flowing through the transistors 124 (currents sunk in the transistors 124) is ΣIRE FO[i]=IREF0 flows, but IREF0 is equal to ICREF-ICM0 Like, that is, ICREF-ICM0=ΣIREF0[i] Equation (3) The gate potential of the transistor 138 is set so that Since 134 and transistor 138 form a current mirror, Current ICM0 also flows.

[0191] Between time T07 and time T08, the signal line OR is set to “H” and the signal line OPR[j] is set to VOP R[j], signal line OPR[j+1] to VOPR[j+1], and signal line OREF to VREF. Then, the hold nodes O[j] of the column input circuit OM[j] and OM[j+1], The potential of the holding node O[j+1] becomes VOPR[j], VOPR[j+1]. VOPR[j] and VOPR[j+1] may be different or the same for each column, but the transistors 11 2 is turned on and the value should not exceed VDD. Transistor 113 is connected to the gate. When the appropriate bias potential is supplied from the signal line OB, it operates as a constant current source and Since the transistor 112 operates as a source follower, the signal lines VO[j] and VO[j +1] to output voltage VOPR[j]-Vtho, output voltage VOPR[j+1]-Vtho is output. Note that Vtho is the threshold voltage of the transistor 112. Therefore, the output current The initial value of the output voltage can be kept constant regardless of the value of the initial value IOF[j].

[0192] A current IC[j] flows through the transistor 132 (sources), and a current I CM0 flows (sinks) into the transistor 124 of the memory cell MEM[i,j]. The current I0[i,j] flows (is drawn) and the transistor of the memory cell MEM[i+1,j] Since the current I0[i+1,j] flows (is drawn) into the transistor 124, the signal line RW[i] When the potential of is the reference potential and the potential of signal line RW[i+1] is the reference potential, IC[j]-ICM0-ΣI0[i,j]=IOF[j] Equation (4) holds true.

[0193] Before moving on to the explanation of the operation after time T09, let us consider the potential of the signal line RW[i] with respect to the reference potential. (Hereinafter, the potential of the signal line RW[i] is VW[i]. Here, VW[i] is the potential corresponding to the second analog data. The potential of the signal line RW[i] is input to the transistor 124 via the capacitor 125. Since the potential change of the signal line RW[i] is superimposed on the gate potential, the potential change of the transistor 12 More specifically, the capacitance of the capacitance element 125 and the gate potential of the transistor 4 are not increased. The capacitance coupling coefficient, which can be calculated from the gate capacitance and parasitic capacitance of the transistor 124, is The potential change multiplied by the potential change is the increment in the gate potential of the transistor 124. For the sake of simplicity, the potential multiplied by the capacitive coupling capacitance coefficient is designated as VW[i]. The potential actually supplied to the signal line RW[i] is appropriately converted by using the capacitive coupling capacitance coefficient. Just calculate it.

[0194] At this time, the current flowing through the transistor 124 in the memory cell MEM[i,j] (i,j) is The current flowing into the inductor (I[i,j]) is I[i,j]=k(VPR-VX[i,j]+VW[i]-Vth) 2 Formula (5) In addition, the current flowing through the transistor 124 in the reference memory cell REF[i] ( The sink current IREF[i] is IREF[i] = k (VPR + VW[i] - Vth) 2 Formula (6) It becomes.

[0195] In the reference column output circuit CREF, the reference memory cell REF[i] is connected to the signal line BREF. The sum of the currents IREF[i] flowing through the transistors 124 (currents sunk therein), ΣIREF [i]=IREF flows, but IREF and ICREF-ICM are equal. Mari, ICREF-ICM=ΣIREF[i] Equation (7) The gate potential of the transistor 138 is set so that Since the transistor 134 and the transistor 138 form a current mirror, the transistor 134 A current ICM also flows through

[0196] Here, the current IC[j] flows (sources) through the transistor 132, and the transistor 134 A current ICM flows (is drawn) into the memory cell MEM[i,j], and a current I[i,j] flows into the memory cell MEM[i,j]. A current I[i+1,j] flows (absorbs) through the memory cell MEM[i+1,j]. Therefore, the difference ΔI[j] between the initial value IOF[j] of the current flowing through the signal line B[j] is ΔI[j] =(IC[j]-ICM-ΣI[i,j])-(IC[j]-ICM0-ΣI0[i,j ]) =ΣIREF[i]-ICREF-ΣI[i,j]+ICREF-ΣIREF0[i]+ ΣI0[i,j] =Σk(VPR+VW[i]-Vth) 2 -Σk(VPR-VX[i,j]+VW[i] -Vth) 2 -Σk(VPR-Vth) 2 +Σk(VPR-VX[i,j]-Vth) 2 = 2kΣ(VW[i] VX[i,j]) Equation (8) Here, Σ(VW[i] VX[i,j]) is the potential V corresponding to the first analog data. X[i,j] and the potential VW[i] corresponding to the second analog data. That is, the sum of the products of the first analog data and the second analog data can be calculated. It will be possible.

[0197] In the above derivation, the current flowing through the transistor 132 and the transistor 136 (the current output It can be seen that IC[j] and ICREF may be different as long as they are each constant. In other words, the signal lines FG[j], B[j+1], and FGREF are set to independent voltages. The transistors 132 and 136 are constant current sources that supply optimum constant currents. It can be made to function as such.

[0198] Between time T09 and time T10, the potential of the signal line RW[i] is VW[i], and the potential of the signal line RW If the potential of [i+1] is the reference potential, the differential current ΔI[j]=2kΣ The output is (VW[i] VX[i,j]) = 2k VW[i] VX[i,j]. That is, the first address stored in the memory cell MEM[i,j] is output from the column output circuit OUT[j]. The second analog data corresponds to the selection signal to be applied to the memory cell MEM[i,j]. The log data and data corresponding to the product are output.

[0199] Between time T11 and time T12, the potential of the signal line RW[i] is set to the reference potential, i+1] is VW[i+1]. Then, the differential current ΔI[j]=2 kΣ(VW[i]·VX[i,j])=2k·VW[i+1]·VX[i+1,j] is output. That is, the column output circuit OUT[j] outputs a signal to the memory cell MEM[i+1,j]. The first analog data stored and the selection signal applied to the memory cell MEM[i+1,j] and data corresponding to the product of is output.

[0200] Between time T13 and time T14, the potential of the signal line RW[i] is VW[i], and the potential of the signal line RW If the potential of [i+1] is VW[i+1], the differential current ΔI[j]= 2kΣ(VW[i]·VX[i,j])=2k·(VW[i]·VX[i,j]+VW[ i+1]·VX[i+1,j]) is output from the column output circuit OUT[j]. , a first analog signal stored in a plurality of memory cells MEM[i,j], MEM[i+1,j] data and a signal to be applied to each of the memory cells MEM[i,j] and MEM[i+1,j] Then, second analog data corresponding to the selection signal and data corresponding to the sum of products are output.

[0201] From time T09 to time T14, the potentials of the signal lines B[j] and B[j+1] are When the resistance value of the resistor 115 is R, R·ΔI[j], R·ΔI[j+1], that is, From equation (8), 2kRΣ(VW[i]·VX[i,j]), kRΣ(VW[i]·VX[ i, j+1]). Therefore, if the capacitive coupling ratio of the capacitive element 114 is CC, The potential of the output signal line VO[j] and the output signal line VO[j+1] is VOPR[j]-Vth o+CC·kRΣ(VW[i]·VX[i,j]), VOPR[j+1]-Vtho+C C·kRΣ(VW[i]·VX[i,j+1]), and VOPR[j]-Vtho, The result of the multiplication and accumulation operation with the value of VOPR[j+1]-Vtho set to "0" is output. That is, , and write a certain initial value to the retention node O[j] and the retention node O[j+1]. This allows the offset to be cancelled to almost zero.

[0202] The values ​​of VOPR[j] and VOPR[j+1] are determined by the transistor 112 being a source follower. It can be adjusted within the range in which it operates as a power amplifier, and can be used directly as an input signal for the next circuit. In other words, offset cancellation and current-to-voltage conversion are possible at the same time.

[0203] In the APS 100 shown in this embodiment, as described above, the output current of the memory cell MEM is converted into a voltage and applied to a first terminal of a capacitance element 114 in the offset circuit 110. The potential of the second terminal (i.e., node O) of the capacitance element 114 is initially set to a certain initial value. By inserting the resistor into the resistor and then making it a floating node, the offset of the initial value of the output current is canceled. Therefore, only the difference from the initial value of the output current can be converted to a voltage and output. This can be done.

[0204] In this configuration, the transistor in the offset circuit has a drain voltage of 100 V in the saturation region. Even if the drain current changes due to a change in voltage, the data written to each memory cell The drain potential of the transistor in the offset circuit changes depending on the potential, and the output current There is no risk of any difference occurring.

[0205] Therefore, when the input potential is a value that represents "0," that is, the reference potential, no data is written to each memory cell. Regardless of the potential representing the weighting coefficients inserted, the output can be set to a certain initial value. This allows for highly accurate multiply-and-accumulate operations.

[0206] The APS 100 described in this embodiment is the same as the APS 50 described in the third embodiment. In comparison, by adding only resistor elements, the product-sum operation and current-voltage Therefore, there is little risk of an increase in the substrate area required for the multiply-and-accumulate circuit. Good productivity.

[0207] As described above, by using the analog multiply-and-accumulate circuit shown in this embodiment, it is possible to efficiently perform multiply-and-accumulate. In addition, a semiconductor device capable of performing a multiply-and-accumulate operation with high accuracy can be provided. It is possible to provide a semiconductor device capable of carrying out the above-mentioned operations.

[0208] (Embodiment 5) In this embodiment, details of the display panel 20 shown in the first embodiment will be described.

[0209] 《Pixel circuit》 First, a circuit configuration that can be used for the pixel 14 in FIG. 3 will be described with reference to FIG. cormorant.

[0210] The pixel 14 shown in FIG. 19A includes a transistor 3431, a capacitor 3233, and a liquid crystal element. It has a child 3432.

[0211] One of the source electrode or the drain electrode of the transistor 3431 is electrically connected to the source line 22. and the other is electrically connected to node 3436. The gate electrode of the transistor 3431 is electrically connected to the gate line 21. The transistor 3431 is connected to a node 3436 The EEPROM has a function of controlling the writing of data signals to the EEPROM.

[0212] One of the pair of electrodes of the capacitor 3233 is a wiring to which a specific potential is supplied (hereinafter, referred to as a “capacitor line”). CL), and the other is electrically connected to node 3436. The potential of the capacitance line CL is appropriately set according to the specifications of the pixel 14. The capacitance element 3233 is It has a function of holding data written in the node 3436 .

[0213] A common potential is applied to one of a pair of electrodes of the liquid crystal element 3432, and a normal potential is applied to the other. The liquid crystal contained in the liquid crystal element 3432 is electrically connected to the node 3436. The orientation state is determined by the potential written to 6.

[0214] The mode of the liquid crystal element 3432 may be, for example, TN mode, STN mode, VA mode, ASM(Axially Symmetric Aligned Micro-cell ) mode, OCB (Optically Compensated Birefring ence) mode, FLC (Ferroelectric Liquid Crystal l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, MVA mode, PVA (Patterned Vertical Al ignment) mode, IPS mode, FFS mode, or TBA (Transve Alternatively, a 3D bend alignment mode may be used. ECB (Electrically Controlled Birefringe) nce) mode, PDLC (Polymer Dispersed Liquid Crystal ystal) mode, PNLC (Polymer Network Liquid Cr However, there are various modes, including but not limited to these. Various modes can be used.

[0215] The pixel 14 shown in FIG. 19B includes a transistor 3431, a capacitor 3233, and a transistor The display panel includes a resistor 3232 and a light-emitting element 3125.

[0216] A data signal is applied to one of the source electrode and the drain electrode of the transistor 3431. The other end is electrically connected to the source line 22 and the other end is electrically connected to a node 3435. The gate electrode of the transistor 3431 is electrically connected to the gate line 21 to which a gate signal is applied. The transistor 3431 has a function of controlling writing of a data signal to the node 3435. Yes.

[0217] One of a pair of electrodes of the capacitor 3233 is electrically connected to the node 3435, and the other is The capacitor 3233 is electrically connected to the node 3437. It functions as a storage capacitor to hold data.

[0218] One of the source electrode and the drain electrode of the transistor 3232 is connected to the potential supply line VL_a. The other end of the transistor 3232 is electrically connected to a node 3437. The gate electrode is electrically connected to a node 3435. The transistor 3232 is a light-emitting element. It has the function of controlling the current flowing through 3125.

[0219] One of the anode and the cathode of the light-emitting element 3125 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 3437.

[0220] As the light-emitting element 3125, for example, an organic EL element can be used. For example, an inorganic EL element made of an inorganic material may be used.

[0221] For example, the potential supply line VL_a has a function of supplying VDD. b has the function of supplying VSS.

[0222] <Cross-section> Next, a configuration example of the display panel 20 will be described with reference to the cross-sectional views of FIG. 20 and FIG. .

[0223] The display panel 20 shown in FIGS. 20A and 20B has an electrode 4015. is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. The electrode 4015 is also formed on the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. The electrode 4015 is electrically connected to the wiring 4014 through the formed opening. The electrode layer 4030 is formed from the same conductive layer.

[0224] The pixel 14 provided on the first substrate 4001 has a transistor. 20A illustrates a transistor 3431 included in the pixel 14, and FIG. The transistor 3232 included in element 14 is illustrated.

[0225] The transistors 3431 and 3232 are provided over an insulating layer 4102. The transistors 3431 and 3232 each have an electrode 517 formed on the insulating layer 4102. An insulating layer 4103 is formed on the electrode 517. A semiconductor layer 512 is formed on the insulating layer 4103. An electrode 510 and an electrode 511 are formed on the semiconductor layer 512. An insulating layer 4110 and an insulating layer 4111 are formed on the electrode 511. An electrode 516 is formed on the insulating layer 4111. The electrodes 510 and 511 are connected to the wiring 4 It is formed from the same conductive layer as 014.

[0226] In the transistors 3431 and 3232, the electrode 517 functions as a gate electrode. The electrode 510 functions as either a source electrode or a drain electrode, and the electrode 511 The electrode 516 functions as the back gate electrode. It functions as a pole.

[0227] The transistors 3431 and 3232 have a bottom gate structure and a back gate. By controlling the threshold voltage of the transistor, the on-state current can be increased. In order to simplify the manufacturing process, the electrode 516 may be omitted in some cases. good.

[0228] In the transistors 3431 and 3232, the semiconductor layer 512 serves as a channel formation region. The semiconductor layer 512 may be formed of crystalline silicon, polycrystalline silicon, or amorphous silicon. , metal oxide, organic semiconductor, or the like may be used. In order to increase the conductivity of the semiconductor layer 512 or to control the threshold of the transistor, Impurities may be introduced into the semiconductor.

[0229] When a metal oxide is used as the semiconductor layer 512, the semiconductor layer 512 contains indium (In). When the semiconductor layer 512 is a metal oxide containing indium, the semiconductor layer 5 The semiconductor layer 512 has high carrier mobility (electron mobility). The element M is preferably aluminum (Al), gallium (Ga), or the like. Other elements that can be used for M include aluminum (Ga) or tin (Sn). are boron (B), silicon (Si), titanium (Ti), iron (Fe), and nickel (Ni) , Germanium (Ge), Yttrium (Y), Zirconium (Zr), Molybdenum (M o), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), Tantalum (Ta), tungsten (W), etc. However, the element M is the aforementioned element In some cases, a combination of multiple elements may be used. For example, the bond energy with oxygen is For example, the bond energy between oxygen and indium is higher than that between indium and oxygen. The semiconductor layer 512 is preferably a metal oxide containing zinc (Zn). Metal oxides such as tantalum oxide may be prone to crystallization.

[0230] The semiconductor layer 512 is not limited to a metal oxide containing indium. For example, indium-free, zinc-containing metals such as zinc tin oxide and gallium tin oxide. Metal oxides containing gallium, metal oxides containing tin, etc. may also be used.

[0231] The display panel 20 shown in FIGS. 20A and 20B further includes a capacitor 3233. The element 3233 has a region where the electrode 511 and the electrode 4021 overlap with each other via an insulating layer 4103. The electrode 4021 is formed from the same conductive layer as the electrode 517.

[0232] FIG. 20A shows an example of a liquid crystal display panel using liquid crystal elements as display elements. In FIG. 3A, a liquid crystal element 3432, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a The polar layer 4031 and the liquid crystal layer 4008 are sandwiched between the polar layer 4031 and the liquid crystal layer 4008. The insulating layer 4032 and the insulating layer 4033 functioning as a film are provided. 31 is provided on the second substrate 4006 side, and a first electrode layer 4030 and a second electrode layer 4031 are superimposed via a liquid crystal layer 4008.

[0233] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. and the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0234] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0235] The specific resistance of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 11 Ω cm or more, and more preferably 1×10 12 In addition, this specification The resistivity values ​​stated herein are those measured at 20°C.

[0236] When an OS transistor is used as the transistor 3431, the transistor 3431 is turned off. Therefore, the current value in the OFF state (OFF current value) can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, thereby reducing power consumption. It has an effect.

[0237] In addition, in the display panel, black matrix (light-shielding layer), polarizing member, phase difference member, reflector Optical members (optical substrates) such as anti-reflection members may be provided as appropriate. For example, a polarizing substrate and Circularly polarized light produced by a retardation substrate may be used. etc. may also be used.

[0238] FIG. 20B is an example of a display panel using light-emitting elements such as EL elements as display elements. EL elements are divided into organic EL elements and inorganic EL elements.

[0239] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. In addition to the light-emitting compound, the EL layer also contains a material with high hole injection properties, a material with high hole transport properties, and materials with high electron transport properties, hole blocking materials, materials with high electron transport properties, materials with high electron injection properties, or a bipolar substance (a substance having high electron transporting and hole transporting properties). The EL layer can be formed by deposition (including vacuum deposition), transfer, printing, inkjet, or coating. The method may be the same as that described above.

[0240] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. This is a localized emission that uses

[0241] FIG. 20B illustrates an example in which an organic EL element is used as the light emitting element 3125.

[0242] In FIG. 20B, the light-emitting element 3125 is a transistor 323 provided in the pixel 14. The light emitting element 3125 is electrically connected to the first electrode layer 4030. The light emitting layer 4511 and the second electrode layer 4031 are laminated together, but the present invention is not limited to this structure. The configuration of the light emitting element 3125 can be changed appropriately according to the direction of the light extracted from the light element 3125. It is possible to do so.

[0243] The partition 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the side of the opening is a continuous curved It is preferable to form the inclined surface so that the inclined surface is formed with a certain rate.

[0244] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0245] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 3125, the second electrode layer A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 40 The space sealed by 05 is sealed with a filler 4514. A protective film (lamination film) that is highly airtight and has little outgassing so as not to be exposed to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. It is.

[0246] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, poly Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (ethylene vinyl acetate) or the like can be used. Agents may also be included.

[0247] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0248] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0249] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves visibility of the displayed image.

[0250] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0251] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0252] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or derivatives thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, or a copolymer or derivative thereof consisting of two or more of aniline, pyrrole and thiophene. conductors, etc.

[0253] In order for the light emitting element 3125 to emit light to the outside, at least the first electrode layer 4030 or the second electrode layer 4031 is provided. It is sufficient that one of the two electrode layers 4031 is transparent. Both top emission and bottom emission structures are available. It is classified as a surface emission (dual emission) structure. The top emission structure is The bottom emission structure refers to the case where light is extracted from the substrate 4001. The dual-side emission structure refers to a structure in which light is extracted from both the substrate 4006 and the substrate 4001. For example, in the case of a top emission structure, the second electrode layer 4031 may be made transparent. In the case of a dual-side emission structure, the first electrode layer 4030 may be made transparent. The first electrode layer 4030 and the second electrode layer 4031 may be transparent.

[0254] <Substrate 4001> The substrate 4001 and the like must be made of a material that is heat-resistant enough to withstand the heat treatment during the manufacturing process. For example, a material having a thickness of 0.1 mm or more and 0.7 mm or less can be used for the substrate 4001. Specifically, a material that has been polished to a thickness of about 0.1 mm can be used.

[0255] For example, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200 mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800 10th generation (2950mm x 3400mm) and other large glass substrates 4001, etc. This allows the manufacture of large-sized display devices. .

[0256] An organic material, an inorganic material, or a composite material of an organic material and an inorganic material is used for the substrate 4001. For example, inorganic materials such as glass, ceramics, and metals can be used for the substrate 4001. There can be.

[0257] Specifically, non-alkali glass, soda-lime glass, potash glass, crystal glass, The substrate 40 is made of luminosilicate glass, tempered glass, chemically tempered glass, quartz, sapphire, or the like. 01, etc. Specifically, it can be used as an inorganic oxide film, an inorganic nitride film, or an inorganic oxynitride film. For example, a silicon oxide film, a silicon nitride film, etc. can be used for the substrate 4001. A silicon oxide film, a silicon nitride film, an aluminum oxide film, etc. can be used for the substrate 4001, etc. Stainless steel or aluminum can be used for the substrate 4001. can.

[0258] For example, single crystal semiconductor substrates, polycrystalline semiconductor substrates, silicon or silicon carbide substrates, A compound semiconductor substrate such as germanium, an SOI substrate, etc. can be used for the substrate 4001, etc. This allows semiconductor elements to be formed on the substrate 4001 or the like.

[0259] For example, organic materials such as resin, resin film, or plastic are used for the substrate 4001. Specifically, polyester, polyolefin, polyamide, polyimide, A resin film or plate such as polycarbonate or acrylic resin is used as the substrate 4001, etc. can be used.

[0260] For example, a metal plate, a thin glass plate, or a film of an inorganic material is laminated to a resin film, etc. The composite material can be used for the substrate 4001. For example, a fibrous or particulate metal A composite material in which glass or inorganic materials are dispersed in a resin film is used as a substrate 4001, etc. For example, a fibrous or particulate resin or organic material can be mixed with an inorganic material. The dispersed composite material can be used for the substrate 4001 or the like.

[0261] In addition, a single layer material or a material having multiple layers laminated thereon can be used for the substrate 4001, etc. For example, a material that is laminated with a base material and an insulating film that prevents the diffusion of impurities contained in the base material can be It can be used for the substrate 4001, etc. Specifically, the glass and the impurities contained in the glass A layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc., which prevents diffusion Alternatively, a material in which a plurality of films are laminated can be used for the substrate 4001. Silicon oxide film, silicon nitride film or oxynitride film that prevents the diffusion of impurities through oil and resin A material having a silicon film or the like laminated thereon can be used for the substrate 4001 or the like.

[0262] Specifically, polyester, polyolefin, polyamide, polyimide, polycarbonate A resin film such as acrylic resin, a resin plate, or a laminated material is applied to the substrate 4001, etc. It can be used.

[0263] Specifically, polyester, polyolefin, polyamide (nylon, aramid, etc.), Polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin or silicone A material containing a resin having a siloxane bond such as corn can be used for the substrate 4001. do.

[0264] Specifically, polyethylene terephthalate (PET), polyethylene naphthalate (PE N), polyethersulfone (PES) or acrylic resin is used for the substrate 4001, etc. Alternatively, cycloolefin polymer (COP), cycloolefin copolymer Rimer (COC), etc. can be used.

[0265] Moreover, paper or wood can be used for the substrate 4001 and the like.

[0266] For example, a flexible substrate can be used for the substrate 4001 or the like.

[0267] Note that a method of forming a transistor, a capacitor, or the like directly on a substrate can be used. In addition, for example, a transistor or A capacitor element or the like is formed, and the formed transistor or capacitor element or the like is transferred to a substrate 4001 or the like. This allows a transistor to be formed on a flexible substrate, for example. Alternatively, a capacitor element or the like can be formed.

[0268] <Substrate 4006> For example, the material that can be used for the substrate 4001 can be used for the substrate 4006 . For example, a light-transmitting material selected from materials that can be used for the substrate 4001 is It can be used for the substrate 4006. Alternatively, an anti-reflection film having a thickness of, for example, 1 μm or less can be provided on one surface. A material on which a stopper film is formed can be used for the substrate 4006. Specifically, a three-layer dielectric A material having 15 or more layers, preferably 5 or more layers, more preferably 15 or more layers, is used for the substrate 4006. This allows the reflectance to be suppressed to 0.5% or less, preferably 0.08% or less. Alternatively, a birefringent material selected from the materials usable for the substrate 4001 may be used. A material that is resistant to folding can be used for the substrate 4006 .

[0269] For example, aluminosilicate glass, tempered glass, chemically tempered glass, sapphire, etc. This can be suitably used for the substrate 4006 arranged on the side closer to the user of the panel. This makes it possible to prevent the display panel from being damaged or scratched during use.

[0270] For example, cycloolefin polymer (COP), cycloolefin copolymer (COC) A resin film such as triacetyl cellulose (TAC) is preferably used for the substrate 4006. This can reduce the weight or, for example, the risk of injury from a fall. The frequency of occurrence of damage, etc. can be reduced.

[0271] Also, for example, a material having a thickness of 0.1 mm or more and 0.7 mm or less may be used for the substrate 4006. In particular, a polished substrate can be used to reduce the thickness.

[0272] FIG. 21A shows a transistor 3431 shown in FIG. 20A that is a top-gate transistor. FIG. 21(B) shows a cross-sectional view of the case where a resistor is provided. 32 is a cross-sectional view of a transistor 3232 provided with a top-gate transistor. is.

[0273] In the transistors 3431 and 3232 in FIG. 21(A) and (B), the electrode 517 is a gate The electrode 510 functions as either a source electrode or a drain electrode. The electrode 511 functions as the other of the source electrode and the drain electrode.

[0274] For details of other components in Figures 21(A) and (B), please refer to the descriptions in Figures 20(A) and (B). Please refer to the attached document.

[0275] In this specification, unless otherwise specified, the on-current is the current when a transistor is in the on-state. The on-state (sometimes abbreviated as on) refers to the drain current when the In this case, the voltage between the gate and source (VG) of an n-channel transistor is equal to the threshold voltage (Vth) or higher, and for p-channel transistors, this refers to the state where VG is below Vth. For example, the on-current of an n-channel transistor is the drain current when VG is equal to or higher than Vth. The on-current of a transistor is determined by the voltage between the drain and source (VD ) may be dependent on

[0276] In this specification, unless otherwise specified, the off-state current refers to the current flowing when a transistor is in an off state. The drain current when the device is in the off state (sometimes abbreviated as "off") is In this case, VG is lower than Vth for n-channel transistors, and Vth is lower than Vth for p-channel transistors. In a transistor, this means that VG is higher than Vth. For example, in an n-channel transistor The off-state current of a transistor is the drain current when VG is lower than Vth. The off-state current may depend on VG. Therefore, if the off-state current of the transistor is 10 -21 A The off-state current of the transistor is less than 10 -21 There exists a value of VG that is less than A. It is sometimes said that...

[0277] In addition, the off-state current of a transistor may depend on V. Unless otherwise specified, the current is set for absolute values ​​of VD of 0.1V, 0.8V, 1V, 1.2V, and 1 .8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V Alternatively, it may represent a current flowing through a semiconductor device that includes the transistor. It may represent the off-state current at the VD used.

[0278] In the present specification and the like, when describing the connection relationship of a transistor, is expressed as "one of the source and drain" (or the first electrode, or the first terminal), and the source The other of the source and drain is called the "other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because it changes depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. should be used appropriately depending on the situation. It can be replaced.

[0279] In the present specification, when it is explicitly stated that X and Y are connected, X In the present invention, the case where X and Y are electrically connected and the case where X and Y are directly connected are It is assumed that such disclosure is made in the detailed instructions, etc.

[0280] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0281] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When X and Y are connected without any intermediate devices (electrodes, display elements, light-emitting elements, loads, etc.) It is.

[0282] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch can be in a conductive state (ON state) or a non-conductive state (OFF state). ) and has the function of controlling whether or not current flows. It has the function of selecting and switching the path through which current flows. X and Y are electrically connected. When X and Y are connected to each other, this includes the case where X and Y are directly connected to each other. EXAMPLES

[0283] In this embodiment, the OS-APS shown in the third embodiment was fabricated on a glass substrate. A simulation was performed on the multiplication characteristics of the OS-APS shown in FIG.

[0284] The optical microscope photograph of the prototype OS-APS chip is shown in Figure 22. FIG. 22(A) is a photograph of the entire -APS, and FIG. 22(B) is an enlarged photograph of the memory cell MC portion.

[0285] FIG. 22A shows a portion corresponding to the circuit CSC, the circuit CSK, and the memory cell MC in FIG. are shown respectively.

[0286] FIG. 22B shows the transistors M01, M02, and M03 of the memory cell MC. 1 and the portions corresponding to the capacitance element C0 are shown.

[0287] 23 and 24 show the configuration of one memory cell MC of the OS-APS described in the fourth embodiment. FIG. 23 shows the simulation results of the multiplication characteristics of the offset filter according to one embodiment of the present invention. The results are shown for a case where the offset circuit is not included as a comparative example in FIG. Shows.

[0288] The multiplication characteristics were calculated by changing the input voltage over time. The horizontal axis is time (seconds) and the vertical axis is output voltage (V). The weighting factor "W" is 1.3V for W="1", 1.8V for W="0.5", 2.3V for W="0", When W=“-0.5”, 2.8V was given, and when W=“-1”, 3.3V was given. -If APS multiplication is performed ideally, the straight line of the multiplication result of each weighting coefficient will be “0”. They intersect at a corresponding point.

[0289] When an offset circuit is provided as shown in FIG. 23, the lines representing the multiplication results of the weighting coefficients intersect at one point. On the other hand, if there is no offset circuit as in Figure 24, the product is equivalent to "0". The points where the lines crossed were different for each weighting coefficient, and they did not intersect at a single point.

[0290] Next, we constructed a neural network using the prototype OS-APS shown in Figure 22, and performed learning and prediction. A simulation was conducted in which the theory was carried out.

[0291] First, the 36-pixel (=6×6) image data ("1", "2", Learning was conducted on the following two models: "3" and "4":

[0292] Next, an image was prepared by adding 10% noise to the image data in FIG. 25(A) (FIG. 25 (B)) and performed inference on these images. Even in this case, the images were correctly recognized with an accuracy of over 95%.

[0293] As described above, by using the OS-APS, which is one embodiment of the present invention, a neural network can be constructed. It was confirmed that image recognition could be achieved through machine learning. EXAMPLES

[0294] In this embodiment, a display device using a flexible touch panel that can be folded into three parts is used. They created a device and demonstrated that character recognition is possible using a neural network.

[0295] The flexible touch panel was fabricated as follows. First, one of the substrates (glass substrate) was A peeling layer (tungsten film) is formed on the substrate, and transistors and light-emitting elements are formed on the peeling layer. A peeling layer was formed on the other substrate. A layer to be peeled off including an electrode of a touch sensor using a conductive oxide film and a color filter is formed. Next, the two prepared substrates were bonded together with an adhesive layer, and then each prepared substrate was peeled off from the peeled layer. The device was fabricated by attaching a flexible substrate using an adhesive.

[0296] A top-emission type organic EL element was used as the light-emitting element.

[0297] The semiconductor layer in which the transistor channel is formed is made of crystalline gold containing In, Ga, and Zn. Metal oxides were applied.

[0298] The manufactured display device is shown in Figure 26. The display device has three flexible touch panels 5001. In FIG. 26, the flexible touch panel 5 The display surface of 001 is curved so that there are both convex and concave parts. It shows.

[0299] In FIG. 26, handwritten input character 5003 "S" is clearly shown.

[0300] In this embodiment, handwritten characters input to a flexible touch panel are processed by a neural network. We verified whether the workpiece could be identified using a flexible touch panel. The touch signal output from the touch sensor is input to a computer, and the computer uses the pre-trained neural network to The result was that the flexible touch panel It was confirmed that character recognition was possible without any problems even for handwritten characters entered into the system. [Explanation of symbols]

[0301] 1 Information terminal 1a Information terminal 2 Display section 2a Display section 3a Case 3b Housing 3c Case 4 Hinge 5 Server 10. Touch Panel System 11 Pixel section 12 Gate Driver 13 Source Driver 14 pixels 15 Touch Sensor 16 Sensing circuit 19 NN circuit 20 Display Panel 21 Gate line 22 Source Line 25 Host 31 Input Layer 32 Middle Class 33 Output layer 41_1 Neuron 41_2 Neuron 41_3 Neuron 42_1 Neuron 42_2 Neuron 42_3 Neuron 43_1 Neuron 43_2 Neuron 43_3 Neuron 50 APS 51 Memory Cell Array 52 Circuit 53 Circuit 54 Circuit 60 Image receiving device 61 Display section 62 Input Area 63 areas 64 Antenna 65 Internet lines 66 Servers 70 Touch Panel System 72 Encoder 73 Image Processing Circuit 74 Decoder 75 Analog Front End 76 Receiving circuit 77 Decoder 81 Top cover 82 FPC 83 FPC 84 FPC 87 Backlight unit 88 Light source 89 Frames 90 Printed Circuit Board 91 Battery 92 Lower cover 100 APS 110 Offset circuit 111 Transistor 112 Transistor 113 Transistor 114 Capacitive element 115 Resistance element 120 Memory Cell Array 123 Transistor 124 Transistor 125 Capacitive element 130 Current source circuit 131a constant current circuit 131b Constant current circuit 132 Transistor 133 Transistor 134 Transistor 135 Capacitive element 136 Transistor 137 Transistor 138 Transistor 139 Capacitive element 140 Transistor 141 Transistor 510 electrode 511 Electrode 512 Semiconductor layer 516 Electrode 517 Electrode 3125 Light emitting element 3232 Transistor 3233 Capacitive element 3431 Transistor 3432 Liquid crystal elements 3435 nodes 3436 nodes 3437 nodes 4001 Substrate 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4014 Wiring 4015 Electrode 4018 FPC 4019 Anisotropic conductive layer 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4102 Insulating layer 4103 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4510 Bulkhead 4511 Light-emitting layer 4514 Filling material 5001 Flexible touch panel 5002 Case 5003 Handwritten characters

Claims

[Claim 1] An electronic device including a first circuit, a display unit, a source driver, a touch sensor, and a host, the first circuit comprises a neural network; The display unit has a flexible display, The touch sensor includes a sensing circuit. the sensing circuit has a function of detecting handwritten characters input to the touch sensor as image information and transmitting the image information to the neural network, and a function of notifying the host of the input to the touch sensor; the neural network has a function of analyzing the image information and converting it into character information, and a function of outputting the character information to the source driver; the source driver has a function of synthesizing the image data received from the host and the character information received from the neural network and displaying the synthesized image on the display unit; the analysis of the image information is performed by inference using the neural network; The neural network is implemented using multiply-and-accumulate operations; the first circuit includes an analog multiply-accumulate circuit; the multiply-and-accumulate operation is performed by the analog multiply-and-accumulate circuit; The analog product-sum operation circuit is an electronic device having a memory cell array, a current source circuit, a current sink circuit, a current mirror circuit, a high power supply potential, and a low power supply potential.

Images