Semiconductor Device

Abstract

To improve the production yield of a display device and increase the resistance of the display device against ESD.SOLUTION: A display device includes a substrate, a display unit, a connection terminal, a first wire, and a second wire. The first wire has a part that is electrically connected to the connection terminal and exists between the connection terminal and the display unit. The second wire includes a part that is electrically connected to the connection terminal, exists between the connection terminal and an end part of the substrate, and has a side surface exposed at the end part of the substrate. The display unit has a transistor. The transistor has a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer and the second wire contain a metal oxide.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] Display devices using organic electroluminescence (EL) elements and liquid crystal elements are known. In addition, other examples of display devices include light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs) and electronic paper that displays images using an electrophoretic method.

[0004] In addition, oxide semiconductors using metal oxides have been attracting attention as semiconductor materials that can be used for transistors that constitute pixels of display devices. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer that serves as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0005] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility than those using amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-7399 A Summary of the Invention [Problem to be solved by the invention]

[0007] During the manufacturing process of a display device, overvoltage caused by electrostatic discharge (ESD) can destroy transistors, capacitors, etc. In particular, when manufacturing a display device using an insulating substrate such as a large glass substrate, electric charges tend to accumulate in wiring, etc., which has been a cause of reduced yields.

[0008] An object of one embodiment of the present invention is to improve the manufacturing yield of a display device, to increase resistance of a display device to ESD, to provide a highly reliable display device, or to provide a display device having a novel structure.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a display device including a substrate, a display portion, a connection terminal, a first wiring, and a second wiring. The first wiring is electrically connected to the connection terminal and has a portion located between the connection terminal and the display portion. The second wiring is electrically connected to the connection terminal and is located between the connection terminal and an end portion of the substrate, and has a portion whose side surface is exposed at the end portion of the substrate. The display portion includes a transistor. The transistor includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer and the second wiring contain metal oxide.

[0011] In the above, it is preferable that the semiconductor layer and the second wiring are provided on the same surface and contain the same metal element.

[0012] In the above, the semiconductor layer preferably has a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode, and the second region and the second wiring preferably have a lower resistance than the first region.

[0013] In the above, the second wiring preferably has a higher resistance than the first wiring.

[0014] In the above, it is preferable that the semiconductor device further includes a third wiring electrically connected to the transistor. In this case, it is preferable that the third wiring and the first wiring are provided on the same plane and contain the same metal element.

[0015] In the above, it is preferable that the connection terminal includes a part of the first wiring.

[0016] In the above, it is preferable to have an FPC electrically connected to the connection terminal. In this case, it is preferable that the FPC has a portion overlapping with the second wiring.

[0017] In the above, the substrate preferably has a first portion overlapping the first wiring and a second portion overlapping the connection terminal and the second wiring, wherein the first portion is curved so that the first wiring faces outward, and the second portion preferably has a region overlapping the first wiring or the display unit.

[0018] Another embodiment of the present invention is a method for manufacturing a display device, comprising the steps of: forming a transistor including a semiconductor layer, a plurality of connection terminals, and wirings that electrically connect the plurality of connection terminals over a substrate; cutting a part of the substrate and a part of the wirings to electrically separate the plurality of connection terminals; and connecting an FPC to the plurality of connection terminals. Furthermore, the semiconductor layer and the wirings are preferably formed by processing the same metal oxide film. Effect of the Invention

[0019] According to one embodiment of the present invention, the manufacturing yield of a display device can be improved, resistance of the display device to ESD can be increased, a highly reliable display device can be provided, or a display device having a novel structure can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0021] [Figure 1] 1A to 1D are diagrams showing configuration examples of a display device. [Diagram 2] 2A to 2D are diagrams showing configuration examples of a display device. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the display device. [Figure 4] 4A and 4B are diagrams showing an example of a cross-sectional configuration of a display device. [Diagram 5] 5A and 5B are diagrams showing an example of a cross-sectional configuration of a display device. [Figure 6] 6A and 6B are diagrams showing an example of a cross-sectional configuration of a display device. [Figure 7] 7A and 7B are diagrams showing an example of a cross-sectional configuration of a display device. [Figure 8] 8A to 8C are diagrams showing configuration examples of a display device. [Figure 9] 9A to 9C are diagrams showing configuration examples of a display device. [Figure 10] 10A to 10L are diagrams showing examples of wiring configurations. [Figure 11] FIG. 11 is a diagram showing an example of a cross-sectional configuration of a display device. [Figure 12] FIG. 12 is a diagram showing an example of a cross-sectional configuration of a display device. [Figure 13] FIG. 13 is a diagram showing an example of a cross-sectional configuration of a display device. [Figure 14] 14A to 14E are diagrams showing configuration examples of a TEG. [Figure 15] Figure 15A is a block diagram of a display device, and Figures 15B and 15C are circuit diagrams of a pixel. [Figure 16] Figures 16A, 16C, and 16D are circuit diagrams of the display device, and Figure 16B is a timing chart. [Figure 17] 17A and 17B are diagrams showing a configuration example of a display module. [Figure 18] 18A to 18C are diagrams showing configuration examples of electronic devices. [Figure 19] 19A to 19E are diagrams showing configuration examples of electronic devices. [Figure 20] 20A to 20G are diagrams showing configuration examples of electronic devices. [Figure 21] 21A to 21D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

[0024] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0025] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and do not limit the numbers.

[0026] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0027] In addition, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0028] In addition, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchangeable with the terms "conductive film" and "insulating film".

[0029] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0030] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or a substrate having an IC mounted thereon using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0031] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0032] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0033] In addition, in this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0034] (Embodiment 1) In this embodiment, a structural example and a manufacturing method example of a display device according to one embodiment of the present invention will be described.

[0035] One embodiment of the present invention is a display device in which a display portion and a plurality of connection terminals are provided over a substrate.

[0036] The display section is a region for displaying an image, and includes a plurality of pixels, each of which includes a display element, arranged in a matrix. Each pixel preferably includes one or more display elements and one or more transistors.

[0037] The connection terminal is a terminal to which an FPC (Flexible Printed Circuit), an IC, etc. The connection terminal is made up of at least one conductive layer, and has a configuration in which the surface is exposed.

[0038] In addition, a first wiring is provided between the connection terminal and the display unit. The first wiring is electrically connected to the connection terminal and has a function of supplying a signal or potential supplied from the connection terminal to the display unit or a driver circuit for driving the display unit. The first wiring is preferably low resistance. The first wiring is preferably located on the same plane as electrodes or wiring constituting a transistor or a display element, and is preferably formed by processing the same conductive film as these.

[0039] In addition, a second wiring is provided to electrically connect the multiple connection terminals during the manufacturing process of the display device. Since the multiple connection terminals are electrically connected by the second wiring, the influence of ESD during the manufacturing process of the display device can be mitigated and the elements and wirings of the display device can be suitably prevented from being damaged. In the manufacturing process of the display device, various processes can cause ESD, such as substrate transportation, plasma processing in film formation and etching, wet etching, development processing, and cleaning processing.

[0040] The second wiring is preferably cut simultaneously with the substrate in a process of dividing (also called cutting) the substrate after the display section and the multiple connection terminals are formed. This allows the multiple connection terminals to be electrically separated simultaneously in the substrate dividing process. Thereafter, a display device (display module) can be completed by connecting an FPC or an IC to the multiple connection terminals.

[0041] The second wiring is preferably formed by processing a semiconductor film, and in this case, the second wiring is preferably formed of a semiconductor film having a high carrier concentration and a low resistance.

[0042] In particular, it is preferable to form the second wiring by processing the same semiconductor film as the semiconductor layer of the transistor included in the display portion or the driver circuit. The semiconductor layer of the transistor has a channel formation region where a channel can be formed, and a low-resistance region sandwiching the channel formation region and having a lower resistance than the channel formation region. The second wiring is preferably formed of a semiconductor film with reduced resistance, similar to the low-resistance region of the semiconductor layer. The semiconductor layer may be formed including a silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon) film, an organic semiconductor film, or the like, but it is particularly preferable to use a metal oxide film (also called an oxide semiconductor film) that exhibits semiconductor characteristics.

[0043] After the substrate is cut, the second wiring has a cut surface (also referred to as an end surface or a side surface) exposed near an end surface (also referred to as an end surface) of the substrate. Here, when a low-resistance material such as a metal film is used as the second wiring, electrical noise may be transmitted from the exposed end surface of the second wiring to the connection terminal, or the cut surface of the second wiring may come into contact with a housing or various components constituting a device in which the display device is mounted, causing an electrical short circuit of the connection terminal. On the other hand, in the display device according to one embodiment of the present invention, a semiconductor film having a lower conductivity than a metal film is used as the second wiring, and therefore the above-mentioned problems are unlikely to occur. In particular, by using a metal oxide film as the second wiring, the contact resistance when the second wiring comes into contact with a metal member can be increased compared to the case of using a metal film.

[0044] The electrical resistivity, resistance per unit length of the wiring, or sheet resistance of the second wiring is preferably at least 2 times, preferably at least 5 times, more preferably at least 10 times, and even more preferably at least 100 times, and is preferably at most 10,000 times, preferably at most 5,000 times, and more preferably at most 1,000 times, that of the first wiring at room temperature. For example, the electrical resistivity calculated from the resistance or sheet resistance is 1×10 -7 [Ω m] or more 1×10 -3 [Ω·m] or less, preferably 1×10 -6 [Ω m] or more 1×10 -4 It is preferable to use a metal oxide film having a resistivity of [Ω·m] or less for the second wiring.

[0045] Furthermore, it is preferable that a part of the FPC connected to the connection terminal is provided so as to overlap the second wiring remaining on the substrate side. In particular, it is preferable that a part of the FPC is provided so as to extend to a position where it overlaps with the end face of the substrate and cover the exposed end face of the second wiring. This makes it possible to suitably prevent the housing and various components constituting the device in which the display device is mounted from contacting the end face of the second wiring.

[0046] Moreover, by using a flexible material for the substrate, a bendable display device (flexible display) may be obtained. In this case, the substrate includes a support substrate, a support film, a protective film, etc. Furthermore, by bending the portion (first portion) of the substrate overlapping with the first wiring on the opposite side to the display surface side of the display unit so that the first wiring faces outward, the connection terminals of the substrate and the portion (second portion) overlapping with the second wiring can be made to overlap with part of the first wiring or the display unit. This allows the connection terminals and the FPC to be folded back to the back side of the display surface, thereby realizing miniaturization of the device in which the display device is mounted.

[0047] A more specific example of the display device will be described below with reference to the drawings.

[0048] [Display device configuration example 1] A display device 10 shown in Fig. 1A includes a substrate 21, a substrate 22, a display unit 11, a plurality of connection terminals 12, a plurality of wires 13, and a wire 14. Fig. 1A corresponds to a perspective view of the wire 14 before it is cut.

[0049] The display unit 11 is provided in the area where the substrate 21 and the substrate 22 overlap. The display unit 11 is a portion for displaying images, and a plurality of pixels (not shown) are provided in a matrix. Note that the substrate 22 does not have to be provided if it is not necessary.

[0050] Examples of the display element provided in the pixel of the display unit 11 include a liquid crystal element and a light emitting element.

[0051] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers.

[0052] The organic EL element (OLED) may be of a bottom emission type that emits light to the surface on which the light is formed, a top emission type that emits light to the opposite side to the surface on which the light is formed, or a dual emission type that emits light to both sides, and any of these may be used. In particular, the use of a top emission type light emitting element is preferred because it can increase the aperture ratio, making it easy to achieve high definition, and can increase the luminance of the light emitting element.

[0053] Light emitting diodes (LEDs) include macro LEDs (also called giant LEDs), mini LEDs, micro LEDs, and the like, from large to large. Here, LED chips with a side dimension exceeding 1 mm are called macro LEDs, LEDs with a side dimension of more than 100 μm and 1 mm or less are called mini LEDs, and LEDs with a side dimension of 100 μm or less are called micro LEDs. It is particularly preferable to use mini LEDs or micro LEDs as the LEDs applied to the display unit 11. By using micro LEDs, an extremely high-definition display device can be realized.

[0054] As the display element, a liquid crystal element such as a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. Also, a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element, a display element using a microcapsule type, an electrophoresis type, an electrowetting type, an electronic liquid powder type, etc. can be used.

[0055] The connection terminal 12, the wiring 13, and the wiring 14 are provided on the substrate 21. The connection terminal 12 functions as a terminal for electrically connecting to an FPC 16, which will be described later, an IC 19, etc. The connection terminal 12 is provided in an area of ​​the substrate 21 that is not covered by the substrate 22.

[0056] The wiring 13 electrically connects the connection terminal 12 to the display unit 11 of the display device 10, a driving circuit (not shown), or the like.

[0057] The wiring 14 has a function of electrically connecting the multiple connection terminals 12. The wiring 14 preferably has a shape that allows the multiple connection terminals 12 to be easily electrically separated in a single cutting step. For example, as shown in FIG. 1A, the wiring 14 preferably has a comb-like shape having multiple portions extending from the respective connection terminals 12 and a portion to which these multiple portions are connected. In this case, it is preferable that the portions of the wiring 14 extending from the connection terminals 12 intersect with the scribe lines (shown by dashed lines) of the substrate 21, because this allows the wiring 14 to be cut simultaneously in the cutting step of the substrate 21.

[0058] Fig. 1B shows a perspective view after cutting the substrate 21 and the wiring 14. Fig. 1B shows a substrate 21a separated from the substrate 21 and wiring 14a after cutting.

[0059] A scriber, a laser scriber, a cutter, a shearing device, or the like can be used to divide the substrate 21. When a flexible film or the like is used as the substrate 21, a cutter, a laser cutter, a press cutter, a punching device, or the like may be used. As the punching device, there is one that uses a metal mold, and one that uses a Thompson mold (a mold in which a steel blade is embedded in a wooden mold).

[0060] By cutting wiring 14 at the same time as dividing substrate 21, a plurality of wirings 15 are formed on substrate 21, and a plurality of connection terminals 12 are electrically separated from each other. Each of wirings 15 is electrically connected to one connection terminal 12. In addition, the end of wiring 15 opposite connection terminal 12 is in a state where the cut surface (also called side surface or end surface) is exposed at the end of substrate 21.

[0061] 1C corresponds to a perspective view after FPC 16 is attached to a plurality of connection terminals 12. Note that an IC may be attached separately from FPC 16, or an FPC with an IC mounted thereon may be attached to connection terminals 12.

[0062] 1D is a schematic cross-sectional view of a cut surface of the substrate 21 of the display device 10 and its vicinity. In FIG. 1D, the cut substrate 21a and wiring 14a are also clearly shown.

[0063] The display device 10 has a transistor 30, a wiring 13, a connection terminal 12, a wiring 15, and the like between a substrate 21 and a substrate 22. The substrate 21 and the substrate 22 are bonded together by an adhesive layer 25. The transistor 30 is a transistor that constitutes a pixel of the display unit 11, or a transistor that constitutes a drive circuit that drives the display unit 11.

[0064] The transistor 30 is provided on an insulating layer 41 on a substrate 21, and has a semiconductor layer 31, a conductive layer 32, and an insulating layer 33. A part of the conductive layer 32 functions as a gate electrode. A part of the insulating layer 33 functions as a gate insulating layer. A region of the semiconductor layer 31 that overlaps with the conductive layer 32 functions as a channel formation region. In addition, a pair of low-resistance regions 34 are provided in the semiconductor layer 31 with the channel formation region sandwiched therebetween.

[0065] It is preferable to use a metal oxide (oxide semiconductor) exhibiting semiconductor properties as the semiconductor layer 31. Although silicon, an organic semiconductor, or the like may be used for the semiconductor layer 31, by using an oxide semiconductor, a display device with high performance can be manufactured at low cost compared to the case where silicon, an organic semiconductor, or the like is used.

[0066] The pair of low-resistance regions 34 function as a source region and a drain region of the transistor 30. The low-resistance regions 34 have a lower resistance than the channel formation region. The low-resistance regions 34 can also be referred to as a region with a higher carrier concentration than the channel formation region, a region with a larger amount of oxygen vacancies, a region with a higher hydrogen concentration, or a region with a higher impurity concentration.

[0067] Moreover, an insulating layer 42 is provided to cover the transistor 30, and a wiring 13 is provided on the insulating layer 42. Fig. 1D shows an example in which the wiring 13 is electrically connected to the low-resistance region 34 of the transistor 30 through an opening provided in the insulating layer 42. Moreover, an insulating layer 43 is provided to cover the wiring 13.

[0068] 1D shows an example in which a part of the wiring 13 constitutes the connection terminal 12. In the connection terminal 12, a part of the insulating layer 43 on the wiring 13 is removed. Note that, although an example in which the wiring 13 is electrically connected to one of the source or drain of the transistor 30 is shown here, the wiring 13 may be electrically connected to the gate of the transistor 30.

[0069] Moreover, wiring 15 is provided at the end of substrate 21. Wiring 15 is provided on the same surface as semiconductor layer 31 (i.e., on insulating layer 41). Wiring 15 and semiconductor layer 31 are preferably formed by processing the same semiconductor film. Moreover, wiring 15, like low-resistance region 34 of semiconductor layer 31, preferably has a lower resistance than the channel formation region. Moreover, wiring 15 preferably has a higher resistance than wiring 13.

[0070] Further, in the vicinity of the end face (end portion) of the substrate 21, the cut surface (also referred to as end face or side surface) of the wiring 15 is exposed. FIG. 1D shows an example in which the side surface of the substrate 21, the side surface of the insulating layer 41, the side surface of the wiring 15, the side surface of the insulating layer 42, and the side surface of the insulating layer 43 are aligned. Note that, in cases where each insulating layer and wiring 15 shrink or expand in the film surface direction due to stress relaxation when the substrate 21a is cut, these side surfaces (end surfaces) may not be aligned. For example, the end surface of the wiring 15 may be located inside the end surface of the substrate 21 or may protrude outside.

[0071] In this specification, the term "edge of the substrate" refers to a region including a range of 10 mm inward from the edge of the substrate, a region including a range of up to 5 mm, or a region including a range of up to 3 mm, and a region of the substrate overlapping with the aforementioned region. Furthermore, the term "edge of the substrate" also includes the edge of the substrate.

[0072] The FPC 16 is connected to the connection terminal 12 via a connector 17. The FPC 16 has an area that overlaps with the wiring 15. The FPC 16 also overlaps with the end face of the substrate 21 and the end face of the wiring 15, and is provided so as to cover them. Therefore, even if the end face of the wiring 15 is exposed, it is protected by a part of the FPC 16, so that it is possible to suitably prevent a conductive member from contacting the multiple wirings 15 and electrically shorting them. In addition, by configuring the end face of the wiring 15 to be covered by the FPC 16, it may be possible for the FPC 16 to shield or reduce electrical noise that may be input to the wiring 15 from the outside.

[0073] Although the above describes an example in which wiring 14 is cut at the same time as dividing substrate 21, wiring 14 may be cut in a process different from dividing substrate 21. In this case, the end face of wiring 15 may be located inside the end face of substrate 21, and the surface may not be exposed.

[0074] Below, examples of the top surface shapes of the wiring 15 etc. are described. Fig. 2A is a schematic top view of the connection terminal 12 and the vicinity of the end of the substrate 21. Fig. 2A also clearly shows the substrate 21a after division and the wiring 14a after cutting.

[0075] As shown in FIG. 2A, the wiring 15 is provided so as to extend from the connection terminal 12 to the cut surface (end surface) of the substrate 21.

[0076] 2A shows an example in which the width of the wiring 15 is narrower than the width of the connection terminal 12. FIG. 2B shows an example in which the width of the wiring 15 is approximately the same as the width of the connection terminal 12. Although not shown here, the width of the wiring 15 may be wider than the width of the connection terminal 12. The wider the width of the wiring 15, the smaller the electrical resistance can be. The width of the wiring 15 can be selected according to the required value of the wiring resistance.

[0077] 2C shows an example in which the arrangement interval of the wirings 15 at the end of the substrate 21 is narrower than the arrangement interval of the connection terminals 12. This allows the width of the cut portions of the wirings 14 to be reduced in the process of dividing the substrate 21, thereby improving the process yield.

[0078] 2D shows an example in which only the wiring 14 is cut without dividing the substrate 21. For example, by cutting the wiring 14 with a laser processing machine or a cutter, or by removing a part of the wiring 14 by etching, it is possible to cut only the wiring 14 without dividing the substrate 21, and electrically separate the multiple connection terminals 12.

[0079] 2D, processing marks 14b that are generated when cutting wiring 14 are indicated by dashed lines. The form of processing marks 14b varies depending on the method of cutting wiring 14. For example, when wiring 14 is cut with a laser processing machine, a cutter, or the like, processing marks 14b correspond to scratches, irregularities, openings, and the like left in an insulating film provided on the upper or lower part of wiring 14, or in substrate 21, etc. When wiring 14 is cut by etching, openings provided in an insulating film covering wiring 14 correspond to processing marks 14b.

[0080] Here, when a plurality of display devices are manufactured using a large substrate, the step of cutting the wiring 14 preferably also serves as a step of dividing the substrate into individual display devices, thereby improving productivity.

[0081] As an example, Fig. 3 shows the substrate 21 before cutting. Here, an example is shown in which a total of six display devices, three vertically and two horizontally, are formed on one substrate 21. Also, Fig. 3 shows a number of cutting lines 20a to 20c as dashed lines.

[0082] 3 shows an example in which a strip-shaped substrate 22 is provided across a plurality of display devices arranged in the vertical direction. In FIG. 3, the connection terminals 12, a portion of the wiring 13, and the wiring 14 are provided in an area of ​​the substrate 21 that is not covered by the substrate 22.

[0083] Cutting line 20b is a cutting line that divides two display devices adjacent in the horizontal direction. Cutting line 20c is a cutting line that divides two display devices adjacent in the vertical direction. Cutting line 20a is a cutting line that is parallel to cutting line 20b and divides substrate 21 and wiring 14.

[0084] [Cross-section example 1] A more specific example of the cross-sectional configuration of the display device 10 will be described below.

[0085] [Configuration Example 1] 4A shows a cross-sectional view of the display device 10. FIG 4A shows an example of a cross-sectional view of a region including an end portion of the substrate 21, a wiring 15, a connection terminal 12, a wiring 13, and a transistor 30a provided in the display portion 11.

[0086] For ease of explanation, the display element in the display unit 11, the substrate 22, etc. are not shown.

[0087] The transistor 30a includes a semiconductor layer 31 provided over an insulating layer 41, an insulating layer 33 over the semiconductor layer 31, and a conductive layer 32 over the insulating layer 33 overlapping with a channel formation region of the semiconductor layer 31. The semiconductor layer 31 also includes a pair of low-resistance regions 34 that sandwich the channel formation region. A part of the conductive layer 32 functions as a gate electrode, and a part of the insulating layer 33 functions as a gate insulating layer.

[0088] The transistor 30a has a gate electrode above the semiconductor layer 31, and is a so-called top-gate transistor.

[0089] The insulating layer 33 is processed so that its top surface shape generally coincides with that of the conductive layer 32. The insulating layer 42 is provided to cover the transistor 30a and is provided in contact with the top surface of the low-resistance region 34 of the semiconductor layer 31. A pair of conductive layers 35 functioning as a source electrode and a drain electrode are provided on the insulating layer 41. The conductive layers 35 are electrically connected to the low-resistance region 34 through openings provided in the insulating layer 42, respectively.

[0090] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in this case, it is also called "top surface shapes roughly match."

[0091] The wiring 13 electrically connected to the connection terminal 12 is located on the same plane as a pair of conductive layers 35 electrically connected to the transistor 30a (i.e., on the insulating layer 42). Here, the wiring 13 is preferably formed by processing the same conductive film as the conductive layers 35.

[0092] An insulating layer 43 is provided to cover the insulating layer 42 and the conductive layer 35. The insulating layer 43 may function as a planarization layer. A conductive layer 38 is provided over the insulating layer 43. The conductive layer 38 can be used as a pixel electrode, a wiring, or the like.

[0093] The connection terminal 12 has a laminated structure in which a conductive layer 32p, a conductive layer 35p, and a conductive layer 38p are laminated.

[0094] The conductive layer 32p is located on the same plane as the conductive layer 32. In this case, the conductive layer 32p is preferably formed by processing the same conductive film as the conductive layer 32.

[0095] The conductive layer 35p constitutes a part of the wiring 13. The conductive layer 35p is electrically connected to the conductive layer 32p through an opening provided in the insulating layer 42. The conductive layer 35p is located on the same plane as the conductive layer 35. In this case, the conductive layer 35p is preferably formed by processing the same conductive film as the conductive layer 35.

[0096] The conductive layer 38p is provided on the insulating layer 43, and is electrically connected to the conductive layer 35p through an opening provided in the insulating layer 43. The conductive layer 38p is located on the same plane as the conductive layer 38. In this case, the conductive layer 38p is preferably formed by processing the same conductive film as the conductive layer 38.

[0097] Here, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that maintains its conductivity even if oxidized for the surface of the connection terminal 12. In particular, it is preferable to use a conductive oxide or a conductive nitride as the conductive layer located on the surface side of the connection terminal 12.

[0098] In the configuration of the connection terminal 12 shown in Fig. 4A, the exposed surface of the conductive layer 38p corresponds to the portion that is connected to the FPC 16, etc. Therefore, it is preferable to use a conductive oxide material or the like for at least the upper portion of the conductive layer 38p. For example, it is preferable to apply a laminated structure of a conductive film containing a metal or alloy and a conductive film containing a conductive oxide to the conductive layer 38p, since this can reduce the electrical resistance.

[0099] The configuration of the connection terminal 12 is not limited to this, and it is sufficient that the connection terminal 12 has at least one of the conductive layer 32p, the conductive layer 35p, and the conductive layer 38p. In particular, it is preferable that the connection terminal 12 includes the conductive layer 35p.

[0100] Wiring 15 is provided on the end of substrate 21. Fig. 4A shows an example in which substrate 21, insulating layer 41, wiring 15, insulating layer 42, and insulating layer 43 are laminated at the end of substrate 21, and the end faces (cut surfaces) of these layers are approximately aligned.

[0101] The wiring 15 is located on the same plane as the semiconductor layer 31 of the transistor 30a (here, on the insulating layer 41). In particular, the wiring 15 is preferably formed by processing the same film as the semiconductor layer 31. In addition, the wiring 15 preferably has low resistance like the low-resistance region 34 of the semiconductor layer 31.

[0102] 4A, connection portion 18 between conductive layer 35p and wiring 15 is indicated by a dashed line. Here, at connection portion 18, conductive layer 35p and wiring 15 are electrically connected through an opening provided in insulating layer 42.

[0103] [Configuration Example 2] FIG. 4B differs from FIG. 4A mainly in that the configuration of the transistors and part of the configuration of the connection terminal 12 are different.

[0104] 4B has a conductive layer 36 overlapping a channel formation region of the semiconductor layer 31 between the substrate 21 and the insulating layer 41. In the transistor 30b, the conductive layer 36 functions as a first gate electrode, and the conductive layer 32 functions as a second gate electrode. At this time, a part of the insulating layer 41 functions as a first gate insulating layer, and a part of the insulating layer 33 functions as a second gate insulating layer.

[0105] Different potentials or signals may be applied to the conductive layer 32 and the conductive layer 36. Alternatively, the conductive layer 32 and the conductive layer 36 may be electrically connected to each other and the same potential or signal may be applied to each other. Alternatively, the conductive layer 36 and one of the pair of conductive layers 35 may be electrically connected to each other.

[0106] The connection terminal 12 has a conductive layer 36p. The conductive layer 36p is located on the same plane as the conductive layer 36. In this case, the conductive layer 36p is preferably formed by processing the same conductive film as the conductive layer 36.

[0107] The conductive layer 36p and the conductive layer 32p are electrically connected via openings provided in parts of the insulating layer 41 and the insulating layer 33.

[0108] [Configuration Example 3] FIG. 5A differs from FIG. 4A mainly in that some of the transistor configurations are different.

[0109] 5A, an insulating layer 33 is provided to cover the upper surface and side surfaces of the semiconductor layer 31 (i.e., the upper surface and side surfaces of the low-resistance region 34). Similarly, the upper surface and side surfaces of the wiring 15 are also covered with the insulating layer 33.

[0110] [Configuration Example 4] FIG. 5B differs from FIG. 4B mainly in that some of the transistor configurations are different.

[0111] 5B, an insulating layer 33 is provided to cover the upper surface and side surfaces of the semiconductor layer 31 (i.e., the upper surface and side surfaces of the low-resistance region 34). Similarly, the upper surface and side surfaces of the wiring 15 are also covered with the insulating layer 33.

[0112] [Configuration Example 5] FIG. 6A shows an example in which a transistor 40 having a different configuration from the above is used.

[0113] The transistor 40 has a conductive layer 32 provided on a substrate 21, an insulating layer 33 covering the conductive layer 32, a semiconductor layer 31 located on the insulating layer 33 and having an area overlapping with the conductive layer 32, and a pair of conductive layers 35 in contact with an upper surface of the semiconductor layer 31.

[0114] The transistor 40 is a so-called bottom-gate transistor having a gate electrode below the semiconductor layer 31 .

[0115] A region of the semiconductor layer 31 that overlaps with the conductive layer 32 and is not in contact with the conductive layer 35 functions as a channel formation region. A region of the semiconductor layer 31 in contact with the conductive layer 35 functions as a low-resistance region 34.

[0116] Further, an insulating layer 45 is provided to cover the transistor 40, and an insulating layer 43 and a conductive layer 38 are provided over the insulating layer 45. A part of the insulating layer 45 is provided in contact with an upper surface of a channel formation region of the semiconductor layer 31.

[0117] The connection terminal 12 has a conductive layer 32p, a conductive layer 35p, and a conductive layer 38p. The conductive layer 32p and the conductive layer 35p are electrically connected to each other via an opening provided in the insulating layer 33. The conductive layer 35p and the conductive layer 38p are electrically connected to each other via an opening provided in the insulating layer 45 and the insulating layer 43.

[0118] The wiring 15 is provided on the insulating layer 33. Furthermore, at the connection portion 18, the conductive layer 35p and the wiring 15 come into contact with each other and are electrically connected to each other.

[0119] Here, if the insulating layer 45 is configured to be in contact with the upper surface of the wiring 15, a stacked structure similar to that of the channel formation region of the transistor 40 is realized, which may cause the wiring 15 to have high resistance. Therefore, as shown in Fig. 6A, it is preferable that the insulating layer 45 is processed so as not to be in contact with the upper surface of the wiring 15. Fig. 6A shows an example in which the insulating layer 43 is provided in contact with the upper surface of the wiring 15.

[0120] [Configuration Example 6] FIG. 6B differs from FIG. 6A mainly in that an insulating layer 46 is provided instead of the insulating layer 43, and that a conductive layer 37 is provided.

[0121] The insulating layer 46 functions as a barrier film that prevents diffusion of water, hydrogen, and the like from the outside. The insulating layer 46 may also have a function of releasing oxygen contained in the insulating layer 45 to the outside.

[0122] The transistor 40a has a conductive layer 37 functioning as a second gate electrode. The conductive layer 37 has a region overlapping with a channel formation region of the semiconductor layer 31 with the insulating layers 45 and 46 interposed therebetween. The conductive layer 37 is preferably formed by processing the same conductive film as the conductive layer 38.

[0123] The connection terminal 12 includes a conductive layer 32p, a conductive layer 35p, and a conductive layer 38p. The conductive layers 35p and 38p are electrically connected to each other via openings provided in the insulating layers 45 and .

[0124] The insulating layer 45 is processed so as not to come into contact with the upper surface of the wiring 15. Moreover, the insulating layer 46 extends beyond the end of the insulating layer 45 and is provided in contact with the upper surface of the wiring 15.

[0125] [Variations] In the following, an example will be described in which the semiconductor layer 31 of the transistor and the wiring 15 are formed by processing different films.

[0126] [Variation 1] FIG. 7A differs from the configuration shown in FIG. 6A mainly in that a conductive layer 39 and an insulating layer 46 are included.

[0127] 7A includes a conductive layer 39 functioning as a second gate electrode. The conductive layer 39 is provided over an insulating layer 45 and has a portion that overlaps with a channel formation region of the semiconductor layer 31 with the insulating layer 45 interposed therebetween. An insulating layer 46 is provided in contact with an upper surface and a side surface of the conductive layer 39.

[0128] It is preferable that the conductive layer 39 contains the same material as the semiconductor layer 31. In particular, it is preferable that the conductive layer 39 and the semiconductor layer 31 are composed of a metal oxide containing one or more of the same metal elements. In particular, it is preferable that the conductive layer 39 and the semiconductor layer 31 have approximately the same composition (content) of the metal elements.

[0129] The connection terminal 12 includes a conductive layer 32p, a conductive layer 35p, and a conductive layer 38p. The conductive layer 35p and the conductive layer 38p are electrically connected to each other via openings provided in the insulating layer 45, the insulating layer 46, and the insulating layer 43.

[0130] Wiring 15a is provided at the end of substrate 21. Wiring 15a is provided on insulating layer 45. Wiring 15a is preferably formed by processing the same conductive film as conductive layer 39. Insulating layer 46 is provided in contact with the upper surface and side surfaces of wiring 15a.

[0131] At the connection portion 18, the conductive layer 35p and the wiring 15a are electrically connected through an opening provided in the insulating layer 45.

[0132] [Modification 2] FIG. 7B shows an example in which the wiring 15a extends to the connection terminal 12. In FIG.

[0133] The connection terminal 12 includes a conductive layer 32p, a conductive layer 35p, a part of the wiring 15a, and a conductive layer 38p. The conductive layer 35p and the part of the wiring 15a are electrically connected through an opening provided in the insulating layer 45. The wiring 15a and the conductive layer 38p are electrically connected through openings provided in the insulating layer 46 and the insulating layer 43.

[0134] With this configuration, the connection terminal 12 can also function as the connection portion 18 .

[0135] In each of the configuration examples and modified examples illustrated here, the connection terminals and the wirings electrically connected to the connection terminals can be formed using a conductive film or a semiconductor film that constitutes the transistors and pixels of the display portion, etc. Therefore, the connection terminals and the wirings can be formed without increasing the number of steps, and therefore a display device with high reliability can be realized at low cost without increasing the manufacturing cost.

[0136] [Display device configuration example 2] An example of the configuration of a flexible and bendable display device will be described below.

[0137] [Configuration Example 1] 8A is a schematic top view of the display device 10a. The display device 10a has a flexible substrate 51. The substrate 51 is provided with a display unit 11, a pair of circuit units 52, a circuit unit 53, a plurality of wirings 13, a plurality of connection terminals 12, and a plurality of wirings 15.

[0138] The circuit unit 52 and the circuit unit 53 have a function of driving the display unit 11. Two circuit units 52 are provided on either side of the display unit 11. The circuit unit 53 is provided between the display unit 11 and the wiring 13. The circuit unit 52 has a function as, for example, a gate driver, and the circuit unit 53 has a function as, for example, a source driver or a part thereof. For example, the circuit unit 53 may include a buffer circuit or a demultiplexer circuit.

[0139] The above-mentioned various display elements, such as a liquid crystal element or a light-emitting element, can be used as the display element provided in the display unit 11. In particular, it is preferable to use an organic EL element as the display element.

[0140] The substrate 51 has a top surface shape in which the portion on which the wiring 13, the connection terminal 12, and the wiring 15 are provided protrudes more than other portions. In other words, the width of the portion of the substrate 51 on which the wiring 13, the connection terminal 12, and the wiring 15 are provided is smaller than the width of the portion on which the display unit 11 is provided.

[0141] Furthermore, the protruding portion of the substrate 51 has a region (curved portion 50a) that can be curved in a region overlapping with the wiring 13. Furthermore, the substrate 51 has a pair of regions (curved portions 50b) that can be curved in a region where the display unit 11 is provided. As shown in Fig. 8A, by having a portion of the substrate 51 have a protruding shape, the curving direction of the curving portion 50a and the curving direction of the curving portion 50b can be set to intersect.

[0142] 8B and 8C are perspective views of the display device 10a when the substrate 51 is bent to the side opposite the display surface side at the bendable portion 50a and the bendable portion 50b. Fig. 8B is a perspective view including the display surface side, and Fig. 8C is a perspective view including the side opposite the display surface side. Fig. 8C also clearly shows the FPC 16 connected to the connection terminal 12.

[0143] 8B, by curving both sides of the display unit 11, when the display device 10a is incorporated into an electronic device, curved display units can be provided on both sides of the electronic device, thereby realizing an electronic device with high functionality.

[0144] 8B and 8C, the curved portion 50a allows a portion of the substrate 51 to be folded back to the opposite side to the display surface side. Specifically, the protruding portion of the substrate 51 can be folded back so that the wiring 13 faces outward. This allows the connection terminals 12 and the wiring 15 to be disposed on the opposite side to the display surface side, and further allows the FPC 16 to be disposed on the opposite side to the display surface side. This makes it possible to reduce the area of ​​the non-display portion when the display device 10a is incorporated into an electronic device.

[0145] 8C, a part of FPC 16 can be configured to cover the end of substrate 51 on the side opposite to the display surface. This makes it possible to prevent wiring 15 from coming into contact with components such as the housing of the electronic device even if a part of wiring 15 (such as an end face or a cut surface) is exposed, thereby realizing a highly reliable electronic device.

[0146] 8C shows an example in which an IC 19 is mounted on the FPC 16. The IC 19 is formed on, for example, a single crystal semiconductor substrate, and has a semiconductor chip including a circuit that functions as a source driver.

[0147] [Configuration Example 2] 9A, 9B, and 9C show a top view and a perspective view of a display device 10b having a partly different configuration from that described above.

[0148] The display device 10b has a connection terminal 12a to which the FPC 16 is connected and a connection terminal 12b to which the IC 19 is connected, at the protruding portion of the substrate 51. In addition, a plurality of wirings 15 are electrically connected to the connection terminal 12a or the connection terminal 12b, respectively. This allows the IC 19 to be mounted on the substrate 51, as shown in FIG. 9C.

[0149] Furthermore, the substrate 51 is provided with a notch 54. The notch 54 is a portion where, for example, a camera lens, various sensors such as an optical sensor, a lighting device, or a design of the electronic device can be arranged. By cutting out a part of the display unit 11, an electronic device with a more stylish design can be realized. This also makes it possible to increase the screen occupancy rate relative to the surface of the housing of the electronic device.

[0150] [Example of wiring configuration] In the above-mentioned display device 10a and display device 10b, the smaller the radius of curvature of the curved portion 50a, the thinner the thickness of the display device 10a or display device 10b including the protruding portion can be, so that the degree of freedom in designing electronic devices can be increased. On the other hand, by making the radius of curvature of the curved portion 50a smaller, there is a risk that the wiring 13 located at the curved portion 50a may be broken. Below, a configuration example of the wiring 13 that can be suitably used for the curved portion 50a will be described.

[0151] 10A to 10L show the top shapes of two adjacent wirings 13, including the portions located at the curved portion 50a.

[0152] 10A has a shape in which curved portion 50a is thinner (narrower) than other portions, which makes it less likely for cracks to occur when wiring 13 is curved, and allows for increased strength.

[0153] 10B, 10C, and 10D, the wiring 13 has an opening 13a extending over the range of the curved portion 50a in the extension direction of the wiring 13. It can also be said that the wiring 13 has a shape branched into a plurality of thin portions. With this configuration, even if a portion of the wiring 13 is broken, the other portions can maintain electrical continuity.

[0154] Furthermore, opening 13a is a highly adhesive portion where an insulating layer (e.g., insulating layer 42) located under wiring 13 and an insulating layer (e.g., insulating layer 43) located over wiring 13 come into contact with each other. Therefore, a thin branched portion of wiring 13 located at curved portion 50a can be sandwiched between the highly adhesive portions, and peeling of wiring 13 at curved portion 50a can be suppressed.

[0155] Fig. 10B shows an example in which one opening 13a is provided across the curved portion 50a, and the wiring 13 branches into two. Fig. 10C shows an example in which two openings 13a are provided across the curved portion 50a, and the wiring 13 branches into three. Fig. 10C shows an example in which three openings 13a are provided across the curved portion 50a, and the wiring 13 branches into four. However, this is not limited to this, and four or more openings 13a may be provided.

[0156] 10D, the portion of wiring 13 located at curved portion 50a has a shape that bulges in the width direction. This allows the width of the multiple branched portions to be increased, thereby reducing the wiring resistance.

[0157] 10E and 10F show an example in which a plurality of openings 13b are provided in the wiring 13. The length of the openings 13b in the extension direction of the wiring 13 is shorter than the length of the curved portion 50a. This makes it possible to reduce the wiring resistance while increasing the strength and adhesion of the wiring 13.

[0158] Fig. 10E shows an example in which the openings 13b are arranged alternately left and right, while Fig. 10F shows an example in which the openings 13b are arranged in an aligned manner, so that the wiring 13 has a lattice shape.

[0159] 10G and 10H show an example in which openings 13a extending over the curved portion 50a and openings 13b shorter than the length of the curved portion 50a are mixed together. With such a configuration, it is possible to further improve the adhesion.

[0160] Fig. 10G shows an example in which openings 13b of the same shape are arranged across curved portion 50a. However, this is not limited thereto, and openings 13b of different shapes may be arranged in the extension direction of wiring 13. Fig. 10H shows, as an example, an example in which the length of openings 13b becomes shorter the closer to the center of curved portion 50a.

[0161] 10I and 10J show examples of wiring 13 having a shape in which thin and thick parts are alternately repeated. By using such a shape, the thin parts of wiring 13 can be made to have high adhesion, so that peeling of the film of wiring 13 can be suppressed. Furthermore, by providing a plurality of such thin parts, it is possible to increase not only the strength of wiring 13 against bending in the extension direction but also the strength against twisting.

[0162] Fig. 10I shows a case where two adjacent wires 13 have the same shape. Fig. 10J shows a case where the shapes of the two wires 13 are different so that the thick and thin parts of the wires 13 are arranged alternately. By using the configuration shown in Fig. 10J, the distance between the two adjacent wires can be narrowed, and the wiring density can be increased.

[0163] 10K and 10L show an example in which the wiring 13 has a plurality of intersections 13c. In addition, substantially diamond-shaped openings 13d are provided so as to sandwich one of the intersections. With this configuration, the wiring 13 can have high strength against bending and twisting, high adhesion, and low wiring resistance.

[0164] Fig. 10K shows an example of a shape in which the intersections 13c are arranged in a line in the extension direction of the wiring 13. Fig. 10L shows an example of a shape in which a plurality of intersections 13c (here, three lines) are arranged in the extension direction of the wiring 13.

[0165] 10, the outline of the wiring 13 and the outline of each opening are preferably curved or rounded, such as in an arc, without corners (either acute or obtuse angles). If the wiring 13 has corners, the corners may become the starting points of cracks when an external force is applied, and in the worst case, the wiring 13 may break. Therefore, by making the outline of the wiring 13 and the outline of the openings round, the wiring 13 is less susceptible to cracks.

[0166] The above is a description of an example of the wiring configuration.

[0167] [Cross-section example 2] A more specific example of the cross-sectional configuration of the display device will be described below.

[0168] [Configuration Example 1] A schematic cross-sectional view of the display device 10a is shown in Fig. 11. Fig. 11 corresponds to a cross section of the display device 10a shown in Fig. 8A taken along dashed line ST.

[0169] 11 shows a cross section including the display unit 11, the circuit unit 52, the curved portion 50a, and the connection terminal 12. The display unit 11 is provided with a transistor 750 and a capacitance element 790. The circuit unit 52 is provided with a transistor 752. The connection terminal 12 is connected to an FPC 716 via a connector 780.

[0170] The transistor 750 and the transistor 752 are transistors in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Note that the present invention is not limited to this, and a transistor in which silicon (amorphous silicon, polycrystalline silicon, or single crystal silicon) or an organic semiconductor is used for the semiconductor layer can also be used.

[0171] The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be significantly reduced. Therefore, a pixel including such a transistor can hold an electric signal such as an image signal for a long time and can set a long interval for writing an image signal or the like. Thus, the frequency of a refresh operation can be reduced, leading to reduced power consumption.

[0172] In addition, the transistor used in this embodiment mode can achieve a relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor capable of high speed driving in a display device, a switching transistor of a pixel and a driver transistor used in a circuit portion can be formed over the same substrate. That is, a configuration without using a driver circuit formed of a silicon wafer or the like is also possible, and the number of components of the display device can be reduced. In addition, by using a transistor capable of high speed driving in a pixel, a high-quality image can be provided.

[0173] The capacitor 790 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has a low resistance like the source and drain regions of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. A wiring obtained by processing the same film as the source and drain electrodes of the transistor 750 is connected to the upper electrode.

[0174] An insulating layer 770 functioning as a planarization film is provided over the transistor 750, the transistor 752, and the capacitor 790.

[0175] The transistor 750 in the display portion 11 and the transistor 752 in the circuit portion 52 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the circuit portion 53 is similar to the circuit portion 52.

[0176] Note that the structures of the transistor 750 and the transistor 752 can be those of Cross-Sectional Structure Example 1.

[0177] Regarding the configurations of the wiring 13, the connection terminal 12, and the wiring 15, the above-mentioned cross-sectional configuration example 1 and the modified examples can be used.

[0178] The display device 10a includes a substrate 51, which functions as a support substrate, and a substrate 740. As the substrate 51 and the substrate 740, for example, a glass substrate or a flexible substrate such as a plastic substrate can be used.

[0179] The transistor 750, the transistor 752, the capacitor 790, and the like are provided over an insulating layer 744. The substrate 51 and the insulating layer 744 are attached to each other with an adhesive layer 742.

[0180] The display device 10a also includes a light emitting element 782, a colored layer 736, a light blocking layer 738, and the like.

[0181] The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive layer 788. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is provided over the insulating layer 770 and functions as a pixel electrode. In addition, an insulating layer 730 is provided to cover an end portion of the conductive layer 772, and an EL layer 786 and a conductive layer 788 are stacked over the insulating layer 730 and the conductive layer 772.

[0182] The conductive layer 772 can be formed using a material that is reflective to visible light. For example, a material containing aluminum, silver, or the like can be used. The conductive layer 788 can be formed using a material that transmits visible light. For example, an oxide material containing indium, zinc, tin, or the like can be used. Therefore, the light-emitting element 782 is a top-emission light-emitting element that emits light to the side opposite to the surface where the light is formed (the side of the substrate 740).

[0183] The EL layer 786 may include organic compounds or inorganic compounds such as quantum dots, etc. The EL layer 786 includes a light-emitting material that emits light when a current is passed through it.

[0184] Examples of the luminescent material include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, inorganic compounds (quantum dot materials, etc.), etc. Examples of the material that can be used for the quantum dot include colloidal quantum dot materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0185] The light-shielding layer 738 and the colored layer 736 are provided on one surface of the insulating layer 746. The colored layer 736 is provided at a position overlapping with the light-emitting element 782. The light-shielding layer 738 is provided in an area of ​​the display unit 11 that does not overlap with the light-emitting element 782. The light-shielding layer 738 may also be provided overlapping with the circuit unit 52, etc.

[0186] The substrate 740 is bonded to the other surface of the insulating layer 746 by an adhesive layer 747. The substrate 740 and the substrate 51 are bonded to each other by a sealing layer 732.

[0187] Here, a light-emitting material that emits white light is used as the EL layer 786 of the light-emitting element 782. The white light emitted by the light-emitting element 782 is colored by the coloring layer 736 and emitted to the outside. The EL layer 786 is provided across pixels that exhibit different colors. By arranging pixels, each of which is provided with a coloring layer 736 that transmits any of red (R), green (G), or blue (B), in a matrix form in the display unit 11, the display device 10a can perform full-color display.

[0188] A conductive film having transparency and reflectivity may be used as the conductive layer 788. In this case, a microresonator (microcavity) structure may be realized between the conductive layer 772 and the conductive layer 788, and a configuration may be adopted in which light of a specific wavelength is intensified and emitted. In this case, an optical adjustment layer for adjusting the optical distance may be disposed between the conductive layer 772 and the conductive layer 788, and the thickness of the optical adjustment layer may be made different between pixels of different colors, thereby increasing the color purity of the light emitted from each pixel.

[0189] When the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, when the EL layer 786 is formed by coloring, the colored layer 736 and the optical adjustment layer described above may not be provided.

[0190] Here, an inorganic insulating film functioning as a barrier film with low moisture permeability is preferably used for each of the insulating layers 744 and 746. By sandwiching the light-emitting element 782, the transistor 750, and the like between the insulating layers 744 and 746, deterioration of the light-emitting element 782, the transistor 750, and the like can be suppressed, and a highly reliable display device can be realized.

[0191] [Configuration Example 2] Fig. 12 shows a cross-sectional view of a display device 10a having a configuration that is partially different from that of Fig. 11. Fig. 12 also clearly shows that a portion of the display device 10a is curved at a curved portion 50a and folded back to the side opposite the display surface side.

[0192] The display device 10a shown in Fig. 12 includes a resin layer 743 between the adhesive layer 742 and the insulating layer 744 shown in Fig. 11. Also, a protective layer 749 is provided instead of the substrate 740.

[0193] The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The insulating layer 744 is a layer containing an inorganic insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the substrate 51 are attached to each other by an adhesive layer 742. The resin layer 743 is preferably thinner than the substrate 51.

[0194] The protective layer 749 is attached to the sealing layer 732. As the protective layer 749, a glass substrate, a resin film, or the like can be used. As the protective layer 749, an optical member such as a polarizing plate (including a circular polarizing plate) or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be applied. Furthermore, the protective layer 749 may include a member that constitutes a part of the housing of the electronic device (for example, a part that becomes a screen).

[0195] In addition, the EL layer 786 of the light-emitting element 782 is provided in an island shape over the insulating layer 730 and the conductive layer 772. By forming the EL layer 786 so that each subpixel has a different light emission color, color display can be realized without using the coloring layer 736.

[0196] A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 has a layered structure in which an insulating layer 741a, an insulating layer 741b, and an insulating layer 741c are layered in this order from the conductive layer 788 side. In this case, it is preferable to use an inorganic insulating film having a high barrier property against impurities such as water for the insulating layer 741a and the insulating layer 741c, and an organic insulating film functioning as a planarizing film for the insulating layer 741b. It is also preferable that the protective layer 741 is provided so as to extend to the circuit portion 52 and the like.

[0197] In addition, it is preferable that the organic insulating film covering the transistor 750, the transistor 752, and the like is formed in an island shape inside the sealing layer 732. In other words, it is preferable that the end of the organic insulating film is located inside the sealing layer 732 or in a region overlapping with the end of the sealing layer 732. FIG. 12 shows an example in which the insulating layer 770, the insulating layer 730, and the insulating layer 741b are processed into an island shape. For example, in a portion overlapping with the sealing layer 732, the insulating layer 741c and the insulating layer 741a are provided in contact with each other. In this way, by configuring the surface of the organic insulating film covering the transistor 750 and the transistor 752 not to be exposed outside the sealing layer 732, it is possible to suitably prevent water or hydrogen from diffusing from the outside to the transistor 750 and the transistor 752 through the organic insulating film. This suppresses fluctuations in the electrical characteristics of the transistors, and realizes a display device with extremely high reliability.

[0198] 12, curved portion 50a has a portion where inorganic insulating films such as insulating layer 744 are not provided, in addition to substrate 51 and adhesive layer 742. Curved portion 50a has a configuration in which insulating layer 770 containing an organic material covers wiring 13 to prevent wiring 13 from being exposed. In the configuration shown in FIG. 12, curved portion 50a has a layered structure in which resin layer 743, wiring 13, and insulating layer 770 are layered.

[0199] By providing as little inorganic insulating film as possible in the curved portion 50a and by laminating only a conductive layer containing a metal or alloy and a layer containing an organic material, it is possible to prevent cracks from occurring when the display device 10a is bent. Also, by not providing a substrate 51 in the curved portion 50a, a part of the display device 10a can be bent with an extremely small radius of curvature.

[0200] In addition, in the region overlapping with the connection terminal 12, the support 720 is attached to the resin layer 743 via an adhesive layer 748. The support 720 may be made of a material having higher rigidity than the substrate 51, etc. Alternatively, the support 720 may be a part of the housing of the electronic device, or a part of a member disposed inside the electronic device.

[0201] 12, a conductive layer 761 is provided over the protective layer 741. The conductive layer 761 can be used as a wiring or an electrode.

[0202] In addition, when a touch sensor is provided on the display device 10a, the conductive layer 761 can function as an electrostatic shielding film for preventing electrical noise generated when driving a pixel from being transmitted to the touch sensor. In this case, a predetermined constant potential may be applied to the conductive layer 761.

[0203] Alternatively, the conductive layer 761 can be used as, for example, an electrode of a touch sensor. This allows the display device 10a to function as a touch panel. For example, the conductive layer 761 can be used as an electrode or wiring of a capacitive touch sensor. In this case, the conductive layer 761 can be used as a wiring or electrode to which a detection circuit is connected, or a wiring or electrode to which a sensor signal is input. In this way, by forming a touch sensor on the light-emitting element 782, the number of components can be reduced, and the manufacturing cost of electronic devices and the like can be reduced.

[0204] The conductive layer 761 is preferably provided in a portion that does not overlap with the light-emitting element 782. For example, the conductive layer 761 can be provided in a portion that overlaps with the insulating layer 730. As a result, there is no need to use a transparent conductive film with relatively low conductivity as the conductive layer 761, and a metal or alloy with high conductivity can be used, which can improve the sensitivity of the sensor.

[0205] Note that the type of the touch sensor that can be configured using the conductive layer 761 is not limited to the capacitance type, and various types such as a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure sensitive type can be used. Alternatively, two or more of these types may be used in combination.

[0206] [Configuration Example 3] 13 is a schematic cross-sectional view of a display device 10b in which a liquid crystal element is used as the display element. In FIG. 13, a cross-sectional view of a region including a circuit section 52, a display section 11, and a connection terminal 12 is shown.

[0207] 13 includes a transistor 721, a transistor 722, a liquid crystal element 710, and the like between a substrate 701 and a substrate 705. The substrate 701 and the substrate 705 are attached to each other with a sealing layer 732.

[0208] Here, bottom-gate transistors are used as the transistor 721 and the transistor 722. The above-described cross-sectional structure example 1 can be used for the transistor, the wiring 13, the connection terminal 12, the wiring 15, and the like.

[0209] The liquid crystal element 710 includes a conductive layer 711, a liquid crystal 712, and a conductive layer 713. The conductive layer 713 is provided over a substrate 701. One or more insulating layers are provided over the conductive layer 713, and the conductive layer 711 is provided over the insulating layer. The liquid crystal 712 is located between the conductive layer 711 and the substrate 705. The conductive layer 713 is electrically connected to a wiring 723 and functions as a common electrode. The conductive layer 711 is electrically connected to a transistor 721 and functions as a pixel electrode. A common potential is applied to the wiring 723.

[0210] 13 is a liquid crystal element to which a lateral electric field mode (for example, FFS (Fringe Field Switching) mode) is applied. A conductive layer 711 has a top surface shape having a comb shape or slits. In the liquid crystal element 710, the alignment state of liquid crystal 712 is controlled by an electric field generated between the conductive layer 711 and the conductive layer 713.

[0211] In addition, a capacitor 790 functioning as a storage capacitor is formed by a stacked structure of the conductive layers 711, 713, and one or more insulating layers sandwiched between the conductive layers 711 and 713. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0212] A material that transmits visible light or a material that reflects visible light can be used for the conductive layer 711 and the conductive layer 713. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0213] When a reflective material is used for either or both of the conductive layer 711 and the conductive layer 713, the display device 10b becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for both the conductive layer 711 and the conductive layer 713, the display device 10b becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element.

[0214] 13 shows an example of a transmissive liquid crystal display device. A polarizing plate 755 and a light source 757 are provided on the outer side of a substrate 701, and a polarizing plate 756 is provided on the outer side of a substrate 705. The light source 757 functions as a backlight.

[0215] A light-shielding layer 738 and a colored layer 736 are provided on the surface of the substrate 705 facing the substrate 701. An insulating layer 734 functioning as a planarizing layer is provided to cover the light-shielding layer 738 and the colored layer 736. A spacer 727 is provided on the surface of the insulating layer 734 facing the substrate 701.

[0216] The liquid crystal 712 is located between an alignment film 725 that covers the conductive layer 711 and an alignment film 726 that covers the insulating layer 734. Note that the alignment films 725 and 726 do not have to be provided if they are not necessary.

[0217] 13, optical members (optical films) such as a retardation film and an anti-reflection film, a protective film, an antifouling film, etc. may be appropriately provided outside the substrate 705. Examples of anti-reflection films include an AG (Anti Glare) film and an AR (Anti Reflection) film.

[0218] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal 712. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0219] In addition, the liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0220] Also, a scattering type liquid crystal using a polymer dispersed type liquid crystal, a polymer network type liquid crystal, or the like can be used as the liquid crystal 712. In this case, a configuration for performing black and white display without providing the colored layer 736, or a configuration for performing color display using the colored layer 736 can be used.

[0221] Furthermore, as a method for driving the liquid crystal element, a time-division display method (also called a field sequential driving method) that performs color display based on a time-division additive color mixing method may be applied. In this case, the coloring layer 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0222] The display device 10b shown in FIG. 13 has a structure in which an organic insulating film functioning as a planarizing layer is not provided on the formation surface side of the conductive layer 711 functioning as a pixel electrode and the conductive layer 713 functioning as a common electrode. In addition, bottom-gate transistors that can be manufactured in a relatively short process are used as the transistors 721 and the like included in the display device 10b. As described above, the wiring 13, the connection terminal 12, the wiring 15, and the like can be manufactured in a common process with the manufacturing process of the transistors, the liquid crystal element, and the like without adding any special process. With such a structure, the manufacturing cost can be reduced and the manufacturing yield can be increased, making it possible to provide a highly reliable display device at a low cost.

[0223] This completes the description of Cross-Sectional Configuration Example 2.

[0224] [About the components] Components such as transistors that can be applied to a display device will be described below.

[0225] 〔substrate〕 There are no significant limitations on the material of the substrate, but it is necessary that the substrate has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate. Furthermore, any of these substrates on which a semiconductor element is provided may be used as the substrate.

[0226] A flexible substrate may be used as the substrate, and the display device may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the display device. The peeling layer can be used to separate the display device from the substrate after a part or whole of the display device is completed thereon, and to transfer the display device to another substrate. In this case, the display device can be transferred to a substrate having poor heat resistance or a flexible substrate.

[0227] [Transistor] The transistor includes a conductive layer functioning as a gate electrode, a semiconductor layer, a conductive layer functioning as a source electrode, a conductive layer functioning as a drain electrode, and an insulating layer functioning as a gate insulating layer.

[0228] Note that the structure of a transistor included in a display device of one embodiment of the present invention is not particularly limited. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor may be used. In addition, the transistor may have either a top-gate type or a bottom-gate type structure. Alternatively, gate electrodes may be provided above and below a channel.

[0229] The crystallinity of a semiconductor material used in a transistor is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of transistor characteristics.

[0230] In particular, a transistor using a metal oxide film for a semiconductor layer in which a channel is formed will be described below.

[0231] As a semiconductor material for a transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A representative example is a metal oxide containing indium, such as CAC-OS described later.

[0232] A transistor using a metal oxide which has a wider band gap and a lower carrier concentration than silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time owing to its low off-state current.

[0233] The semiconductor layer may be, for example, a film represented by an In-M-Zn system oxide containing indium, zinc, and M (M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0234] When the metal oxide constituting the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferable. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0235] The semiconductor layer is a metal oxide film with a low carrier concentration. For example, the semiconductor layer has a carrier concentration of 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm -3 A metal oxide having a carrier concentration of 1000 or more can be used. Such a metal oxide is called a high-purity intrinsic or substantially high-purity intrinsic metal oxide. The oxide semiconductor has a low density of defect states and is therefore a metal oxide having stable characteristics.

[0236] Note that the present invention is not limited to these, and an oxide semiconductor having an appropriate composition may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of a transistor that is required. In order to obtain the semiconductor characteristics of a transistor that is required, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, and the like of the semiconductor layer to be appropriate.

[0237] When silicon or carbon, which is one of the group 14 elements, is contained in the metal oxide constituting the semiconductor layer, oxygen vacancies increase in the semiconductor layer, causing it to become n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0238] In addition, when an alkali metal or an alkaline earth metal is bonded to a metal oxide, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer obtained by secondary ion mass spectrometry is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0239] In addition, if the metal oxide that constitutes the semiconductor layer contains nitrogen, electrons that act as carriers are generated, the carrier concentration increases, and the transistor tends to become n-type. As a result, transistors that use metal oxides that contain nitrogen tend to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer obtained by secondary ion mass spectrometry is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0240] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, which include c-axis-aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0241] Note that the above-described non-single-crystal oxide semiconductor can be preferably used for a semiconductor layer of a transistor disclosed in one embodiment of the present invention. As the non-single-crystal oxide semiconductor, an nc-OS or a CAAC-OS can be preferably used.

[0242] The semiconductor layer may be a mixed film having two or more of a CAAC-OS region, a polycrystalline oxide semiconductor region, an nc-OS region, a pseudo-amorphous oxide semiconductor region, and an amorphous oxide semiconductor region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0243] In addition, a semiconductor layer of the transistor disclosed in one embodiment of the present invention is preferably made of cloud-aligned composite oxide semiconductor (CAC-OS), which can impart excellent electrical characteristics or high reliability to the transistor.

[0244] In the following, we explain about CAAC (c-axis aligned crystal). CAAC is an example of a crystal structure.

[0245] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0246] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0247] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that constitute the unit cell. In particular, in crystals having a layered structure, it is common to take two axes parallel to the plane direction of the layer as the a-axis and b-axis, and an axis intersecting the layer as the c-axis. A representative example of such a crystal having a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, a crystal of InGaZnO4 having a layered YbFe2O4 type crystal structure can be classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0248] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly identified in an image observed by TEM. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, for example, in an nc-OS film, crystal grain boundaries may not be clearly identified.

[0249] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus using X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane analysis. When the nc-OS film is subjected to electron beam diffraction (also called selected area electron beam diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal parts, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to or smaller than the size of the crystal part, a ring-shaped region of high brightness is observed in a circular pattern, and multiple spots are sometimes observed within the ring-shaped region.

[0250] The nc-OS film has a lower defect level density than the amorphous oxide semiconductor film. However, in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher defect level density than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility.

[0251] The nc-OS film can be formed by reducing the oxygen flow ratio during film formation compared with the CAAC-OS film. Also, the nc-OS film can be formed by lowering the substrate temperature during film formation compared with the CAAC-OS film. For example, since the nc-OS film can be formed even when the substrate temperature is relatively low (for example, a temperature of 130 °C or lower) or when the substrate is not heated, it is suitable for use when using a large glass substrate, a resin substrate, etc., and can improve productivity.

[0252] An example of the crystal structure of a metal oxide will be described. The metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) with the substrate temperature being 100 °C or higher and 130 °C or lower is likely to have either an nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, the metal oxide formed with the substrate temperature at room temperature (R.T.) is likely to have an nc crystal structure. Here, the room temperature (R.T.) as used herein includes the temperature when the substrate is not intentionally heated.

[0253] <Configuration of CAC-OS> Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0254] CAC-OS is a material in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0255] The metal oxide preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0256] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0257] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In the present specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0258] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0259] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0260] On the other hand, CAC-OS is a material composition of metal oxide. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0261] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0262] In addition, GaO X3 The region where In is the main component and X2Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0263] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0264] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, and for example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0265] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0266] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region with high brightness and multiple bright spots are observed within the ring-shaped region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0267] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0268] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0269] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the metal oxide is expressed. X2 ZincY2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved by distributing the regions in which the main component is a cloud-like structure in the metal oxide.

[0270] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 By distributing regions in which the main components are such as those mentioned above in the metal oxide, leakage current can be suppressed and good switching operation can be achieved.

[0271] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0272] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS ideal for a variety of semiconductor devices including displays.

[0273] In addition, since a transistor having a CAC-OS semiconductor layer has high field-effect mobility and high driving capability, a display device with a narrow frame width (also called a narrow frame) can be provided by using the transistor in a driver circuit, typically a scan line driver circuit that generates a gate signal. In addition, a display device with a small number of wirings connected to the display device can be provided by using the transistor in a signal line driver circuit (particularly, a demultiplexer connected to an output terminal of a shift register in the signal line driver circuit).

[0274] Moreover, unlike transistors using low-temperature polysilicon, transistors having CAC-OS in the semiconductor layer do not require a laser crystallization process. This makes it possible to reduce manufacturing costs even for display devices using large-area substrates. Furthermore, in large-sized display devices with high resolution such as ultra-high vision ("4K resolution", "4K2K", "4K") and super-high vision ("8K resolution", "8K4K", "8K"), by using transistors having CAC-OS in the semiconductor layer in the driving circuit and display section, writing can be performed in a short time and display defects can be reduced, which is preferable.

[0275] Alternatively, silicon may be used for the semiconductor in which the channel of the transistor is formed. Although amorphous silicon may be used as the silicon, it is preferable to use silicon having crystallinity. For example, it is preferable to use microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

[0276] [Conductive Layer] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or alloys containing these as main components. Films containing these materials can be used as a single layer or a laminated structure. For example, there are a single layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, and a three-layer structure in which an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a three-layer structure in which an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film. Alternatively, oxides such as indium oxide, tin oxide, zinc oxide, etc. may be used. Furthermore, copper containing manganese is preferably used because it enhances the controllability of the shape by etching.

[0277] [Insulating layer] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic and epoxy, resins having siloxane bonds, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0278] Moreover, the light emitting element is preferably provided between a pair of insulating films with low water permeability, which can prevent impurities such as water from entering the light emitting element and suppress deterioration of the reliability of the device.

[0279] Examples of the insulating film having low water permeability include a film containing nitrogen and silicon, such as a silicon nitride film or a silicon nitride oxide film, and a film containing nitrogen and aluminum, such as an aluminum nitride film. In addition, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, etc. may also be used.

[0280] For example, the water vapor permeability of a low-permeability insulating film is 1×10 -5 [g / (m 2 ·day)] or less, preferably 1 × 10 -6 [g / (m 2 ·day)] or less, preferably 1×10 -7 [g / (m 2 ·day)] or less, and more preferably 1×10 -8 [g / (m 2 ·day)] or less.

[0281] The above is a description of the components.

[0282] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0283] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0284] (Embodiment 2) The second wiring (wiring 14) exemplified in the first embodiment can be applied not only to display devices but also to various semiconductor devices. That is, the second wiring (wiring 14) can be suitably applied to a semiconductor circuit without a display function formed on a single crystal substrate, a glass substrate, or a film substrate.

[0285] Furthermore, in the research, development, and production management of various semiconductor devices including display devices, a TEG (Test Element Group) is known as an element for evaluation to evaluate electrical characteristics of manufactured elements and circuits. Such a TEG has a terminal for contacting a measurement probe. In many cases, the terminal has an area much larger than the element to be measured, and is therefore susceptible to the effects of ESD. Therefore, the electrical characteristics of the element to be measured may fluctuate due to the effects of ESD.

[0286] In this embodiment, an example in which the wiring 14 illustrated in the first embodiment is applied to a TEG will be described.

[0287] 14A shows a schematic top view of the TEG 100a. The TEG 100a has a device under test 101, a plurality of terminals 102, wiring 103, and wiring 14.

[0288] Various elements or circuits can be used as the element under test 101. For example, a transistor, a resistor, a capacitor, a wiring, or a circuit including one or more of these can be used. In addition, various elements can be used as the element under test 101 depending on the purpose of the measurement, such as an element for evaluating contact resistance or an element for evaluating dielectric breakdown voltage.

[0289] Here, an example is shown having four terminals 102 electrically connected to the element under test 101. For example, in the case where a transistor is used as the element under test 101, each of the four terminals 102 corresponds to a terminal electrically connected to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode of the transistor via wirings 103, respectively.

[0290] The wiring 14 is electrically connected to the four terminals 102. Here, the four terminals 102 can be electrically separated by cutting the wiring 14 along the cutting line 120 shown in FIG. 14A. As shown in FIG. 14A, it is preferable that the wiring 14 has a top surface shape having parallel arranged portions (also called comb-shaped portions) so that all the terminals 102 can be electrically separated by cutting once. In addition, although an example in which the wiring 14 has a linear shape is shown here, for example, at least a part of the wiring 14 may have a gentle meandering shape, an S-shape, or a shape in which a plurality of S-shapes are connected (also called a bellows shape), etc.

[0291] It is preferable to cut the wiring 14 immediately before the measurement. There are no particular limitations on the method for cutting the wiring 14, but a laser cutter can be suitably used.

[0292] In this manner, by configuring the multiple terminals 102 of the TEG 100a to be electrically connected by wiring 14 until immediately before measurement, the effects of ESD caused by charging of the substrate during or after the manufacturing process can be mitigated, and the measured element 101 can be suitably prevented from being destroyed or its electrical characteristics changed.

[0293] 14B shows a TEG 100b in which two of the four terminals 102 are electrically connected by the wiring 14. In this manner, instead of electrically connecting all the terminals 102, only the terminals 102 to be electrically connected to electrodes, etc., of the element 101 under test that have a low withstand voltage may be selected and electrically connected by the wiring 14 in accordance with the configuration of the element 101 under test.

[0294] 14C shows an example of a TEG 100c having a two-terminal device under test 101. FIG 14D shows an example of a TEG 100d having a three-terminal device under test 101.

[0295] 14E shows an example of a TEG 100e having wiring 14p that electrically connects two of the four terminals 102 and wiring 14q that electrically connects the other two. As shown in FIG 14E, when there are two or more electrically insulated wirings 14, it is preferable to have a top surface shape that allows these to be cut at one time.

[0296] The number of terminals 102 is not limited to the above, and may be five or more terminals depending on the configuration of device under test 101.

[0297] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0298] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0299] 15A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0300] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0301] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0302] The driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may have at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register.

[0303] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0304] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 15A is connected to various wirings, such as a gate line GL that is a wiring between a gate driver 504a and a pixel circuit 501, or a data line DL that is a wiring between a source driver 504b and a pixel circuit 501. In Fig. 15A, the protection circuit 506 is hatched to distinguish the protection circuit 506 from the pixel circuit 501.

[0305] In addition, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0306] Furthermore, the pixel circuits 501 shown in FIG. 15A can have the configuration shown in FIG. 15B or FIG. 15C, for example.

[0307] 15B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0308] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0309] 15C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0310] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0311] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0312] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0313] (Embodiment 4) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors described in the first embodiment can be used as the transistors used in the pixel circuits described below.

[0314] [Circuit configuration] 16A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0315] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0316] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0317] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0318] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0319] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistor M1 and the transistor M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potentials of the nodes are held is short (specifically, when the frame frequency is 30 Hz or more), a transistor including a semiconductor such as silicon may be used.

[0320] [Driving method example] Next, an example of an operation method of the pixel circuit 400 will be described with reference to Fig. 16B. Fig. 16B is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0321] 16B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0322] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0323] The node N1 is connected to a potential V ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0324] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0325] The node N1 receives a second data potential V data At this time, the second data potential V data In response to this, the potential of the node N2 changes by a potential dV. w The potential obtained by adding the second data potential V to the potential dV is input. Note that, although the potential dV is shown to be a positive value in FIG. 16B, it may be a negative value. data is the potential V ref It may be lower.

[0326] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0327] In this manner, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0328] In addition, the pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0329] [Example of application] [Example using liquid crystal element] 16C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0330] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0331] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted.

[0332] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, and therefore can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0333] [Example using light-emitting element] 16D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0334] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and a drain connected to the potential V H The other electrode of the capacitor C2 is connected to a wiring to which a potential V com The light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0335] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0336] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L The value of can be changed appropriately.

[0337] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, HDR display can be realized. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0338] Note that the circuits are not limited to those illustrated in FIGS. 16C and 16D, and may be configured to include additional transistors, capacitors, and the like.

[0339] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0340] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0341] A display module 6000 shown in FIG. 17A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0342] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0343] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0344] The display device 6006 may have a function as a touch panel.

[0345] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0346] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0347] FIG. 17B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0348] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0349] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0350] Light 6018 emitted from the light-emitting unit 6015 passes through the light-guiding unit 6017a, the upper part of the display device 6006, and the light-guiding unit 6017b to reach the light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0351] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation is performed.

[0352] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0353] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0354] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0355] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0356] Electronic device 6500 shown in FIG. 18A is a portable information terminal that can be used as a smartphone.

[0357] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0358] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0359] The display portion 6502 has a cutout portion, and a camera 6507 and a light source 6508 are provided so as to engage with the cutout portion. With this structure, the area occupied by the display portion 6502 with respect to the housing 6501 can be increased.

[0360] 18B shows an example in which the display portion 6502 has an opening, and a camera 6507 and a ring-shaped light source 6509 surrounding the camera 6507 are disposed inside the opening. A speaker 6505 is provided so as to engage with a notch in the display portion 6502. The display portion 6502 may be used as a light source for illuminating a subject. With this configuration, the area occupied by the display portion 6502 relative to the housing 6501 can be made larger.

[0361] FIG. 18C is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0362] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0363] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0364] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0365] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0366] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0367] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0368] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0369] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0370] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0371] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0372] FIG. 19A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0373] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0374] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0375] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0376] The housing 8001 has a mount having electrodes, and can be connected to a strobe device or the like in addition to the finder 8100 .

[0377] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0378] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0379] The button 8103 has a function such as a power button.

[0380] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0381] FIG. 19B is a diagram showing the external appearance of the head mounted display 8200.

[0382] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0383] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0384] The mounting unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that contact the user, capable of detecting a current that flows with the movement of the user's eyeballs. The mounting unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The mounting unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0385] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0386] 19C, 19D, and 19E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0387] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform three-dimensional display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0388] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG. 19E, and a more realistic image can be displayed.

[0389] The electronic device shown in Figures 20A to 20G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0390] The electronic device shown in Fig. 20A to Fig. 20G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, etc. The functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have multiple display units. In addition, the electronic device may have a function of providing a camera or the like to capture still images and videos and store them on a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, etc.

[0391] The electronic device shown in FIGS. 20A to 20G will be described in detail below.

[0392] 20A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0393] FIG. 20B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 20B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and phone calls, titles of e-mail and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, icons 9050 and the like may be displayed at the position where the information 9051 is displayed.

[0394] 20C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

[0395] FIG. 20D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0396] 20E, 20F, and 20G are perspective views showing a foldable mobile information terminal 9201. FIG. 20E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 20G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 20F is a perspective view of a state in the middle of changing from one of FIG. 20E and FIG. 20G to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0397] 21A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0398] 21A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display unit in addition to operation buttons.

[0399] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0400] 21B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display unit 7500 is incorporated in the housing 7211.

[0401] 21C and 21D show an example of digital signage.

[0402] 21C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0403] 21D shows a digital signage 7400 attached to a cylindrical pole 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pole 7401.

[0404] The larger the display unit 7500, the more information can be provided at one time, and the larger the display area, the more easily it catches people's attention, which has the effect of increasing the effectiveness of advertising, for example.

[0405] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes, but also for providing information desired by the user, such as route information, traffic information, and commercial facility guide information.

[0406] 21C and 21D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly communicate with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0407] Furthermore, a game using the information terminal 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0408] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 21A to 21D.

[0409] Although the electronic device in this embodiment has a display portion, one embodiment of the present invention can also be applied to an electronic device that does not have a display portion. [Explanation of symbols]

[0410] 10, 10a, 10b: display device, 11: display section, 12, 12a, 12b: connection terminal, 13, 14, 14a, 14p, 14q, 15, 15a: wiring, 13a, 13b, 13d: opening, 13c: intersection, 14b: processing mark, 16: FPC, 17: connector, 18: connection section, 19: IC, 20a, 20b, 20c: cutting line, 21, 21a, 22: substrate, 25: adhesive layer , 30, 30a, 30b, 30c, 30d, 40, 40a, 40b: transistor, 31: semiconductor layer, 32, 32p, 35, 35p, 36, 36p, 37, 38, 38p, 39: conductive layer, 33, 41, 42, 43, 45, 46: insulating layer, 34: low resistance region, 50a, 50b: curved portion, 51: substrate, 52, 53: circuit portion, 54: notch portion, 100a, 100b , 100c, 100d, 100e: TEG, 101: device to be measured, 102: terminal, 103: wiring, 120: cutting line, 701, 705: substrate, 710: liquid crystal element, 711, 713: conductive layer, 712: liquid crystal, 720: support, 721, 722, 750, 752: transistor, 723: wiring, 725, 726: alignment film, 727: spacer, 730, 734, 74 1a, 741b, 741c, 744, 746, 770: insulating layer, 732: sealing layer, 736: colored layer, 738: light-shielding layer, 740: substrate, 741: protective layer, 742, 747, 748: adhesive layer, 743: resin layer, 749: protective layer, 755, 756: polarizing plate, 757: light source, 761, 772, 788: conductive layer, 782: light-emitting element, 786: EL layer, 790: capacitance element

Claims

1. A first insulating layer is provided on a substrate; A semiconductor layer and a first wiring are provided on the first insulating layer, A second insulating layer is provided on the semiconductor layer; a third insulating layer on the first insulating layer; a first conductive layer on the second insulating layer; a second conductive layer on the third insulating layer; a fourth insulating layer covering the semiconductor layer, the first conductive layer, the second conductive layer, and the first wiring; the fourth insulating layer has a first opening and a second opening reaching the semiconductor layer, a third opening reaching the second conductive layer, and a fourth opening reaching the first wiring, a third conductive layer, a fourth conductive layer and a fifth conductive layer on the fourth insulating layer; the third conductive layer is electrically connected to the semiconductor layer through the first opening; the fourth conductive layer is electrically connected to the semiconductor layer through the second opening; the fifth conductive layer is electrically connected to the second conductive layer through the third opening; the fifth conductive layer is electrically connected to the first wiring through the fourth opening; a fifth insulating layer covering the third conductive layer, the fourth conductive layer, the fifth conductive layer and the fourth insulating layer; the fifth insulating layer has a fifth opening reaching the fifth conductive layer; a sixth conductive layer and a seventh conductive layer on the fifth insulating layer; The sixth conductive layer can function as a pixel electrode, the seventh conductive layer is electrically connected to the fifth conductive layer through the fifth opening; the first wiring includes the same material as the semiconductor layer; the second conductive layer comprises the same material as the first conductive layer; the fifth conductive layer includes the same material as the third conductive layer and the fourth conductive layer; The seventh conductive layer comprises the same material as the sixth conductive layer.

2. In claim 1, an eighth conductive layer and a ninth conductive layer between the substrate and the first insulating layer; the eighth conductive layer has a region overlapping the semiconductor layer and the first conductive layer; the first insulating layer and the third insulating layer have a sixth opening reaching the ninth conductive layer; the second conductive layer is electrically connected to the ninth conductive layer through the sixth opening.

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