Semiconductor packages and semiconductor electronic devices

Abstract

This semiconductor package is provided with: a base part having a first surface that comprises a first side and a second side that is connected to the first side; a wiring multilayer body (20) which has a second surface that is arranged on the first surface so as to extend along the first side of the first surface, while also extending along the second side; and a peripheral wall part which surrounds the first surface together with the wiring multilayer body (20). The wiring multilayer body (20) comprises: a plurality of insulating layers stacked in layers; at least two first wiring conductors which are arranged on different insulating layers among the plurality of insulating layers; and interlayer conductors (221, 222) which are arranged on a lateral surface (22) so as to connect at least two first wiring conductors.

Description

[Technical field]

[0001] The present disclosure relates to semiconductor packages and semiconductor electronic devices. [Background technology]

[0002] There is a semiconductor package that houses an electronic component and electrically connects the electronic component to an external substrate or the like. The semiconductor package has a conductor line for connecting the connection terminal of the electronic component to the outside of the semiconductor package. In the specification of U.S. Patent Application Publication No. 2017 / 0135204, via hole conductors that connect conductor lines on different insulating layers are arranged together at the end of a substrate to connect the upper and lower conductor lines sandwiching an RF signal layer and a ground layer. Summary of the Invention [Means for solving the problem]

[0003] One aspect of the present disclosure is A base having a first surface including a first side and a second side connected to the first side; a wiring stack portion located on the first surface along the first side of the first surface and having a second surface along the second side; a peripheral wall portion surrounding the first surface together with the wiring stack portion; Equipped with The wiring stack portion is A plurality of insulating layers stacked in layers; At least two first wiring conductors located on different insulating layers of the plurality of insulating layers; a first interlayer conductor located on the second surface and connecting the at least two first wiring conductors; having When a portion protruding outward from the first side is defined as a protruding portion, and a portion located inward from the first side is defined as an inner portion, a first ground conductor located on a first upper surface of the protrusion; an interlayer ground conductor extending between the insulating layers and across the protruding portion and the inner portion; a second interlayer conductor located on the second surface and connecting the first ground conductor and the interlayer ground conductor; Have death, before the protruding portion has a height in a direction in which the insulating layers overlap that is smaller than that of the inner portion; the first interlayer conductor is located in the inner portion, and at least a portion of the second interlayer conductor is located in the protruding portion, and the first interlayer conductor and the second interlayer conductor are located with a gap between them. A semiconductor package. Effect of the Invention

[0004] According to the present disclosure, it is possible to more appropriately connect different layers in a semiconductor package. [Brief description of the drawings]

[0005] [Figure 1] 1 is an overall perspective view of a semiconductor electronic device with a lid removed; [Figure 2A] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Figure 2B] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Figure 3A] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Figure 3B] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Figure 4A] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Figure 4B] FIG. 4 is a diagram illustrating a conductor portion on an insulating layer. [Diagram 5] 11A and 11B are diagrams illustrating a conductor portion on the lower surface of an insulating layer. [Figure 6] FIG. 2 is a diagram showing a side surface of a wiring laminate. [Figure 7A] FIG. 11 is a perspective view showing a first modified example of a semiconductor package. [Figure 7B] FIG. 11 is a perspective view showing a second modified example of a semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Hereinafter, an embodiment will be described with reference to the drawings. FIG. 1 is an overall perspective view of a semiconductor electronic device 1 of the present embodiment with a lid 8 removed. The semiconductor electronic device 1 includes a semiconductor package 6, an electronic component 7, a lid 8, and the like.

[0007] The semiconductor package 6 includes a substrate 10 (base), a wiring stack 20 (wiring stack portion), and a wall 30 (peripheral wall portion). The semiconductor package 6 may include a fastener used for fixing to an external substrate or the like.

[0008] Substrate 10 has top surface 11 (first surface) which is the surface on the +Z side, and wiring stack 20 is located along one side (first side, here the side located on the +X side and extending in the Y direction) of top surface 11. Wiring stack 20 and wall body 30 form a frame-shaped housing that annularly surrounds top surface 11. Substrate 10 is substantially rectangular (corners may be rounded or chamfered) in plan view when viewed from the Z direction, but is not limited to this.

[0009] The wiring laminate 20 has a plurality of insulating layers stacked in layers, and wiring conductors (first wiring conductors) such as signal lines, ground lines, and power supply lines are located on the upper surface of each insulating layer (at least two of them). The wiring laminate 20 is divided into a protruding portion 21a in which a part of the insulating layers continuous in the vertical direction (Z direction) protrudes outward (+X side) from the first side of the upper surface 11 (substrate 10) in a plan view, and an inner portion 21b other than the protruding portion 21a located inward (-X side) from the first side. Connection terminals (not shown) located on the upper surface 211a (first upper surface) and the lower surface of the protruding portion 21a are connected to external wiring and the like. In addition, two surfaces along the side (second side; here, two sides extending in the X direction) of the upper surface 11 connected to the first side are side surfaces 22 and 23 (second surfaces). A part of the upper surface 24 (second upper surface) of the inner portion 21b is joined to the wall body 30. A portion of the upper surface 24 is located outside (on the +X side) of the wall body 30. A conductor surface 24a (second conductor) may be located on the upper surface 24. The conductor surface 24a is connected to a conductor 223 (first conductor) located at the boundary between the side surfaces 22 and 23 and the wall body 30.

[0010] The wall 30 is located along the outer edge of the substrate 10 in a plan view, and has an annular shape surrounding the upper surface 11. The wall 30 is joined to the upper surface of the wiring stack 20 in a portion where it overlaps with the wiring stack 20 in a plan view, and is joined to the substrate 10 in a portion where it does not overlap with the wiring stack 20. The upper surface of the wall 30 has a uniform height here, but is not limited to this. The semiconductor package 6 has the upper surface 11 of the substrate 10 as its bottom surface, and the periphery of the upper surface 11 is surrounded by the wiring stack 20 and the wall 30, forming a box shape having a recess that is open upward.

[0011] The wall 30 may have an opening 31 on one surface forming a side surface of the semiconductor package 6, which is different from the side on which the wiring stack 20 is located (the side of the first edge of the upper surface 11). For example, when the electronic component 7 includes an optical component such as a photodiode or a laser diode, light can pass through this opening 31. The opening 31 may be formed by partitioning the inside and outside of the semiconductor package 6 with a light-transmitting member such as glass or a transparent resin.

[0012] The wiring laminate 20 and the wall 30 are obtained by determining a three-dimensional shape and may be produced, for example, by stacking a plurality of insulating sheets (ceramic green sheets) formed by mixing powder of a material (e.g., aluminum oxide and silicon oxide, etc.) with an organic binder and a solvent to prepare a slurry, pressing and firing the sheets, and then performing processing such as cutting and punching as necessary. In the manufacture of the wiring laminate 20, for example, the above-mentioned conductor metal, binder and organic solvent are mixed to prepare a metal paste. Next, when stacking the insulating sheets, the metal paste is applied to each insulating sheet by screen printing or the like. Then, as described above, the sheets are stacked together with ordinary insulating sheets, pressed, and fired. A metallized layer may be located on the upper surface of the wall 30. This can improve the bonding strength between the wall 30 and the lid 8. The metallized layer may be formed by coating or firing, or by plating or the like. The wall 30 may be a separate member from the wiring stack 20, and may be made of a metal such as FeNiCo.

[0013] The lid 8 is joined to the upper surface of the wall 30 and covers the upper surface of the recess. The wall 30 is a conductor, and is, for example, a metal containing iron, copper, nickel, chromium, cobalt, molybdenum, or tungsten, or an alloy thereof.

[0014] As described above, the wiring laminate 20 has wiring conductors for transmitting signals and the like located on the upper surfaces (surfaces) of some or all of the insulating layers. These wiring conductors may include signal lines, ground lines, power supply lines, and the like. The paths (electrical paths) of the signals and power supplies by one or more wiring conductors connect the inside and outside of the recess of the semiconductor package 6.

[0015] The electronic component 7 is located on the upper surface 11 of the substrate 10 and is fitted inside the recess. One end of the electrical path inside the semiconductor package 6 and a terminal of the electronic component 7 are connected by a bonding wire or the like (not shown), and one end of the electrical path outside the semiconductor package 6 (the end opposite to the above-mentioned one end) is connected to an external substrate or the like via a connection terminal (not shown), thereby transmitting and receiving signals, supplying power, and the like.

[0016] On the side surfaces 22, 23 of the wiring laminate 20, there are positioned interlayer conductors 221 (first interlayer conductor) and 222 (second interlayer conductor) that connect wiring conductors on different insulating layers as described below.

[0017] In addition, a conductor 223 (metallized layer; first conductor) is located along the outer edge of the side surfaces 22, 23 that contacts the substrate 10 or the wall 30. This conductor 223 is intended to prevent the brazing material used for bonding from solidifying excessively and remaining on the bonding surface by allowing the brazing material to flow appropriately along the conductor 223 when bonding the wiring laminate 20 to the substrate 10 and the wall 30, thereby making it difficult for cracks to occur when stress is applied to the semiconductor package 6.

[0018] Next, the electrical paths located on the insulating layers of the wiring stack 20 will be described. 2A to 4B are diagrams illustrating conductor portions on six insulating layers 201 to 206. Also, Fig. 5 is a diagram illustrating the back surface side of insulating layer 206, which is the lowest layer among the six insulating layers 201 to 206. All of Figs. 2A to 5 are shown as seen in a plan view from the top side. Note that the number of insulating layers in the embodiment may be more than six layers.

[0019] 2A shows the uppermost insulating layer 201. A conductor surface 2011 extends over the entire upper surface of the insulating layer 201. A wall body 30 is joined onto the conductor surface 2011 via a brazing material or the like.

[0020] FIG. 2B shows the insulating layer 202, which is the second layer from the top among the six layers. In the insulating layer 202, there are a land 2021 to which a via hole conductor in a via hole penetrating the insulating layer 201 and a via hole conductor in a via hole penetrating the insulating layer 202 are connected, and a signal line 2022 extending from the land 2021 to the side surfaces 22 and 23. That is, the signal line 2022 is electrically connected to a land 2034 (see FIG. 3A) through a via hole conductor. Here, only one pair of a land 2021 and a land 2034 is shown for the purpose of explanation, but this is not limited thereto. Three or more lands 2021 and lands 2034 may be arranged in an appropriate positional relationship.

[0021] The insulating layers 201 and 202 have a cutout portion (recess) on the right side (−X side) of the figure.

[0022] 3A shows the top of insulating layer 203, which is the third layer from the top out of the six layers. Shown here are a pair of signal lines 2032, a pair of power supply lines 2033, and a land 2034. The depth (width in the X direction) of the cutout portion of insulating layer 203 is smaller than the cutout portions of insulating layers 201 and 202, and one end (upper surface of insulating layer 203) of power supply line 2033 and signal line 2032 located near the edge of this cutout portion are exposed inside the cutout portions of insulating layers 201 and 202, respectively.

[0023] The power supply line 2033 is connected to the other end located on the side surface 22, 23, and the signal line 2032 is connected to a land 2034. The land 2034 overlaps with the land 2021 in a planar perspective view, and these lands 2034 and 2021 are electrically connected via a via hole conductor in a via hole penetrating the insulating layer 202.

[0024] The exposed ends of the power supply line 2033 and the signal line 2032 in the -X direction are connected to the electronic component 7 by bonding wires or the like inside the semiconductor package 6, and power is supplied at a predetermined voltage (including ground voltage) to the electronic component 7. Note that, although shown here as the power supply line 2033 and the signal line 2032, they may be transmission lines (collectively referred to as wiring conductors) for DC signals, signals switched at low frequencies (low frequencies are frequencies at which consideration of impedance matching is not required, as described later), and the like.

[0025] FIG. 3B shows the insulating layer 204, which is the fourth layer from the top among the six layers. The left side (+X side) of the insulating layer 204 in the figure is the upper surface of the protruding portion 21a, and is exposed to the outer surface of the semiconductor package 6. In this exposed portion, one end of the signal line 2041 and ground conductors 2042, 2043 (ground conductors) are arranged side by side. Here, the signal line 2041 is a pair of two lines that form a differential line, and the ground conductors 2042 (part of the ground conductor 2043) are located on both sides (±Y direction) of each pair of differential lines. A connection terminal (lead terminal) not shown is joined to this end of the signal line 2041, and the connection terminal is connected to an external signal line or the like. The signal line 2041 and the ground conductors 2042, 2043 in FIG. 3B are shown enlarged for the purpose of explanation, and their size, interval, and number may be appropriately determined according to the number of signals, the size of the semiconductor package 6, and the like.

[0026] The signal line 2041 and the ground conductor 2042 are connected to the right side (-X side) of the figure by passing under the covering layer 2046. Since the insulating layer 204 does not have a cutout portion, the right side (-X side) ends of the signal line 2041 and the ground conductors 2042, 2043 are exposed to the inner surface (recess) side of the semiconductor package 6 inside the cutout portion of the insulating layer 203. The covering layer 2046 is, for example, an insulating thin film such as alumina. The right end of the signal line 2041 and the electronic component 7 are connected via a bonding wire (not shown) or the like, and a signal is transmitted between the electronic component 7. The signal to be transmitted is an RF signal, and may be a signal of 1 MHz or more, particularly a GHz band signal.

[0027] The ground conductors 2042 are in contact with the via hole conductors 2044. The via hole conductors 2044 are connected to a ground conductor surface 2051 on the insulating layer 205 through via holes penetrating the insulating layer 204. In addition, in a portion not corresponding to the protrusion 21a in plan view (a portion other than the protrusion 21a), a via hole conductor 2045 may be located which passes through a via hole penetrating an insulating layer (not shown) located between the insulating layers 203 and 204 and connects to a ground conductor surface on the insulating layer.

[0028] The ends of the ground conductor 2043 at both ends in the Y direction are exposed to the side surfaces 22 and 23 at the protruding portion 21a. This exposed portion E1 (first region) is joined (connected) to the interlayer conductor 222 located on the side surface. On the other hand, the portion other than the exposed portion E1 (the adjacent portion D1 (second region) to the interlayer conductor 221) is located away from the side surfaces 22 and 23, respectively, and is located adjacent to the interlayer conductor 221 at a distance of dm or more here. Accordingly, between the exposed portion E1 and the adjacent portion D1, the edge (side) of the ground conductor 2043 extends in a direction along the first side (a direction perpendicular to the side surfaces 22 and 23) to connect the adjacent portion D1 and the side surface 22.

[0029] FIG. 4A shows the fifth insulating layer 205 from the top among the six layers. A ground conductor surface 2051 (interlayer ground conductor) spreads on the insulating layer 205. The ground conductor surface 2051 extends across the exposed portion E2 and the adjacent portion D2 (i.e., the range of the protrusion 21a and the range other than the protrusion 21a in a planar perspective), and includes the entire range of the signal line 2041 on the insulating layer 204 in a planar perspective. The ground conductor surface 2051 is exposed to the side surfaces 22 and 23 in the exposed portion E2, like the ground conductor 2043 of the insulating layer 204, and is separated from the side surfaces 22 and 23 by a predetermined distance (distance dm) in the adjacent portion D2. The side forming the boundary between these regions extends along the first side (perpendicular to the side surfaces 22 and 23). The position of this side substantially overlaps, in plan view, the edge of the ground conductor 2042 between the exposed portion E1 and the adjacent portion D1 on the insulating layer 204 in FIG. 3B.

[0030] As described above, the wiring laminate 20 is shaped by cutting, punching, etc. after fabrication. Although slight variations in the positions of the cutting and punching are unavoidable from a physical standpoint, because the boundaries between the exposed portions E1, E2 and the adjacent portions D1, D2 are along the first sides (perpendicular to the side surfaces 22, 23) in this way, even if some variations occur, there is no deviation in the position of the boundaries in the X direction. Therefore, the exposed portions E1, E2 are unlikely to be wider or narrower than necessary, and in particular, the occurrence of unintended short circuits due to unnecessary exposed portions is suppressed.

[0031] 4B shows the top of the insulating layer 206, which is the lowest of the six layers. The lower surface (bottom surface) of this insulating layer 206 forms the lower surface of the protruding portion 21a. A signal line 2062 and a power supply line 2063 are located on the insulating layer 206.

[0032] One end of the signal line 2062 is exposed on the side surfaces 22 and 23 and is in contact with one interlayer conductor 221. The other end opposite to the one end is connected to a via hole conductor 2064, and passes through the insulating layer 206 via the via hole conductor 2064 to be connected to a wiring conductor 2066 shown in Fig. 5. The wiring conductor 2066 is exposed on the lower surface of the protrusion 21a and is connected to an external wiring or the like via a connection terminal or the like.

[0033] One end of the power supply line 2063 is exposed on the side surfaces 22 and 23, and is in contact with an interlayer conductor 221 different from the one in contact with the signal line 2062. The other end opposite to the one end is connected to a via hole conductor 2065, and passes through the insulating layer 206 via the via hole conductor 2065 to connect to a wiring conductor 2067 shown in Fig. 5. The wiring conductor 2067 is exposed on the lower surface of the protrusion 21a, and is connected to an external wiring or the like via a connection terminal or the like.

[0034] 6 is a side view of the side surface 22. In this embodiment, the side surface 23 is the same as the side surface 22 when seen in a planar perspective from the side of the side surface 22, and therefore a description thereof will be omitted. The interlayer conductor 221 includes planar interlayer conductors 221a and 221b located in an area surrounded by a conductor 223 on the side surface of the inner portion 21b. The interlayer conductor 221a connects the signal lines 2022 and 2062 of the different insulating layers 202 and 206. The interlayer conductor 221b connects the power supply lines 2033 and 2063 of the different insulating layers 203 and 206. The interlayer conductors 221 may be located on the inner surface of a recess having a shape such as a semi-cylindrical shape. The interlayer conductor 222 is located outside (+X side) the interlayer conductor 221, and connects a ground conductor 2043 (here, a ground conductor on the upper surface of the protrusion 21a; a first ground conductor) of the different insulating layers 204 and 205 to a ground conductor surface 2051 on the side surface of the protrusion 21a. Here, the length of the interlayer conductor 222 in the X direction may be shorter than the length of the ground conductor 2043 in the X direction (length E1 in FIG. 3B). For signals that are not intended to transmit voltage changes such as grounding and power supply, DC signals with unchanging voltage, and low-frequency AC signals, for example, signals of 1 MHz or less, whose transmission signal frequency is not so high as to require impedance matching and do not generate electromagnetic radiation from exposed parts, a part of the electrical path can be exposed on the surface of the semiconductor package 6. In the conventional power supply line using a via hole conductor, there are restrictions on the minimum distance (clearance) required between the surrounding signal lines in the insulating layer and the positional relationship, so that there is a limit to miniaturization. However, by having the electrical path exposed on the side surfaces 22 and 23 in this way, it becomes possible to easily determine the electrical path by detouring the insulating layer 204 where many signal lines 2041 are located. The upper surface 24 of the inner portion 21b is a conductor surface 24a that is connected to the conductor 223 as described above.

[0035] [Variations] 7A and 7B are perspective views showing modified examples of the semiconductor package 6. FIG. 7A shows a semiconductor package 6a of Modification 1. In this semiconductor package 6a, the wiring stack 20 and the wall body 30 are integrated into a stack 20a. In this case, the laminated insulating layers each have an annular structure. This makes it unnecessary to provide the conductor 223 located along the joint surface between the wall body 30 and the edge of the wiring stack 20. The structure of the other portion (wiring stack portion) corresponding to the wiring stack 20 is the same as that of the above embodiment, and therefore description thereof will be omitted.

[0036] 7B shows a semiconductor package 6b of Modification 2. In this semiconductor package 6b, the substrate 10, the wiring laminate 20, and the wall 30 are all integrated into a laminate 20b. In this case, the insulating layer in the portion corresponding to the substrate 10 is plate-shaped, and the insulating layer in the other portion is annular like the laminate 20a described above. Since it is not a combination of multiple members, the conductor 223 is not necessary.

[0037] In the portion (wiring stack portion) corresponding to the wiring stack 20, in this modified example 2, the ground conductor 2043a does not contact the side surfaces 22, 23, and therefore the stack 20b does not have the interlayer conductor 222 on the side surfaces. The other configurations and structures are the same as those of the above embodiment, and therefore will not be described. As such, wiring stack 20 need not be a separate structure, but may be part of a stack that is integrally formed with walls 30 and / or substrate 10.

[0038] As described above, the semiconductor package 6 of this embodiment includes the substrate 10 having the top surface 11 including a first side and a second side connected to the first side, the wiring laminate 20 located on the top surface 11 along the first side of the top surface 11 and having side surfaces 22, 23 along the second side, and the wall body 30 surrounding the top surface 11 together with the wiring laminate 20. The wiring laminate 20 includes a plurality of insulating layers 201-206 overlapped in a layered manner, at least two first wiring conductors such as signal lines 2022, 2062 and power supply lines 2033, 2063 located on different insulating layers (202, 203, 206, etc.) in the plurality of insulating layers 201-206, and an interlayer conductor 221 located on the side surfaces 22, 23 and connecting the at least two first wiring conductors. According to this semiconductor package 6, control signals, ground voltages, and supply power, which conventionally have been connected between different insulating layers via via holes, can be transmitted through the side of the semiconductor package. This eliminates the need to provide via holes at the required intervals even if there are many signal lines, and allows different insulating layers to be connected more appropriately. This also allows for a smaller package size compared to the number of signal lines.

[0039] Furthermore, the interlayer conductor 221 is a conductor that transmits low-frequency AC or DC signals, such as power supply, etc. For such signals, even if the electrical path is partially exposed to the outside of the insulating layer, impedance mismatch at the boundary where the exposed portion switches over does not become a problem, and the interlayer conductor 221 can be used without any problem.

[0040] Furthermore, the electrical path including the interlayer conductor 221 (first interlayer conductor) may be a grounding conductor. In this case, the electrical path may be exposed to the outside of the insulating layer, and the grounding conductors between different insulating layers can be appropriately connected.

[0041] Furthermore, the wiring stack 20 may have two interlayer conductors 221a, 221b extending side by side on the side surfaces 22, 23. This makes it possible to transmit a variety of types of signals and voltages in a small space.

[0042] Furthermore, the wiring stack 20 may have recesses located on the side surfaces 22 and 23, and the interlayer conductor 221 may be a conductor located within the recesses. This allows the area of ​​the interlayer conductor 221 to be larger than its width in the X direction.

[0043] The wiring laminate 20 has a protruding portion 21a protruding outward from the first side and having an upper surface 211a, an inner portion 21b located inside (-X side) from the first side, a ground conductor 2043 located on the upper surface 211a of the protruding portion 21a, a ground conductor surface 2051 extending across the protruding portion 21a and the inner portion 21b between the insulating layers, and an interlayer conductor 222 located on the side surfaces 22 and 23 and connecting the ground conductor 2043 and the ground conductor surface 2051. In the protruding portion 21a having a connection terminal of a signal line, a ground conductor between signal wirings is often arranged, and space tends to be insufficient due to miniaturization. By connecting the ground conductors at both ends to other layers via the outer side surfaces, the number of via holes can be reduced, and by having an appropriate ground surface, it is possible to reduce signal loss while suppressing an increase in size.

[0044] Moreover, the interlayer conductor 222 is located on the outer side (+X side) than the interlayer conductor 221 on the side surfaces 22 and 23. That is, by positioning the interlayer conductor 222, which connects the conductor of the layer including the upper surface 211a of the protrusion 21a to the conductor of another layer, on the side of the protrusion 21a, a plurality of interlayer conductors can be arranged efficiently.

[0045] Furthermore, the length in the X direction of the interlayer conductor 222 on the side surfaces 22 and 23 may be shorter than the length in the X direction of the ground conductor 2043 on the upper surface 211a. In other words, as long as the interlayer conductor 222 has a necessary width, the ground conductor 2043 does not need to be in contact with the interlayer conductor 222 over the entire width, and there is no need to use more conductive members than necessary.

[0046] In addition, at least one of the ground conductor 2043 and the ground conductor surface 2051 has, in planar perspective, an exposed portion E1 connected to the side surfaces 22 and 23, an adjacent portion D1 located away from the side surfaces 22 and 23 and adjacent to the interlayer conductor 221 at a distance of dm or more, and a side along the first side connecting the exposed portion E1 and the adjacent portion D1. That is, since the adjacent portion D1 is separated from the side surfaces 22 and 23, the adjacent portion D1 is not cut during manufacturing. Furthermore, since the edge of the portion connecting the adjacent portion D1 and the side surfaces 22 and 23 is perpendicular to the side surfaces 22 and 23 and is not inclined, even if the cutting position is shifted, the exposed range of the ground conductor 2043 and the ground conductor surface 2051 on the side surfaces 22 and 23 does not change. When the interlayer conductors 221 and 222 are present on the side surfaces 22 and 23, a shift in the exposed surface may lead not only to a shift in the connection range but also to a short circuit due to an unintended connection with other portions. Therefore, by defining the range of the ground conductor in this manner, alignment can be easily performed without having to improve the precision of cutting during manufacturing compared to conventional techniques, and an appropriate electrical path can be obtained.

[0047] Furthermore, the wiring laminate 20 has a conductor 223 located along at least the outer edge of the side surfaces 22, 23 that contacts the substrate 10 or the wall 30. When the wiring laminate 20 is joined to the substrate 10 and the wall 30, the brazing material used for joining flows appropriately along the conductor 223, thereby preventing the brazing material from solidifying excessively and remaining on the joining surface, making it difficult for cracks to occur when stress is applied to the semiconductor package 6.

[0048] Furthermore, the wiring laminate 20 has an upper surface 24 connected to the side surfaces 22 and 23, and a conductor surface 24a located on the upper surface 24, and the conductor surface 24a may be connected to the conductor 223. This allows the wiring laminate 20 to be grounded more stably.

[0049] Moreover, the semiconductor electronic device 1 of this embodiment includes the above-mentioned semiconductor package 6 and an electronic component 7 located on the upper surface 11 of the substrate 10. According to this semiconductor electronic device 1, it is possible to properly connect electrical paths such as a ground line and a power supply line, thereby allowing the electronic component 7 to operate properly.

[0050] The above-described embodiment is merely an example, and various modifications are possible. For example, in the above embodiment, the same interlayer conductors 221, 222 are located at the same position on both side surfaces 22, 23 in planar perspective from the same direction (located symmetrically with respect to a plane located midway between side surfaces 22, 23), but this is not limited to the above. Side surfaces 22, 23 may have interlayer conductors at different positions, numbers, sizes, or shapes depending on the wiring pattern, etc.

[0051] Furthermore, when multiple interlayer conductors are used for different purposes, i.e., for multiple purposes such as a ground line, a power supply line, or a signal line for a low-frequency signal, the positional relationship between the interlayer conductors may be adjusted.

[0052] Furthermore, the semiconductor package 6 does not necessarily have to have the interlayer conductor 222. If there is space in the protruding portion 21a, interlayer connection may be achieved by a normal via hole conductor without using the interlayer conductor 222.

[0053] In the above embodiment, the interlayer conductor 221 is positioned so as to straddle the fourth insulating layer having the RF signal line, but this is not limited thereto. The interlayer conductor may connect any different layers.

[0054] In addition, the interlayer conductor is not limited to a rectangular shape extending in the Z direction. It may extend obliquely on the side surfaces 22 and 23, or may have a curved or folded line shape. In addition, the thickness (direction perpendicular to the Z direction) does not have to be uniform.

[0055] In the above embodiment, the lid 8 is described as being separate from the semiconductor package 6, but the semiconductor package 6 may include the lid 8.

[0056] Furthermore, the method for producing the semiconductor package 6 is not limited to using an insulating sheet as described above, but may be produced by other methods.

[0057] Furthermore, the semiconductor package 6 does not have to have the protruding portion 21a, and the protruding portion 21a does not have to be a protrusion of a part of the intermediate insulating layer. The top or bottom insulating layer may be included. Furthermore, the protruding portion 21a does not have to protrude over the entire length of the first side, and the protruding portion 21a may have a notch.

[0058] Furthermore, the semiconductor package 6 may be manufactured and sold separately from the electronic component 7. In this case, the lid 8 may be sold in a state where it is not joined to the semiconductor package 6. In addition, the specific details of the configuration, materials, structure, etc. shown in the above embodiment can be appropriately changed without departing from the spirit of the present disclosure. The scope of the present invention includes the scope described in the claims and their equivalents. [Industrial Applicability]

[0059] The present disclosure can be applied to semiconductor packages and semiconductor electronic devices.

Claims

1. A base having a first surface including a first side and a second side connected to the first side; a wiring stack portion located on the first surface along the first side of the first surface and having a second surface along the second side; a peripheral wall portion surrounding the first surface together with the wiring stack portion; Equipped with The wiring stack portion is A plurality of insulating layers stacked in layers; At least two first wiring conductors located on different insulating layers of the plurality of insulating layers; a first interlayer conductor located on the second surface and connecting the at least two first wiring conductors; having When a portion protruding outward from the first side is defined as a protruding portion, and a portion located inward from the first side is defined as an inner portion, a first ground conductor located on a first upper surface of the protrusion; an interlayer ground conductor extending between the insulating layers and across the protruding portion and the inner portion; a second interlayer conductor located on the second surface and connecting the first ground conductor and the interlayer ground conductor; having the protruding portion has a height in a direction in which the insulating layers overlap that is smaller than that of the inner portion; the first interlayer conductor is located in the inner portion, and at least a portion of the second interlayer conductor is located in the protruding portion, and the first interlayer conductor and the second interlayer conductor are located with a gap between them. Semiconductor package.

2. 2. The semiconductor package according to claim 1, wherein the first interlayer conductor is a conductor for a low-frequency AC signal or a DC signal.

3. 2. The semiconductor package according to claim 1, wherein the first interlayer conductor is a ground conductor.

4. 2. The semiconductor package according to claim 1, wherein the wiring stack portion has two of the first interlayer conductors extending side by side on the second surface.

5. the wiring stack portion has a recess located on the second surface, The first interlayer conductor is a conductor located within the recess.

2. The semiconductor package of claim 1.

6. 2. The semiconductor package according to claim 1, wherein in a direction parallel to the second surface and perpendicular to the direction in which the insulating layers overlap, the length of the second interlayer conductor is shorter than the length of the first grounding conductor on the first upper surface.

7. At least one of the first grounding conductor and the interlayer grounding conductor has, in a planar perspective view, a first region connected to a second surface, a second region located away from the second surface and adjacent to the first interlayer conductor, and a side along the first side connecting the first region and the second region.

2. The semiconductor package of claim 1.

8. The semiconductor package according to claim 1 , wherein the wiring stack portion has a first conductor located along at least an outer edge of the second surface that is in contact with the base portion or the peripheral wall portion.

9. the wiring stack portion has a second upper surface connected to the second surface and a second conductor located on the second upper surface, The second conductor and the first conductor are connected to each other.

9. The semiconductor package according to claim 8.

10. A base having a first surface including a first side and a second side connected to the first side; a wiring stack portion located on the first surface along the first side of the first surface and having a second surface along the second side; a peripheral wall portion surrounding the first surface together with the wiring stack portion; Equipped with The wiring stack portion is A plurality of insulating layers stacked in layers; At least two first wiring conductors located on different insulating layers of the plurality of insulating layers; a first interlayer conductor located on the second surface and connecting the at least two first wiring conductors; having When a portion protruding outward from the first side is defined as a protruding portion, and a portion located inward from the first side is defined as an inner portion, a first ground conductor located on a first upper surface of the protrusion; an interlayer ground conductor extending between the insulating layers and across the protruding portion and the inner portion; a second interlayer conductor located on the second surface and connecting the first ground conductor and the interlayer ground conductor; having At least one of the first grounding conductor and the interlayer grounding conductor has, in a planar perspective view, a first region connected to a second surface, a second region located away from the second surface and adjacent to the first interlayer conductor, and a side along the first side connecting the first region and the second region. Semiconductor package.

11. A semiconductor package according to any one of claims 1 to 10; an electronic component located on the first surface; A semiconductor electronic device comprising:

Images