Semiconductor device, memory device, and electronic device

Abstract

Provided is a semiconductor device having a large storage capacity. The semiconductor device has first to sixth insulators, first to third conductors, and first to third material layers. The first insulator and the first material layer overlap the first conductor. The second material layer, the second conductor, the second insulator, and the third insulator overlap a first region of the first material layer. The third material layer is disposed in a second region of the first material layer, and in a region including top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator, the fourth insulator is disposed on the third material layer, the sixth insulator is disposed on the fourth insulator, and the fifth insulator is disposed on the sixth insulator. The third conductor is disposed on the fifth insulator that overlaps the second region of the first material layer. The first to third material layers have an oxide containing indium, element M (M is aluminum, gallium, tin, or titanium), and zinc.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operation method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), storage devices, and sensors are used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components are being improved in various aspects, including miniaturization and low power consumption.

[0004] In particular, the amount of data handled by the above-mentioned electronic devices is increasing, and there is a demand for storage devices with large storage capacities. As a means for increasing storage capacity, for example, Patent Document 1 discloses a three-dimensional NAND memory element that uses a metal oxide as a channel formation region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2016 / 149004 Summary of the Invention [Problem to be solved by the invention]

[0006] The semiconductor layer of a transistor constituting a memory element or the like is divided into a channel formation region and a low resistance region. In particular, when a metal oxide is used as the semiconductor layer of a NAND memory having a three-dimensional structure, how to form the low resistance region of the metal oxide is important. In the metal oxide used as the semiconductor layer of the transistor, a region with a low carrier concentration (or in this specification, etc., may be described as intrinsic, substantially intrinsic, etc.) functions as the channel formation region, and a region with a high carrier concentration functions as the low resistance region. Therefore, in the manufacture of a three-dimensional NAND memory using a metal oxide as the semiconductor layer, it is an issue to separately form the channel formation region and the low resistance region. In addition, after separately forming the channel formation region and the low resistance region, it is preferable to form a film with high barrier properties in the channel formation region so that the carrier concentration in the channel formation region does not change due to the diffusion of impurities, etc. In order to increase the data capacity of the NAND memory, it is preferable to separately form the channel formation region and the low resistance region small, and increase the number of cell transistors per string. Note that a cell transistor is an example of a memory cell, and includes transistors having a structure capable of storing data.

[0007] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with a large data capacity.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to apply a memory device including the novel semiconductor device.An object of one embodiment of the present invention is to provide an electronic device including the memory device.

[0008] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0009] (1) One aspect of the present invention is a semiconductor device having a columnar first conductor, a second conductor, a third conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a first material layer, a second material layer, and a third material layer. The first material layer has a first region and a second region. The first insulator is located adjacent to the first conductor, and the first material layer is located adjacent to the first insulator. The second material layer is located adjacent to the first region of the first material layer, the second conductor is located adjacent to the second material layer, the second insulator is located adjacent to the second conductor, and the third insulator is located adjacent to the second insulator. The third material layer is located so as to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer, the fourth insulator is located so as to be adjacent to the third material layer, the sixth insulator is located so as to be adjacent to the fourth insulator, the fifth insulator is located so as to be adjacent to the sixth insulator, and the third conductor is located in a region adjacent to the fifth insulator and overlapping with the first region of the first material layer. The second insulator functions as a barrier insulating film that prevents oxygen from diffusing into the second conductor, the fourth insulator functions as a tunnel insulating film, the sixth insulator functions as a charge storage layer, and the fifth insulator functions as a gate insulating film. The first material layer has an oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc, the second material layer has an oxide containing indium, an element M, and zinc, and the third material layer has an oxide containing indium, an element M, and zinc.

[0010] (2) One aspect of the present invention is a semiconductor device having a columnar first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a first material layer, a second material layer, and a third material layer. The first material layer has a first region and a second region. The first insulator is located adjacent to the first conductor, the first material layer is located adjacent to the first insulator, the second material layer is located adjacent to the first region of the first material layer, the second conductor is located adjacent to the second material layer, the second insulator is located adjacent to the second conductor, and the third insulator is located adjacent to the second insulator. The third material layer is located so as to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer, the fourth insulator is located so as to be adjacent to the third material layer, the fourth conductor is located in a region adjacent to the fourth insulator and overlapping with the first region of the first material layer, the fifth insulator is located so as to cover the fourth conductor and the fourth insulator, and the third conductor is located in a region adjacent to the fifth insulator and overlapping with the first region of the first material layer. In addition, the second insulator functions as a barrier insulating film that prevents oxygen from diffusing into the second conductor, the fourth insulator functions as a tunnel insulating film, the fourth conductor functions as a floating gate electrode, and the fifth insulator functions as a gate insulating film. The first material layer comprises an oxide containing indium, the element M (wherein M is aluminum, gallium, tin, or titanium), and zinc, the second material layer comprises an oxide containing indium, the element M, and zinc, and the third material layer comprises an oxide containing indium, the element M, and zinc.

[0011] (3) In the above configuration (1) or (2), the first material layer may have a fourth material layer and a fifth material layer. In particular, it is preferable that the fourth material layer is located adjacent to the first insulator, the fifth material layer is located adjacent to the fourth material layer, the first region of the first material layer is located in the fifth material layer, and the second region of the first material layer is located in the fifth material layer. It is also preferable that the ratio of the number of atoms of the element M to indium contained in the second material layer is greater than the ratio of the number of atoms of the element M to indium contained in the fifth material layer. It is also preferable that the ratio of the number of atoms of the element M to indium contained in the fourth material layer is greater than the ratio of the number of atoms of the element M to indium contained in the fifth material layer.

[0012] (4) In any one of the above configurations (1) to (3), the second region of the first material layer may have a higher oxygen concentration than the first region of the first material layer.

[0013] (5) In any one of the above configurations (1) to (4), the film thickness of the second region of the first material layer may be smaller than the film thickness of the first region of the first material layer.

[0014] (6) Another embodiment of the present invention is a memory device including the semiconductor device described above in any one of (1) to (5) and a peripheral circuit.

[0015] (7) Another embodiment of the present invention is an electronic device including the storage device described in any one of (1) to (6) above and a housing.

[0016] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may themselves be a semiconductor device or may have a semiconductor device.

[0017] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0018] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0019] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0020] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0021] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0022] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0023] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be rephrased as "resistance", "load", "region having a resistance value", and the like, and conversely, the terms "resistance", "load", and "region having a resistance value" can be rephrased as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0024] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" includes a circuit element including a pair of electrodes and a dielectric included between the electrodes. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like may be rephrased as "capacitance". Conversely, the term "capacitance" may be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" may be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the electrostatic capacitance may be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0025] In addition, in this specification, etc., a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, etc., the terms source and drain may be rephrased. In addition, in this specification, etc., when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, etc., one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0026] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0027] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0028] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0029] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0030] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0031] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0032] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulating body".

[0034] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wiring" are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0035] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0036] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When an impurity is contained, for example, the defect level density in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, a transition metal other than the main component, and in particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, oxygen, a Group 1 element other than hydrogen, a Group 2 element, a Group 13 element, a Group 15 element, and the like.

[0037] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0038] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0039] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0040] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0041] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with a large data capacity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a memory device including the novel semiconductor device can be applied. According to one embodiment of the present invention, an electronic device including the memory device can be provided.

[0042] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0043] FIG. 1 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. 2A and 2B are top views for explaining a configuration example of a semiconductor device. 3A to 3C are cross-sectional views for explaining configuration examples of a semiconductor device. 4A and 4B are top views for explaining a configuration example of a semiconductor device. 5A and 5B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 6A and 6B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 7A and 7B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 8A and 8B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 9A and 9B are cross-sectional views for explaining a manufacturing example of a semiconductor device. FIG. 10A is a cross-sectional view for explaining a manufacturing example of a semiconductor device, and FIG. 10B is a perspective view for explaining the manufacturing example of a semiconductor device. 11A and 11B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 12A and 12B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 13A and 13B are cross-sectional views for explaining a manufacturing example of a semiconductor device. FIG. 14A is a cross-sectional view illustrating a configuration example of a semiconductor device, and FIG. 14B is a cross-sectional view illustrating a manufacturing example of the semiconductor device. 15A and 15B are top views for explaining a configuration example of a semiconductor device. FIG. 16 is a cross-sectional view for explaining a configuration example of a semiconductor device. 17A and 17B are top views for explaining a configuration example of a semiconductor device. FIG. 18 is a cross-sectional view for explaining a configuration example of a semiconductor device. 19A and 19B are top views for explaining a configuration example of a semiconductor device. FIG. 20 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 21 is a top view illustrating a configuration example of a semiconductor device. FIG. 22 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 23 is a top view illustrating a configuration example of a semiconductor device. FIG. 24 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 25 is a top view illustrating a configuration example of a semiconductor device. FIG. 26 is a cross-sectional view for explaining a configuration example of a semiconductor device. 27A and 27B are top views for explaining a configuration example of a semiconductor device. FIG. 28 is a cross-sectional view for explaining a configuration example of a semiconductor device. 29A and 29B are top views for explaining a configuration example of a semiconductor device. 30A to 30C are cross-sectional views for explaining configuration examples of a semiconductor device. 31A and 31B are top views for explaining a configuration example of a semiconductor device. 32A and 32B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 33A and 33B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 34A and 34B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 35A and 35B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 36A and 36B are cross-sectional views for explaining a manufacturing example of a semiconductor device. FIG. 37A is a cross-sectional view for explaining a manufacturing example of a semiconductor device, and FIG. 37B is a perspective view for explaining the manufacturing example of a semiconductor device. 38A and 38B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 39A and 39B are cross-sectional views for explaining a manufacturing example of a semiconductor device. 40A and 40B are cross-sectional views for explaining a manufacturing example of a semiconductor device. FIG. 41 is a cross-sectional view for explaining a manufacturing example of a semiconductor device. FIG. 42A is a cross-sectional view illustrating a configuration example of a semiconductor device, and FIG. 42B is a cross-sectional view illustrating a manufacturing example of the semiconductor device. 43A and 43B are top views for explaining a configuration example of a semiconductor device. FIG. 44 is a cross-sectional view for explaining a configuration example of a semiconductor device. 45A and 45B are top views for explaining a configuration example of a semiconductor device. FIG. 46 is a cross-sectional view for explaining a configuration example of a semiconductor device. 47A and 47B are top views for explaining a configuration example of a semiconductor device. FIG. 48 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 49 is a top view for explaining a configuration example of a semiconductor device. FIG. 50 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 51 is a top view for explaining a configuration example of a semiconductor device. FIG. 52 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 53 is a top view for explaining a configuration example of a semiconductor device. FIG. 54 is a cross-sectional view for explaining a configuration example of a semiconductor device. 55A and 55B are top views for explaining a configuration example of a semiconductor device. 56A and 56B are top views for explaining a configuration example of a semiconductor device. 57A and 57B are top views for explaining a configuration example of a semiconductor device. 58A and 58B are top views for explaining a configuration example of a semiconductor device. FIG. 59A is a diagram for explaining the classification of IGZO crystal structures, FIG. 59B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 59C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. 60A and 60B are circuit diagrams showing configuration examples of a semiconductor device. FIG. 61 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 62 is a circuit diagram showing a configuration example of a semiconductor device. 63A and 63B are timing charts showing an example of the operation of the semiconductor device. 64A and 64B are timing charts showing an example of the operation of the semiconductor device. FIG. 65A is a perspective view for explaining an example of the configuration of the semiconductor device, FIG. 65B is a top view for explaining an example of the configuration of the semiconductor device, and FIG. 65C is a cross-sectional view for explaining an example of the configuration of the semiconductor device. FIG. 66A is a perspective view for explaining a configuration example of the semiconductor device, FIG. 66B is a top view for explaining the configuration example of the semiconductor device, and FIG. 66C is a cross-sectional view for explaining the configuration example of the semiconductor device. 67A and 67B are cross-sectional views for explaining a configuration example of a semiconductor device. 68A and 68B are cross-sectional views for explaining a configuration example of a semiconductor device. FIG. 69 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 70 is a cross-sectional view for explaining a configuration example of a semiconductor device. FIG. 71A is a top view for explaining a configuration example of a semiconductor device, and FIGS. 71B to 71D are cross-sectional views for explaining the configuration example of the semiconductor device. 72A to 72C are perspective views for explaining configuration examples of a semiconductor device. FIG. 73 is a top view for explaining a configuration example of a semiconductor device. FIG. 74 is a block diagram for explaining an example of a storage device. FIG. 75A is a perspective view showing an example of a semiconductor wafer, FIG. 75B is a perspective view showing an example of a chip, and FIGS. 75C and 75D are perspective views showing an example of an electronic component. FIG. 76 is a block diagram illustrating the CPU. 77A to 77J are perspective views or schematic diagrams for explaining an example of a product. 78A to 78E are perspective views or schematic diagrams for explaining an example of a product. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0045] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0046] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0047] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0048] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0049] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0050] The embodiments described in this specification will be described with reference to the drawings. However, it is possible to implement the embodiments in many different ways, and it is easily understood by those skilled in the art that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views and the like, the description of some components may be omitted in order to ensure the clarity of the drawings.

[0051] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0052] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0053] (Embodiment 1) In this embodiment, a structure example of a semiconductor device that functions as a memory device according to one embodiment of the present invention and a manufacturing method of the semiconductor device will be described. Note that this embodiment deals with a semiconductor device that has a cell transistor including a charge storage layer.

[0054] <Configuration Example 1 of Semiconductor Device> The configuration of a semiconductor device having cell transistors CTrA and CTrB will be described with reference to Figures 1, 2A, and 2B. Figure 1 is a cross-sectional view of the semiconductor device. Figure 2A is a top view of a portion of dashed line M1-M2 shown in Figure 1, and Figure 2B is a top view of a portion of dashed line M3-M4 shown in Figure 1. Note that in the cross-sectional view of Figure 1, the top view of Figure 2A, and the top view of Figure 2B, some elements are omitted for clarity.

[0055] In FIG. 1, the semiconductor device has an insulator 411A arranged above a substrate (not shown), an insulator 411B arranged above insulator 411A, and an insulator 411C arranged above insulator 411B.

[0056] The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon, semiconductor substrates made of germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and the like. Examples of semiconductor substrates include semiconductor substrates having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides and substrates having metal oxides. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0057] A flexible substrate may be used as the substrate. As a method for providing a transistor on a flexible substrate, a method may be used in which a transistor is formed on a non-flexible substrate, and then the transistor is peeled off and transferred to a substrate that is a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. As the substrate, a sheet, film, or foil in which fibers are woven may be used. The substrate may also have elasticity. The substrate may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The substrate has a region with a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. By making the substrate thin, the weight of a semiconductor device having a transistor can be reduced. By making the substrate thin, even when glass or the like is used, the substrate may have elasticity or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate due to a drop or the like. That is, a robust semiconductor device can be provided.

[0058] As the flexible substrate, for example, a metal, an alloy, a resin, a glass, or a fiber thereof can be used. The lower the linear expansion coefficient of the flexible substrate, the more preferable it is, since deformation due to the environment is suppressed. As the flexible substrate, for example, a substrate having a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid, in particular, has a low linear expansion coefficient and is therefore suitable for use as a flexible substrate.

[0059] In the manufacturing example described in this embodiment mode, since a heat treatment is included in the process, it is preferable to use a material having high heat resistance and a low thermal expansion coefficient as the substrate.

[0060] 1, 2A, and 2B, the semiconductor device has a region 491. The region 491 is a region in which an opening is formed during a manufacturing process of the semiconductor device, and an insulator, a conductor, a semiconductor, or the like is formed in the opening through the manufacturing process of the semiconductor device. Note that the opening can be a cylindrical opening, for example, as shown in FIG. 2A and FIG. 2B. In FIG. 2B, for example, in the region 491, an insulator 412a (insulator 412b, insulator 412c), a conductor 431a (conductor 431b, conductor 431c), a material layer 451a (material layer 451b, material layer 451c), a material layer 452, an insulator 413, and a conductor 432 are arranged in this order from the side surface of the opening.

[0061] The semiconductor device also includes a region 492A and a region 492B. The regions 492A and 492B are regions in which openings are formed during a manufacturing process of the semiconductor device, and an insulator, a conductor, or the like is formed in the openings through the manufacturing process of the semiconductor device. Note that the openings can be slit-shaped openings, for example, as shown in FIG. 2A and FIG. 2B. The region 492A includes a part of the material layer 453, a part of the insulator 414, a part of the insulator 421, a part of the insulator 415, a part of the conductor 434a, a part of the conductor 434b, and the insulator 416A. The region 492B includes a part of the material layer 453, a part of the insulator 414, a part of the insulator 421, a part of the insulator 415, a part of the conductor 434a, a part of the conductor 434b, and the insulator 416B. 1, a part of conductor 434a, a part of insulator 414, a part of insulator 421, and a part of insulator 415 are disposed between insulator 411A and insulator 411B. A part of an area of ​​conductor 434b, a part of insulator 414, a part of insulator 421, and a part of insulator 415 are disposed between insulator 411B and insulator 411C.

[0062] Moreover, the material layer 452 has a region 471 and a region 472. The region 471 is located adjacent to the material layer 453, and the region 472 is located adjacent to the material layer 451a (material layer 451b, material layer 451c). Note that the region 471 becomes a channel formation region of the cell transistor CTrA (cell transistor CTrB) in the manufacturing process of the semiconductor device, and the region 472 becomes a low resistance region in the manufacturing process of the semiconductor device.

[0063] In the cell transistor CTrB, the conductor 434b functions as a first gate electrode and a word line that applies a potential to the first gate electrode, the insulator 415 surrounded by the conductor 434b in FIG. 2A functions as a gate insulating film, the insulator 421 surrounded by the conductor 434b in FIG. 2A functions as a charge storage layer, and the insulator 414 surrounded by the conductor 434b functions as a tunnel insulating film. The conductor 431b functions as one of the source electrode and the drain electrode, and the conductor 431c functions as the other of the source electrode and the drain electrode. In FIG. 2A, the region of the material layer 452 surrounded by the conductor 434b functions as a channel formation region. Depending on the material contained in the material layer 453, the region of the material layer 453 in contact with the material layer 452 may also function as a channel formation region. The insulator 413 functions as a gate insulating film, and the conductor 432 functions as a second gate electrode and a wiring that applies a potential to the second gate electrode.

[0064] 2A, the conductor 434b can be replaced with the conductor 434a to be regarded as a top view of the cell transistor CTrA. In the cell transistor CTrA, the conductor 434a functions as a first gate electrode and a word line that applies a potential to the first gate electrode, the insulator 415 surrounded by the conductor 434a in FIG. 2A functions as a first gate insulating film, the insulator 421 surrounded by the conductor 434a in FIG. 2A functions as a charge storage layer, and the insulator 414 surrounded by the conductor 434a in FIG. 2A functions as a tunnel insulating film. The conductor 431a functions as one of the source electrode or the drain electrode, and the conductor 431b functions as the other of the source electrode or the drain electrode. In FIG. 2A, the region of the material layer 452 surrounded by the conductor 434a functions as a channel formation region. Depending on the material contained in the material layer 453, the region of the material layer 453 in contact with the material layer 452 may also function as a channel formation region. The insulator 413 functions as a second gate insulating film, and the conductor 432 functions as a second gate electrode and a wiring for applying a potential to the second gate electrode.

[0065] As an example, the insulator 412a functions as a barrier insulating film that suppresses the diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.) from the insulator 411A into the conductor 431a. In other words, the insulator 412a can suppress the effect of the impurities on the conductor 431a. Similarly, as an example, the insulator 412b functions as a barrier insulating film that suppresses the diffusion of impurities from the insulator 411B into the conductor 431b, and the insulator 412c functions as a barrier insulating film that suppresses the diffusion of impurities from the insulator 411C into the conductor 431c.

[0066] In this specification and the like, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0067] Next, the material layer 451a (material layer 451b, material layer 451c), the material layer 452, and the material layer 453 included in the cell transistor CTrA and the cell transistor CTrB will be described.

[0068] For example, the material layer 451a functions as a barrier film that suppresses diffusion of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.) into the material layer 452. By providing the material layer 451a having the function of suppressing impurity permeation between the material layer 452 and the conductor 431a, it is possible to reduce the electrical resistance between the material layer 452 and the conductor 431a. Similarly, for example, the material layer 451b functions as a barrier film that suppresses diffusion of impurities from the material layer 452 to the conductor 431b, and the material layer 451c functions as a barrier film that suppresses diffusion of impurities from the material layer 452 to the conductor 431c.

[0069] 1 are OS transistors, it is preferable to use, for example, a metal oxide that functions as an oxide semiconductor for the material layer 452, and it is preferable to use, for example, a material containing a metal element and oxygen contained in the metal oxide for the material layer 451a (material layer 451b, material layer 451c). It is also preferable to use, for example, a material containing a metal element and oxygen contained in the metal oxide for the material layer 453, similar to the material layer 451.

[0070] In addition, when the cell transistor CTrA and the cell transistor CTrB in FIG. 1 are OS transistors, in the material layer 452, the region 471 functioning as a channel formation region has a larger oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V O Since the region 471 has a low impurity concentration or low oxygen vacancy, it is a high resistance region with a low carrier concentration. Therefore, the region 471 can be said to be i-type (intrinsic) or substantially i-type.

[0071] A transistor using a metal oxide has impurities or oxygen vacancies (V O ), electrical characteristics are likely to fluctuate and reliability may decrease. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H.) and generate electrons that serve as carriers. For this reason, if oxygen vacancies are present in a region in an oxide semiconductor in which a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region in an oxide semiconductor in which a channel is formed, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0072] 1 are OS transistors, the material layer 452 is preferably a multi-layer structure including a material layer 452A and a material layer 452B as shown in Fig. 3A. Fig. 3A is an enlarged view of the region in which the cell transistor CTrA in Fig. 1 is formed.

[0073] The material layer 451a (material layer 451b, material layer 451c), material layer 452A, material layer 452B, and material layer 453 formed in a later step can be made of one or more materials selected from indium, element M (element M can be, for example, aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.), and zinc. In particular, metal oxides containing indium, gallium, and zinc have a high band gap and function as intrinsic (also called I-type) or substantially intrinsic semiconductors.

[0074] The cell transistors CTrA and CTrB, whose channel formation regions contain the metal oxide, have a characteristic of having a very low off-state current, which means that the leakage current in the cell transistors CTrA and CTrB in the off-state can be reduced, and therefore the power consumption of the semiconductor device can be reduced in some cases.

[0075] For example, a metal oxide having element M may be used as material layer 451a (material layer 451b, material layer 451c). It is preferable that material layer 451a (material layer 451b, material layer 451c) has a higher concentration of element M than material layer 452B. Gallium oxide may be used as material layer 451a (material layer 451b, material layer 451c). A metal oxide such as In (indium)-M-Zn (zinc) oxide may be used as material layer 451a (material layer 451b, material layer 451c). Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 451a (material layer 451b, material layer 451c) is larger than the atomic ratio of element M to In in the metal oxide used in material layer 452B. Moreover, the thickness of the material layer 451a (material layer 451b, material layer 451c) is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Moreover, the material layer 451a (material layer 451b, material layer 451c) is preferably crystalline. When the material layer 451a (material layer 451b, material layer 451c) is crystalline, the release of oxygen in the material layer 452A and the material layer 452B can be suitably suppressed. For example, if the material layer 451a (material layer 451b, material layer 451c) has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the material layer 452A and the material layer 452B may be suppressed.

[0076] Also, for example, material layer 452A and material layer 452B are preferably oxides having different chemical compositions. Specifically, the atomic ratio of element M to the metal element as the main component in the metal oxide used in material layer 452B is preferably larger than the atomic ratio of element M to the metal element as the main component in the metal oxide used in material layer 452A. Also, the atomic ratio of element M to In in the metal oxide used in material layer 452B is preferably larger than the atomic ratio of element M to In in the metal oxide used in material layer 452A. Also, material layer 452B may have the same composition as material layer 451a (material layer 451b, material layer 451c).

[0077] Also, for example, the atomic ratio of element M to the metal element that is the main component of material layer 453 may be greater than the atomic ratio of element M to the metal element that is the main component of the metal oxide used in material layer 452A. Also, the atomic ratio of element M to In in the metal oxide used in material layer 453 may be greater than the atomic ratio of element M to In in the metal oxide used in material layer 452A. Also, material layer 453 may have the same composition as material layer 452A.

[0078] 1 are OS transistors, the material layer 453 may be a multi-layer structure including a material layer 453A and a material layer 453B, as shown in FIG 3B. FIG 3B is an enlarged view of the region in which the cell transistor CTrA in FIG 1 is formed.

[0079] It is preferable that material layer 453A and material layer 453B are oxides having different chemical compositions. Specifically, the atomic ratio of element M to the main component metal element in the metal oxide used for material layer 453B is greater than the atomic ratio of element M to the main component metal element in the metal oxide used for material layer 453A. Also, material layer 453B may have the same composition as material layer 451a (material layer 451b, material layer 451c).

[0080] In addition, in the cell transistor CTrA shown in Fig. 3B, when the material layer 452 has the material layer 452A and the material layer 452B as shown in Fig. 3A, that is, when the material layer 452 has the material layer 452A and the material layer 452B and the material layer 453 has the material layer 453A and the material layer 453B as shown in Fig. 3C, the atomic ratio of the element M to the main component metal element in the metal oxide used in the material layer 452B is preferably larger than the atomic ratio of the element M to the main component metal element in each of the metal oxides used in the material layers 452A and 453A. In addition, the atomic ratio of the element M to the main component metal element in the metal oxide used in the material layer 453B is preferably larger than the atomic ratio of the element M to the main component metal element in each of the metal oxides used in the material layers 452A and 453A. In addition, the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 451a (material layer 451b, material layer 451c) is preferably greater than the atomic ratio of element M to the main component metal element in each of the metal oxides used in material layers 452A and 453A.

[0081] In this case, the compositions of material layer 451a (material layer 451b, material layer 451c), material layer 452B, and material layer 453B may be the same as each other. Also, material layer 453A may have the same composition as material layer 452A.

[0082] Here, the metal oxide contained in material layer 452A, material layer 452B, and material layer 453 in the cell transistor CTrA shown in FIG. 3A or FIG. 3C is assumed to be a metal oxide containing In, gallium (hereinafter, abbreviated as Ga), and zinc (hereinafter, abbreviated as Zn), and specific examples of atomic ratios of In, Ga, and Zn in metal oxides that can be applied to material layer 452A, material layer 452B, and material layer 453, respectively, will be described.

[0083] For example, the material layer 452B may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or In:Ga:Zn=1:1:0.5. For example, the material layer 452A may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or In:Ga:Zn=1:1:1. For example, the material layer 453 may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or an atomic ratio of Ga and Zn of Ga:Zn=2:1 or Ga:Zn=2:5.

[0084] 3C, a specific example of the case where the material layer 453 has a laminated structure may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of Ga:Zn=2:5 ...1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2: Alternatively, a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a value close to this may be used for the material layer 453A, and gallium oxide may be used for the material layer 453B.

[0085] Also, for example, when the atomic ratio of In to element M in the metal oxide used for material layer 452B is smaller than the atomic ratio of In to element M in the metal oxide used for material layer 452A, an In-Ga-Zn oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, In:Ga:Zn=10:1:3 or thereabouts, or the like, can be used as material layer 452A.

[0086] As a composition other than those mentioned above, for example, a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these may be used for the material layer 452A. Alternatively, for example, indium oxide may be used for the material layer 452A.

[0087] It is preferable to combine these material layers 451a (material layers 451b and 451c), 452A, 452B, and 453 (material layers 453A and 453B) so as to satisfy the above-mentioned atomic ratio relationship. For example, in the case of the cell transistor CTrA in FIG. 3A, it is preferable to make the material layers 452B and 453 metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close thereto, and the material layer 452A metal oxides having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close thereto. For example, in the case of the cell transistor CTrA in FIG. 3C, it is preferable that the material layer 452B and the material layer 453B are made of a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition close thereto, and the material layer 452A is made of a metal oxide having a composition of In:Ga:Zn=4:2:z, where z is 3 or more and 4.1 or less or a composition close thereto. The above composition indicates the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. It is also preferable to increase the ratio of In in the composition of the material layer 452A, since this can increase the on-current or field effect mobility of the transistor.

[0088] By the way, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide in which the atomic ratio is In:Ga:Zn=A:B:C (A+B+C=1) if a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≦r 2where r can be, for example, 0.20, preferably 0.10, and more preferably 0.05.

[0089] Under such conditions, by arranging material layer 452A so as to be in contact with material layer 452B, it is possible to suppress the diffusion of impurities and oxygen from insulator 413 and / or conductor 432 to material layer 452A via material layer 452B. Similarly, by arranging material layer 453B so as to be in contact with material layer 452B, it is possible to suppress the diffusion of impurities and oxygen from insulator 414, insulator 421, insulator 415, conductor 434a (conductor 434b), insulator 416A, etc. to material layer 453A and material layer 452A via material layer 453B. Similarly, by arranging material layer 451a (material layer 451b, material layer 451c) so as to be in contact with material layer 452A, it is possible to suppress diffusion of impurities and oxygen from conductor 431a (conductor 431b, conductor 431c), insulator 412a (insulator 412b, insulator 412c), insulator 411A (insulator 411B, insulator 411C), etc., to material layer 452A via material layer 451a (material layer 451b, material layer 451c).

[0090] In addition, when a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) is applied as the cell transistor CTrA and the cell transistor CTrB in FIG. 1, the material layer 452 can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0091] In addition, when Si transistors are applied to the cell transistors CTrA and CTrB, the material layer 452 may be a single layer or a multi-layer structure as shown in Fig. 3A and Fig. 3C. In the fabrication examples in this specification and the like, the material layer 452 is described as a single layer.

[0092] The material applicable to the material layer 453 may be a metal oxide applicable to the material layer 451 and / or the material layer 452, or a material functioning as a tunnel insulating film, for example, a material applicable to the insulator 414 described later in detail. Note that the material layer 453 may be a multi-layer structure or a single layer structure as shown in FIGS. 3B and 3C.

[0093] When the cell transistor CTrA and the cell transistor CTrB are Si transistors, the material layer 451 is preferably, for example, a conductor containing impurities (elements or ions) for diffusing into the interface of the material layer 452 on the formation surface of the material layer 451 and into the region near the interface.

[0094] The conductor can be made of a material containing one or more metal elements selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.

[0095] Moreover, when the cell transistor CTrA and the cell transistor CTrB are configured as n-type transistors, the impurity is an n-type impurity (donor). For example, phosphorus, arsenic, etc. can be used as the n-type impurity. Moreover, in this example of the manufacturing method, when the cell transistor CTrA and the cell transistor CTrB are configured as p-type transistors, the impurity is a p-type impurity (acceptor). For example, boron, aluminum, gallium, etc. can be used as the p-type impurity.

[0096] The material layer 451 may be made of a material capable of forming a silicide at the interface with the material layer 452 on the formation surface of the material layer 451 and in a region near the interface. Examples of materials capable of forming a silicide include nickel, cobalt, molybdenum, tungsten, and titanium.

[0097] 1, 2A, and 2B show a configuration in which one region 491 is provided between the region 492A and the region 492B, but one embodiment of the present invention is not limited to this. For example, one embodiment of the present invention may have a configuration in which multiple regions 491 are provided between the region 492A and the region 492B.

[0098] A specific example of the configuration is shown in FIG. 4A. FIG. 4A shows a top view of a semiconductor device in which a plurality of regions 491 are provided. Note that this top view is a top view of the semiconductor device in FIG. 1 along the dashed line M3-M4, and is an expanded view in which a plurality of regions 491 are provided. The semiconductor device shown in FIG. 4A has a plurality of regions 492 in a slit shape, and a plurality of regions 491 are provided between adjacent regions 492. For example, the regions 491 may be arranged in a line in a direction having an angle with respect to the slit-shaped region 492. Alternatively, the regions 491 may be arranged in a staggered manner. Note that the region 492 does not have to be slit-shaped, and may instead be, for example, cylindrical. FIG. 4B shows a configuration in which a cylindrical opening is provided in the region 494 instead of the slit-shaped opening formed in the region 492, and the material layer 453 and the insulators 414 to 416 are formed in the region 494. The shape of region 494 is not limited to a cylinder, and may be a columnar shape with a bottom surface that is any two-dimensional shape such as an ellipse or a polygon. Regions 494 may be positioned along rows in two or more different directions, rather than along a row in one direction like region 492 in Fig. 4A. Alternatively, region 494 may be positioned without following the regularity described above.

[0099] <<Semiconductor device manufacturing example 1>> Next, an example of a method for manufacturing the semiconductor device shown in FIGS. 1, 2A, and 2B will be described.

[0100] First, the laminate 400 shown in Fig. 5A is fabricated. The laminate 400 has, as an example, an insulator 411A, a sacrificial layer 401A, an insulator 411B, a sacrificial layer 401B, and an insulator 411C. The insulator 411A is disposed above a substrate (not shown), the sacrificial layer 401A is disposed on the insulator 411A, the insulator 411B is disposed on the sacrificial layer 401A, the sacrificial layer 401B is disposed on the insulator 411B, and the insulator 411C is disposed on the sacrificial layer 401B.

[0101] Various materials can be used for the sacrificial layer 401A and the sacrificial layer 401B. For example, silicon nitride, silicon oxide, aluminum oxide, etc. may be used as an insulator. Alternatively, silicon, gallium, germanium, etc. may be used as a semiconductor. Alternatively, aluminum, copper, titanium, tungsten, tantalum, etc. may be used as a conductor. In other words, for the sacrificial layer 401A and the sacrificial layer 401B, a material that can obtain an etching selectivity with respect to the materials used in other parts may be used.

[0102] The insulators 411A to 411C are preferably made of a material with a reduced concentration of impurities such as water or hydrogen. For example, the amount of desorption of hydrogen from the insulators 411A to 411C, calculated as hydrogen molecules, is 2×10 per area of ​​any one of the insulators 411A to 411C in the range of 50° C. to 500° C., as measured by thermal desorption spectroscopy (TDS). 15 molecules / cm 2 Less than or equal to 1×10 15 molecules / cm 2 Less than or equal to 5×10 14 molecules / cm 2 The following may be used. The insulators 411A to 411C may be formed using an insulator that releases oxygen when heated. However, materials that can be used for the insulators 411A to 411C are not limited to those described above.

[0103] As the insulators 411A to 411C, for example, a single layer or a stack of insulators containing one or more materials selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. may be used. Also, for example, a material containing silicon oxide or silicon oxynitride may be used. However, materials that can be used for the insulators 411A to 411C are not limited to those described above.

[0104] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0105] In the next step, as shown in FIG. 5B, an opening is formed in a region 491 in the laminate 400 shown in FIG. 5A by, for example, forming a resist mask and performing an etching process.

[0106] The resist mask can be formed by, for example, a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced in some cases. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used.

[0107] Next, as shown in FIG. 6A, an insulator 412 is formed on the side surfaces of the opening of region 491 so as to cover insulators 411A to 411C, sacrificial layer 401A, and sacrificial layer 401B.

[0108] 1 in a later step. Therefore, in this specification and the like, the term "insulator 412" may be replaced with the term "insulator 412a," "insulator 412b," and "insulator 412c" as appropriate.

[0109] As described above, the insulator 412 preferably functions as a barrier insulating film that suppresses diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.)) from the insulator 411A (insulator 411B, insulator 411C) into the material layer 452. In particular, the insulator 412 is preferably a barrier insulating film that prevents the penetration of oxygen atoms or oxygen molecules.

[0110] As the insulator 412, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. In particular, when an oxide semiconductor described later is used as the material layer 452, for example, it is preferable to use aluminum oxide or the like, which has a high function of capturing and fixing hydrogen, as the insulator 412. This can suppress impurities such as water and hydrogen from diffusing from the insulator 411A (insulator 411B, insulator 411C) side to the material layer 452 through the conductor 431a (conductor 431b, conductor 431c) and the material layer 451a (material layer 451b, material layer 451c) in FIG. 1.

[0111] 1, 2B, and 6A, the insulator 412 is illustrated as a single layer; however, one embodiment of the present invention is not limited to this. The insulator 412 illustrated in FIGS. 1, 2B, and 6A may have a structure in which, for example, a plurality of layers of the above-mentioned materials are stacked. For example, in FIGS. 1 and 2B, silicon oxide may be used for the insulator 412 in contact with the conductor 431a (conductor 431b and conductor 431c), and aluminum oxide, hafnium oxide, or the like may be used for the insulator 412 in contact with the insulator 411A (insulator 411B and insulator 411C).

[0112] Subsequently, as shown in FIG. 6B, a conductor 431 is formed on the surface on which the insulator 412 is formed.

[0113] 1 in a later step. Therefore, in this specification and the like, the description of the conductor 431 can be appropriately replaced with the description of the conductor 431a, the conductor 431b, and the conductor 431c.

[0114] Furthermore, as described above, the conductor 431 functions as a film for forming the conductors 431a, 431b, and 431c, and thus the conductor 431 becomes the source and drain electrodes of the cell transistors CTrA and CTrB in FIG. 1 in a later process.

[0115] The conductor 431 is preferably a material with high conductivity. As the conductor 431, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0116] In particular, when an oxide semiconductor described later is used for the material layer 452, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used as the conductor 431. In this case, the conductor 431 is preferably made of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like.

[0117] 1, 2B, and 6, the conductor 431 is illustrated as a single layer, but one embodiment of the present invention is not limited to this. The conductor 431 illustrated in FIGS. 1, 2B, and 6 may have a structure in which a plurality of layers of the above-mentioned materials are stacked, for example. Specifically, for example, the conductor 431 may have a structure in which a first layer is made of a conductive material that has a function of suppressing permeation of impurities such as water or hydrogen, and a second layer is made of a conductive material that is not easily oxidized or a material that maintains its conductivity even when it absorbs oxygen.

[0118] Then, as shown in FIG. 7A, a material layer 451 is formed on the surface on which the conductor 431 is formed.

[0119] 1 in a later step. Therefore, in this specification and the like, the description of the material layer 451 can be appropriately replaced with the material layer 451a, the material layer 451b, and the material layer 451c.

[0120] By forming the material layer 451 on the surface on which the conductor 431 is formed so as to be in contact with the material layer 451, a low resistance region may be formed in the material layer 451 near the interface with the conductor 431. In addition, by carrying out a heat treatment at this time, a compound may be formed by a component contained in the material layer 451 and a component contained in the conductor 431. In this manufacturing example, it is assumed that appropriate materials are selected for the conductor 431 and the material layer 451, respectively, so that the compound has low resistance.

[0121] For materials applicable to the material layer 451, the description of the material layer 451a (the material layer 451b and the material layer 451c) in the structural example 1 of the semiconductor device can be referred to.

[0122] Subsequently, as shown in FIG. 7B, a material layer 452 is formed on the surface on which the material layer 451 is formed.

[0123] As described above, a portion of the material layer 452 functions as a channel formation region of the cell transistor CTrA and the cell transistor CTrB in FIG.

[0124] Note that for materials that can be used for the material layer 452, the description of Structural example 1 of the semiconductor device can be referred to.

[0125] Next, as shown in FIG. 8A, an insulator 413 is deposited on the surface on which the material layer 452 is formed.

[0126] As described above, the insulator 413 functions as the second gate insulating film of each of the cell transistors CTrA and CTrB in FIG.

[0127] For example, silicon oxide or silicon oxynitride is preferably used as the insulator 413. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used as the insulator 413.

[0128] Similarly to the insulator 412, the insulator 413 preferably functions as a barrier insulating film that suppresses the permeation of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.)).

[0129] 1 are OS transistors, that is, when a metal oxide that functions as an oxide semiconductor is used as the material layer 452, for example, it is preferable to use an insulating material having a function of suppressing oxygen transmission as the insulator 413. For example, it is preferable to use silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like as the insulator 413. By forming such an insulator 413, it is possible to prevent oxygen from being released from the material layer 452 and the oxygen from diffusing into the insulator 413. This makes it possible to prevent a decrease in resistance of the material layer 452 caused by oxygen being released from the material layer 452.

[0130] For example, an insulating material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used as the insulator 412. For example, aluminum oxide can be used as the insulator 412. However, materials that can be used for the insulator 412 are not limited to those described above, and for example, a material that can be used for the insulators 411A to 411C described above as a film with a reduced concentration of impurities such as water and hydrogen can be used as the insulator 412.

[0131] 1, 2B, and 8A, the insulator 413 is illustrated as a single layer, but one embodiment of the present invention is not limited to this. The insulator 413 illustrated in FIGS. 1, 2B, and 8A may have a structure in which multiple layers of the above-mentioned materials are stacked, for example. For example, in FIGS. 1 and 2B, silicon oxide may be used for the insulator 412 in contact with the material layer 452, and aluminum oxide, hafnium oxide, or the like may be used for the insulator 412 in contact with the conductor 432.

[0132] In particular, consider the case where, for example, a metal oxide that functions as an oxide semiconductor is used as the material layer 452. For example, by forming aluminum oxide by a sputtering method, oxygen is supplied to the insulator 413, and the oxygen supplied to the insulator 413 is supplied to the material layer 452. When oxygen is supplied to the material layer 452, the amount of oxygen contained in the oxide semiconductor increases, so that a decrease in the resistance of the oxide semiconductor can be prevented.

[0133] Then, as shown in FIG. 8B, a conductor 432 is formed on the formation surface of the insulator 413 so as to fill the remaining openings in the region 491.

[0134] As described above, the conductor 432 functions as the second gate electrodes of the cell transistors CTrA and CTrB in FIG. 1, and as a wiring that applies a potential to the second gate electrodes.

[0135] The conductor 432 may be made of a material containing one or more metal elements selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. The conductor 432 may also be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

[0136] As the conductor 432, for example, a conductive material containing oxygen and a metal element contained in a metal oxide applicable to the material layer 451 or the material layer 452 may be used. The above-mentioned conductive material containing a metal element and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen mixed in from a surrounding insulator or the like may be captured in some cases.

[0137] In addition, a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen is preferably used as the conductor 432. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used, and may be formed as a single layer or a stacked layer.

[0138] The conductor 432 may have a structure in which a plurality of the above-mentioned materials are stacked. For example, the conductor 432 may have a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. The conductor 432 may have a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. The conductor 432 may have a stacked structure in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined. By applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, oxygen may be diffused in the region of the conductor in contact with the insulator. This may allow a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. Similarly, by applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may be diffused in the region of the conductor in contact with the insulator. This may allow a stacked structure in which a material containing a metal element and a conductive material containing nitrogen are combined.

[0139] 9A, in the next step, for example, a resist mask is formed and an etching process is performed on the laminate 400 to form slit-shaped openings in the regions 492A and 492B. Note that in this step, the openings in the regions 492A and 492B are described as being slit-shaped, but as shown in FIG. 4B, the openings in the regions 492A and 492B may be cylindrical.

[0140] For details of the formation of the resist mask and the etching process, please refer to the explanation of FIG. 5B.

[0141] 9B, the sacrificial layers 401A and 401B are removed from the side surfaces of the openings formed in the regions 492A and 492B by etching or the like, and the regions of the insulator 412, the conductor 431, and the material layer 451 surrounded by the sacrificial layer 401A and the regions of the insulator 412, the conductor 431, and the material layer 451 surrounded by the sacrificial layer 401B are removed to form the recesses 493A and 493B in the laminate 400. As a result, the insulator 412a (insulator 412b, insulator 412c), the conductor 431a (conductor 431b, conductor 431c), and the material layer 451a (material layer 451b, material layer 451c) are formed in the region of the material layer 452 that overlaps with the region 472.

[0142] Note that recesses 493A and 493B may be formed together with the openings of regions 492A and 492B in the manufacturing process of the semiconductor device shown in Fig. 9A. In addition, the conditions of etching and the like may be different between the steps of removing sacrificial layers 401A and 401B, a portion of the insulator 412, a portion of the conductor 431, and a portion of the material layer 451c. Therefore, in the step shown in Fig. 9B, the conditions of etching and the like may be changed depending on the material to be removed.

[0143] Incidentally, when a material having a metal oxide is applied as the material layer 452, that is, when the cell transistors CTrA and CTrB in FIG. 1 are OS transistors, after forming the openings of the regions 492A and 492B, the recesses 493A and 493B, respectively, a process may be performed to supply oxygen to the region 471 of the material layer 452 exposed in the recesses 493A and 493B from the openings of the regions 492A and 492B. In this case, FIG. 10A shows a state in which oxygen is supplied to the region 471 as a process 10. The process of supplying oxygen may be, for example, a heat treatment in an oxygen atmosphere.

[0144] Moreover, the process 10 for supplying oxygen can be, for example, a microwave process in an atmosphere containing oxygen. In this case, microwaves, high frequency such as RF, oxygen plasma, oxygen radicals, or the like are irradiated to the region 471. For the microwave process, it is preferable to use a microwave processing device having a power source for generating high density plasma using microwaves. Moreover, the microwave processing device may have a power source for applying RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. Moreover, by applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently guided to the material layer 452. Moreover, the microwave process is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Moreover, it is preferable to perform the process with an oxygen flow rate ratio (O2 / O2+Ar) of 50% or less, preferably 10% or more and 30% or less. Moreover, the process temperature may be 750° C. or less, preferably 500° C. or less, for example, about 400° C. Furthermore, after the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0145] As the process 10 for supplying oxygen, a microwave process is performed in an atmosphere containing oxygen, whereby oxygen gas is turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region 471 of the material layer 452 (material layer 452A when the cell transistor CTrA and cell transistor CTrB have the configurations shown in Figs. 3A and 3C). At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 471. That is, microwaves, high frequency waves such as RF, oxygen plasma, or the like can be applied to the region 472 shown in Fig. 10A. The V O H can be split off and hydrogen H can be removed from the region 471. That is, in the region 471, O H→H+V O )" and "V O +O→null” reaction occurs, and the hydrogen concentration in the region 471 can be reduced. Therefore, the oxygen vacancies in the region 471 and the VO H can be reduced, lowering the carrier concentration.

[0146] 10A, conductor 431a (conductor 431b, conductor 431c) are provided so as to overlap with region 472. Conductor 431a (conductor 431b, conductor 431c) blocks the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., and therefore these effects do not reach region 472. As a result, in region 472, V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0147] In this manner, the oxygen vacancies in the region 471 of the material layer 452 and the V O By removing H, the region 471 can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 472 functioning as the source region or drain region can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the cell transistors CTrA and CTrB, and suppresses variations in the electrical characteristics of the cell transistors within the semiconductor device.

[0148] In addition, when a material having silicon is applied as the material layer 452, that is, when the cell transistors CTrA and CTrB in FIG. 1 are Si transistors, after forming the openings of the regions 492A and 492B, the recesses 493A and 493B, respectively, a process of supplying impurities from the openings of the regions 492A and 492B to the region 471 of the material layer 452 exposed in the recesses 493A and 493B may be performed. In this case, FIG. 9A shows a state in which impurities are supplied to the material layer 452 exposed in the recesses 493A and 493B as a process 10. It is preferable to perform a heat treatment on the semiconductor device during the process 10. It is to be noted that, when the cell transistors CTrA and CTrB are n-type transistors, a p-type impurity (acceptor) is used as the impurity in order to make the region 471 a p-type channel formation region. For example, boron, aluminum, gallium, etc. can be used as the p-type impurity. When the cell transistor CTr is a p-type transistor, an n-type impurity (donor) is used as an impurity to make the region 471 an n-type channel formation region. For example, phosphorus, arsenic, or the like can be used as the n-type impurity.

[0149] In addition, in the material layer 452, a region not exposed to the recess 493A and the recess 493B, that is, a region 472 in contact with the material layer 451a, the material layer 451b, and the material layer 451c, may have a lower resistance than the region 471. This is because, for example, a low-resistance compound may be generated by a component contained in the conductor 431a (conductor 431b, conductor 431c) and a component of the material layer 452 near the interface with the material layer 451a (material layer 451b, material layer 451c). Or, the region 471 has a higher resistance than the region 472 due to the process 10. Therefore, the region 472 functions as a low-resistance region of the cell transistor CTrA and the cell transistor CTrB.

[0150] As described above, in the process of supplying oxygen and impurities to material layer 452, oxygen may be supplied from the terminal outlet as shown in Fig. 10B, instead of supplying from the openings of regions 492A and 492B. The process of supplying oxygen to material layer 452 may combine the supply of oxygen from the openings of regions 492A and 492B in Fig. 10A and the supply of oxygen from the terminal outlet in Fig. 10B. Fig. 10B is a perspective view of the structure shown in Fig. 10A.

[0151] In the next step, as shown in FIG. 11A, a material layer 453 is deposited on the side surfaces of the openings of regions 492A and 492B shown in FIG. 9B (the side surfaces of insulators 411A to 411C), recesses 493A, and recesses 493B.

[0152] 1 are OS transistors, the material applicable to the material layer 453 is preferably a metal oxide applicable to the material layer 451 and / or the material layer 452. For the metal oxide, refer to the description of the material layer 451 and the material layer 452 formed in the steps shown in FIGS. 7A and 7B.

[0153] The material layer 453 may have a stacked structure of a plurality of metal oxides which can be used for the material layer 451 and / or the material layer 452.

[0154] After the material layer 453 is formed, oxygen may be supplied to the material layer 453 and a region of the material layer 452 in contact with the material layer 453 by using a microwave treatment or the like as treatment 10, similar to the steps shown in FIGS. 10A and 10B (not shown).

[0155] Furthermore, when a material containing silicon is used as the material layer 452, that is, when the cell transistors CTrA and CTrB in FIG. 1 are Si transistors, the material applicable to the material layer 453 can be a metal oxide applicable to the material layer 451 and / or the material layer 452, or a material applicable to the insulator 414 described later.

[0156] 11A, the material layer 453 and the material layer 451c are illustrated as having the same thickness, but the semiconductor device according to one embodiment of the present invention is not limited to this. The thickness of the material layer 453 may be thicker or thinner than the thickness of the material layer 451c.

[0157] 11B, in the next step, an insulator 414 is formed on the side surfaces of the openings of the regions 492A and 492B shown in FIG. 11A and on the formed recesses. That is, the insulator 414 is formed on the formation surface of the material layer 453.

[0158] As described above, the insulator 414 functions as a tunnel insulating film for the cell transistor CTrA and the cell transistor CTrB.

[0159] As the insulator 414, for example, silicon oxide or silicon oxynitride is preferably used. Alternatively, as the insulator 414, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, as the insulator 414, an insulator having any of these stacked layers may be used.

[0160] After the insulator 414 is formed, oxygen may be supplied to the material layer 453 and the region of the material layer 452 in contact with the material layer 453 through the insulator 414 by using a microwave treatment or the like as treatment 10, similar to the process shown in Figures 10A and 10B (not shown).

[0161] When at least one of the material layers 451 to 453 is a material containing a metal oxide, the insulator 414 can be an insulator obtained by stacking the above-mentioned material and a material applicable to the insulator 413. In particular, by using a material having a function of suppressing permeation of impurities such as oxygen, water, and hydrogen as the insulator 414, diffusion of water or hydrogen into the material layers 451 to 453 and desorption of oxygen from the material layers 451 to 453 can be prevented in some cases. Note that when microwave treatment is performed as the process 10, for example, after silicon oxide or silicon oxynitride is formed on the formation surface of the material layer 453, the microwave treatment may be performed, and then a material having a function of suppressing permeation of impurities such as oxygen, water, and hydrogen may be formed to form the insulator 414.

[0162] In the next step, as shown in Fig. 12A, an insulator 421 is formed on the side surfaces of the openings of the regions 492A and 492B shown in Fig. 11B and on the recesses that are formed. That is, the insulator 421 is formed on the formation surface of the insulator 414.

[0163] As described above, the insulator 421 functions as a charge storage layer for the cell transistor CTrA and the cell transistor CTrB.

[0164] For example, silicon nitride or silicon nitride oxide can be used as the insulator 421. However, materials that can be used for the insulator 421 are not limited to these. As an alternative to the insulator 421, a conductor, a semiconductor, or the like can be used in some cases.

[0165] 12A, the thickness of the insulator 421 is illustrated as being substantially the same as the thickness of the material layer 451a (material layer 451b, material layer 451c), the conductor 431a (conductor 431b, conductor 431c), and the insulator 412a (insulator 412b, insulator 412c), but the semiconductor device according to one aspect of the present invention is not limited thereto. The thickness of the insulator 421 for filling a part of each of the recesses 493A and 493B may be thickened as long as the insulator 415, the conductor 434a, and the conductor 434b are formed in the recesses 493A and 493B in a later process. Also, the thickness of the insulator 421 may be thinned as long as the insulator 421 functions as a charge storage layer.

[0166] In the next step, as shown in Fig. 12B, an insulator 415 is formed on the side surfaces of the openings of the regions 492A and 492B shown in Fig. 12A and on the recesses that have been formed. That is, the insulator 415 is formed on the formation surface of the insulator 421.

[0167] As described above, the insulator 415 functions as a gate insulating film for the cell transistors CTrA and CTrB.

[0168] The insulator 415 is preferably made of, for example, silicon oxide or silicon oxynitride. The insulator 415 can be made of, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. The insulator 415 may be a stack of these materials. The insulator 415 is preferably thicker than the insulator 414. When the insulator 415 is made thicker than the insulator 414, charge can be transferred from the material layer 453 to the insulator 421 through the insulator 414.

[0169] In the next step, as shown in Fig. 13A, a conductor 434 is formed on the side surfaces of the openings of the regions 492A and 492B shown in Fig. 12B and on the formed recesses. That is, the conductor 434 is formed on the formation surface of the insulator 415.

[0170] The conductor 434 can be made of, for example, a material that can be used for the conductor 432 described above.

[0171] 13B, in the next step, the conductor 434 included in the region 492A and the region 492B is removed by forming a resist mask and performing an etching process or the like so that the conductor 434 remains only in the recessed portion described above. This forms the conductor 434a and the conductor 434b. At this time, the exposed portion of the insulator 415 may be removed.

[0172] For details of the formation of the resist mask and the etching process, please refer to the explanation of FIG. 5B.

[0173] As described above, the conductor 434a functions as the gate electrode of the cell transistor CTrA and as a word line that applies a potential to the gate electrode, and the conductor 434b functions as the gate electrode of the cell transistor CTrB and as a word line that applies a potential to the gate electrode.

[0174] In the next step, as shown in FIG. 1A, an insulator 416A is deposited to fill the opening in region 492A, and an insulator 416B is deposited to fill the opening in region 492B.

[0175] For the insulator 416A and the insulator 416B, for example, the above-mentioned material applicable to the insulator 413 can be used.

[0176] By carrying out the above-mentioned steps, the semiconductor device shown in FIG. 1A can be manufactured.

[0177] <Configuration Example 2 of Semiconductor Device> A configuration example of a semiconductor device functioning as a memory device according to one embodiment of the present invention is not limited to the configurations shown in Fig. 1, Fig. 2A, and Fig. 2B. The configuration of the semiconductor device can be changed as appropriate depending on the case, situation, or need from the circuit configurations shown in Fig. 1, Fig. 2A, and Fig. 2B.

[0178] For example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 14A, 15A, and 15B. Figure 14A is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 15A is a top view of a portion of the dashed line N1-N2 shown in Figure 14, and Figure 15B is a top view of a portion of the dashed line N3-N4 shown in Figure 14. Note that in the cross-sectional view of Figure 14, the top view of Figure 15A, and the top view of Figure 15B, some elements are omitted for clarity.

[0179] 14A, 15A, and 15B, the step shown in FIG. 14B is performed instead of the step shown in FIG. 9B, and part of the material layer 452 is removed by etching or the like to an extent that the insulator 413 is not exposed in the recesses 493A and 493B. In this manner, in the semiconductor device of one embodiment of the present invention, the material layer 452 may have a different thickness between a region 471 of the material layer 452 in which the recesses 493A and 493B are formed and a region 472 of the material layer 452 that overlaps with the conductor 431a (the conductor 431b and the conductor 431c).

[0180] <Configuration Example 3 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 16, 17A, and 17B. Figure 16 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 17A is a top view of a portion of the dashed line P1-P2 shown in Figure 16, and Figure 17B is a top view of a portion of the dashed line P3-P4 shown in Figure 16. Note that in the cross-sectional view of Figure 16, the top view of Figure 17A, and the top view of Figure 17B, some elements are omitted for clarity.

[0181] The semiconductor device in Figures 16, 17A, and 17B has a structure in which, after the process shown in Figure 13B, a resist mask is formed and an etching process is performed to remove material layer 453, insulator 414, insulator 421, insulator 415, and conductor 434 contained in region 492A and region 492B, and insulator 416A is deposited so as to fill the opening in region 492A, and insulator 416B is deposited so as to fill the opening in region 492B.

[0182] 16, 17A, and 17B are configured such that the insulator 414, the insulator 421, the insulator 415, and the material layer 453 are removed to such an extent that the conductor 434a and the conductor 434b remain after the step shown in FIG. 13B. At this time, a part of the insulators 411A to 411C may be removed. Note that FIG. 16 shows a configuration in which the material layer 453a, the insulator 414a, the insulator 421a, the insulator 415a, and the conductor 434a are formed in the recess 493A, and the material layer 453b, the insulator 414b, the insulator 421b, the insulator 415b, and the conductor 434b are formed in the recess 493B.

[0183] In addition, the etching process after the step shown in FIG. 13B may be stopped until a portion of insulator 415 is removed and insulator 414 is exposed in the opening of region 492A, or until a portion of insulator 414 is removed and material layer 453 is exposed in the opening of region 492A, and insulators 416A and 416B in FIG. 1 may be formed on the side surfaces of the openings of regions 492A and 492B, respectively (not shown).

[0184] For details of the formation of the resist mask and the etching process, please refer to the explanation of FIG. 5B.

[0185] <Configuration Example 4 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 18, 19A, and 19B. Figure 18 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 19A is a top view of a portion of the dashed line Q1-Q2 shown in Figure 18, and Figure 19B is a top view of a portion of the dashed line Q3-Q4 shown in Figure 18. Note that in the cross-sectional view of Figure 18, the top view of Figure 19A, and the top view of Figure 19B, some elements are omitted for clarity.

[0186] 18, 19A, and 19B have a configuration in which the process shown in FIG. 9B or 10A is performed by omitting the process of forming the material layer 453 in FIG. 11A and performing the processes in and after FIG. 11B. If the insulator 414 functions sufficiently as a barrier insulating film to prevent diffusion of impurities into the material layer 452, the material layer 453 does not need to be provided. In this case, since it is not necessary to provide the material layer 453, the process of manufacturing the semiconductor device can be shortened.

[0187] <Configuration Example 5 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 20 and 21. Figure 20 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 21 is a top view of a portion of dashed line R3-R4 shown in Figure 20. Note that the top view of the portion of dashed line R1-R2 shown in Figure 20 may have a configuration almost similar to that of Figure 2A. Note that in the cross-sectional view of Figure 20 and the top view of Figure 21, some elements are omitted for clarity.

[0188] The semiconductor device of Figures 20 and 21 has a configuration in which, in the step shown in Figure 6B, the step of forming material layer 451 of Figure 7A is not performed, and the steps from Figure 7B onwards are performed. If the components, impurities, etc. contained in material layer 452 do not diffuse into conductor 431a (conductor 431b, conductor 431c) and the conductivity of conductor 431a (conductor 431b, conductor 431c) does not decrease, it is not necessary to provide material layer 451 that functions as a barrier film for the components, impurities, etc. In this case, since there is no need to provide material layer 451, the process for manufacturing the semiconductor device can be shortened.

[0189] <Configuration Example 6 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 22 and 23. Figure 22 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 23 is a top view of a portion of dashed line S3-S4 shown in Figure 22. Note that the top view of the portion of dashed line S1-S2 shown in Figure 22 may have a configuration almost similar to that of Figure 2A. Note that in the cross-sectional view of Figure 22 and the top view of Figure 23, some elements are omitted for clarity.

[0190] The semiconductor device of Fig. 22 and Fig. 23 has a configuration in which the process shown in Fig. 5B is performed by omitting the process of forming the insulator 412 of Fig. 6A and performing the processes of Fig. 6B and after. If the components, impurities, etc. contained in the insulator 411A (insulator 411B, insulator 411C) do not diffuse into the conductor 431a (conductor 431b, conductor 431c) and the conductivity of the conductor 431a (conductor 431b, conductor 431c) does not decrease, it is not necessary to provide the insulator 412 that functions as a barrier insulating film for the components, impurities, etc. In this case, since there is no need to provide the insulator 412, the process for manufacturing the semiconductor device can be shortened.

[0191] <Configuration Example 7 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 24 and 25. Figure 24 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 25 is a top view of a portion of the dashed line T3-T4 shown in Figure 24. Note that the top view of the portion of the dashed line T1-T2 shown in Figure 24 may have a configuration almost similar to that of Figure 2A. Note that in the cross-sectional view of Figure 24 and the top view of Figure 25, some elements are omitted for clarity.

[0192] The semiconductor device shown in Figures 24 and 25 has a configuration in which a conductor is formed on the side surface of the opening of region 491 in the step shown in Figure 5B, and the steps from Figure 6A to Figure 7A are not performed, but the steps from Figure 7B onwards are performed. Note that a portion of the conductor is removed in the step of forming recesses 493A and 493B in Figure 9B. As a result, conductor 461a, conductor 461b, and conductor 461c shown in Figure 24 are formed.

[0193] The conductor 461a, the conductor 461b, and the conductor 461c are preferably made of a conductive material that forms a low-resistance region near the interface with the material layer 452.

[0194] For example, when the material layer 452 is made of a material containing metal oxide, the conductors 461a, 461b, and 461c each have a resistance value of 2.4×10 3 [Ω / sq] or less, preferably 1.0×10 3 The conductive material may be, for example, a metal film such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium, a nitride film such as Al-Ti nitride or titanium nitride, or an oxide film such as indium tin oxide or In-Ga-Zn oxide.

[0195] The conductors 461a, 461b, and 461c are not limited to the above-mentioned conductive materials as long as they are materials that can reduce the resistance of the material layer 452. For example, an insulator such as silicon nitride may be used instead of the conductors 461a, 461b, and 461c.

[0196] 9B, by performing heat treatment after the steps of forming recesses 493A and 493B and forming conductor 461a, conductor 461b, and conductor 461c, in a region where conductor 461a, conductor 461b, and conductor 461c are in contact with material layer 452, a compound may be formed in the vicinity of the interface between material layer 452 and conductor 461a, conductor 461b, and conductor 461c by components contained in conductor 461a, conductor 461b, and conductor 461c and components contained in material layer 452. The compound reduces the resistance of region 472 of material layer 452 in contact with conductor 461a, conductor 461b, and conductor 461c.

[0197] The heat treatment may be performed in an atmosphere containing nitrogen. The heat treatment may cause a metal element that is a component of the conductor 461a (conductor 461b and conductor 461c) to diffuse from the conductor 461a (conductor 461b and conductor 461c) to the material layer 452, or a metal element that is a component of the material layer 452 to the conductor 461a (conductor 461b and conductor 461c), and the material layer 452 and the conductor 461a, conductor 461b, and conductor 461c may form a metal compound. At this time, the metal element of the material layer 452 may be alloyed with the metal elements of the conductor 461a, conductor 461b, and conductor 461c. When the metal elements of the material layer 452 are alloyed with the metal elements of the conductor 461a, the conductor 461b, and the conductor 461c, the metal elements become relatively stable, so that a highly reliable semiconductor device can be provided.

[0198] Moreover, the heat treatment causes hydrogen in the material layer 452 to diffuse to a region 472 of the material layer 452 in contact with the conductor 461a, the conductor 461b, and the conductor 461c, and when the hydrogen enters the oxygen vacancies present in the region, the hydrogen becomes relatively stable. The hydrogen in the oxygen vacancies present in the region 471 of the material layer 452 exposed to the recesses 493A and 493B escapes from the oxygen vacancies, diffuses to the region 472, and enters the oxygen vacancies present in the region 472 of the material layer 452, and becomes relatively stable, by the heat treatment at 250° C. or higher. Thus, the resistance of the region 472 is lowered, and the region 471 is purified (reduced impurities such as water and hydrogen) to become higher in resistance.

[0199] Furthermore, for example, when the material layer 452 is made of a material containing silicon, the material layer 452 may come into contact with the conductor 461a, the conductor 461b, and the conductor 461c, and thereby impurities (such as elements and ions) contained in the conductor 461a, the conductor 461b, and the conductor 461c may diffuse into the material layer 452. In this case, depending on the situation or in some cases, it is preferable to form the recesses 493A and 493B in FIG. 9B and to perform heat treatment after the step of forming the conductors 461a, 461b, and 461c. That is, impurity regions are formed on the surfaces of the material layer 452 that come into contact with the conductors 461a, 461b, and 461c, and in the vicinity of the interfaces.

[0200] When the impurities contained in the conductors 461a, 461b, and 461c are n-type impurities (donors), an n-type impurity region may be formed in the region 472 of the material layer 452 or near the interfaces between the material layer 452 and the conductors 461a, 461b, and 461c. On the other hand, when the impurities contained in the conductors 461a, 461b, and 461c are p-type impurities (acceptors), a p-type impurity region may be formed in the region 472 of the material layer 452 or near the interfaces between the material layer 452 and the conductors 461a, 461b, and 461c. That is, as a result, carriers may be formed in the region 472 of the material layer 452 or near the interfaces between the region 472 of the material layer 452 and the conductors 461a, 461b, and 461c, and the resistance of the region 472 may be reduced.

[0201] Furthermore, by performing heat treatment, a metal silicide may be formed in the vicinity of the interface between the conductor 461a, the conductor 461b, and the conductor 461c in the region 472 of the material layer 452 and the conductor 461b, and the conductor 461c due to the conductive materials contained in the conductor 461a, the conductor 461b, and the conductor 461c and the components contained in the material layer 452. By forming a metal silicide in the vicinity of the interface between the conductor 461a, the conductor 461b, and the conductor 461c in the region 472 of the material layer 452, the resistance may be reduced in the vicinity of the interface between the conductor 461a, the conductor 461b, and the conductor 461c in the region 472 of the material layer 452.

[0202] 24 and 25, it is preferable not to perform heat treatment before the step of forming the recesses 493A and 493B and forming the conductors 461a, 461b, and 461c in FIG. 9B. This is because, in the step shown in FIG. 5B, conductors for forming the conductors 461a, 461b, and 461c are formed in the material layer 452, and if heat treatment is performed at this stage, the resistance may be reduced in the region of the material layer 452 in contact with the conductors. Therefore, in the case of manufacturing the semiconductor device of FIG. 24 and 25, it is preferable to perform the above-mentioned heat treatment after forming the recesses 493A and 493B and forming the conductors 461a, 461b, and 461c in FIG. 9B.

[0203] <Configuration Example 8 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 26, 27A, and 27B. Figure 26 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 1, 2A, and 2B. Also, Figure 27A is a top view of a portion of the dashed dotted line U1-U2 shown in Figure 26, and Figure 27B is a top view of a portion of the dashed dotted line U3-U4 shown in Figure 26. Note that in the cross-sectional view of Figure 26, the top view of Figure 27A, and the top view of Figure 27B, some elements are omitted for clarity.

[0204] The semiconductor device in FIGS. 26, 27A, and 27B has a configuration in which, in the process shown in FIG. 8A, the process of forming the conductor 432 in FIG. 8B is not performed, and the processes in and after FIG. 9A are performed.

[0205] That is, the semiconductor devices in FIGS. 26, 27A, and 27B are configured such that the second gate electrode and the wiring for applying a potential to the second gate electrode are not provided.

[0206] Note that a configuration example of a semiconductor device functioning as a memory device according to one embodiment of the present invention may be a combination of any of the above-described configuration examples 1 to 8 of the semiconductor device.

[0207] The insulators, conductors, semiconductors, material layers, and the like disclosed in this specification can be formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the PVD method include a sputtering method, a resistance heating deposition method, an electron beam deposition method, and a PLD (Pulsed Laser Deposition) method. Examples of the CVD method include a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Vapor Deposition) method and an ALD (Atomic Layer Deposition) method.

[0208] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0209] In the thermal CVD method, a source gas and an oxidant are fed simultaneously into a chamber, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the materials are reacted near or on a substrate to deposit the materials on the substrate, thereby forming a film.

[0210] In addition, in the ALD method, the chamber may be under atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, two or more types of raw material gases may be sequentially supplied to the chamber by switching each switching valve (also called a high-speed valve), and an inert gas (argon, nitrogen, etc.) may be introduced simultaneously with or after the first raw material gas so that the multiple raw material gases are not mixed, and then the second raw material gas is introduced. When the inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas may be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the first raw material gas may be exhausted by vacuum evacuation, and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction order multiple times until a desired thickness is obtained while controlling the gas introduction order, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise adjustment of the film thickness, making this method suitable for fabricating fine FETs.

[0211] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. In addition, the combination is not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0212] For example, when forming a hafnium oxide film using a film formation device that uses the ALD method, two types of gas are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0213] For example, when forming an aluminum oxide film using a film formation device that uses the ALD method, two types of gas are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0214] For example, when forming a silicon oxide film using a film formation apparatus that utilizes the ALD method, hexachlorodisilane is adsorbed onto the surface to be formed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0215] For example, when forming a tungsten film using a film forming apparatus using the ALD method, WF6 gas and B2H6 gas are repeatedly introduced in sequence to form an initial tungsten film, and then WF6 gas and H2 gas are repeatedly introduced in sequence to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0216] For example, when an oxide semiconductor film, such as an In-Ga-Zn-O film, is formed by a film forming apparatus using the ALD method, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Also, mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer may be formed using these gases. Note that, instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0217] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0218] (Embodiment 2) This embodiment describes a configuration example of a semiconductor device functioning as a memory device according to one embodiment of the present invention, which is different from that in Embodiment 1, and an example of a manufacturing method of the semiconductor device. Note that this embodiment describes a semiconductor device having a cell transistor including a floating gate electrode.

[0219] <Configuration Example 9 of Semiconductor Device> The configuration of a semiconductor device having cell transistors CTrA and CTrB will be described with reference to Fig. 28, Fig. 29A, and Fig. 29B. Fig. 28 is a cross-sectional view of the semiconductor device. Fig. 29A is a top view of a portion of dashed line A1-A2 shown in Fig. 28, and Fig. 29B is a top view of a portion of dashed line A3-A4 shown in Fig. 28. Note that in the cross-sectional view of Fig. 28, the top view of Fig. 29A, and the top view of Fig. 29B, some elements are omitted for clarity.

[0220] In FIG. 28, the semiconductor device has an insulator 311A ​​arranged above a substrate (not shown), an insulator 311B arranged above insulator 311A, and an insulator 311C arranged above insulator 311B.

[0221] For the substrate, for example, the description of the substrate in the first embodiment can be referred to.

[0222] 28, 29A, and 29B, the semiconductor device has a region 391. The region 391 is a region where an opening is formed during the manufacturing process of the semiconductor device, and an insulator, a conductor, a semiconductor, or the like is formed in the opening through the manufacturing process of the semiconductor device. Note that the opening can be a cylindrical opening, for example, as shown in FIG. 29A and FIG. 29B. In FIG. 29B, for example, insulator 312a (insulator 312b, insulator 312c), conductor 331a (conductor 331b, conductor 331c), material layer 351a (material layer 351b, material layer 351c), material layer 352, insulator 313, and conductor 332 are arranged in this order from the side surface of the opening in region 391.

[0223] The semiconductor device also has a region 392A and a region 392B. The regions 392A and 392B are regions in which openings are formed during a manufacturing process of the semiconductor device, and an insulator, a conductor, or the like is formed in the openings through the manufacturing process of the semiconductor device. Note that the openings can be slit-shaped openings, for example, as shown in FIG. 29A and FIG. 29B. The region 392A includes a part of the material layer 353, a part of the insulator 314, a part of the insulator 315, a part of the conductor 334a, a part of the conductor 334b, and an insulator 316A. The region 392B includes a part of the material layer 353, a part of the insulator 314, a part of the insulator 315, a part of the conductor 334a, a part of the conductor 334b, and an insulator 316B. 28, conductor 333a, part of conductor 334a, part of insulator 314, and part of insulator 315 are disposed between insulator 311A ​​and insulator 311B. Furthermore, conductor 333b, a partial region of conductor 334b, part of insulator 314, and part of insulator 315 are disposed between insulator 311B and insulator 311C.

[0224] Moreover, the material layer 352 has a region 371 and a region 372. The region 371 is located adjacent to the material layer 351a (material layer 351b, material layer 351c), and the region 372 is located adjacent to the material layer 353. Note that the region 371 becomes a channel formation region of the cell transistor CTrA (cell transistor CTrB) in the manufacturing process of the semiconductor device, and the region 372 becomes a low resistance region in the manufacturing process of the semiconductor device.

[0225] In the cell transistor CTrB, the conductor 334b ​​functions as a first gate electrode and a word line that applies a potential to the first gate electrode, the insulator 315 surrounded by the conductor 334b ​​in FIG. 29A functions as a gate insulating film, the conductor 333b functions as a floating gate electrode (sometimes referred to as a floating gate electrode), and the insulator 314 surrounded by the conductor 333b in FIG. 29A functions as a tunnel insulating film. The conductor 331b functions as one of the source electrode and the drain electrode, and the conductor 331c functions as the other of the source electrode and the drain electrode. In FIG. 29A, the region of the material layer 352 surrounded by the conductor 334b ​​functions as a channel formation region. Depending on the material contained in the material layer 353, the region of the material layer 353 in contact with the material layer 352 may also function as a channel formation region. The insulator 313 functions as a gate insulating film, and the conductor 332 functions as a second gate electrode and a wiring that applies a potential to the second gate electrode.

[0226] 29A, the conductor 333b is replaced with the conductor 333a, and the conductor 334b ​​is replaced with the conductor 334a, so that the cell transistor CTrA can be regarded as a top view of the cell transistor CTrA. In the cell transistor CTrA, the conductor 334a functions as a first gate electrode and a word line that applies a potential to the first gate electrode, the insulator 315 surrounded by the conductor 334a in FIG. 29A functions as a first gate insulating film, the conductor 333a functions as a floating gate electrode, and the insulator 314 surrounded by the conductor 333a in FIG. 29A functions as a tunnel insulating film. The conductor 331a functions as one of the source electrode or the drain electrode, and the conductor 331b functions as the other of the source electrode or the drain electrode. In FIG. 29A, the region of the material layer 352 surrounded by the conductor 334a functions as a channel formation region. Depending on the material contained in the material layer 353, a region of the material layer 353 in contact with the material layer 352 may also function as a channel formation region. The insulator 313 functions as a second gate insulating film, and the conductor 332 functions as a second gate electrode and a wiring that applies a potential to the second gate electrode.

[0227] The insulator 312a, for example, functions as a barrier insulating film that suppresses the diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.) from the insulator 311A ​​into the conductor 331a. In other words, the insulator 312a can suppress impurities in the conductor 331a. Similarly, the insulator 312b, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from the insulator 311B into the conductor 331b, and the insulator 312c, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from the insulator 311C into the conductor 331c.

[0228] Next, the material layer 351a (material layer 351b, material layer 351c), the material layer 352, and the material layer 353 included in the cell transistor CTrA and the cell transistor CTrB will be described.

[0229] For example, the material layer 351a functions as a barrier film that suppresses diffusion of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.) into the material layer 352. By providing the material layer 351a, which has a function of suppressing impurity permeation, between the material layer 352 and the conductor 331a, it is possible to reduce the electrical resistance between the material layer 352 and the conductor 331a. Similarly, for example, the material layer 351b functions as a barrier film that suppresses diffusion of impurities from the material layer 352 into the conductor 331b, and the material layer 351c functions as a barrier film that suppresses diffusion of impurities from the material layer 352 into the conductor 331c.

[0230] 28 are OS transistors, it is preferable to use, for example, a metal oxide that functions as an oxide semiconductor for the material layer 352, and it is preferable to use, for example, a material containing a metal element and oxygen contained in the metal oxide for the material layer 351a (material layer 351b, material layer 351c). It is also preferable to use, for example, a material containing a metal element and oxygen contained in the metal oxide for the material layer 353, similar to the material layer 351.

[0231] In addition, when the cell transistor CTrA and the cell transistor CTrB in FIG. 28 are OS transistors, in the material layer 352, the region 371 functioning as a channel formation region has a higher oxygen vacancy (V O ) or the impurity concentration is low, resulting in a high resistance region with a low carrier concentration. Therefore, region 371 can be said to be i-type (intrinsic) or substantially i-type.

[0232] 28 are OS transistors, the material layer 352 is preferably a multi-layer structure including a material layer 352A and a material layer 352B, as shown in Fig. 30A. Fig. 30A is an enlarged view of the region in which the cell transistor CTrA in Fig. 28 is formed.

[0233] The material layer 351a (material layer 351b, material layer 351c), material layer 352A, material layer 352B, and material layer 353 formed in a later step can be made of one or more materials selected from indium, element M (element M can be, for example, aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.), and zinc. In particular, metal oxides containing indium, gallium, and zinc have a high band gap and function as intrinsic (also called I-type) or substantially intrinsic semiconductors.

[0234] The cell transistors CTrA and CTrB, whose channel formation regions contain the metal oxide, have a characteristic of having a very low off-state current, which means that the leakage current in the cell transistors CTrA and CTrB in the off-state can be reduced, and therefore the power consumption of the semiconductor device can be reduced in some cases.

[0235] For example, a metal oxide having element M may be used as material layer 351a (material layer 351b, material layer 351c). It is preferable that material layer 351a (material layer 351b, material layer 351c) has a higher concentration of element M than material layer 352B. Gallium oxide may be used as material layer 351a (material layer 351b, material layer 351c). A metal oxide such as In (indium)-M-Zn (zinc) oxide may be used as material layer 351a (material layer 351b, material layer 351c). Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 351a (material layer 351b, material layer 351c) is larger than the atomic ratio of element M to In in the metal oxide used in material layer 352B. Moreover, the thickness of the material layer 351a (material layer 351b, material layer 351c) is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Moreover, the material layer 351a (material layer 351b, material layer 351c) is preferably crystalline. When the material layer 351a (material layer 351b, material layer 351c) is crystalline, it is possible to suitably suppress the release of oxygen from the material layer 352A and the material layer 352B. For example, if the material layer 351a (material layer 351b, material layer 351c) has a crystal structure such as a hexagonal crystal structure, it may be possible to suppress the release of oxygen from the material layer 352A and the material layer 352B.

[0236] Also, for example, it is preferable that the material layers 352A and 352B are oxides having different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the metal element as the main component in the metal oxide used in the material layer 352B is larger than the atomic ratio of element M to the metal element as the main component in the metal oxide used in the material layer 352A. It is preferable that the atomic ratio of element M to In in the metal oxide used in the material layer 352B is larger than the atomic ratio of element M to In in the metal oxide used in the material layer 352A. Also, the material layer 352B may have the same composition as the material layer 351a (material layer 351b, material layer 351c).

[0237] Also, for example, the atomic ratio of element M to the metal element that is the main component of material layer 353 may be greater than the atomic ratio of element M to the metal element that is the main component of the metal oxide used in material layer 352A. Also, the atomic ratio of element M to In in the metal oxide used in material layer 353 may be greater than the atomic ratio of element M to In in the metal oxide used in material layer 352A. Also, the same composition as that of material layer 352A may be used for material layer 353.

[0238] 28 are OS transistors, the material layer 353 may be a multi-layer structure including a material layer 353A and a material layer 353B, as shown in Fig. 30B. Fig. 30B is an enlarged view of the region in which the cell transistor CTrA in Fig. 28 is formed.

[0239] The material layers 353A and 353B are preferably oxides having different chemical compositions. Specifically, the atomic ratio of element M to the main component metal element in the metal oxide used in the material layer 353B is preferably larger than the atomic ratio of element M to the main component metal element in the metal oxide used in the material layer 353A. The material layer 353B may have the same composition as the material layer 351a (material layers 351b and 351c).

[0240] In addition, in the cell transistor CTrA shown in Fig. 30B, when the material layer 352 has the material layer 352A and the material layer 352B as shown in Fig. 30A, that is, when the material layer 352 has the material layer 352A and the material layer 352B and the material layer 353 has the material layer 353A and the material layer 353B as shown in Fig. 30C, the atomic ratio of the element M to the main component metal element in the metal oxide used in the material layer 352B is preferably larger than the atomic ratio of the element M to the main component metal element in each of the metal oxides used in the material layers 352A and 353A. In addition, the atomic ratio of the element M to the main component metal element in the metal oxide used in the material layer 353B is preferably larger than the atomic ratio of the element M to the main component metal element in each of the metal oxides used in the material layers 352A and 353A. In addition, it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 351a (material layer 351b, material layer 351c) is greater than the atomic ratio of element M to the main component metal element in each of the metal oxides used in material layers 352A and 353A.

[0241] In this case, the material layers 351a (material layers 351b and 351c), 352B, and 353B may have the same composition. The material layer 353A may have the same composition as the material layer 352A.

[0242] Here, the metal oxide contained in the material layer 352A, the material layer 352B, and the material layer 353 in the cell transistor CTrA shown in FIG. 30A or FIG. 30C is assumed to be a metal oxide containing In, gallium (hereinafter, abbreviated as Ga), and zinc (hereinafter, abbreviated as Zn), and specific examples of the atomic ratio of In, Ga, and Zn in the metal oxide that can be applied to each of the material layer 352A, the material layer 352B, and the material layer 353 will be described.

[0243] For example, the material layer 352B may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or In:Ga:Zn=1:1:0.5. For example, the material layer 352A may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or In:Ga:Zn=1:1:1. For example, the material layer 353 may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or an atomic ratio of Ga and Zn of Ga:Zn=2:1 or Ga:Zn=2:5.

[0244] 30C, a specific example of the case where the material layer 353 has a laminated structure may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or a metal oxide having an atomic ratio of Ga:Zn=2:5 ...1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:5 or a metal oxide having an atomic ratio of Ga:Zn=2:1 or a metal oxide having an atomic ratio of Ga:Zn=2 Alternatively, a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or a value close to this may be used for the material layer 353A, and gallium oxide may be used for the material layer 353B.

[0245] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for material layer 352B is smaller than the atomic ratio of In to element M in the metal oxide used for material layer 352A, an In-Ga-Zn oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, In:Ga:Zn=10:1:3 or thereabouts, or the like, can be used as material layer 352A.

[0246] As a composition other than those mentioned above, for example, a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these may be used for the material layer 352A. Alternatively, for example, indium oxide may be used for the material layer 352A.

[0247] It is preferable to combine these material layers 351a (material layers 351b and 351c), 352A, 352B, and 353 (material layers 353A and 353B) so as to satisfy the above-mentioned atomic ratio relationship. For example, in the case of the cell transistor CTrA in FIG. 30A, it is preferable to make the material layers 352B and 353 metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close thereto, and the material layer 352A metal oxides having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close thereto. For example, in the case of the cell transistor CTrA in FIG. 30C, it is preferable that the material layer 352B and the material layer 353B are made of a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition close thereto, and the material layer 352A is made of a metal oxide having a composition of In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1 or a composition close thereto. The above composition indicates the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. It is also preferable to increase the ratio of In as the composition of the material layer 352A, since this can increase the on-current or field effect mobility of the transistor.

[0248] By the way, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide in which the atomic ratio is In:Ga:Zn=A:B:C (A+B+C=1) if a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≦r 2where r can be, for example, 0.20, preferably 0.10, and more preferably 0.05.

[0249] Under such conditions, by arranging the material layer 352A so as to be in contact with the material layer 352B, it is possible to suppress the diffusion of impurities and oxygen from the insulator 313 and / or the conductor 332 to the material layer 352A via the material layer 352B. Similarly, by arranging the material layer 353B so as to be in contact with the material layer 352B, it is possible to suppress the diffusion of impurities and oxygen from the insulator 314, the conductor 333a (conductor 333b), the insulator 315, the conductor 334a (conductor 334b), the insulator 316A, etc. to the material layer 353A and the material layer 352A via the material layer 353B. Similarly, by arranging material layer 351a (material layer 351b, material layer 351c) so as to be in contact with material layer 352A, it is possible to suppress diffusion of impurities and oxygen from conductor 331a (conductor 331b, conductor 331c), insulator 312a (insulator 312b, insulator 312c), insulator 311A ​​(insulator 311B, insulator 311C), etc., into material layer 352A via material layer 351a (material layer 351b, material layer 351c).

[0250] Furthermore, when Si transistors are applied to the cell transistors CTrA and CTrB in FIG. 28, the material layer 352 can be, for example, amorphous silicon (hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0251] In addition, when Si transistors are applied to the cell transistors CTrA and CTrB, the material layer 352 may be a single layer or a multi-layer structure as shown in Fig. 30A and Fig. 30C. In the fabrication examples in this specification and elsewhere, the material layer 352 will be described as a single layer.

[0252] Moreover, the material applicable to the material layer 353 may be a metal oxide applicable to the material layer 351 and / or the material layer 352, or a material that functions as a tunnel insulating film, for example, a material applicable to the insulator 314 described later in detail. Note that the material layer 353 may be a multi-layer structure or a single layer structure as shown in Figs. 30B and 30C.

[0253] When the cell transistor CTrA and the cell transistor CTrB are Si transistors, the material layer 351 is preferably, for example, a conductor containing impurities (elements or ions) for diffusing into the interface of the material layer 352 on the formation surface of the material layer 351 and into the region near the interface.

[0254] The conductor can be made of a material containing one or more metal elements selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.

[0255] Moreover, when the cell transistor CTrA and the cell transistor CTrB are configured as n-type transistors, the impurity is an n-type impurity (donor). For example, phosphorus, arsenic, etc. can be used as the n-type impurity. Moreover, in this example of the manufacturing method, when the cell transistor CTrA and the cell transistor CTrB are configured as p-type transistors, the impurity is a p-type impurity (acceptor). For example, boron, aluminum, gallium, etc. can be used as the p-type impurity.

[0256] The material layer 351 may be made of a material capable of forming a silicide at the interface with the material layer 352 on the formation surface of the material layer 351 and in the region near the interface. Examples of materials capable of forming a silicide include nickel, cobalt, molybdenum, tungsten, and titanium.

[0257] 28, 29A, and 29B show a configuration in which one region 391 is provided between the region 392A and the region 392B, but one embodiment of the present invention is not limited to this. For example, one embodiment of the present invention may have a configuration in which multiple regions 391 are provided between the region 392A and the region 392B.

[0258] A specific example of the configuration is shown in FIG. 31A. FIG. 31A shows a top view of a semiconductor device in which a plurality of regions 391 are provided. Note that this top view is a top view of the semiconductor device in FIG. 28 taken along dashed line A3-A4, and is an expanded view in which a plurality of regions 391 are provided. The semiconductor device shown in FIG. 31A has a plurality of regions 392 in a slit shape, and a plurality of regions 391 are provided between adjacent regions 392. For example, the arrangement of the plurality of regions 391 may be such that the plurality of regions 391 are provided in a line or in a plurality of lines in a direction having an angle with respect to the slit-shaped region 392. As another arrangement, for example, the plurality of regions 391 may be arranged in a staggered manner. Note that the region 392 does not have to be slit-shaped, and may instead be, for example, cylindrical. FIG. 31B shows a configuration in which a cylindrical opening is provided in the region 394 instead of the slit-shaped opening formed in the region 392, and the material layer 353 and the insulators 314 to 316 are formed in the region 394. The shape of region 394 is not limited to a cylinder, and may be a columnar shape with a bottom surface that is any two-dimensional shape such as an ellipse or a polygon. Regions 394 may be positioned along rows in two or more different directions, rather than along a row in one direction like region 392 in Fig. 31A. Alternatively, region 394 may be positioned without following the regularity described above.

[0259] <<Semiconductor device manufacturing example 2>> Next, an example of a method for manufacturing the semiconductor device shown in FIGS. 28, 29A, and 29B will be described.

[0260] First, the laminate 300 shown in Fig. 32A is fabricated. The laminate 300 has, as an example, an insulator 311A, a sacrificial layer 301A, an insulator 311B, a sacrificial layer 301B, and an insulator 311C. The insulator 311A ​​is disposed above a substrate (not shown), the sacrificial layer 301A is disposed on the insulator 311A, the insulator 311B is disposed on the sacrificial layer 301A, the sacrificial layer 301B is disposed on the insulator 311B, and the insulator 311C is disposed on the sacrificial layer 301B.

[0261] Various materials can be used for the sacrificial layer 301A and the sacrificial layer 301B. For example, silicon nitride, silicon oxide, aluminum oxide, etc. may be used as an insulator. Alternatively, silicon, gallium, germanium, etc. may be used as a semiconductor. Alternatively, aluminum, copper, titanium, tungsten, tantalum, etc. may be used as a conductor. In other words, for the sacrificial layer 301A and the sacrificial layer 301B, a material that can obtain an etching selectivity with respect to the materials used in other parts may be used.

[0262] The insulators 311A ​​to 311C are preferably made of materials with reduced concentrations of impurities such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 311A ​​to 311C is calculated as 2×10 per area of ​​any one of the insulators 311A ​​to 311C when converted into hydrogen molecules in the range of 50° C. to 500° C. by thermal desorption spectroscopy (TDS). 15 molecules / cm 2 Less than or equal to 1×10 15 molecules / cm 2 Less than or equal to 5×10 14 molecules / cm 2 The insulators 311A ​​to 311C may be formed using an insulator that releases oxygen when heated. However, materials that can be used for the insulators 311A ​​to 311C are not limited to those described above.

[0263] As the insulators 311A ​​to 311C, for example, insulators containing one or more materials selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc., may be used in a single layer or a stacked layer. Also, for example, a material containing silicon oxide or silicon oxynitride may be used. However, materials that can be used for the insulators 311A ​​to 311C are not limited to those described above.

[0264] In the next step, as shown in FIG. 32B, an opening is formed in a region 391 in the laminate 300 shown in FIG. 32A by, for example, forming a resist mask and performing an etching process.

[0265] The resist mask can be formed by, for example, a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced in some cases. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used.

[0266] Next, as shown in FIG. 33A, an insulator 312 is formed on the side surface of the opening of region 391 so as to cover insulators 311A ​​to 311C, sacrificial layer 301A, and sacrificial layer 301B.

[0267] The insulator 312 functions as a film for forming the insulators 312a, 312b, and 312c in Fig. 28 in a later step. Therefore, in this specification and the like, the description of the insulator 312 may be appropriately replaced with the insulators 312a, 312b, and 312c.

[0268] As described above, the insulator 312 preferably functions as a barrier insulating film that suppresses diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.)) from the insulator 311A ​​(insulator 311B, insulator 311C) into the material layer 352. In particular, the insulator 312 is preferably a barrier insulating film that prevents the penetration of oxygen atoms or oxygen molecules.

[0269] For example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used as the insulator 312. In particular, when an oxide semiconductor described later is used as the material layer 352, it is preferable to use, for example, aluminum oxide, which has a high function of capturing and fixing hydrogen, as the insulator 312. This can suppress impurities such as water and hydrogen from diffusing from the insulator 311A ​​(insulator 311B, insulator 311C) side to the material layer 352 through the conductor 331a (conductor 331b, conductor 331c) and the material layer 351a (material layer 351b, material layer 351c) in FIG. 28.

[0270] 28, 29B, and 33A, the insulator 312 is illustrated as a single layer, but one embodiment of the present invention is not limited thereto. The insulator 312 illustrated in FIGS. 28, 29B, and 33A may have a structure in which, for example, a plurality of layers of the above-mentioned materials are stacked. For example, in FIGS. 28 and 29B, silicon oxide may be used for the insulator 312 in contact with the conductor 331a (conductor 331b, conductor 331c), and aluminum oxide, hafnium oxide, or the like may be used for the insulator 312 in contact with the insulator 311A ​​(insulator 311B, insulator 311C).

[0271] Subsequently, as shown in FIG. 33B, a conductor 331 is formed on the surface on which the insulator 312 is formed.

[0272] 28. Therefore, in this specification and the like, the description of the conductor 331 can be appropriately replaced with the description of the conductor 331a, the conductor 331b, and the conductor 331c.

[0273] Furthermore, as described above, the conductor 331 functions as a film for forming the conductors 331a, 331b, and 331c, and therefore the conductor 331 becomes the source electrode and drain electrode of the cell transistors CTrA and CTrB in FIG. 28 in a later process.

[0274] The conductor 331 is preferably a material with high conductivity. As the conductor 331, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0275] In particular, when an oxide semiconductor described later is used for the material layer 352, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used as the conductor 331. In this case, the conductor 331 is preferably made of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like.

[0276] 28, 29B, and 33, the conductor 331 is illustrated as a single layer, but one embodiment of the present invention is not limited to this. The conductor 331 illustrated in FIGS. 28, 29B, and 33 may have a structure in which, for example, a plurality of layers of the above-mentioned materials are stacked. Specifically, for example, the conductor 331 may have a structure in which a first layer is made of a conductive material that has a function of suppressing permeation of impurities such as water or hydrogen, and a second layer is made of a conductive material that is not easily oxidized or a material that maintains its conductivity even when it absorbs oxygen.

[0277] Then, as shown in FIG. 34A, a material layer 351 is formed on the surface on which the conductor 331 is formed.

[0278] 28. Therefore, in this specification and the like, the material layer 351 can be appropriately replaced with the material layer 351a, the material layer 351b, and the material layer 351c.

[0279] By forming the material layer 351 on the surface on which the conductor 331 is formed so as to be in contact with the material layer 351, a low resistance region may be formed in the material layer 351 near the interface with the conductor 331. In addition, by carrying out a heat treatment at this time, a compound may be formed by the components contained in the material layer 351 and the components contained in the conductor 331. In this manufacturing example, it is assumed that appropriate materials are selected for the conductor 331 and the material layer 351, respectively, so that the compound has low resistance.

[0280] For materials applicable to the material layer 351, the description of the material layer 351a (the material layer 351b and the material layer 351c) in the ninth structural example of the semiconductor device may be referred to.

[0281] Subsequently, as shown in FIG. 34B, a material layer 352 is formed on the surface on which the material layer 351 is formed.

[0282] As described above, a partial region of the material layer 352 functions as a channel formation region of the cell transistor CTrA and the cell transistor CTrB in FIG.

[0283] For materials that can be used for the material layer 352, the description of Structural Example 9 of the semiconductor device can be referred to.

[0284] Next, as shown in FIG. 35A, an insulator 313 is formed on the surface on which the material layer 352 is formed.

[0285] As described above, the insulator 313 functions as the second gate insulating film of each of the cell transistors CTrA and CTrB in FIG.

[0286] It is preferable to use, for example, silicon oxide or silicon oxynitride as the insulator 313. Furthermore, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used as the insulator 313.

[0287] Similarly to the insulator 312, the insulator 313 preferably functions as a barrier insulating film that suppresses the permeation of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (NO, NO, NO, etc.)).

[0288] 28 are OS transistors, that is, when a metal oxide functioning as an oxide semiconductor is used as the material layer 352, for example, it is preferable to use an insulating material having a function of suppressing oxygen permeation as the insulator 313. For example, it is preferable to use silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like as the insulator 313. By forming such an insulator 313, it is possible to prevent oxygen from being released from the material layer 352 and the oxygen from diffusing into the insulator 313. This makes it possible to prevent the resistance of the material layer 352 from decreasing due to oxygen being released from the material layer 352.

[0289] For example, an insulating material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used as the insulator 312. For example, aluminum oxide or the like can be used as the insulator 312. However, materials that can be used for the insulator 312 are not limited to those described above, and for example, a material that can be used for the above-described insulators 311A ​​to 311C as a film with a reduced concentration of impurities such as water and hydrogen can be used as the insulator 312.

[0290] 28, 29B, and 35A, the insulator 313 is illustrated as a single layer, but one embodiment of the present invention is not limited to this. The insulator 313 illustrated in FIGS. 28, 29B, and 35A may have a structure in which, for example, multiple layers of the above-mentioned materials are stacked. For example, in FIGS. 28 and 29B, silicon oxide may be used for the insulator 312 in contact with the material layer 352, and aluminum oxide, hafnium oxide, or the like may be used for the insulator 312 in contact with the conductor 332.

[0291] In particular, consider the case where, for example, a metal oxide that functions as an oxide semiconductor is used as the material layer 352. For example, by forming aluminum oxide by a sputtering method, oxygen is supplied to the insulator 313, and the oxygen supplied to the insulator 313 is supplied to the material layer 352. Supplying oxygen to the material layer 352 increases the amount of oxygen contained in the oxide semiconductor, thereby preventing a decrease in the resistance of the oxide semiconductor.

[0292] Then, as shown in FIG. 35B, a conductor 332 is formed on the formation surface of the insulator 313 so as to fill the remaining openings in the region 391.

[0293] As described above, the conductor 332 functions as the second gate electrodes of the cell transistors CTrA and CTrB in FIG. 28, and as a wiring that applies a potential to the second gate electrodes.

[0294] The conductor 332 may be made of a material containing one or more metal elements selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. The conductor 332 may also be made of a semiconductor with high electrical conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.

[0295] As the conductor 332, for example, a conductive material containing oxygen and a metal element contained in a metal oxide applicable to the material layer 351 or the material layer 352 may be used. The above-mentioned conductive material containing a metal element and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen mixed in from a surrounding insulator or the like may be captured in some cases.

[0296] In addition, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen as the conductor 332. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like, and the conductor 332 may be formed as a single layer or a stacked layer.

[0297] The conductor 332 may be configured by stacking a plurality of the above-mentioned materials. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. By applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, oxygen may be diffused in the region of the conductor in contact with the insulator. This may allow a stacked structure to be formed by combining a material containing a metal element and a conductive material containing oxygen. Similarly, by applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may be diffused in the region of the conductor in contact with the insulator. This may allow a stacked structure to be formed by combining a material containing a metal element and a conductive material containing nitrogen.

[0298] 36A, in the next step, for example, a resist mask is formed and an etching process is performed on the laminate 300 to form slit-shaped openings in the regions 392A and 392B. Note that in this step, the openings in the regions 392A and 392B are described as being slit-shaped, but as shown in FIG 31B, the openings in the regions 392A and 392B may be cylindrical.

[0299] For details of the formation of the resist mask, the etching process, and the like, please refer to the explanation of FIG. 32B.

[0300] 36B, the sacrificial layers 301A and 301B are removed from the side surfaces of the openings formed in the regions 392A and 392B by etching or the like, and the regions of the insulator 312, the conductor 331, and the material layer 351 surrounded by the sacrificial layer 301A and the regions of the insulator 312, the conductor 331, and the material layer 351 surrounded by the sacrificial layer 301B are removed to form the recesses 393A and 393B in the laminate 300. As a result, the insulator 312a (insulator 312b, insulator 312c), the conductor 331a (conductor 331b, conductor 331c), and the material layer 351a (material layer 351b, material layer 351c) are formed in the region of the material layer 352 overlapping with the region 372.

[0301] Note that recesses 393A and 393B may be formed together with the openings of regions 392A and 392B in the manufacturing process of the semiconductor device shown in Fig. 36A. In addition, the conditions of etching and the like may be different between the steps of removing sacrificial layers 301A and 301B, a portion of the insulator 312, a portion of the conductor 331, and a portion of the material layer 351c. Therefore, in the step shown in Fig. 36B, the conditions of etching and the like may be changed depending on the material to be removed.

[0302] Incidentally, when a material having a metal oxide is applied as the material layer 352, that is, when the cell transistors CTrA and CTrB in FIG. 28 are OS transistors, after forming the openings of the regions 392A and 392B, the recesses 393A and 393B, respectively, a process may be performed to supply oxygen to the region 371 of the material layer 352 exposed in the recesses 393A and 393B from the openings of the regions 392A and 392B. In this case, FIG. 37A shows a state in which oxygen is supplied to the region 371 as a process 10. The process of supplying oxygen may be, for example, a heat treatment in an oxygen atmosphere.

[0303] Moreover, the process 10 for supplying oxygen can be, for example, a microwave process in an atmosphere containing oxygen. In this case, microwaves, high frequency such as RF, oxygen plasma, oxygen radicals, or the like are irradiated to the region 371. For the microwave process, it is preferable to use a microwave processing device having a power source for generating high density plasma using microwaves. Moreover, the microwave processing device may have a power source for applying RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. Moreover, by applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently guided to the material layer 352. Moreover, the microwave process is preferably performed under reduced pressure, and the pressure may be set to 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Moreover, it is preferable to perform the process at an oxygen flow rate ratio (O2 / O2+Ar) of 50% or less, preferably 10% or more and 30% or less. Moreover, the process temperature may be set to 750°C or less, preferably 500°C or less, for example, about 400°C. Furthermore, after the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0304] As the process 10 for supplying oxygen, a microwave process is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region 371 of the material layer 352 (material layer 352A when the configurations of the cell transistors CTrA and CTrB are as shown in Figs. 30A and 30C). At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 371. That is, microwaves, high frequency waves such as RF, oxygen plasma, or the like can be applied to the region 372 shown in Fig. 37A. The V O H can be split off and hydrogen H can be removed from the region 371. O H→H+V O )" and "V O +O→null” occurs, and the hydrogen concentration in the region 371 can be reduced. Therefore, the oxygen vacancies in the region 371 and the VO H can be reduced, lowering the carrier concentration.

[0305] On the other hand, in region 372 shown in Fig. 37A, conductor 331a (conductor 331b, conductor 331c) are provided so as to overlap. Conductor 331a (conductor 331b, conductor 331c) blocks the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so these effects do not reach region 372. As a result, in region 372, V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0306] In this manner, the oxygen vacancies in the region 371 of the material layer 352 and the V O By removing H, the region 371 can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 372 that functions as the source region or drain region can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the cell transistors CTrA and CTrB, and suppresses variations in the electrical characteristics of the cell transistors within the semiconductor device.

[0307] Also, when a material containing silicon is applied as the material layer 352, that is, when the cell transistors CTrA and CTrB in FIG. 28 are Si transistors, after forming the openings of the regions 392A and 392B, the recesses 393A and 393B, respectively, a process of supplying impurities from the openings of the regions 392A and 392B to the region 371 of the material layer 352 exposed in the recesses 393A and 393B may be performed. In this case, FIG. 36A shows a state in which impurities are supplied to the material layer 352 exposed in the recesses 393A and 393B as a process 10. It is preferable to perform a heat treatment on the semiconductor device during the process 10. It is to be noted that when the cell transistors CTrA and CTrB are n-type transistors, a p-type impurity (acceptor) is used as the impurity to make the region 371 a p-type channel formation region. For example, boron, aluminum, gallium, etc. can be used as the p-type impurity. When the cell transistor CTr is a p-type transistor, an n-type impurity (donor) is used as an impurity to make the region 371 an n-type channel formation region. For example, phosphorus, arsenic, or the like can be used as the n-type impurity.

[0308] In addition, in the material layer 352, a region not exposed to the recess 393A and the recess 393B, that is, a region 372 in contact with the material layer 351a, the material layer 351b, and the material layer 351c, may have a lower resistance than the region 371. This is because, for example, a low-resistance compound may be generated by a component contained in the conductor 331a (conductor 331b, conductor 331c) and a component of the material layer 352 near the interface with the material layer 351a (material layer 351b, material layer 351c). Or, this is because the resistance of the region 371 becomes higher than that of the region 372 by the process 10. Therefore, the region 372 functions as a low-resistance region of the cell transistor CTrA and the cell transistor CTrB.

[0309] As described above, in the process of supplying oxygen and impurities to material layer 352, oxygen may be supplied from the terminal outlet as shown in Fig. 37B, rather than from the openings of regions 392A and 392B. The process of supplying oxygen to material layer 352 may combine the supply of oxygen from the openings of regions 392A and 392B in Fig. 37A and the supply of oxygen from the terminal outlet in Fig. 37B. Fig. 37B is a perspective view of the structure shown in Fig. 37A.

[0310] In the next step, as shown in FIG. 38A, a material layer 353 is deposited on the side surfaces of the openings of regions 392A and 392B shown in FIG. 36B (the side surfaces of insulators 311A ​​to 311C), recesses 393A, and recesses 393B.

[0311] 28 are OS transistors, the material applicable to the material layer 353 is preferably a metal oxide applicable to the material layer 351 and / or the material layer 352. For the metal oxide, refer to the description of the material layer 351 and the material layer 352 formed in the steps shown in FIGS. 34A and 34B.

[0312] The material layer 353 may have a structure in which a plurality of metal oxides applicable to the material layer 351 and / or the material layer 352 are stacked.

[0313] Furthermore, after forming the material layer 353, oxygen may be supplied to the material layer 353 and the region of the material layer 352 in contact with the material layer 353 by using a microwave treatment or the like as process 10, similar to the process shown in Figures 37A and 37B (not shown).

[0314] Furthermore, when a material containing silicon is used as the material layer 352, that is, when the cell transistors CTrA and CTrB in FIG. 28 are Si transistors, the material applicable to the material layer 353 may be a metal oxide applicable to the material layers 351 and / or 352, or a material applicable to the insulator 314 described later.

[0315] 38A, the material layer 353 and the material layer 351c are illustrated as having the same thickness, but the semiconductor device according to one embodiment of the present invention is not limited to this. The thickness of the material layer 353 may be thicker or thinner than the thickness of the material layer 351c.

[0316] In the next step, as shown in Fig. 38B, an insulator 314 is formed on the side surfaces of the openings of the regions 392A and 392B shown in Fig. 38A and on the recesses that have been formed. That is, the insulator 314 is formed on the formation surface of the material layer 353.

[0317] As described above, the insulator 314 functions as a tunnel insulating film for the cell transistor CTrA and the cell transistor CTrB.

[0318] It is preferable to use, for example, silicon oxide or silicon oxynitride as the insulator 314. Alternatively, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used as the insulator 314. Alternatively, the insulator 314 may be a stack of these insulators.

[0319] Furthermore, after forming the insulator 314, similar to the process shown in Figures 37A and 37B, oxygen may be supplied to the material layer 353 and the region of the material layer 352 in contact with the material layer 353 through the insulator 314 using a microwave process or the like as process 10 (not shown).

[0320] When at least one of the material layers 351 to 353 is a material containing metal oxide, the insulator 314 can be an insulator obtained by stacking the above-mentioned material and a material applicable to the insulator 313. In particular, by using a material having a function of suppressing permeation of impurities such as oxygen, water, and hydrogen as the insulator 314, it may be possible to prevent diffusion of water or hydrogen into the material layers 351 to 353 and desorption of oxygen from the material layers 351 to 353. Note that when a microwave treatment is performed as the process 10, for example, a film of silicon oxide or silicon oxynitride may be formed on the formation surface of the material layer 353, and then the microwave treatment may be performed, and then a film of a material having a function of suppressing permeation of impurities such as oxygen, water, and hydrogen may be formed to form the insulator 314.

[0321] In the next step, as shown in Fig. 39A, a conductor 333 is formed on the side surfaces of the openings of the regions 392A and 392B shown in Fig. 38B and on the recesses that are formed. That is, the conductor 333 is formed on the formation surface of the insulator 314.

[0322] For example, the material applicable to the conductor 332 described above can be used as the conductor 333. However, the material applicable to the conductor 333 is not limited thereto. As a substitute for the conductor 333, an insulator, a semiconductor, or the like can be used in some cases.

[0323] 39B, in the next step, conductor 333 in the remaining portions of recesses 393A and 393B and conductor 333 included in regions 392A and 392B are removed by forming a resist mask and etching, etc., so that conductor 333 remains in parts of recesses 393A and 393B described above. As a result, conductor 333a is formed in recess 393A, and conductor 333b is formed in recess 393B.

[0324] As described above, the conductor 333a functions as the floating gate electrode of the cell transistor CTrA, and the conductor 333b functions as the floating gate electrode of the cell transistor CTrB.

[0325] For details of the formation of the resist mask, the etching process, and the like, please refer to the explanation of FIG. 32B.

[0326] 39B, the thicknesses of the conductor 333a and the conductor 333b are illustrated as being thicker than, for example, the thicknesses of the material layer 351a (material layer 351b, material layer 351c), the conductor 331a (conductor 331b, conductor 331c), and the insulator 312a (insulator 312b, insulator 312c), but the semiconductor device according to one embodiment of the present invention is not limited thereto. The thickness of the conductor 333a for filling a part of the recess 393A may be thickened as long as the insulator 315 and the conductor 334a are formed in the recess 393A in a later step. The thickness of the conductor 333a may be thinned as long as the conductor 333a functions as a floating gate electrode. Similarly, the thickness of conductor 333b for filling part of recess 393B may be made thick so long as insulator 315 and conductor 334b ​​are formed in recess 393B in a later process, and the thickness of conductor 333b may be made thin so long as conductor 333b functions as a floating gate electrode.

[0327] In the next step, as shown in Fig. 40A, an insulator 315 is formed on the side surfaces of the openings of the regions 392A and 392B shown in Fig. 39B and on the recesses that have been formed. That is, the insulator 315 is formed on the formation surfaces of the conductors 333a, 333b, and 314.

[0328] As described above, the insulator 315 functions as a gate insulating film for the cell transistors CTrA and CTrB.

[0329] As the insulator 315, for example, silicon oxide or silicon oxynitride can be used. As the insulator 315, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used. As the insulator 315, an insulator having these stacked layers can be used. The insulator 315 is preferably thicker than the insulator 314. By making the insulator 315 thicker than the insulator 314, charge can be transferred from the material layer 353 to the conductor 333a and the conductor 333b through the insulator 314.

[0330] In the next step, as shown in Fig. 40B, a conductor 334 is formed on the side surfaces of the openings of the regions 392A and 392B shown in Fig. 39A and on the recesses that are formed. That is, the conductor 334 is formed on the formation surface of the insulator 315.

[0331] The conductor 334 can be made of, for example, a material that can be used for the conductor 332 described above.

[0332] 41, in the next step, the conductor 334 included in the region 392A and the region 392B is removed by forming a resist mask and performing an etching process or the like so that the conductor 334 remains only in the recessed portion described above. This forms the conductor 334a and the conductor 334b. At this time, the exposed portion of the insulator 315 may be removed.

[0333] For details of the formation of the resist mask, the etching process, and the like, please refer to the explanation of FIG. 32B.

[0334] As described above, the conductor 334a functions as the gate electrode of the cell transistor CTrA and as a word line that applies a potential to the gate electrode, and the conductor 334b ​​functions as the gate electrode of the cell transistor CTrB and as a word line that applies a potential to the gate electrode.

[0335] In the next step, as shown in FIG. 28A, an insulator 316A is deposited so as to fill the opening in region 392A, and an insulator 316B is deposited so as to fill the opening in region 392B.

[0336] For the insulators 316A and 316B, for example, the materials applicable to the insulator 313 described above can be used.

[0337] By carrying out the above-mentioned steps, the semiconductor device shown in FIG. 28A can be manufactured.

[0338] <Configuration Example 10 of Semiconductor Device> A configuration example of a semiconductor device functioning as a memory device according to one embodiment of the present invention is not limited to the configurations shown in Fig. 28, Fig. 29A, and Fig. 29B. The configuration of the semiconductor device can be changed as appropriate from the circuit configurations shown in Fig. 28, Fig. 29A, and Fig. 29B depending on the case, situation, or need.

[0339] For example, the configuration of the semiconductor device in Fig. 28, Fig. 29A, and Fig. 29B may be changed to the configuration of the semiconductor device shown in Fig. 42A, Fig. 43A, and Fig. 43B. Fig. 42A is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Fig. 28, Fig. 29A, and Fig. 29B. Fig. 43A is a top view of a portion of the dashed line B1-B2 shown in Fig. 42, and Fig. 43B is a top view of a portion of the dashed line B3-B4 shown in Fig. 42. Note that in the cross-sectional view in Fig. 42, the top view in Fig. 43A, and the top view in Fig. 43B, some elements are omitted for clarity.

[0340] 42A, 43A, and 43B, the step shown in Fig. 42B is performed instead of the step shown in Fig. 36B, and a part of the material layer 352 is removed by etching or the like to such an extent that the insulator 313 is not exposed in the recesses 393A and 393B. As described above, in the semiconductor device of one embodiment of the present invention, the material layer 352 may have a different thickness between a region 371 of the material layer 352 in which the recesses 393A and 393B are formed and a region 372 of the material layer 352 that overlaps with the conductor 331a (conductor 331b, conductor 331c).

[0341] <Configuration Example 11 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 44, 45A, and 45B. Figure 44 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 28, 29A, and 29B. Also, Figure 45A is a top view of a portion of the dashed line C1-C2 shown in Figure 44, and Figure 45B is a top view of a portion of the dashed line C3-C4 shown in Figure 44. Note that in the cross-sectional view of Figure 44, the top view of Figure 45A, and the top view of Figure 45B, some elements are omitted for clarity.

[0342] The semiconductor device in Figures 44, 45A, and 45B has a configuration in which, after the process shown in Figure 40B, a resist mask is formed and an etching process is performed to remove material layer 353, insulator 314, insulator 315, and conductor 334 contained in region 392A and region 392B, and insulator 316A is deposited so as to fill the opening in region 392A, and insulator 316B is deposited so as to fill the opening in region 392B.

[0343] That is, the semiconductor devices in Figures 44, 45A, and 45B have a configuration in which the insulator 314, the insulator 315, and the material layer 353 have been removed to such an extent that the conductor 334a and the conductor 334b ​​remain after the step shown in Figure 40B. At this time, a part of the insulators 311A ​​to 311C may be removed. Note that Figure 44 shows a configuration in which the material layer 353a, the insulator 314a, the insulator 315a, and the conductor 334a are formed in the recess 393A, and the material layer 353b, the insulator 314b, the insulator 315b, and the conductor 334b ​​are formed in the recess 393B.

[0344] It should be noted that the etching process or the like after the step shown in FIG. 40B may be stopped until a portion of insulator 315 is removed and insulator 314 is exposed in the opening of region 392A, or until a portion of insulator 314 is removed and material layer 353 is exposed in the opening of region 392A, and insulators 316A and 316B in FIG. 28 may be formed on the side surfaces of the openings of regions 392A and 392B, respectively (not shown).

[0345] For details of the formation of the resist mask, the etching process, and the like, please refer to the explanation of FIG. 32B.

[0346] <Configuration Example 12 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 46, 47A, and 47B. Figure 46 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 28, 29A, and 29B. Also, Figure 47A is a top view of a portion of the dashed line D1-D2 shown in Figure 46, and Figure 47B is a top view of a portion of the dashed line D3-D4 shown in Figure 46. Note that in the cross-sectional view of Figure 46, the top view of Figure 47A, and the top view of Figure 47B, some elements are omitted for clarity.

[0347] The semiconductor device in Figures 46, 47A, and 47B has a configuration in which the process shown in Figure 36B or 37A is performed by omitting the process of forming material layer 353 in Figure 38A and performing the processes in and after Figure 38B. If insulator 314 functions sufficiently as a barrier insulating film to prevent diffusion of impurities into material layer 352, material layer 353 does not need to be provided. In this case, since there is no need to provide material layer 353, the process of manufacturing the semiconductor device can be shortened.

[0348] <Configuration Example 13 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B may be changed to the configuration of the semiconductor device shown in FIG. 48 and FIG. 49. FIG. 48 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B. Also, FIG. 49 is a top view of a portion of the dashed line E3-E4 shown in FIG. 48. Note that the top view of the portion of the dashed line E1-E2 shown in FIG. 48 may have a configuration almost similar to that of FIG. 29A. Note that in the cross-sectional view of FIG. 48 and the top view of FIG. 49, some elements are omitted for clarity.

[0349] The semiconductor device of Figures 48 and 49 has a configuration in which, in the step shown in Figure 33B, the step of forming material layer 351 of Figure 34A is not performed, and the steps from Figure 34B onwards are performed. If the components, impurities, etc. contained in material layer 352 do not diffuse into conductor 331a (conductor 331b, conductor 331c) and the conductivity of conductor 331a (conductor 331b, conductor 331c) does not decrease, it is not necessary to provide material layer 351 that functions as a barrier film for the components, impurities, etc. In this case, since there is no need to provide material layer 351, the steps for manufacturing the semiconductor device can be shortened.

[0350] <Configuration Example 14 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B may be changed to the configuration of the semiconductor device shown in FIG. 50 and FIG. 51. FIG. 50 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B. Also, FIG. 51 is a top view of a portion of the dashed line F3-F4 shown in FIG. 50. Note that the top view of the portion of the dashed line F1-F2 shown in FIG. 50 may have a configuration almost similar to that of FIG. 29A. Note that in the cross-sectional view of FIG. 50 and the top view of FIG. 51, some elements are omitted for clarity.

[0351] The semiconductor device in Fig. 50 and Fig. 51 has a configuration in which, in the step shown in Fig. 32B, the step of forming the insulator 312 in Fig. 33A is not performed, and the steps in Fig. 33B and after are performed. If the components, impurities, etc. contained in the insulator 311A ​​(insulator 311B, insulator 311C) do not diffuse into the conductor 331a (conductor 331b, conductor 331c) and the conductivity of the conductor 331a (conductor 331b, conductor 331c) does not decrease, it is not necessary to provide the insulator 312 that functions as a barrier insulating film for the components, impurities, etc. In this case, since it is not necessary to provide the insulator 312, the steps for manufacturing the semiconductor device can be shortened.

[0352] <Configuration Example 15 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B may be changed to the configuration of the semiconductor device shown in FIG. 52 and FIG. 53. FIG. 52 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in FIG. 28, FIG. 29A, and FIG. 29B. Also, FIG. 53 is a top view of a portion of the dashed line G3-G4 shown in FIG. 52. Note that the top view of the portion of the dashed line G1-G2 shown in FIG. 52 may have a configuration almost similar to that of FIG. 29A. Note that in the cross-sectional view of FIG. 52 and the top view of FIG. 53, some elements are omitted for clarity.

[0353] The semiconductor device shown in Figures 52 and 53 has a configuration in which a conductor is formed on the side surface of the opening of region 391 in the step shown in Figure 32B, and the steps from Figure 33A to Figure 34A are not performed, but the steps from Figure 34B onwards are performed. Note that a portion of the conductor is removed in the step of forming recesses 393A and 393B in Figure 36B. As a result, conductor 361a, conductor 361b, and conductor 361c shown in Figure 52 are formed.

[0354] The conductor 361a, the conductor 361b, and the conductor 361c are preferably made of a conductive material that forms a low resistance region near the interface with the material layer 352.

[0355] For example, when the material layer 352 is made of a material containing a metal oxide, the conductors 361a, 361b, and 361c each have a resistance of 2.4×10 3 [Ω / sq] or less, preferably 1.0×10 3 The conductive material may be, for example, a metal film such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium, a nitride film such as Al-Ti nitride or titanium nitride, or an oxide film such as indium tin oxide or In-Ga-Zn oxide.

[0356] Furthermore, the conductors 361a, 361b, and 361c are not limited to the above-mentioned conductive materials as long as they are materials that can reduce the resistance of the material layer 352. For example, an insulator such as silicon nitride may be used instead of the conductors 361a, 361b, and 361c.

[0357] 36B, by performing a heat treatment after the steps of forming the recesses 393A and 393B and forming the conductors 361a, 361b, and 361c, in a region where the conductors 361a, 361b, and 361c contact the material layer 352, a compound may be formed in the vicinity of the interface between the material layer 352 and the conductors 361a, 361b, and 361c by the components contained in the conductors 361a, 361b, and 361c and the components contained in the material layer 352. The compound reduces the resistance of a region 372 of the material layer 352 that contacts the conductors 361a, 361b, and 361c.

[0358] The heat treatment may be performed in an atmosphere containing nitrogen. The heat treatment may cause the metal elements of the conductor 361a (conductor 361b and conductor 361c) to diffuse from the conductor 361a (conductor 361b and conductor 361c) to the material layer 352, or the metal elements of the material layer 352 to diffuse to the conductor 361a (conductor 361b and conductor 361c), and the material layer 352 and the conductors 361a, 361b, and 361c may form a metal compound. At this time, the metal elements of the material layer 352 may be alloyed with the metal elements of the conductors 361a, 361b, and 361c. By alloying the metal elements of the material layer 352 with the metal elements of the conductors 361a, 361b, and 361c, the metal elements become relatively stable, thereby providing a highly reliable semiconductor device.

[0359] Moreover, the heat treatment causes hydrogen in the material layer 352 to diffuse into a region 372 of the material layer 352 in contact with the conductors 361a, 361b, and 361c, and when the hydrogen enters into oxygen vacancies present in the region, the hydrogen becomes relatively stable. The hydrogen in oxygen vacancies present in the region 371 of the material layer 352 exposed to the recesses 393A and 393B escapes from the oxygen vacancies, diffuses into the region 372, and enters into oxygen vacancies present in the region 372 of the material layer 352, and becomes relatively stable, by the heat treatment at 250° C. or higher. Thus, the resistance of the region 372 is lowered, and the region 371 is purified (reduced impurities such as water and hydrogen) and becomes relatively stable.

[0360] Furthermore, for example, when the material layer 352 is made of a material containing silicon, the material layer 352 may come into contact with the conductors 361a, 361b, and 361c, and thus impurities (such as elements and ions) contained in the conductors 361a, 361b, and 361c may diffuse into the material layer 352. In this case, depending on the situation or in some cases, it is preferable to form the recesses 393A and 393B in FIG. 36B and to perform heat treatment after the step of forming the conductors 361a, 361b, and 361c. That is, impurity regions are formed on the surfaces of the material layer 352 that come into contact with the conductors 361a, 361b, and 361c, and in the vicinity of the interfaces.

[0361] When the impurities contained in the conductors 361a, 361b, and 361c are n-type impurities (donors), an n-type impurity region may be formed in the region 372 of the material layer 352 or near the interfaces between the material layer 352 and the conductors 361a, 361b, and 361c. On the other hand, when the impurities contained in the conductors 361a, 361b, and 361c are p-type impurities (acceptors), a p-type impurity region may be formed in the region 372 of the material layer 352 or near the interfaces between the material layer 352 and the conductors 361a, 361b, and 361c. That is, as a result, carriers may be formed in the region 372 of the material layer 352 or near the interfaces between the region 372 of the material layer 352 and the conductors 361a, 361b, and 361c, and the resistance of the region 372 may be reduced.

[0362] Furthermore, by performing heat treatment, a metal silicide may be formed in the vicinity of the interface between the conductor 361a, the conductor 361b, and the conductor 361c in the region 372 of the material layer 352 and the conductor 361b, and the conductor 361c due to the conductive materials contained in the conductor 361a, the conductor 361b, and the conductor 361c and the components contained in the material layer 352. By forming a metal silicide in the vicinity of the interface between the conductor 361a, the conductor 361b, and the conductor 361c in the region 372 of the material layer 352, the resistance may be reduced in the vicinity of the interface between the conductor 361a, the conductor 361b, and the conductor 361c in the region 372 of the material layer 352.

[0363] In addition, when manufacturing the semiconductor device of Figures 52 and 53, it is preferable not to perform heat treatment in a step before the step of forming the recess 393A and the recess 393B and forming the conductor 361a, the conductor 361b, and the conductor 361c in Figure 36B. This is because, in the step shown in Figure 32B, conductors for forming the conductors 361a, the conductor 361b, and the conductor 361c are formed in the material layer 352, and if heat treatment is performed at this stage, the resistance may be reduced in the region of the material layer 352 in contact with the conductors. Therefore, when manufacturing the semiconductor device of Figures 52 and 53, it is preferable to perform the above-mentioned heat treatment after forming the recess 393A and the recess 393B and forming the conductor 361a, the conductor 361b, and the conductor 361c in Figure 36B.

[0364] <Configuration Example 16 of Semiconductor Device> Also, for example, the configuration of the semiconductor device in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 54, 55A, and 55B. Figure 54 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device in Figures 28, 29A, and 29B. Also, Figure 55A is a top view of a portion of the dashed line H1-H2 shown in Figure 54, and Figure 55B is a top view of a portion of the dashed line H3-H4 shown in Figure 54. Note that in the cross-sectional view of Figure 54, the top view of Figure 55A, and the top view of Figure 55B, some elements are omitted for clarity.

[0365] The semiconductor device in FIGS. 54, 55A, and 55B has a configuration in which, in the process shown in FIG. 35A, the process of forming the conductor 332 in FIG. 35B is not performed, and the processes in and after FIG. 36A are performed.

[0366] That is, the semiconductor devices in FIGS. 54, 55A, and 55B are configured such that the second gate electrode and the wiring for applying a potential to the second gate electrode are not provided.

[0367] Note that a configuration example of a semiconductor device functioning as a memory device according to one embodiment of the present invention may be a combination of any of the above-described configuration examples 9 to 16 of the semiconductor device.

[0368] Note that the insulator, conductor, semiconductor, material layer, and the like disclosed in this embodiment can be formed by the film formation method described in the first embodiment.

[0369] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0370] (Embodiment 3) This embodiment describes a configuration example for increasing the storage capacity of the semiconductor device described in Embodiment 1 and Embodiment 2. Note that this embodiment describes the semiconductor device described in Embodiment 2 as an example, but this embodiment can also be applied to the semiconductor device described in Embodiment 1.

[0371] 56A and 56B are top views showing the configuration of a semiconductor device in which an insulator 319 is newly formed in the region 391 and outside the region 391 shown in FIGS. 29A and 29B, respectively.

[0372] Specifically, openings are first formed in region 391 and outside region 391 in FIGS. 29A and 29B, and then insulator 319 is formed so as to fill the openings.

[0373] As the insulator 319, for example, a material that can be used for the insulators 311A ​​to 311C can be used. As specific examples, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, aluminum nitride oxide, or the like can be used for the insulator 319. Alternatively, the insulator 319 may be a film having multiple layers instead of a single film.

[0374] 56A, the opening is formed, for example, so as to divide region 391 and to separate conductor 332 into two, conductor 332_1 and conductor 332_2. In other words, by forming the opening in region 391, each of conductor 332, insulator 313, material layer 352, material layer 353, insulator 314, conductor 333b, and insulator 315 included in region 391 is divided into two. FIG. 56A shows a configuration in which conductor 332 is divided into two, conductor 332_1 and conductor 332_2, insulator 313 is divided into two, insulator 313_1 and insulator 313_2, material layer 352 is divided into two, material layer 352_1 and material layer 352_2, material layer 353 is divided into two, material layer 353_1 and material layer 353_2, insulator 314 is divided into two, insulator 314_1 and insulator 314_2, conductor 333b is divided into two, conductor 333b_1 and conductor 333b_2, and insulator 315 is divided into two, insulator 315_1 and insulator 315_2.

[0375] Moreover, by forming an opening in the region 391 and its periphery as shown in Fig. 56A, the region 391 in Fig. 29B and the periphery outside the region 391 have the configuration shown in Fig. 56B. Specifically, Fig. 56B shows a configuration in which the conductor 332 is divided into two parts, conductor 332_1 and conductor 332_2, the insulator 313 is divided into two parts, insulator 313_1 and insulator 313_2, the material layer 352 is divided into two parts, material layer 352_1 and material layer 352_2, the material layer 351 is divided into two parts, material layer 351a_1 and material layer 351a_2, the conductor 331a is divided into two parts, conductor 331a_1 and conductor 331a_2, and the insulator 312a is divided into two parts, insulator 312a_1 and insulator 312a_2.

[0376] 56A and 56B, by configuring a semiconductor device so that region 391 is divided by insulator 319, it is possible to double the number of cell transistors provided in region 391. In other words, since the number of strings provided in region 391 can be doubled, the semiconductor device having the configuration shown in Figures 56A and 56B can have a larger memory capacity than the semiconductor device having the configuration shown in Figures 29A and 29B.

[0377] Furthermore, the semiconductor device of one embodiment of the present invention is not limited to the structures shown in Fig. 56A and Fig. 56B. Although the structure in which the region 391 is divided into two is shown in Fig. 56A and Fig. 56B, for example, the region 391 may be divided into three as shown in Fig. 57A. Or, for example, the region 391 may be divided into four as shown in Fig. 57B.

[0378] FIG. 57A shows an example of a configuration in which the area 391 in FIG. 29B is divided into three. Specifically, FIG. 57A shows a configuration in which conductor 332 is divided into three parts: conductor 332_1, conductor 332_2, and conductor 332_3; insulator 313 is divided into three parts: insulator 313_1, insulator 313_2, and insulator 313_3; material layer 352 is divided into three parts: material layer 352_1, material layer 352_2, and material layer 352_3; material layer 351a is divided into three parts: material layer 351a_1, material layer 351a_2, and material layer 351a_3; conductor 331a is divided into three parts: conductor 331a_1, conductor 331a_2, and conductor 331a_3; and insulator 312a is divided into three parts: insulator 312a_1, insulator 312a_2, and insulator 312a_3.

[0379] 57B shows an example of a configuration in which the region 391 in FIG. 29B is divided into four. Specifically, in FIG. 57A, the conductor 332 is divided into four, conductor 332_1, conductor 332_2, conductor 332_3, and conductor 332_4, the insulator 313 is divided into four, conductor 313_1, insulator 313_2, insulator 313_3, and insulator 313_4, the material layer 352 is divided into four, conductor 352_1, material layer 352_2, material layer 352_3, and material layer 352_4, and the material layer 351 is divided into four, conductor 332_1, conductor 332_2, material layer 332_3, and material layer 352_4. a is divided into four parts: material layer 351a_1, material layer 351a_2, material layer 351a_3, and material layer 351a_4; conductor 331a is divided into four parts: conductor 331a_1, conductor 331a_2, conductor 331a_3, and conductor 331a_4; and insulator 312a is divided into four parts: insulator 312a_1, insulator 312a_2, insulator 312a_3, and insulator 312a_4.

[0380] Although the above example shows the semiconductor device having the region 391 divided into two, three, and four regions, the semiconductor device of one embodiment of the present invention may have the region 391 divided into five or more regions.

[0381] 56A and 56B , the semiconductor device of one embodiment of the present invention may have an opening provided across two or more regions 391 and filled with the insulator 319. Specifically, in a structure in which a plurality of regions 391 are provided between two slit-shaped regions 392 as shown in Fig. 58A , an opening may be provided so as to be substantially parallel to the slit-shaped region 392 and so as to span the conductors 332 of the plurality of regions 391, and the insulator 319 may be filled in the opening.

[0382] In the configuration of FIG. 58A, the word line electrically connected to the first gate of the cell transistor is provided between the insulator 311A ​​and the insulator 311B and between the insulator 311B and the insulator 311C, as shown in FIG. 28. Therefore, when an opening is provided so as to span a plurality of regions 391 and an insulator 319 is provided in the opening, it is necessary to provide the opening so that the first gate of the cell transistor and the word line are in a conductive state with an external circuit, etc. Specifically, in the configuration of FIG. 58A, the insulator 319 is provided so as to be approximately parallel to the slit-shaped region 392, so that the first gate of the cell transistor and the word line are in a conductive state with an external circuit, etc.

[0383] Also, as long as the first gate and word line of the cell transistor are in a conductive state with an external circuit or the like, the position and shape of the opening and the insulator 319 are not particularly limited. For example, as shown in FIG. 58B, an opening may be provided in a direction having an angle with respect to the slit-shaped region 392, and the insulator 319 may be provided in the opening. In this case, by preventing a part of the opening from being formed inside the regions 392 on both sides on the upper surface of FIG. 58B, the first gate and word line of the cell transistor can be in a conductive state with the external circuit or the like, and the semiconductor device having the configuration of FIG. 58B can be operated. On the other hand, if the opening is provided up to the inside of the regions 392 on both sides, the first gate of the cell transistor will be in a non-conductive state with the external circuit or the like, and the semiconductor device in this case will not operate normally.

[0384] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0385] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0386] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0387] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 59A. Fig. 59A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0388] As shown in FIG. 59A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0389] The structure in the bold frame shown in Fig. 59A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from energetically unstable "Amorphous" and "Crystal".

[0390] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 59B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" (the vertical axis represents the intensity in arbitrary units (au)). The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 59B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 59B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 59B is 500 nm.

[0391] As shown in Figure 59B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 59B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0392] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 59C. FIG. 59C is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 59C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0393] As shown in FIG. 59C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0394] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 59A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0395] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0396] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0397] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0398] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0399] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0400] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0401] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0402] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0403] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0404] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0405] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0406] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0407] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0408] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0409] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0410] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0411] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0412] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0413] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0414] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0415] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0416] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0417] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0418] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0419] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0420] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0421] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0422] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm3 The following applies.

[0423] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0424] In this specification, the term "normally on" refers to a state in which a channel exists even when no voltage is applied to the gate, and a current flows through the transistor. The term "normally off" refers to a state in which the current flowing through the transistor per 1 μm of channel width is less than 1×10 at room temperature when no potential is applied to the gate or when a ground potential is applied to the gate. -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0425] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm3 To the following:

[0426] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0427] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0428] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0429] (Embodiment 5) In this embodiment, a NAND memory, which is an example of the semiconductor device described in the first embodiment, will be described.

[0430] <Example of circuit configuration of semiconductor device> First, the circuit configuration of a NAND memory, which is an example of a semiconductor device, will be described with reference to FIG. 60A. FIG. 60A shows a circuit diagram of a NAND memory of one string. The NAND memory of one string has memory cells MC[1] to MC[n], wirings WL[1] to WL[n] for controlling them, wirings BL and SL, transistors STr and BTr for selecting the string, wirings SSL for controlling the transistors STr, and wirings BSL for controlling the transistors BTr. Note that the wirings WL function as wirings for applying a potential to a control gate (sometimes simply referred to as a gate in this specification) of a cell transistor of a memory cell MC described later, and the wirings SL and BL may function as wirings for applying a potential to a first terminal and / or a second terminal of a cell transistor of a memory cell MC described later.

[0431] Each memory cell MC has a cell transistor CTr. Generally, the cell transistor is a transistor that operates with normally-on characteristics and has a control gate and a charge storage layer. The charge storage layer is provided in a region overlapping the channel formation region via a tunnel insulating film, and the control gate is provided in a region overlapping the charge storage layer via a blocking film. A write potential is applied to the control gate of the cell transistor, and a predetermined potential is applied to one of the first terminal or the second terminal of the cell transistor, generating a tunnel current, and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. As a result, the threshold voltage of the cell transistor in which electrons are injected into the charge storage layer becomes high. The NAND memory is a semiconductor device that utilizes this principle, and the detailed operating principle will be described later. A floating gate may be used instead of the charge storage layer, and in the second embodiment, the cell transistor included in the semiconductor device is described as a transistor having a floating gate.

[0432] In terms of circuit configuration, the first terminal of the cell transistor CTr is electrically connected in series with the second terminal of the cell transistor CTr of the adjacent memory cell MC. That is, the circuit configuration shown in FIG. 1A is configured such that n cell transistors CTr are electrically connected in series. In addition, the second terminal of the cell transistor CTr of the memory cell MC[1] is electrically connected with the first terminal of the transistor STr, and the first terminal of the cell transistor CTr of the memory cell MC[n] is electrically connected with the first terminal of the transistor BTr. The control gates of the cell transistors CTr of the memory cells MC[1] to MC[n] are electrically connected with the wirings WL[1] to WL[n], respectively. The second terminal of the transistor STr is electrically connected with the wiring SL, and the gate of the transistor STr is electrically connected with the wiring SSL. The second terminal of the transistor BTr is electrically connected with the wiring BL, and the gate of the transistor BTr is electrically connected with the wiring BSL.

[0433] The channel formation region of the cell transistor CTr preferably has one or more materials selected from the above, such as silicon, germanium, gallium arsenide, silicon carbide (SiC), and metal oxides described in the fourth embodiment. In particular, when the channel formation region contains one or more metal oxides selected from indium, element M (element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc, the metal oxide may function as a wide-gap semiconductor, and a cell transistor having the metal oxide in the channel formation region has a characteristic of having a very low off-current. In other words, the leakage current in the cell transistor CTr in the off state can be reduced, and therefore the power consumption of the semiconductor device may be reduced. In addition, the channel formation regions of the transistor STr and the transistor BTr may also have the above-mentioned metal oxides.

[0434] In addition, the channel formation region of the transistor STr and / or the transistor BTr may have a different structure from the channel formation region of the cell transistor CTr. For example, the channel formation region of the cell transistor CTr may be made of a material containing the above-mentioned metal oxide, and the channel formation region of the transistor STr and / or the transistor BTr may be made of a material containing silicon.

[0435] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. 60A. One embodiment of the present invention may have a circuit configuration in which the semiconductor device illustrated in FIG. 60A is appropriately modified depending on the situation or need. For example, one embodiment of the present invention may be a semiconductor device in which a backgate is provided in the cell transistor CTr as illustrated in FIG. 60B. Note that the semiconductor device illustrated in FIG. 60B has a configuration in which, in addition to the configuration of the semiconductor device illustrated in FIG. 1A, backgates are provided in the cell transistors CTr included in the memory cells MC[1] to MC[n], and the wirings BGL are electrically connected to the backgates. The semiconductor device illustrated in FIG. 60B may have a configuration in which the wirings BGL are not electrically connected to the backgates of the cell transistors CTr included in the memory cells MC[1] to MC[n], but are electrically connected independently to the backgates to supply different potentials to each of the backgates. Note that an operation example of the semiconductor device illustrated in FIG. 60B will be described later.

[0436] Incidentally, if it is desired to further increase the storage capacity of the semiconductor device shown in Figures 60A and 60B, the semiconductor devices shown in Figures 60A and 60B may be arranged in a matrix. For example, when the semiconductor devices shown in Figure 60A are arranged in a matrix, the circuit configuration becomes the configuration shown in Figure 61. In this specification and the like, the NAND memory of multiple strings shown in Figure 61 is referred to as one block of NAND memory.

[0437] The semiconductor device shown in FIG. 61 is a semiconductor device in which the semiconductor device shown in FIG. 60A is arranged in one column and m columns (m is an integer of 1 or more), and the wiring WL is electrically connected to be shared with the memory cells MC in the same row. That is, the semiconductor device shown in FIG. 61 is a matrix-shaped semiconductor device with n rows and m columns, and has memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG. 61 is electrically connected by wiring WL[1] to wiring WL[n], wiring BL[1] to wiring BL[m], wiring BSL[1] to wiring BSL[m], wiring SL[1] to wiring SL[m], and wiring SSL[1] to wiring SSL[m]. Specifically, the control gate of the cell transistor CTr of the memory cell MC[j,i] (j is an integer of 1 to n, and i is an integer of 1 to m) is electrically connected to the wiring WL[j]. The wiring SL[i] is electrically connected to the second terminal of the transistor STr[i], and the wiring BL[i] is electrically connected to the second terminal of the transistor BTr.

[0438] Note that FIG. 61 only illustrates memory cell MC[1,1], memory cell MC[1,i], memory cell MC[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC[j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[n,m], wiring WL[1], wiring WL[j], wiring WL[n], wiring BL[1], wiring BL[i], wiring BL[m], wiring BSL[1], wiring BSL[i], wiring BSL[m], wiring SL[1], wiring SL[i], wiring SL[m], wiring SSL[1], wiring SSL[i], wiring SSL[m], cell transistor CTr, transistor BTr[1], transistor BTr[i], transistor BTr[m], transistor STr[1], transistor STr[i], and transistor STr[m].

[0439] FIG. 62 shows m columns (m is an integer equal to or greater than 1) of semiconductor devices each including the semiconductor device shown in FIG. 60B. Note that the semiconductor device shown in FIG. 62 has a configuration in which a backgate is provided in each of the transistors included in all the memory cells MC, and therefore the semiconductor device shown in FIG. 62 has wirings BGL[1] to BGL[m] for electrically connecting to the respective backgates. Note that the description of the semiconductor device shown in FIG. 61 should be referred to for the semiconductor device shown in FIG. 62.

[0440] Although the semiconductor device shown in FIG. 61 and FIG. 62 has a configuration in which the semiconductor devices shown in FIG. 60A and FIG. 60B are arranged in a matrix, one embodiment of the present invention is not limited thereto. In some cases, depending on the situation, or as needed, the circuit configuration can be changed. For example, in FIG. 61 and FIG. 62, wirings BSL[1] to BSL[m] are illustrated as wirings for controlling the transistors BTr[1] to BTr[m], respectively, but a single wiring may be electrically connected to the gates of the transistors BTr[1] to BTr[m]. Similarly, the wirings for controlling the transistors STr[1] to STr[m] may also be electrically connected to the gates of the transistors STr[1] to STr[m] as a single wiring, instead of the wirings SSL[1] to SSL[m].

[0441] <<Example of operation>> Next, an example of a method for operating the semiconductor device shown in Figures 60A and 60B will be described with reference to Figures 63A, 63B, 64A, and 64B. Note that the semiconductor device of one embodiment of the present invention may be capable of handling not only binary data but also multi-valued or analog-valued data in some cases. Therefore, in the description of this operating method, data handled in writing and reading is not limited to binary data.

[0442] In addition, the low-level potential and the high-level potential used in the following description do not mean specific potentials, and the specific potentials may be different depending on the wiring. For example, the low-level potential and the high-level potential applied to the wiring BSL may be different from the low-level potential and the high-level potential applied to the wiring BL.

[0443] Potential V PGM is a potential that can inject electrons into the charge storage layer of the cell transistor CTr by applying it to the control gate of the cell transistor CTr, and the potential V PS is a potential that can turn on the cell transistor CTr by applying it to the control gate of the cell transistor CTr.

[0444] In addition, in this operation method example, unless otherwise specified, it is assumed that a potential within a range in which the cell transistor CTr operates normally is applied to the wiring BGL shown in Fig. 60B in advance. Therefore, the operations of the semiconductor devices shown in Fig. 60A and Fig. 60B can be considered to be the same.

[0445] [Write operation] Fig. 63A is a timing chart showing an example of an operation of writing data to a semiconductor device. The timing chart in Fig. 63A shows changes in the magnitude of the potential of a wiring WL[p] (p is an integer between 1 and n), a wiring WL[j] (j is an integer between 1 and n, and is not p), a wiring BSL, a wiring SSL, and a wiring BL. Note that the timing chart in Fig. 63A shows an example of an operation of writing data to a memory cell MC[p].

[0446] Before time T10, a low-level potential is supplied to the wiring BL.

[0447] Furthermore, a low-level potential is constantly supplied to the line SSL between time T10 and time T13, so that a low-level potential is applied to the gate of the transistor STr, turning the transistor STr off.

[0448] Between time T10 and time T11, a high-level potential is supplied to the line BSL. This causes a high-level potential to be applied to the gate of the transistor BTr, turning the transistor BTr on. In addition, as the transistor BTr turns on, a low-level potential supplied from the line BL is applied to the first terminal of the cell transistor CTr of the memory cell MC[n].

[0449] Between time T11 and time T12, the wiring WL[j] is supplied with a potential V PS As a result, a potential V PS is applied. At this time, in the memory cell MC[n], since the low-level potential supplied from the wiring BL is applied to the first terminal of the cell transistor CTr, the cell transistor CTr of the memory cell MC[n] is turned on. This also causes the low-level potential supplied from the wiring BL to be applied to the first terminal of the cell transistor CTr of the memory cell MC[n-1]. In other words, the cell transistors CTr of the memory cells MC[j] are sequentially turned on.

[0450] In addition, between time T11 and time T12, the wiring WL[p] is supplied with a potential V PGM As a result, a potential V PGM is applied. Also, because the above-mentioned operation applies a low-level potential supplied from the wiring BL to the first terminal of the cell transistor CTr of the memory cell MC[p], electrons are injected from the channel formation region of the cell transistor CTr of the memory cell MC[p] into the charge storage layer. This allows data to be written to the memory cell MC[p]. Note that the threshold voltage of the cell transistor CTr increases as electrons are injected from the channel formation region of the cell transistor CTr of the memory cell MC[p] into the charge storage layer.

[0451] It is assumed that the low-level potential supplied from the wiring BL is applied to the first terminal of the transistor STr until time T12. Between time T12 and time T13, the low-level potential is applied to the wiring WL[j] and the wiring WL[p].

[0452] After time T13, a low-level potential is supplied to the wiring BSL. As a result, a low-level potential is applied to the gate of the transistor BTr, so that the transistor BTr is turned off. Although not shown in the timing chart of FIG. 63A, at this time, the low-level potential is not supplied to the wiring BSL, and the potential of the wiring BL is set to a high-level potential, so that the transistor BTr can be turned off.

[0453] By the above operations, data can be written to the semiconductor device shown in FIGS. 60A and 60B.

[0454] [Read operation] Fig. 63B is a timing chart showing an example of an operation for reading data from a semiconductor device. The timing chart in Fig. 63A shows changes in the magnitude of the potential of the wiring WL[p], the wiring WL[q] (q is an integer between 1 and n, and is not p), the wiring WL[j] (j is an integer between 1 and n, and is not p or q), the wiring BSL, the wiring SSL, and the wiring SL, and shows I READ The change in the magnitude of the charge accumulation layer of the cell transistor CTr of the memory cell MC[q] is shown. The timing chart of FIG. 63B shows an example of an operation for reading data from the memory cell MC[p] and the memory cell MC[q]. Electrons are injected into the charge accumulation layer of the cell transistor CTr of the memory cell MC[p], and electrons are not injected into the charge accumulation layer of the cell transistor CTr of the memory cell MC[q].

[0455] Before time T20, a low-level potential is supplied to the line SL.

[0456] Between time T20 and time T21, a high-level potential is supplied to the wiring BSL and the wiring SSL. As a result, a high-level potential is applied to the gates of the transistors BTr and STr, so that the transistors BTr and STr are turned on. In addition, as the transistor STr is turned on, a low-level potential supplied from the wiring SL is applied to the second terminal of the cell transistor CTr of the memory cell MC[1].

[0457] Between time T21 and time T22, the wiring WL[q] and the wiring WL[j] are supplied with a potential V PS As a result, a potential V PS At this time, if a low-level potential supplied from the line SL is applied to the second terminal of the cell transistor CTr of the memory cell MC[q] and / or the memory cell MC[j], the cell transistor CTr is turned on.

[0458] On the other hand, between time T21 and time T22, a low-level potential is supplied to the wiring WL[p]. As a result, a low-level potential is applied to the control gate of the cell transistor CTr of the memory cell MC[p]. In addition, since electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p], the threshold voltage of the cell transistor CTr of the memory cell MC[p] rises. For the above reasons, the cell transistor CTr of the memory cell MC[p] is turned off, and no current flows between the wiring SL and the wiring BL. At this time, by measuring the amount of current flowing through the wiring BL and showing that no current flows between the wiring SL and the wiring BL, it can be said that electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p].

[0459] Between time T22 and time T23, a low-level potential is supplied to each of the wirings WL[p], WL[q], and WL[j], so that a low-level potential is applied to the control gates of the cell transistors CTr of the memory cells MC[1] to MC[n].

[0460] Between time T23 and time T24, the wiring WL[j] is supplied with a potential V PS As a result, a potential V PS At this time, if a low-level potential supplied from the line SL is applied to the first terminal of the cell transistor CTr of the memory cell MC[j], the cell transistor CTr is turned on.

[0461] In addition, between time T23 and time T24, the wiring WL[p] is supplied with a potential V PS As a result, a potential V PS Since electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p], the threshold voltage of the cell transistor CTr of the memory cell MC[p] is increased. PS is applied, the cell transistor CTr is substantially in the on state in this operation example.

[0462] Then, between time T23 and time T24, a low-level potential is supplied to the line WL[q]. This causes a low-level potential to be applied to the control gate of the cell transistor CTr of the memory cell MC[j]. Since the cell transistor CTr of the memory cell MC operates with normally-on characteristics, even if a low-level potential supplied from the line SL is applied to the first terminal of the cell transistor CTr of the memory cell MC[j], the cell transistor CTr is in an on state.

[0463] That is, since each of the cell transistors CTr in the memory cells MC[1] to MC[n] is in the on state, a current flows between each of the source and drain. That is, by measuring the amount of current flowing through the wiring BL at this time and showing that a current flows between the wiring SL and the wiring BL, it can be said that electrons are not injected into the charge storage layer of the cell transistor CTr of the memory cell MC[q].

[0464] From time T24 to time T25, a low-level potential is supplied to each of the wirings WL[p], WL[q], and WL[j], so that a low-level potential is applied to the control gates of the cell transistors CTr of the memory cells MC[1] to MC[n].

[0465] After time T25, a low-level potential is supplied to the wirings BSL and SSL, so that the low-level potential is applied to the gates of the transistors BTr and STr, turning off the transistors BTr and STr.

[0466] In other words, when reading data from a memory cell MC, a low-level potential is applied to the control gate of the cell transistor CTr of the memory cell MC in question, and a high-level potential is applied to the control gate of the cell transistor CTr of the other memory cells MC, and the amount of current flowing between the wiring SL and the wiring BL is measured, thereby reading the data stored in the memory cell MC.

[0467] By the above operation, data can be written to and read from the semiconductor device shown in FIGS. 60A and 60B.

[0468] [Erase operation] Fig. 64A is a timing chart showing an example of an operation for erasing data held in a semiconductor device. The timing chart in Fig. 64A shows changes in the magnitude of the potential of the wiring WL[j] (here, j is an integer greater than or equal to 1 and less than or equal to n), the wiring BSL, the wiring SSL, the wiring BL, and the wiring SL. Note that an erase operation for a general NAND memory is performed in units of one block, and this operation example follows this procedure. However, one embodiment of the present invention is not limited thereto, and for example, an erase operation may be performed for each string.

[0469] Before time T30, a low-level potential is supplied to the wirings BL and SL.

[0470] Between time T30 and time T33, a low-level potential is constantly supplied to the line WL[j].

[0471] Between time T30 and time T31, a high-level potential is supplied to the wiring BSL and the wiring SSL. As a result, a high-level potential is applied to the gates of the transistors BTr and STr, and the transistors BTr and STr are turned on. In addition, as the transistors BTr and STr are turned on, a low-level potential supplied from the wiring SL is applied to the second terminal of the cell transistor CTr in the memory cell MC[1], and a low-level potential supplied from the wiring BL is applied to the first terminal of the cell transistor CTr in the memory cell MC[n].

[0472] Between time T31 and time T32, the wiring BL and the wiring SL are supplied with a potential V ER The potential V ER is set to a potential higher than the high-level potential flowing through the wiring BL and the wiring SL. As a result, the potentials of the channel formation regions of all the cell transistors CTr in the memory cells MC[1] to MC[n] rise, and the electrons injected into the charge storage layers of the cell transistors CTr are pulled out toward the channel formation regions.

[0473] Between time T32 and time T33, a low-level potential is supplied to the wirings BL and SL.

[0474] After time T33, a low-level potential is supplied to the wirings BSL and SSL, so that the low-level potential is applied to the gates of the transistors BTr and STr, turning off the transistors BTr and STr.

[0475] By the above operations, data can be erased from the semiconductor device shown in FIGS. 60A and 60B.

[0476] In the semiconductor device shown in Fig. 60B, by using the wiring BGL, an erase operation different from the above-described erase operation can be performed. An example of the operation is shown in Fig. 64B.

[0477] Before time T40, a low-level potential is supplied to the wirings BL and SL.

[0478] Between time T40 and time T45, a low-level potential is constantly supplied to the line WL[j].

[0479] Between time T40 and time T41, a low-level potential is supplied to the wiring BSL and the wiring SSL. As a result, a low-level potential is applied to the gates of the transistors BTr and STr, so that the transistors BTr and STr are turned off. As a result, a floating state is established between the second terminal of the transistor STr and the first terminal of the transistor BTr.

[0480] In addition, between time T40 and time T41, the wiring BGL is supplied with a potential V BGER A potential V BGER The area between the second terminal of the transistor STr and the first terminal of the transistor BTr is in a floating state, and the potential of the wiring BGL is VBGER As a result, the potential of the channel formation region of each of the cell transistors CTr in the memory cells MC[1] to MC[n] is boosted by capacitive coupling, and the electrons injected into the charge storage layer of each of the cell transistors CTr are pulled out to the channel formation region.

[0481] Between time T41 and time T42, a high-level potential is supplied to the wirings BSL and SSL, whereby a high-level potential is applied to the gates of the transistors BTr and STr, turning on the transistors BTr and STr.

[0482] Between time T42 and time T43, a high-level potential is supplied to the wiring BL, which causes electrons extracted from the charge storage layer of the cell transistor CTr to flow into the wiring BL.

[0483] Between time T43 and time T44, a low-level potential is supplied to the wiring BL. Then, between time T44 and time T45, a low-level potential is supplied to the wiring BSL and the wiring SSL. As a result, a low-level potential is applied to the gates of the transistors BTr and STr, so that the transistors BTr and STr are turned off. Finally, after time T45, a low-level potential is supplied to the wiring BGL.

[0484] As described above, data can be erased from the semiconductor device in FIG. 60B by using the wiring BGL.

[0485] <Structural example of semiconductor device> Next, a structural example of the semiconductor device shown in FIG. 61 or FIG. 62 will be described.

[0486] Fig. 65A to Fig. 65C are examples of schematic diagrams showing a part of the semiconductor device of Fig. 61 or Fig. 62. Fig. 65A shows a perspective view of a part of the semiconductor device, and Fig. 65B shows a top view of Fig. 65A. Furthermore, Fig. 65C shows a cross-sectional view corresponding to the dashed line Z1-Z2 of Fig. 65B.

[0487] The semiconductor device has a structure in which wiring WL and an insulator (a region not shown with hatching in FIGS. 65A to 65C) are stacked.

[0488] An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. Then, in order to provide a memory cell MC in the region AR through which the wiring WL penetrates, an insulator, a conductor, and a semiconductor are formed in the opening. The conductor functions as a source electrode or a drain electrode of the cell transistor CTr of the memory cell MC, and the semiconductor functions as a channel formation region of the cell transistor CTr. Alternatively, the conductor may not be formed, and a channel formation region and a low resistance region may be formed in the semiconductor, and the low resistance region may be used as a source electrode or a drain electrode of the cell transistor CTr. In Figs. 65A to 65C, the region in which the insulator, the conductor, and the semiconductor are formed in the opening is illustrated as a region HL. In particular, in Fig. 65A, the region HL inside the structure is illustrated by a broken line. When a back gate is provided in the transistor of the memory cell MC, the conductor in the region HL may also function as a wiring BGL for electrically connecting to the back gate.

[0489] In other words, in Figure 65C, the semiconductor device shown in either Figure 60A or Figure 60B is formed in region SD1, and the semiconductor device shown in Figure 61 or Figure 62 is formed in region SD2.

[0490] Incidentally, the region TM where the wiring WL is exposed functions as a connection terminal for applying a potential to the wiring WL. That is, by electrically connecting the wiring to the region TM, a potential can be applied to the gate of the cell transistor CTr.

[0491] 1, 2A, and 2B of embodiment 1. In this case, a charge storage layer of the semiconductor device is formed between the wiring WL and the region HL, although not shown.

[0492] 28, 29A, and 29B of the embodiment 2. In this case, a floating gate electrode of the semiconductor device is formed between the wiring WL and the region HL, although not shown.

[0493] Note that the shape of the region TM is not limited to the example configuration shown in Figures 65A to 65C. The configuration of the semiconductor device according to one embodiment of the present invention may be, for example, a configuration in which an insulator is formed on the region TM shown in Figures 65A to 65C, an opening is provided in the insulator, and a conductor PG is formed to fill the opening (Figures 66A to 66C). Note that a wiring ER is formed on the conductor PG, and the wiring ER and the wiring WL are electrically connected to each other. Note that in Figure 66A, the conductor PG provided inside the structure is illustrated by a dashed line, and the dashed line of the region HL is omitted.

[0494] The semiconductor device may have peripheral circuits of the memory cell array, such as a read circuit and a precharge circuit, formed in a lower layer. In this case, Si transistors are formed on a silicon substrate or the like to form the peripheral circuits, and then the semiconductor device according to the aspect of the present invention described in the first or second embodiment is formed on the peripheral circuits. FIGS. 67A and 69 are cross-sectional views in which the peripheral circuits are formed of planar Si transistors and the semiconductor device according to the aspect of the present invention is formed in the upper layer. FIGS. 68A and 70 are cross-sectional views in which the peripheral circuits are formed of FIN Si transistors and the semiconductor device according to the aspect of the present invention is formed in the upper layer. The semiconductor devices shown in FIGS. 67A and 68A are, for example, the semiconductor device shown in FIG. 1, and the semiconductor devices shown in FIGS. 69 and 70 are, for example, the semiconductor device shown in FIG. 28.

[0495] In addition, the semiconductor devices in Figures 67A, 68A, 69, and 70 are illustrated with conductor 1221 for electrically connecting to one of the source or drain of a cell transistor at one end of a string, conductor 1222 and conductor 1223 electrically connected to the back gate electrode of the cell transistor included in the string, insulator 1202, and insulator 1203.

[0496] The conductor 1221 is provided so as to be in contact with the insulator 412, the conductor 431, and the material layer 451 on the upper surface of the stack of the cell transistor. The insulator 1202 is formed so as to cover the stack of the cell transistor and the conductor 1221. The insulator 1202 has an opening so as to expose the back gate electrode (conductor 432) of the cell transistor, and the conductor 1222 is provided so as to fill the opening. The conductor 1223 is provided so as to be in contact with the conductor 1222. The insulator 1203 is formed so as to cover the conductor 1223, the insulator 1202, and the stack of the cell transistor.

[0497] The conductor 1221, the conductor 1222, and the conductor 1223 are preferably made of a material that can be used for the conductor 432, for example.

[0498] The insulator 1202 and the insulator 1203 are preferably made of, for example, a material that can be used for the insulator 412. In particular, the insulator 1202 and the insulator 1203 preferably have a barrier insulating film that suppresses diffusion of impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N2O, NO, NO2, etc.) into the stack of the cell transistor.

[0499] In addition, in the semiconductor devices of Figures 67A, 68A, 69, and 70, transistors corresponding to transistor STr and transistor BTr are omitted, but these transistors may be provided between the stack having the cell transistor and the insulator 1202, and between the stack having the cell transistor and the insulator 1201.

[0500] 67A, 68A, 69, and 70, Si transistors constituting the peripheral circuit are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors. Conductors 1730 are formed to extend in the channel width direction, and are connected to other Si transistors or the conductors 1712 (not shown).

[0501] The substrate 1700 can be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like.

[0502] In addition, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminate film, paper containing a fibrous material, a base film, or the like may be used as the substrate 1700. In addition, a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. In Fig. 67A, Fig. 68A, Fig. 69, and Fig. 70, as an example, a single crystal silicon wafer is used as the substrate 1700.

[0503] Here, the details of the Si transistor will be described. The planar type Si transistor shown in FIG. 67A and FIG. 69 shows a cross-sectional view in the channel length direction, and the planar type Si transistor shown in FIG. 67B shows a cross-sectional view in the channel width direction. The Si transistor has a channel formation region 1793 provided in a well 1792, a low concentration impurity region 1794 and a high concentration impurity region 1795 (collectively simply referred to as impurity regions), a conductive region 1796 provided in contact with the impurity regions, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of metal silicide or the like.

[0504] 68A and 70 show cross-sectional views in the channel length direction, and the FIN type Si transistor shown in Fig. 68B shows a cross-sectional view in the channel width direction. In the Si transistor shown in Fig. 68A, 68B, and 70, a channel formation region 1793 has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and upper surface of the channel formation region 1793. In this embodiment, a case has been shown in which a convex portion is formed by processing a part of a semiconductor substrate, but a semiconductor layer having a convex shape may also be formed by processing an SOI substrate.

[0505] An insulator 1201 is formed on the upper layer of a circuit formed on a substrate 1700 by a Si transistor, a conductor 1712, a conductor 1730, and the like. A conductor 1211 for electrically connecting to the circuit is formed so as to be embedded in the insulator 1201. When a metal oxide is contained in the channel formation region of the cell transistor CTr, it is preferable to use an insulator having a barrier property against hydrogen and the like as the insulator 1201 and the conductor 1211. This is to suppress the diffusion of hydrogen from the Si transistor to the cell transistor CTr through the insulator 1201 and / or the conductor 1211.

[0506] For the insulator 1201, any of the materials that can be used for the insulators 411A to 411C described above can be used.

[0507] For example, tantalum nitride having a barrier property against hydrogen may be used as the conductor 1211. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from a Si transistor can be suppressed while maintaining the conductivity as a wiring.

[0508] It should be noted that the symbols shown in Figures 68A, 68B, 69, and 70 are the same as the symbols shown in Figures 67A and 67B.

[0509] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0510] (Embodiment 6) In this embodiment, a semiconductor device having a different configuration from the semiconductor device described in the first embodiment will be described.

[0511] As an example, the configuration of a cell transistor and a memory cell array of a semiconductor device will be described with reference to FIGS. 71A to 71D, 72A to 72C, and 73. FIG. 71A is a top view of a memory cell array 700, and FIG. 71B is a cross-sectional view of a portion indicated by dashed line Y1-Y2 in FIG. 71A. FIG. 71C is a cross-sectional view of a portion indicated by dashed line Y3-Y4 in FIG. 71A, which is a cross-sectional view explaining a memory string. FIG. 71D is an enlarged cross-sectional view of a portion surrounded by a dashed line in FIG. 71B, and FIGS. 72A and 72B are enlarged perspective views of a portion surrounded by a dashed line in FIG. 71B, which are diagrams explaining a cell transistor 710 functioning as a memory cell. FIG. 72C is an enlarged perspective view of a portion surrounded by a dashed line in FIG. 71C, which is a diagram explaining a transistor functioning as a selection transistor. 71A to 71C, an orthogonal coordinate system consisting of x-axis, y-axis, and z-axis is set for convenience in the following description. Here, the x-axis and y-axis are parallel to the upper surface of the base 720 on which the memory cell array 700 is provided, and the z-axis is perpendicular to the upper surface of the base 720.

[0512] The memory cell array 700 has a stack of conductors 701 (conductors 701_1 to conductors 701_m: m is a natural number of 2 or more) or conductors 702 and insulating films stacked alternately on a base 720, an insulator 703 (insulators 703_1 to 703_4) is provided inside an opening formed to penetrate the stack, an oxide 704 (oxide 704_1 to oxide 704_4) is provided inside the insulator 703, and upper ends of the oxides 704_1 to 704_4 are electrically connected to the oxides 704_1 to 704_4, respectively. The semiconductor device includes a conductor 705 (conductor 705_1 to conductor 705_4), a conductor 706 (conductor 706_1 to conductor 706_4) electrically connected to the lower ends of the oxides 704_1 to 704_4, a conductor 707 (conductor 707_1 to conductor 707_m) electrically connected to the conductors 701_1 to conductor 701_m, and a conductor 708 (conductor 708_1 to conductor 708_m) electrically connected to the conductors 707_1 to conductor 707_m. Note that, in FIG. 71B, four or more stages of the conductors 701 are shown to represent the multiple conductors 701, but this embodiment is not limited to FIG. 71B, and it is sufficient that the semiconductor device includes at least two stages of the conductors 701.

[0513] 71A, the memory cell array 700 has a stacked body on the SOL side connected to the source line SOL and a stacked body on the BIL side electrically connected to the bit line BIL. The source line SOL and the bit line BIL will be described later.

[0514] Here, as shown in FIG. 71A and FIG. 71B, the conductor 701 is provided extending in the x-axis direction. As shown in FIG. 71B and FIG. 71C, the insulator 703 and the oxide 704 are provided extending in the z-axis direction. That is, it is preferable that the conductor 701, the insulator 703, and the oxide 704 are provided perpendicularly intersecting each other. As shown in FIG. 71B, the conductor 707 is provided extending in the z-axis direction. The conductor 708 may be provided extending in the y-axis direction. A conductor functioning as a bit line BIL connected to the conductor 705 may be provided extending in the y-axis direction. A part of the conductor 705 may function as the bit line BIL, and the conductor 705 may be provided extending in the y-axis direction.

[0515] The oxide 704 is formed in a columnar shape and extends in the z-axis direction. The insulator 703 is provided so as to surround the side periphery of the columnar oxide 704. The conductor 707 is formed in a columnar shape and extends in the z-axis direction.

[0516] The lower end of the columnar oxide 704 in the z-axis direction is electrically connected to the conductor 706, and the upper end is electrically connected to the conductor 705. As shown in Fig. 71C, the conductor 706 is electrically connected to the lower ends of two adjacent columnar oxides 704, and the upper ends of the two columnar oxides 704 are each electrically connected to the electrically separated conductor 705.

[0517] Here, the vicinity of the region where the conductor 701 intersects with the insulator 703 and the oxide 704 functions as a cell transistor. The vicinity of the region where the conductor 702 intersects with the insulator 703 and the oxide 704 functions as a selection transistor. The channel length direction of these cell transistors and selection transistors is parallel to the z-axis. The cell transistors or selection transistors are electrically connected in series, and they form a memory string.

[0518] Note that the configuration of the semiconductor device shown in this embodiment is one example, and the present invention is not limited to the number and arrangement of circuit elements, wirings, etc. shown in the drawings of this embodiment. The number and arrangement of circuit elements, wirings, etc. included in the semiconductor device of this embodiment can be appropriately designed and determined according to the circuit configuration and driving method.

[0519] The base 720 on which the memory cell array 700 is provided preferably has an insulating surface. As the substrate having an insulating surface, a semiconductor substrate having an insulating film formed on its surface, an insulating substrate, a conductive substrate having an insulator formed on its surface, or the like may be used. Note that the semiconductor substrate, insulating substrate, or conductive substrate used as the base 720 may be, for example, a substrate that can be used for the semiconductor device described in Embodiment 1.

[0520] Conductor 701 functions as the gate of the cell transistor and is electrically connected to the word line. That is, conductor 701, conductor 707, and conductor 708 also function as part of the word line. Here, conductor 701 is preferably provided in a stepped shape in which lower conductor 701 extends further toward the Y2 side than upper conductor 701, as shown in FIG. 71B. By providing conductor 701 in this way, a part of the upper surface of lower conductor 701 does not overlap with upper conductor 701, so that the corresponding area of ​​each layer of conductor 701 can be connected to each conductor 707.

[0521] The conductor 701 may be made of a conductive material such as silicon doped with impurities or a metal. When silicon is used as the conductor 701, amorphous silicon or polysilicon may be used. In addition, in order to make silicon conductive, p-type impurities or n-type impurities may be added. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel may be used as the conductor 701. When a metal material is used as the conductor 701, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. may be used.

[0522] The conductor 702 is provided on the conductor 701. The conductor 702 functions as the gate of a selection transistor (a bit line side selection transistor: SDT and a source line side selection transistor: SST). The conductor 702 may be made of the same material as the conductor 701. The conductor 702 may be made of the same material as the conductor 701, or may be made of a different material. Depending on the application of the conductors 701 and 702, the materials used for the conductors 701 and 702 may be determined in consideration of the work function and the like.

[0523] As the insulating film provided in the upper layer and the lower layer of the conductor 701 and the conductor 702, an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like having insulating properties can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having voids, etc., have low relative dielectric constants and are therefore suitable for use as the insulating film. Note that an oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and a nitride oxide refers to a material having a composition that contains more nitrogen than oxygen. Also, a metal oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and a metal nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0524] On the other hand, it is also possible to use aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, nitride containing silicon and hafnium, or the like as the insulating film, but since these have a high relative dielectric constant, parasitic capacitance may occur between the conductors 701 or between the conductors 701 and 702. The material used for the insulating film can be determined depending on the design and application of the device.

[0525] 72A, the insulator 703 includes an insulator 703a, an insulator 703b, and an insulator 703c. The insulator 703a is provided on the conductor 701 side, the insulator 703c is provided on the oxide 704 side, and the insulator 703b is provided between the insulator 703a and the insulator 703c. In particular, in a cell transistor near a region where the conductor 701 intersects with the insulator 703 and the oxide 704, the insulator 703a functions as a gate insulating layer, the insulator 703b functions as a charge storage layer, and the insulator 703c functions as a tunnel insulating layer.

[0526] As shown in FIG. 72C, the selection transistor may not have a charge storage layer and a tunnel insulating layer. Therefore, in the bit line side transistor: SDT and the source line side transistor: SST, the insulator 703 may be configured to have only the insulator 703a without providing the insulators 703b and 703c. In addition, in FIG. 72A and FIG. 72C, the oxide 704 has a two-layer structure of the oxide 704a and the oxide 704b, but is not limited thereto. As shown in FIG. 72B, the oxide 704 may have a three-layer structure of the oxide 704a, the oxide 704b, and the oxide 704c, or may have a stacked structure of four or more layers. In addition, the insulator 711 may be provided inside the oxide 704b.

[0527] The insulator 703a is preferably made of silicon oxide or silicon oxynitride. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, these may be stacked to form the insulator 703a.

[0528] The insulator 703b is preferably made of a material that functions as a charge storage layer, and is preferably made of silicon nitride or silicon nitride oxide. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used.

[0529] The insulator 703c is preferably made of silicon oxide or silicon oxynitride. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may also be used. The insulator 703c may be formed by stacking these. The insulator 703c is preferably thinner than the insulator 703a. As will be described in detail later, when writing or erasing data to the cell transistor, charge is transferred between the oxide 704 and the insulator 703b through the insulator 703c. That is, the insulator 703c functions as a tunnel insulating layer.

[0530] In particular, when the insulator 703 is formed in an opening provided in a laminate having the conductor 701, the conductor 702, and an insulating film, the insulator 703 formed at the bottom of the opening needs to be removed by anisotropic etching using dry etching or the like. During anisotropic etching, the side surface of the insulator 703c is also exposed to plasma, radicals, gas, chemicals, and the like. If the side surface of the insulator 703c is damaged by these, a trap center may be generated in the insulator 703c, which may affect the electrical characteristics of the transistor. In order to suppress the generation of the trap center, the side surface of the insulator 703c is required to have high resistance to damage caused by etching. In this case, it is preferable to use aluminum oxide, a stack of silicon oxide and aluminum oxide, or a stack of silicon oxynitride and aluminum oxide as the insulator 703c.

[0531] The insulators 703a, 703b, and 703c can be formed by an ALD method, a CVD method, etc. In order to prevent contamination of the interfaces of the insulators 703a, 703b, and 703c, it is preferable to form the insulators 703a, 703b, and 703c in succession without exposure to the air atmosphere in the same chamber or by using a multi-chamber film formation apparatus having multiple chambers.

[0532] It is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 704. More preferably, it is preferable to use an oxide semiconductor with high field-effect mobility. Such an oxide semiconductor has better on-state characteristics of a transistor and can achieve high mobility, compared to a semiconductor made of silicon or the like.

[0533] For example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 704. In particular, it is preferable to use In-Ga-Zn oxide. Alternatively, In-Ga oxide or In-Zn oxide may be used as oxide 704.

[0534] By using an oxide semiconductor with high field-effect mobility in a semiconductor device, the write, read, or erase operation can be made faster in some cases.

[0535] As shown in Fig. 71D, Fig. 72A, and Fig. 72C, the oxide 704 preferably has an oxide 704a provided on the insulator 703c side and an oxide 704b provided inside the oxide 704a. Fig. 71D is an enlarged view of the cell transistor 710 surrounded by a dashed line in Fig. 71B. In this case, it is preferable to use an oxide having a relatively wide energy gap for the oxide 704a compared to the oxide 704b. Here, an oxide having a wide energy gap is sometimes called a wide gap, and an oxide having a narrow energy gap is sometimes called a narrow gap.

[0536] When the oxide 704a has a wide gap and the oxide 704b has a narrow gap, it is preferable that the energy of the conduction band minimum of the oxide 704a is higher than that of the oxide 704b, or in other words, that the electron affinity of the oxide 704a is smaller than that of the oxide 704b.

[0537] In addition, it is preferable that the oxide 704a and the oxide 704b are combined in such a way that the atomic ratio of each metal atom is different. Specifically, in the metal oxide used for the oxide 704a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 704b. In addition, it is preferable that the atomic ratio of element M to In in the metal oxide used for the oxide 704a is larger than the atomic ratio of element M to In in the metal oxide used for the oxide 704b. In addition, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide 704b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 704a.

[0538] As described in the first embodiment, the oxide 704a may be a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition close thereto. The oxide 704b may be a metal oxide having a composition of In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close thereto. The oxide 704b may be a metal oxide having a composition of In:Zn=5:1, or In:Zn=10:1, or a composition close thereto. The oxide 704b may be indium oxide.

[0539] It is preferable to combine these oxides 704a and 704b so as to satisfy the above-mentioned atomic ratio relationship. For example, it is preferable to make oxide 704a a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition close thereto, and make oxide 704b a metal oxide having a composition of In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1 or a composition close thereto. Note that the above composition indicates the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target.

[0540] The oxide 704a and the oxide 704b may be formed by a sputtering method, a plasma CVD method, a thermal CVD method (such as an ALD method or an MOCVD method), or the like. In order to prevent contamination of the interface between the oxide 704a and the oxide 704b, it is preferable to form the oxides 704a and 704b in succession without exposing them to the air atmosphere in the same chamber or by using a multi-chamber film formation apparatus having multiple chambers. Therefore, it is more preferable to form the oxide 704a and the oxide 704b in succession to the insulator 703a, the insulator 703b, and the insulator 703c.

[0541] It is preferable that the oxide 704a is made of the CAAC-OS described in the fourth embodiment, and the oxide 704b is made of the CAC-OS. When the CAAC-OS is used as the oxide 704a, the c-axis is preferably oriented parallel to the xy plane shown in FIG. 71A, i.e., perpendicular to the z-axis, and from the side surface of the opening toward the center.

[0542] Here, the conduction band minimum changes gradually at the junction between the oxide 704a and the oxide 704b. In other words, the conduction band minimum at the junction between the oxide 704a and the oxide 704b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 704a and the oxide 704b.

[0543] Specifically, the oxide 704a and the oxide 704b have a common element other than oxygen (as a main component), so that a mixed layer with a low defect state density can be formed. For example, when the oxide 704b is an In-Ga-Zn oxide, the oxide 704a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide. This can reduce the defect state density at the interface between the oxide 704a and the oxide 704b. Therefore, the effect of the interface scattering on carrier conduction is reduced, and the cell transistor 710 can obtain a high on-current.

[0544] Note that a more detailed description of metal oxides that can be used as the oxide 704 will be given later.

[0545] As shown in Figures 71D and 72A, oxide 704b is provided so as to be surrounded by oxide 704a. In the case of such a configuration, when carriers are caused to flow in oxide 704 in the direction from conductor 705 to conductor 706 or in the direction from conductor 706 to conductor 705, the carriers mainly flow in the component having the narrow gap. For this reason, when the above configuration is used, a high current driving force, that is, a large on-current and a high field-effect mobility can be obtained in the on-state of the transistor.

[0546] Furthermore, by providing the oxide 704a between the oxide 704b and the insulator 703c, the oxide 704b, which serves as a carrier path, is not in direct contact with the insulator 703c, and the formation of a trap center can be suppressed. The trap center formed at the interface between a semiconductor (oxide semiconductor) and an insulator captures electrons and shifts the threshold voltage of the transistor in the positive direction, which may adversely affect the reliability and on / off characteristics of the transistor. Therefore, a transistor using the oxide is not affected by the electrical characteristics of the trap center, and can therefore obtain a higher current driving force in the on state, that is, a large on-current and a high field-effect mobility. Furthermore, the transistor and a semiconductor device using the transistor can obtain high reliability.

[0547] In addition, the oxide 704 shown in FIG. 71D and FIG. 72A is provided so that the oxide 704a surrounds the oxide 704b, but this embodiment is not limited to this. FIG. 72B shows another example of the cell transistor 710. In FIG. 72B, the cell transistor 710 is provided with the oxide 704a inside the insulators 703a, 703b, and 703c, the oxide 704b inside the oxide 704a, and the oxide 704c inside the oxide 704b. Also, the insulator 711 may be provided so as to be embedded inside the oxide 704c. Note that the insulator 711 is not necessarily provided, and the inside of the oxide 704c may be hollow.

[0548] The oxide 704b may be sandwiched between the oxide 704a and the oxide 704c. In this case, the oxide 704c is preferably a wide gap like the oxide 704a. By providing the wide gap oxide 704c, carriers flowing through the oxide 704 can be confined in the oxide 704b, and a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

[0549] Furthermore, when the insulator 711 is provided inside the oxide 704c, the insulator 711 is preferably a material capable of supplying oxygen to the oxide 704 or a material capable of supplying impurities such as hydrogen or nitrogen. By using an oxide containing as little hydrogen or nitrogen as the insulator 711, oxygen may be supplied to the oxide 704. By supplying oxygen to the oxide 704, impurities such as hydrogen and water contained in the oxide 704 can be removed, and the oxide 704 becomes highly purified. By using an oxide with as few impurities as possible as the oxide 704, a cell transistor and a semiconductor device using the transistor can have high reliability.

[0550] Furthermore, by using an oxide containing hydrogen or nitrogen as the insulator 711, hydrogen or nitrogen may be supplied to the oxide 704. Supplying hydrogen or nitrogen to the oxide 704 may reduce the resistance of the oxide 704. By reducing the resistance of the oxide 704 to a level that does not adversely affect the circuit operation, the cell transistor can be operated at a lower drive voltage. Furthermore, a high current drive force, i.e., a large on-current and high field-effect mobility, can be obtained when the cell transistor is in the on state.

[0551] In addition, the opening formed in the stack in which the cell transistor 710 is provided has a circular upper surface in FIGS. 71A, 72A, 72B, etc., but is not limited thereto. For example, the upper surface may be elliptical or polygonal, such as triangular or rectangular. In addition, in the case of a polygonal shape, the corners may be rounded. In addition, the upper surface shapes of the insulator 703 and the oxide 704 may also change according to the upper surface shape of the opening. In addition, the opening may have a shape in which the cross-sectional area of ​​the opening on the lower side (the conductor 706 side) is narrower than the cross-sectional area of ​​the opening on the upper side (the conductor 705 side).

[0552] A cell transistor is configured by the oxide 704, the insulator 703, and the conductor 701 (any one of the conductors 701_1 to 701_m). Fig. 71 shows an example in which the cell transistors are stacked in m stages (m is a natural number of 4 or more).

[0553] The conductor 705 is electrically connected to the oxide 704 and functions as a part of the source line SOL or the bit line BIL. It is preferable to use a conductive material containing a metal element as the conductor 705. In addition, it is preferable to form a metal compound layer containing the metal element of the conductor 705 and a comp...

Claims

1. A columnar first conductor; A second conductor and a third conductor; a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and a sixth insulator; a first material layer, a second material layer, and a third material layer; having the first insulator is positioned adjacent to the first conductor; the first material layer is positioned adjacent to the first insulator; the first material layer having a first region and a second region; the second material layer is positioned adjacent to the first region of the first material layer; the second conductor is positioned adjacent to the second material layer; the second insulator is positioned adjacent to the second conductor; the third insulator is positioned adjacent to the second insulator, the third material layer is positioned to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer; the fourth insulator is positioned adjacent to the third material layer; the sixth insulator is located adjacent to the fourth insulator, the fifth insulator is located adjacent to the sixth insulator, the third conductor is positioned adjacent to the fifth insulator; the second insulator functions as a barrier insulating film that prevents oxygen from diffusing into the second conductor; The fourth insulator functions as a tunnel insulating film, the sixth insulator functions as a charge storage layer; The fifth insulator functions as a gate insulating film; the first material layer comprises an oxide including indium, an element M, where M is aluminum, gallium, tin, or titanium, and zinc; the second material layer comprises an oxide containing indium, the element M, and zinc; the third material layer comprises an oxide containing indium, element M, and zinc; Semiconductor device.

2. A columnar first conductor; A second conductor, a third conductor, and a fourth conductor; a first insulator, a second insulator, a third insulator, a fourth insulator, and a fifth insulator; a first material layer, a second material layer, and a third material layer; having the first insulator is positioned adjacent to the first conductor; the first material layer is positioned adjacent to the first insulator; the first material layer having a first region and a second region; the second material layer is positioned adjacent to the first region of the first material layer; the second conductor is positioned adjacent to the second material layer; the second insulator is positioned adjacent to the second conductor; the third insulator is positioned adjacent to the second insulator, the third material layer is positioned to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer; the fourth insulator is positioned adjacent to the third material layer; the fourth conductor is located adjacent to the fourth insulator; the fifth insulator is positioned to cover the fourth conductor and the fourth insulator, the third conductor is positioned adjacent to the fifth insulator; the second insulator functions as a barrier insulating film that prevents oxygen from diffusing into the second conductor; The fourth insulator functions as a tunnel insulating film, The fourth conductor functions as a floating gate electrode; The fifth insulator functions as a gate insulating film; the first material layer comprises an oxide including indium, an element M, where M is aluminum, gallium, tin, or titanium, and zinc; the second material layer comprises an oxide containing indium, the element M, and zinc; the third material layer comprises an oxide containing indium, element M, and zinc; Semiconductor device.

3. In claim 1 or 2, the second region of the first material layer has a higher oxygen concentration than the first region of the first material layer; Semiconductor device.

4. 4. A memory device comprising: the semiconductor device according to claim 1; and a peripheral circuit.

5. An electronic device comprising the storage device according to claim 4 and a housing.

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