Accelerator control system, accelerator control method, and accelerator control program

Abstract

In an accelerator control device (10), a metadata buffer (11b) stores metadata including information specifying the location of processing data subject to calculation processing and the content of the calculation processing of an accelerator (20). When metadata on which calculation processing has been performed by the accelerator (20) is stored in the metadata buffer (11b), a polling function (13a) determines the completion of the calculation processing of the accelerator (20). In the accelerator (20), a read function (21b) acquires metadata from the metadata buffer (11b). A calculation function (24) performs calculation processing on processing data subject to calculation processing in accordance with information that is included in the acquired metadata and that specifies the location of the processing data subject to calculation processing and the operation of the accelerator (20). When the calculation processing is completed, a write function (21c) stores metadata in the metadata buffer (11b).

Description

[Technical field]

[0001] The present invention relates to an accelerator control system, an accelerator control method, and an accelerator control program. [Background technology]

[0002] Conventionally, there is known a technology for accelerating processing by incorporating a computation accelerator into a computation system. Because of the limitations of semiconductor miniaturization technology, it has become difficult to improve the operating frequency of processors and to highly integrate computing machines. This technology offloads specific processing to an accelerator, realizing high-performance calculations (see Non-Patent Documents 1 to 3).

[0003] Specifically, the CPU controls the accelerator through the accelerator API and device driver, and the accelerator reads the processing data copied to the kernel memory space and performs arithmetic processing that would take time to execute on the CPU. After executing the arithmetic processing, the accelerator notifies the CPU of the completion of the processing by a hardware interrupt. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] J. Yang, DB Minturn, F. Hady, “When Poll is Better than Interrupt”, FAST, vol.12, pp.3-3, [online], 2012, [Retrieved March 29, 2021], Internet<URL:https: / / www.usenix.org / system / files / conference / fast12 / yang.pdf> [Non-Patent Document 2] “CUDA Toolkit Documentation v11.2.2”, [online], NVIDIA, [Retrieved March 29, 2021], Internet<URL:https: / / docs.nvidia.com / cuda / > [Non-Patent Document 3] K. Gulati, S. P. Khatri, “GPU Architecture and the CUDA Programming Model”, Hardware acceleration of EDA algorithms, pp.23-30, [online], Springer, [Retrieved March 29, 2021], Internet<URL:https: / / link.springer.com / content / pdf / 10.1007%2F978-1-4419-0944-2_3.pdf> Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional technology, it can be difficult to use accelerators to speed up real-time processing. For example, because accelerators are controlled by the CPU, exclusive control and interrupt notifications of processing completion occur each time data is written to the accelerator, calculations are performed, data is read, and other processes are performed. In addition, memory copies occur in the user space and kernel space when data is read or written. These processes cause overhead and increase delays. When multiple accelerators exist, overhead also occurs, reducing scalability. Therefore, it is difficult to use accelerators in the real-time processing domain.

[0006] The present invention has been made in view of the above, and has an object to increase the speed of real-time processing by using an accelerator. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the accelerator control system of the present invention comprises an accelerator control device and an accelerator, wherein the accelerator control device comprises a memory unit that stores control data including information specifying the location of data to be processed and the content of the accelerator's processing, and a judgment unit that judges the completion of processing by the accelerator when the control data that has been processed by the accelerator is stored in the memory unit, and the accelerator comprises an acquisition unit that acquires the control data from the memory unit, an arithmetic unit that performs arithmetic processing on the data to be processed in accordance with information specifying the location of data to be processed and the content of the accelerator's processing contained in the acquired control data, and a storage unit that stores the control data in the memory unit when the arithmetic processing is completed. Effect of the Invention

[0008] According to the present invention, it is possible to increase the speed of real-time processing by using an accelerator. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram illustrating a schematic configuration of an accelerator control system according to the present embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the accelerator control system of the present embodiment. [Diagram 3] FIG. 3 is a diagram illustrating an example of the data structure of the metadata. [Figure 4] FIG. 4 is a diagram illustrating an example of the structure of the metadata buffer. [Diagram 5] FIG. 5 is a diagram for explaining the data buffer. [Figure 6] FIG. 6 is a flowchart showing the accelerator control processing procedure in the accelerator control device. [Figure 7] FIG. 7 is a flowchart showing an accelerator control process procedure in the accelerator. [Figure 8] FIG. 8 is a sequence diagram illustrating a procedure of the accelerator control process. [Figure 9] FIG. 9 is a diagram for explaining an embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a computer that executes an accelerator control program. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are indicated by the same reference numerals.

[0011] [Accelerator control system configuration] Fig. 1 is a schematic diagram illustrating a schematic configuration of an accelerator control system according to the present embodiment. As shown in Fig. 1, the accelerator control system 1 includes an accelerator control device 10 and an accelerator 20. The accelerator control device 10 and the accelerator 20 can communicate data with each other via a communication line such as a bus wiring.

[0012] The accelerator control device 10 is an information processing device realized by using a general-purpose processor such as a CPU (Central Processing Unit). In the accelerator control device 10, an application, which is a process defined by a user, is executed in a user space. In addition, in a kernel space, operation and management of physical devices such as the accelerator 20 and abstraction processing of the physical devices in the user space processing are performed.

[0013] The user memory space and the kernel memory space are realized by semiconductor memory elements such as RAM (Random Access Memory) and flash memory, or storage devices such as hard disks and optical disks, and function as storage units. The storage unit stores in advance the processing programs that operate the accelerator control device 10 and data used during the execution of the processing programs, or stores them temporarily each time processing is performed.

[0014] The control unit realized by using a general-purpose processor executes a processing program stored in the memory, thereby functioning as each functional unit such as a memory management function 12 of the device driver, a metadata control function 13, and an API 14 (described later), as exemplified in Fig. 1. The control unit may also include other functional units (not shown).

[0015] In the accelerator control device 10, data to be processed (hereinafter also referred to as processing data) is placed in a data buffer 11a in a user memory space on a user space. Control data (hereinafter also referred to as metadata) including information specifying the location of the data to be processed and the content of the accelerator's processing is placed in a metadata buffer 11b in a kernel memory space on a kernel space.

[0016] The accelerator 20 is a computation accelerator realized by a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), a DPU (Data Processing Unit), etc., and functions as various functional units such as a metadata access mechanism 21, a function control block 22, a data transfer function 23, and a computation function 24, as illustrated in FIG. 1.

[0017] The accelerator 20 reads the processing data and metadata to offload the arithmetic processing. Specifically, the accelerator 20 monitors whether or not metadata is arranged in the metadata buffer 11b by autonomous polling. If metadata is arranged, the accelerator 20 reads the arranged metadata, analyzes it, and drives the accelerator 20. In addition, the accelerator 20 stores the result of the arithmetic processing on the processing data in the data buffer 11a.

[0018] The accelerator control device 10 can proceed to the next process asynchronously with the accelerator 20. When the accelerator 20 completes the arithmetic process, it places the metadata in the metadata buffer 11b. This causes the accelerator control device 10 to consider the arithmetic process to be complete. The accelerator control device 10 also obtains the result of the arithmetic process on the processing data from the data buffer 11a and proceeds to the next process.

[0019] Specifically, the accelerator control device 10 determines the operation of the accelerator 20 by placing metadata including the location of the processing data and the contents of the computational processing in a metadata buffer 11b in the kernel memory space via a metadata control function 13 implemented in the device driver.

[0020] The accelerator control device 10 creates a data buffer 11a in the user memory space via the memory management function 12, which the accelerator control device 10 and the accelerator 20 can refer to, and places processing data therein.

[0021] The accelerator 20 has a metadata access mechanism 21. The metadata access mechanism 21 has a function of polling the metadata buffer 11b in the kernel memory space, a function of reading metadata, and a function of writing metadata to the metadata buffer, and can autonomously read metadata without relying on an explicit control signal from the accelerator control device 10.

[0022] Information such as the address of the metadata buffer 11b is notified to the accelerator 20 by the accelerator initialization function when the device driver is loaded.

[0023] The accelerator 20 reads the metadata from the metadata buffer 11b, and the metadata analysis function 22a analyzes the data and operates according to the description. The accelerator 20 drives the data reading function 23a in the data transfer function 23 based on the address and length information of the processing data included in the metadata, reads the processing data from the data buffer 11a, and uses it for the calculation in the calculation function 24. The calculation function 24 executes the calculation process based on the calculation information described in the metadata. The metadata analysis function 22a passes the analysis result to the calculation function 24 and sets the calculation process content by the calculation function 24.

[0024] After the arithmetic processing is completed, the result of the arithmetic processing is transferred from the arithmetic function 24 to the data writing function 23b, and written into the data buffer designated by the data transfer control function 22b. Then, a notification that the data transfer is completed is sent from the data transfer function 23 to the completion notification function 22c, and the metadata is written into the metadata buffer 11b by the writing function of the metadata access mechanism 21, and the operation of the accelerator 20 is completed.

[0025] In this way, in the accelerator control system 1, metadata for controlling data transfer and arithmetic processing is placed in the main memory, and the accelerator 20 autonomously polls and reads the metadata. This reduces the overhead of accelerator control such as interrupts, and enables real-time processing.

[0026] In addition, the accelerator 20 can directly transfer processing data to the user space of the accelerator control device 10, and the accelerator control device 10 and the accelerator 20 can be driven asynchronously, thereby reducing delays and CPU utilization.

[0027] Furthermore, since the accelerator 20 can operate by accessing the main memory of the accelerator control device 10, expansion to a plurality of accelerators 20 is possible, and scalability is greatly improved.

[0028] [Accelerator control device] Fig. 2 is a diagram for explaining the accelerator control system of this embodiment. As illustrated in Fig. 2, in the accelerator control device 10, the API 14 is a group of functions that can be called from an application, and provides functions necessary for the operation of the accelerator 20. For example, the API functions as a data buffer securing function, a data buffer releasing function, a metadata creating function, a metadata sending function, and a computation completion detecting function.

[0029] The data buffer securing function generates a data buffer 11a which is a storage area for transmitting data to and receiving data from the accelerator 20. The data buffer securing function calls the memory management function 12 and obtains area information of the data buffer 11a from the memory management function 12.

[0030] The data buffer release function deletes the data buffer 11a. The data buffer release function calls the memory management function 12, notifies it of area information of the data buffer 11a to be released, and releases the area.

[0031] The metadata creation function creates metadata, which is control data to which control information of the accelerator 20 is added. The metadata transmission function transmits the metadata created by the metadata creation function to the metadata control function 13. The computation completion detection function calls the metadata control function 13 and checks, based on the return value of the metadata control function 13, whether the processing of any of the accelerators 20 has ended.

[0032] The device driver exists in the kernel space and provides a set of functions such as a memory management function 12 and a metadata control function 13 for handling a specific device.

[0033] The memory management function 12 is called from the API 14 in the user space, and secures, releases and manages the area of ​​the data buffer 11a.

[0034] The metadata buffer 11b is a storage area for transmitting and receiving metadata to and from the accelerator 20, and is generated by an accelerator initialization function according to the number of accelerators 20. For example, the metadata buffer 11b stores metadata including the location of data to be processed and information specifying the content of the processing of the accelerator. The metadata buffer 11b also stores different metadata for each of the multiple accelerators 20.

[0035] The metadata buffer 11b includes an RQ (Request Queue) buffer that transmits metadata to the accelerator 20 and a CQ (Completion Queue) buffer that receives metadata from the accelerator 20.

[0036] The metadata control function 13 is called from the API 14 in the user space, and performs reading, writing and management of the RQ buffer / CQ buffer of the metadata buffer 11b. The metadata control function 13 has a polling function 13a and a writing function 13b.

[0037] The Polling function 13a polls the CQ buffer to confirm the completion of the calculation. That is, the Polling function 13a functions as a determination unit and monitors whether or not metadata that has been calculated by the accelerator 20 is stored in the metadata buffer 11b. Then, when metadata that has been calculated by the accelerator 20 is stored in the metadata buffer 11b, the Polling function 13a determines that the calculation process by the accelerator 20 is completed. Also, the writing function 13b writes to the RQ buffer.

[0038] [Accelerator] In the accelerator 20, the metadata access mechanism 21 includes a polling function 21a, a read function 21b, and a write function 21c as functions for accessing the metadata buffer 11b in the kernel space.

[0039] The Polling function 21a polls the RQ buffer of the metadata buffer 11b to check whether or not there is metadata in the RQ buffer. That is, the Polling function 21a functions as a monitoring unit and monitors whether or not there is metadata in the metadata buffer 11b.

[0040] The read function 21b functions as an acquisition unit and acquires metadata from the metadata buffer 11b. That is, when the Polling function 21a confirms that metadata is present in the RQ buffer, the read function 21b reads the metadata and transfers it to the function control block 22.

[0041] Furthermore, the writing function 21c writes the metadata into the CQ buffer of the metadata buffer 11b. That is, the writing function 21c functions as a storage unit, and stores the metadata into the metadata buffer 11b when the arithmetic processing is completed.

[0042] The function control block 22 controls the sharing of necessary data and drive / pause timing for each functional unit of the accelerator 20. The function control block 22 includes a metadata analysis function 22a, a data transfer control function 22b, and a completion notification function 22c.

[0043] The metadata analysis function 22a extracts information such as the operation and the address and length of the data buffer 11a from the metadata transmitted from the metadata access mechanism 21. The data transfer control function 22b provides a function for controlling the reading and writing of data in the data transfer function 23. The completion notification function 22c transfers the metadata to be written to the CQ buffer to the metadata access mechanism 21.

[0044] The calculation function 24 functions as a calculation unit and performs calculation processing on the processing data in accordance with the location of the processing data contained in the acquired metadata and information specifying the operation of the accelerator 20 .

[0045] Specifically, the calculation function 24 includes an input control function, a calculation circuit, and an output control function. The calculation circuit has multiple independent calculation circuits, and it is possible to define a calculation for each of them. The input control function inputs data sent from the data reading function 23a of the data transfer function 23 to an appropriate calculation circuit based on the metadata information sent from the function control block 22.

[0046] The output control function transfers the results of the arithmetic processing performed on the processing data output from the arithmetic circuit to the data writing function 23b of the data transfer function 23 at an appropriate timing.

[0047] The data writing function 23b of the data transfer function 23 functions as a storage unit and stores the results of the arithmetic processing on the processing data in the data buffer 11a.

[0048] Next, Fig. 3 is a diagram illustrating an example of the data configuration of metadata. As shown in Fig. 3, the metadata is composed of a total of 256 bits of data, including a 32-bit task ID, a 32-bit operation, a 32-bit length of read data, a 64-bit address of read data, a 32-bit length of write data, and a 64-bit address of write data.

[0049] Moreover, Fig. 4 is a diagram illustrating the structure of the metadata buffer. As shown in Fig. 4, the metadata shown in Fig. 3 is stored in the RQ buffer / CQ buffer. The head information of the RQ buffer shown in Fig. 4 is controlled by the metadata control function 13. The metadata control function 13 forms the metadata transmitted from the metadata transmission function of the API 14 into the configuration shown in Fig. 3, stores it in the RQ buffer, and then shifts the head information to the next position.

[0050] Similarly, when the metadata control function 13 is called by the computation completion detection function of the API 14 using the head information in the CQ buffer, it reads metadata from the CQ buffer and shifts the head to the next position.

[0051] FIG. 5 is a diagram for explaining the data buffer. The memory management function 12 manages the address and state of the data buffer 11a with a table illustrated in FIG. 5. As shown in FIG. 5, the table manages the physical address of the data buffer 11a and the state of that address. When setting metadata for the accelerator 20, the key is referenced to obtain the physical address of the desired data buffer 11a, and the read data address and write data address are set. This allows management to absorb the difference between virtual addresses in the kernel space and the user space.

[0052] [Accelerator control processing] Next, accelerator control processing by the accelerator control system 1 according to this embodiment will be described with reference to Fig. 6 to Fig. 8. Fig. 6 is a flowchart showing the accelerator control processing procedure in the accelerator control device 10. The flowchart in Fig. 6 starts, for example, when an application issues an instruction to start the process.

[0053] First, the accelerator control device 10 secures the data buffer 11a (step S1). The accelerator control device 10 also stores (places) processing data to be passed to the accelerator 20 in the data buffer 11a (step S2).

[0054] The accelerator control device 10 also sets metadata information (step S3) and submits it to the RQ buffer of the metadata buffer 11b (step S4). Then, the accelerator control device 10 performs processing that does not depend on the calculation result of the accelerator 20 (step S5).

[0055] When the accelerator control device 10 uses the calculation result of the accelerator 20, it accesses the CQ buffer of the metadata buffer 11b and checks whether the accelerator 20 has sent metadata (step S6). If there is no metadata in the CQ buffer (step S6, No), the accelerator control device 10 returns the process to step S5. On the other hand, if there is metadata in the CQ buffer (step S6, Yes), the accelerator control device 10 determines that this is a notification of the completion of the calculation process, obtains the calculation result of the processing data from the data buffer 11a, and continues the process (step S7).

[0056] If the accelerator 20 is to be used again (step S8, No), the accelerator control device 10 returns the process to step S2. In this case, the data buffer 11a can be reused. On the other hand, if the accelerator 20 does not need to be used again (step S8, Yes), the accelerator control device 10 releases the area of ​​the data buffer 11a when the application is terminated (step S9). This ends the series of processes.

[0057] 7 is a flowchart showing an accelerator control process procedure in the accelerator 20. The flowchart in Fig. 7 is started, for example, at a predetermined interval. The accelerator 20 monitors the RQ buffer of the metadata buffer 11b by polling (step S11).

[0058] If the metadata is not set in the RQ buffer (step S12, No), the accelerator 20 returns the process to step S11. On the other hand, if the metadata is set in the RQ buffer (step S12, Yes), the accelerator 20 reads and analyzes the metadata (step S13).

[0059] Based on the analysis result, the accelerator 20 acquires the processing data from the data buffer 11a (step S14) and performs the calculation process (step S15). Next, the accelerator 20 writes the processing data that has been calculated into the data buffer 11a (step S16), transmits metadata to the CQ buffer (step S17), and completes the process. After that, the accelerator 20 returns the process to step S11.

[0060] Next, Fig. 8 is a sequence diagram showing the accelerator control processing procedure. In the example shown in Fig. 8, the accelerator 20 is implemented by an FPGA. As shown in Fig. 8, first, the accelerator control device 10 places processing data for arithmetic processing in a shared memory space (data buffer 11a) (step S21). In addition, the accelerator control device 10 places metadata for the accelerator 20 in an RQ buffer of the metadata buffer 11b on the kernel memory space via a device driver (step S22).

[0061] The accelerator 20 monitors whether metadata is placed in the RQ buffer by polling (step S23). If metadata is placed in the RQ buffer, the accelerator 20 reads the metadata, analyzes the processing content described in the metadata and the location of the processing data, and reads the processing data (step S24).

[0062] The accelerator 20 writes the processed data after the computation process to the data buffer 11a (step S25), and writes the metadata to the CQ buffer of the metadata buffer 11b (step S26).

[0063] The accelerator control device 10 accesses the CQ buffer to check whether metadata is arranged therein, and detects the completion of the arithmetic processing of the accelerator 20 when the metadata is arranged therein (step S27). In this case, the accelerator control device 10 obtains the data of the arithmetic processing result from the data buffer 11a (step S28).

[0064] [effect] As described above, in the accelerator control system 1 of this embodiment, the metadata buffer 11b in the accelerator control device 10 stores metadata including the location of the processing data to be processed and information specifying the content of the processing by the accelerator 20. When metadata processed by the accelerator 20 is stored in the metadata buffer 11b, the polling function 13a determines the completion of the processing by the accelerator 20. In the accelerator 20, the read function 21b acquires metadata from the metadata buffer 11b. The processing function 24 performs processing on the processing data to be processed according to the location of the processing data to be processed and information specifying the operation of the accelerator 20, which are included in the acquired metadata. When the processing is completed, the write function 21c stores the metadata in the metadata buffer 11b.

[0065] As a result, the accelerator control system 1 reduces overhead such as exclusive control, interrupt notification of processing completion, memory copy, etc., in processing using the accelerator 20, making it possible to perform real-time processing at high speed.

[0066] In addition, the Polling function 21a monitors whether or not there is metadata in the metadata buffer 11b, which enables the accelerator 20 to perform processing autonomously.

[0067] In addition, the Polling function 13a monitors whether or not there is processed metadata in the metadata buffer 11b. This enables the accelerator control device 10 to perform processing asynchronously with the accelerator 20.

[0068] The data writing function 23b stores the result of the arithmetic processing on the processing data to be processed in the data buffer 11a. This allows the accelerator control device 10 to perform processing asynchronously with the accelerator 20, except when using the arithmetic processing result of the accelerator 20, thereby enabling the speed of processing using the accelerator 20 to be increased.

[0069] Furthermore, the metadata buffer 11b stores different metadata for each of the multiple accelerators 20. This improves scalability using the multiple accelerators 20.

[0070] [Example] Fig. 9 is a diagram for explaining an example. Fig. 9 illustrates the measured values ​​of the time taken for processing data to loop back from the accelerator control device 10 via the accelerator 20 and return in the process by the accelerator control system 1 of the above embodiment (proposed method) and the process by the conventional technology (conventional method). Here, the bus technology used is PCIe Gen3 x8 in the conventional method, and PCIe Gen3 x16 in the proposed method.

[0071] In Fig. 9, for example, for 128Kbyte data, the latency of the conventional method is over 160usec, whereas the latency of the proposed method is 20usec. Thus, it was confirmed that the proposed method can achieve higher speeds than the conventional method.

[0072] [program] A program in which the processing executed by the accelerator control device 10 according to the above embodiment is written in a language executable by a computer can also be created. As an embodiment, the accelerator control device 10 can be implemented by installing an accelerator control program that executes the above accelerator control processing as package software or online software on a desired computer. For example, the accelerator control program can be executed by an information processing device to cause the information processing device to function as the accelerator control device 10. The information processing device referred to here includes desktop or notebook personal computers. In addition, the information processing device also includes mobile communication terminals such as smartphones, mobile phones, and PHS (Personal Handyphone System), and further slate terminals such as PDA (Personal Digital Assistant). The functions of the accelerator control device 10 may be implemented in a cloud server.

[0073] 10 is a diagram showing an example of a computer that executes an accelerator control program. The computer 1000 includes, for example, a memory 1010, a CPU 1020, a hard disk drive interface 1030, a disk drive interface 1040, a serial port interface 1050, a video adapter 1060, and a network interface 1070. These components are connected by a bus 1080.

[0074] The memory 1010 includes a ROM (Read Only Memory) 1011 and a RAM 1012. The ROM 1011 stores a boot program such as a BIOS (Basic Input Output System). The hard disk drive interface 1030 is connected to a hard disk drive 1031. The disk drive interface 1040 is connected to a disk drive 1041. A removable storage medium such as a magnetic disk or an optical disk is inserted into the disk drive 1041. The serial port interface 1050 is connected to a mouse 1051 and a keyboard 1052, for example. The video adapter 1060 is connected to a display 1061, for example.

[0075] Here, the hard disk drive 1031 stores, for example, an OS 1091, an application program 1092, a program module 1093, and program data 1094. Each piece of information described in the above embodiments is stored in the hard disk drive 1031 or memory 1010, for example.

[0076] The accelerator control program is stored in the hard disk drive 1031, for example, as a program module 1093 in which instructions to be executed by the computer 1000 are written. Specifically, the hard disk drive 1031 stores the program module 1093 in which each process executed by the accelerator control device 10 described in the above embodiment is written.

[0077] Furthermore, data used for information processing by the accelerator control program is stored as program data 1094, for example, in the hard disk drive 1031. Then, the CPU 1020 reads out the program module 1093 and the program data 1094 stored in the hard disk drive 1031 into the RAM 1012 as necessary, and executes each of the above-mentioned procedures.

[0078] The program module 1093 and program data 1094 related to the accelerator control program are not limited to being stored in the hard disk drive 1031, and may be stored in, for example, a removable storage medium and read by the CPU 1020 via the disk drive 1041 or the like. Alternatively, the program module 1093 and program data 1094 related to the accelerator control program may be stored in another computer connected via a network such as a LAN or a WAN (Wide Area Network), and read by the CPU 1020 via the network interface 1070.

[0079] Although the embodiment to which the invention made by the present inventor is applied has been described above, the present invention is not limited by the description and drawings which form a part of the disclosure of the present invention according to the present embodiment. In other words, other embodiments, examples, operation techniques, etc. made by those skilled in the art based on the present embodiment are all included in the scope of the present invention. [Explanation of symbols]

[0080] 10 Accelerator control device 11a Data buffer (storage section) 11b Metadata buffer (storage section) 12 Memory Management Functions 13 Metadata Control Functions 13a Polling function (judgment section) 13b Write function 14 API 20 Accelerators 21 Metadata Access Mechanisms 21a Polling function (acquisition part) 21b Reading function 21c Write function (storage section) 22 Function Control Blocks 22a Metadata Analysis Function 22b Data transfer control function 22c Completion notification function 23 Data transfer function 23a Data reading function 23b Data writing function (storage section) 24 Calculation function (calculation section)

Claims

1. An accelerator control device and an accelerator, The accelerator control device includes: a storage unit that stores in advance control data including information specifying the location of data to be processed and the content of the processing by the accelerator; a determination unit that, when the control data that has been subjected to the arithmetic processing by the accelerator is stored in the storage unit, determines the completion of the arithmetic processing by the accelerator asynchronously with the completion of the arithmetic processing, The accelerator comprises: an acquisition unit that monitors the presence or absence of the control data and acquires the control data from the storage unit; a calculation unit that performs a calculation process on the target data of the calculation process in accordance with information that specifies the location of the target data of the calculation process and the operation of an accelerator, the information being included in the acquired control data; a storage unit that stores the control data in the memory unit when the arithmetic processing is completed.

2. 2. The accelerator control system according to claim 1, further comprising a monitoring unit that monitors whether or not the control data is present in the storage unit.

3. 2. The accelerator control system according to claim 1, wherein the determination unit monitors whether or not the control data that has been subjected to the arithmetic processing is present in the storage unit.

4. 2. The accelerator control system according to claim 1, wherein the storage unit further stores a result of the arithmetic processing performed on the data to be arithmetically processed in the memory unit.

5. 2. The accelerator control system according to claim 1, wherein the storage unit stores different control data for each of a plurality of accelerators.

6. An accelerator control method executed by an accelerator control system having an accelerator control device and an accelerator, comprising: the accelerator control system includes a storage unit that stores in advance control data including information specifying the location of data to be processed and the content of the processing by the accelerator; an acquisition step of monitoring the presence or absence of the control data and acquiring the control data from the storage unit; a computing step of performing a computation process on the data to be computed in accordance with information specifying the location of the data to be computed and the operation of an accelerator, the information being included in the acquired control data; a storing step of storing the control data in the storage unit when the arithmetic processing is completed; a determination step of determining completion of the arithmetic processing asynchronously with the completion of the arithmetic processing when the control data that has been arithmetically processed is stored in the storage unit; 23. A method for controlling an accelerator comprising:

7. An accelerator control program for causing a computer to function as the accelerator control system according to any one of claims 1 to 5.

Images