Data processing apparatus, method, device and chip

Abstract

This application relates to the field of data processing, and in particular to a data processing apparatus, method, device, and chip. In this apparatus, a controller module receives a task selection signal from a task request terminal and determines the target task to be executed by the task execution unit based on the task selection signal. The task execution unit selects the corresponding hardware processing module based on the target task to construct the corresponding target task path. The task execution unit receives data to be processed and inputs the data into the target task path to start the target task and obtain the task execution result. The result reading module outputs the task execution result to the task request terminal. This apparatus adapts to the computational needs of various polynomial multiplication tasks through task selection signals and dynamically combined hardware processing modules, improving the scalability of the hardware structure and increasing resource utilization.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to a data processing apparatus, method, device, and chip. Background Technology

[0002] With the continuous development of artificial intelligence and big data algorithms, using encryption algorithms to encrypt data is an important way to protect data security. Mainstream privacy computing technologies such as fully homomorphic encryption (FHE) and zero-knowledge proof (ZKP) all require a large number of polynomial multiplication calculations.

[0003] In related technologies, directly multiplying two polynomials of length N has a time complexity of O(N²). Number Theoretic Transform (NTT) and Inverse Number Theoretic Transform (INTT) can optimize polynomial multiplication, reducing its time complexity to O(N²). The computation speed of NTT / INTT is a crucial factor affecting the efficiency of privacy-preserving computation. However, these technologies suffer from high storage resource consumption and rigid task flows, failing to meet the technical requirements for multiplying long polynomials. Summary of the Invention

[0004] This application addresses the technical problems existing in the prior art by providing a data processing device, method, apparatus, and chip for dynamically configuring hardware processing modules to adapt to the computational needs of various polynomial multiplication tasks, achieving hardware acceleration of polynomial computation tasks, greatly improving the scalability of the hardware structure, and enhancing resource utilization.

[0005] In a first aspect, embodiments of this application provide a data processing method, which is applied to a data processing apparatus, the apparatus comprising: a controller module, a task execution unit, and a result reading module; the data processing method includes:

[0006] The data processing device receives a task selection signal from the task request terminal and determines the target task to be executed by the task execution unit based on the task selection signal; the target task is one or more of the polynomial computation tasks; the polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks;

[0007] The data processing device selects the corresponding hardware processing module based on the target task to construct the corresponding target task path; the hardware processing modules in the task execution unit include: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module; the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs;

[0008] The data processing device receives the data to be processed and inputs the data to be processed into the target task path to start the target task and obtain the task execution result;

[0009] The data processing device outputs the task execution result to the task requesting end.

[0010] Secondly, embodiments of this application provide a data processing apparatus, which includes: a controller module, a task execution unit, and a result reading module;

[0011] The controller module is used to receive a task selection signal from the task request terminal and determine the target task to be executed by the task execution unit based on the task selection signal; the target task is one or more polynomial computation tasks; polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks;

[0012] The task execution unit is used to select the corresponding hardware processing module based on the target task to construct the corresponding target task path; the hardware processing module in the task execution unit includes: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module; the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs;

[0013] The task execution unit is also used to receive data to be processed and input the data to be processed into the target task path to start the target task and obtain the task execution result;

[0014] The result reading module is used to output the task execution result to the task requesting end.

[0015] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising:

[0016] A memory for storing computer programs; a processor for reading and executing the computer programs to implement the data processing apparatus of the second aspect.

[0017] Fourthly, embodiments of this application provide a chip in which a computer program is loaded, the computer program being used to implement the data processing apparatus as described in the second aspect.

[0018] Fifthly, a computer-readable storage medium is provided, comprising instructions that, when executed on a computer, cause the computer to perform the data processing apparatus of the second aspect.

[0019] In this application's technical solution, the data processing device includes a controller module, a task execution unit, and a result reading module. The hardware processing modules within the task execution unit include: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module. In this device, the controller module receives a task selection signal from the task request end and determines the target task to be executed by the task execution unit based on the task selection signal. The task execution unit selects the corresponding hardware processing module based on the target task to construct the corresponding target task path. The task execution unit receives the data to be processed and inputs the data into the target task path to start the target task and obtain the task execution result. The result reading module outputs the task execution result to the task request end. This application's technical solution enables the data processing device to determine the target task based on the task selection signal using the controller module. It supports the individual or combined execution of tasks such as number theory transformations, multiplication, and inverse number theory transformations in polynomial calculation tasks, meeting diverse needs. Furthermore, it is easily adaptable to new computational requirements by expanding the task selection signal and hardware processing modules, exhibiting strong scalability. In terms of task execution mechanism, the task execution unit can dynamically construct the optimal task path based on the target task and configure hardware processing modules as needed, reducing resource waste and inefficiency issues under a fixed architecture. Simultaneously, rapid path construction reduces computational waiting time and improves overall computational efficiency. Regarding resource optimization, the device allocates hardware resources on demand, activating only necessary modules when executing different tasks, saving resources and energy. Furthermore, flexible path construction enables hardware module reuse, improving hardware utilization and reducing hardware deployment costs. In summary, the technical solution of this application adapts to the computational needs of various polynomial multiplication tasks through task selection signals and dynamic construction of hardware processing modules, improving the scalability of the hardware structure and enhancing resource utilization. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a data processing device according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the architecture of a data processing device according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of a data processing device according to an embodiment of this application;

[0023] Figure 4 This is a flowchart illustrating a data processing method according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a medium according to an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] With the continuous development of artificial intelligence and big data algorithms, more and more people are realizing that data has become a valuable resource with rich potential. While continuously exploring and utilizing the value within data, protecting data security and privacy has become a crucial issue. Encrypting data using encryption algorithms is an important way to protect data security; mainstream privacy computing technologies such as FHE and ZKP require a large number of polynomial multiplication calculations.

[0028] Currently, in polynomial multiplication, directly multiplying two polynomials of length N has a time complexity of O(N²). NTT and INTT can optimize polynomial multiplication, reducing its time complexity to O(Nlog₂N).

[0029] In related technologies, number-theoretical transformation (NTT), multiplication, and inverse number-theoretical transformation (INTT) are performed as a whole. When multiplying two polynomials, NTT is first applied to P1 and P2 to obtain P1' and P2', then they are multiplied to obtain M', and finally INTT is applied to obtain the result M. The time complexity of this process is optimized to O(N log²N). However, the above solution requires a large amount of storage space. Taking the above computational requirements as an example, the amount of data that needs to be stored includes two polynomial coefficients of length N and two twiddle factors of length N, totaling 4N data points. For example, when the data width is 255 bits and the polynomial length is 2×18, the amount of data that needs to be stored is enormous, exceeding the on-board storage resources of most FPGAs on the market.

[0030] Secondly, the above scheme lacks flexibility in the computation stage, requiring a complete data processing flow including number-theoretic transformations, multiplication, and inverse number-theoretic transformations. To support larger polynomial multiplications, such as 2×30, limitations in existing chip architecture and hardware circuit design prevent the direct implementation of ordinary number-theoretic transformations and inverse number-theoretic transformations on existing chips or other hardware circuits. Furthermore, existing chips struggle to support matrix number-theoretic transformations and their inverse transformations.

[0031] It is evident that the relevant technologies suffer from several technical problems, including high storage resource consumption, rigid task processes, and inability to meet the technical requirements of long-length polynomial multiplication.

[0032] To address at least one technical problem in the related technologies, embodiments of this application provide a data processing apparatus, method, device, and chip.

[0033] The technical solution provided in this application includes a data processing device comprising: a controller module, a task execution unit, and a result reading module. The controller module is configured to receive a task selection signal from a task requesting end, and determine the target task to be executed by the task execution unit based on the task selection signal; the target task is one or more polynomial computation tasks; polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks. The task execution unit is configured to select a corresponding hardware processing module based on the target task to construct a corresponding target task path; the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs. The task execution unit is further configured to receive data to be processed and input the data to be processed into the target task path to start the target task and obtain a task execution result. The result reading module is configured to output the task execution result to the task requesting end.

[0034] The technical solution of this application, firstly, allows the controller module to determine the target task based on the task selection signal. These target tasks can be one or more polynomial computation tasks. This means that the device can handle the individual execution of number-theoretical transformation tasks, multiplication tasks, and inverse number-theoretical transformation tasks, as well as their combined execution, greatly satisfying the diverse needs of different users or application scenarios. For example, in some complex cryptographic calculations, it may be necessary to perform number-theoretical transformations first, followed by multiplication operations, and finally inverse number-theoretical transformations. This device can easily implement such task combinations. With the development of technology and the emergence of new computational requirements, the device can support more types of polynomial computation tasks or other related tasks simply by expanding the task selection signal and the corresponding hardware processing module. This makes the device highly scalable and adaptable to future developments and changes.

[0035] Furthermore, the task execution unit selects the corresponding hardware processing modules to construct the target task path based on the target task. The number, type, and connection method of the hardware processing modules are related to the task type to which the target task belongs. This dynamic construction method can be optimally configured according to the specific task. For example, for a simple multiplication task, only a few multiplication-related hardware processing modules may need to be connected; while for a complex number theory transformation combination task, multiple number theory transformation and multiplication modules can be flexibly combined to form an efficient task execution path, avoiding the resource waste and inefficiency problems of a fixed architecture. Because it can quickly construct a suitable task path according to the target task, the data to be processed can be directly input into the path to execute the task, reducing unnecessary intermediate steps and waiting time. Compared with the traditional fixed-process calculation method, this device can complete the task more efficiently and improve the overall computing efficiency.

[0036] Next, the data flow of the entire device is clear and unambiguous. It receives task selection signals and data to be processed from the task requester, the controller module determines the task, the task execution unit executes the task, and finally, the result reading module outputs the task execution result back to the task requester. This clear data flow makes the data processing process easy to monitor and manage, and also facilitates troubleshooting and optimization. For users at the task requester, they only need to send the task selection signal and data to be processed to obtain the desired task execution result, without needing to concern themselves with the complex task execution process within the device. This lowers the user's barrier to entry and improves the user experience.

[0037] Finally, by dynamically selecting hardware processing modules based on the target task, the device can achieve on-demand allocation of hardware resources. When executing different tasks, only the necessary hardware processing modules are activated, avoiding resource waste and increased energy consumption caused by running all hardware modules simultaneously. For example, when performing a multiplication task, it is not necessary to activate the hardware modules related to number theory transformations, thus saving hardware resources and power consumption. Because task paths can be flexibly constructed, hardware processing modules can be reused across different tasks, improving the overall utilization rate of hardware resources. This reduces the hardware cost of the device to some extent and also improves its cost-effectiveness.

[0038] In summary, this technical solution demonstrates strong scalability and flexibility. The data processing device, through its controller module, determines the target task based on the task selection signal, supporting the individual or combined execution of tasks such as number-theoretical transformations, multiplication, and inverse number-theoretical transformations in polynomial computation, thus meeting diverse needs. Furthermore, it is easily adaptable to new computational requirements by expanding the task selection signal and hardware processing modules, exhibiting high scalability. Regarding the task execution mechanism, the task execution unit dynamically constructs the optimal task path based on the target task and configures hardware processing modules as needed, reducing resource waste and inefficiency issues under a fixed architecture. Simultaneously, rapid path construction reduces computational waiting time, improving overall computational efficiency. In terms of data interactivity, the data flow is clear, from receiving the task selection signal and data to be processed, to determining and executing the task, and finally outputting results, facilitating monitoring, management, and troubleshooting. Users only need to send signals and data to obtain results, lowering the barrier to entry and enhancing user experience. Regarding resource optimization, the device allocates hardware resources as needed, activating only necessary modules when executing different tasks, saving resources and energy. Simultaneously, flexible path construction enables hardware module reuse, improving hardware utilization and reducing hardware deployment costs. In summary, this technical solution can adapt to the computational needs of various polynomial multiplication tasks by using task selection signals and dynamically combined hardware processing modules, and can directly execute polynomial calculation tasks on the hardware, greatly improving the scalability of the hardware structure and increasing resource utilization.

[0039] The data processing scheme provided in this application embodiment can also be executed by a chip, or by a chip-equipped device working in conjunction with other electronic components, or by a service program installed in an electronic device to implement the data processing scheme.

[0040] Figure 1 This is a schematic flowchart of a data processing apparatus provided in an embodiment of this application, as shown below. Figure 1 As shown, the device includes the following units:

[0041] The controller module is used to receive task selection signals from the task request end and determine the target task to be executed by the task execution unit based on the task selection signals.

[0042] The task execution unit is used to select the corresponding hardware processing module based on the target task in order to construct the corresponding target task path;

[0043] The task execution unit is also used to receive data to be processed and input the data to be processed into the target task path to start the target task and obtain the task execution result;

[0044] The result reading module is used to output the task execution results to the task requesting end.

[0045] In this embodiment, the target task is one or more polynomial computation tasks. Polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks. See the examples below for details, which will not be elaborated upon here.

[0046] In this embodiment, the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs. It is understood that when executing a target task, the data processing device will construct a target task path that adapts to it. The construction of this path is highly targeted; the number, type, and connection method of the hardware processing modules in the path all depend on the type of the target task. When the target task is a single number theory transformation task, the task path will include necessary modules such as an initialization module, a storage module, and a butterfly computation module, building the link according to steps such as initialization, data storage, and butterfly computation. If it is a multiplication task, the initialization module, storage module, and multiplication module will be activated, constructing the path around data input and multiplication operations. When performing complex number theory transformation and multiplication combination tasks, the device will connect the butterfly computation module, multiplication module, etc., in an orderly manner based on the task flow to meet the task requirements. Therefore, the hardware processing modules can be dynamically configured according to the target task, which not only avoids resource waste and improves hardware utilization efficiency but also significantly enhances the flexibility and adaptability of the device, allowing the data processing device to operate efficiently in various scenarios and meet the computing needs of different users.

[0047] In this embodiment, the controller module, as a key component of the data processing device, plays a crucial role in the overall system's control and coordination. The primary function of the controller module is to receive task selection signals from the task requester. This signal is a critical input indicating the target task the system needs to execute. The target task can be one or more polynomial computation tasks, including number theory transformation tasks, multiplication tasks, inverse number theory transformation tasks, etc. For example, when the task selection signal is a specific code (such as 2'b00), the controller can identify and determine that a number theory transformation task should be executed; when it is 2'b01, it determines that a multiplication task should be executed, etc. By accurately interpreting the task selection signal, the controller provides a clear direction for subsequent task execution.

[0048] Furthermore, based on the defined target task, the controller module is responsible for coordinating and scheduling the work of each hardware processing module in the task execution unit. It determines which hardware processing modules need to participate in task execution, as well as the working order and coordination method between these modules, according to the requirements of the target task. For example, when executing a number theory transformation task, the controller will arrange for the initialization module to receive the data to be processed and temporarily store it in the storage module, and then sequentially trigger the butterfly calculation module, the inversion module, etc., to operate according to the predetermined process, ensuring that the entire task can proceed in an orderly manner.

[0049] Furthermore, the controller module monitors and manages each state throughout the entire data processing process in real time. It focuses on the operational status of the hardware processing modules, such as whether the initialization module has completed data storage and whether the butterfly calculation module has finished its calculations. By receiving status signals from each module (such as ntt_btf_finish_in and reverse_finish_in), the controller can accurately understand the progress of task execution and make corresponding decisions based on the status information, such as whether to continue the task process or handle errors.

[0050] It's worth noting that the controller module internally employs a Finite State Machine (FSM) to implement state transitions and control logic. The FSM contains a series of states (such as kIdle, kInitMem, kWaitNTTTF, kWaitINTTTF, kReverse, kPolyNTT, kPolyINTT, kPolyMult, kReadResult, and kFinish), along with the transition conditions and actions between states. Based on the task selection signal and the state signals fed back from various modules, the FSM transitions between different states, thereby achieving precise control over task execution. For example, in the initial state kIdle, if the external start signal poly_start is 1, the state changes from kIdle to kInitMem, entering the memory initialization state.

[0051] In addition to the finite state machine, the controller module also includes signal processing and logic control units. These units are responsible for processing and performing logical operations on task selection signals, feedback signals from various modules, and other relevant signals. For example, they decode task selection signals to determine the specific target task; and analyze module feedback signals to determine whether task execution is normal. Through this signal processing and logic control, the controller can make accurate decisions and ensure the stable operation of the system.

[0052] The controller module receives key information such as task selection signals and start signals (e.g., poly_start) from the task requester. The task requester sends these signals to indicate to the controller the tasks to be executed and when the tasks should start. The controller then begins the corresponding operation based on the received signals.

[0053] The controller module connects to various hardware processing modules (initialization module, storage module, reversal module, butterfly calculation module, multiplication module, modular multiplication module, etc.) within the task execution unit. It sends control signals to these modules, instructing them to perform corresponding operations, and receives status signals and data processing results from each module. For example, the controller sends an instruction to the initialization module, requesting it to receive and store the data to be processed; simultaneously, it receives the computation completion signal `ntt_btf_finish_in` from the butterfly calculation module to determine whether to continue subsequent operations.

[0054] Once the task is completed, the controller module will instruct the result reading module to output the task execution result to the task requesting end. It sends an output command to the result reading module to ensure that the result is returned to the user accurately and in a timely manner.

[0055] Therefore, the controller module can flexibly determine and execute target tasks based on different task selection signals, enabling the data processing device to adapt to diverse application scenarios and user needs. Whether executing a single polynomial calculation task or combining multiple tasks, the controller can effectively schedule and manage them, greatly improving the system's flexibility. By precisely coordinating and scheduling the hardware processing modules in the task execution units, the controller module avoids resource waste and ineffective operations, reducing waiting time and intermediate steps during task execution. For example, dynamically selecting and configuring hardware processing modules according to task requirements allows the system to execute tasks in the optimal way, thereby improving overall task execution efficiency. The controller module's real-time monitoring and management of the system status enables timely detection and handling of anomalies during task execution. When a module malfunctions or an error occurs during task execution, the controller can take corresponding measures, such as pausing the task, performing error recovery, or restarting, ensuring the system's stability and reliability.

[0056] In summary, the controller module plays a crucial role in the data processing device, providing strong support for the device's performance and functionality through precise task control, efficient module coordination, and comprehensive status management.

[0057] As an optional embodiment, the hardware processing module in the task execution unit includes: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module.

[0058] The initialization module is connected to the storage module; the initialization module is used to receive the data to be processed and temporarily store the data to be processed in the storage module.

[0059] The storage module is connected to the inversion module, the butterfly calculation module, and the multiplication module, respectively. The butterfly calculation module and the multiplication module are connected to the modular multiplication module, respectively. The data processing results of the inversion module, the butterfly calculation module, the multiplication module, and the modular multiplication module are output to the read result module through the storage module.

[0060] In some alternative embodiments, the hardware processing module of the task execution unit adopts a modular design, with each module having a clear division of labor and cooperating with each other, thereby achieving task decoupling and flexible dynamic path construction.

[0061] The initialization module is responsible for receiving data to be processed from external task requesters. This data can be polynomial coefficients, twiddle factors, or other data related to polynomial calculations. It performs necessary format conversions or preprocessing on the received data, such as padding with zeros to meet specific data format requirements or performing sign extension. The preprocessed data is then accurately written to the storage module, preparing it for subsequent calculations. On the input side, it connects to the task requester to receive the data to be processed. On the output side, it directly connects to the storage module to temporarily store the processed data.

[0062] The storage module plays a crucial role as a data hub, caching intermediate results and input data at each stage throughout the data processing, ensuring smooth data flow between different modules. It features time-division multiplexing, storing polynomial coefficients and corresponding twiddle factors during the number theory transformation (NTT) and inverse number theory transformation (INTT) stages; and storing the data of the two polynomials involved in the multiplication operation during the multiplication task stage. Through a reasonable address mapping mechanism, it enables fast read and write operations, improving data access efficiency and thus increasing the overall operating speed of the device. During input, it receives data written by the initialization module, as well as data processed and fed back from the inversion module, butterfly calculation module, multiplication module, and modular multiplication module. On the output side, it provides data input sources for the inversion module, butterfly calculation module, and multiplication module, and ultimately transmits the task execution results processed by each module to the result reading module.

[0063] The inversion module is primarily used during the bit-reversal stage, specifically during the preprocessing or post-processing of NTT or INTT, to perform bit-reversal operations on the data. Specifically, it reverses the binary bits of data index i to obtain r, and then swaps the values ​​of P[i] and P[r] to satisfy the specific data format requirements of number theory transformations. The input is the data to be bit-reversed, read from the storage module. The output is the reversed data written back to the storage module for further processing by other modules.

[0064] The butterfly computation module is responsible for executing the core butterfly operations of NTT and INTT, and is a key module for implementing polynomial transformations. It supports parallel computing, fully utilizing hardware resources to significantly improve computation speed and effectively enhance the device's efficiency in handling polynomial computation tasks. Input: The polynomial coefficients and corresponding twiddle factors are read from the storage module as operands for the butterfly computation. Output: The results of the butterfly computation are written to the storage module, and simultaneously sent to the modular multiplication module for modular arithmetic processing.

[0065] The multiplication module performs point-by-point multiplication on the two input polynomials to obtain a new polynomial product. It supports both fixed-point and floating-point multiplication, flexibly selecting the appropriate operation method based on different precision requirements to adapt to diverse computing scenarios. Input is read from the storage module, containing the coefficients of the two polynomials involved in the multiplication. Output writes the calculated product result back to the storage module and sends the result to the modular multiplication module for modular arithmetic.

[0066] The modular multiplication module performs modular arithmetic on the outputs of the butterfly calculation module or the multiplication module, ensuring that the calculation results are within a finite field and meet the requirements of polynomial computation in a specific mathematical domain. For example, the input receives the outputs from the butterfly calculation module and the multiplication module. The output writes the modularly processed results back to the storage module for subsequent output or further processing.

[0067] Taking the NTT task execution as an example, the initialization module receives the polynomial P and the NTT twitch factor W, preprocesses them, and writes them to the storage module. The butterfly calculation module retrieves P and W from the storage module, performs the core butterfly calculation operation, and stores the calculation result back to the storage module. The modular multiplication module performs modular operations on the butterfly calculation result to ensure that the result is within a finite field. The inversion module reverses the bit order of the data in the storage module. The storage module outputs the final processed result through the result reading module.

[0068] Taking a multiplication task as an example, the initialization module receives two polynomials, P1 and P2, preprocesses them, and writes them to the storage module. The multiplication module reads P1 and P2 from the storage module, performs pointwise multiplication, and writes the product back to the storage module. The modular multiplication module performs modular arithmetic on the result of the multiplication. The storage module outputs the final result through the result reading module.

[0069] This modular decoupling allows for the independent design of each hardware processing module, resulting in excellent independence and encapsulation. This facilitates maintenance and upgrades; for example, the multiplication module can be easily upgraded to a higher-precision version without affecting the normal operation of other modules. Storage resource reuse utilizes a time-sharing caching mechanism in the storage module, effectively reducing hardware resource consumption and improving storage utilization, achieving more efficient data processing under limited hardware resources. Parallel processing capabilities: The butterfly computing module and multiplication module support parallel operation, fully leveraging the hardware's parallel computing capabilities, significantly improving the overall data processing throughput and accelerating task execution. In particular, dynamic path adaptation allows for flexible combination of modules based on different task types, such as NTT, INTT, or multiplication tasks, without requiring large-scale modifications to the hardware circuitry, enhancing the device's adaptability and flexibility. On hardware platforms such as FPGAs, polynomial multiplication acceleration can be efficiently implemented while maintaining flexibility and resource utilization, providing strong support for applications in related fields.

[0070] In this embodiment, the result reading module, as a key component of the data processing device responsible for outputting the final data, plays a crucial role in the data flow and task completion process of the entire system. The core function of the result reading module is to read the final data processed by the task execution unit from the storage module. This data is the result of a series of processes, including initialization, reversal, butterfly calculation, multiplication, and modular multiplication, resulting in task execution results such as polynomials after number theory transformations, product results after multiplication operations, or the final polynomial after inverse number theory transformations. This module can accurately locate the position of the result data stored in the storage module and read the data according to predetermined rules and formats. It then outputs the task execution results read from the storage module to the task requesting end. It is responsible for converting the data in its internal processing format into a format suitable for the task requesting end to receive and process, ensuring that the data can be correctly received and used by the task requesting end. For example, it converts binary data into a specific encoding format or encapsulates the data according to the protocol required by the task requesting end.

[0071] Optionally, before outputting the data, the result reading module may perform certain validation operations on the task execution results. By checking the integrity and correctness of the data, it ensures that the data output to the task requesting end is reliable. For example, it may calculate the checksum of the data and compare it with a pre-set value, or check whether the data conforms to specific format specifications. If a problem is found in the data, the result reading module can take appropriate measures, such as rereading the data or sending error information back to the controller module.

[0072] The result reading module first waits for output instructions from the controller module. When the task execution unit completes task processing and the controller module determines that results can be output, it sends an output instruction to the result reading module. This instruction contains key information about the result data, such as the data storage location, data length, and data format. Based on this information, the result reading module prepares to perform the data reading operation. According to the information provided by the controller module, the result reading module accesses the storage module and reads the task execution result data from the specified location. During the reading process, it operates according to the storage module's access rules and interface protocols to ensure that the data is read accurately. If the data volume is large, the result reading module may use a batch reading method to avoid reading too much data at once and causing system resource strain. After reading the data, the result reading module performs necessary processing, such as format conversion and data parsing, to make it conform to the requirements of the task requesting end. Simultaneously, it performs data verification to check the correctness and integrity of the data. If the verification passes, it continues to the next output operation; if the verification fails, it takes appropriate measures depending on the specific situation, such as rereading the data or reporting the error to the controller module. The processed and verified data is then output to the task requesting end. The result reading module sends out data according to the communication protocol and interface specifications agreed upon with the task requester. During the output process, it monitors the data transmission status to ensure that the data is successfully delivered to the task requester. If problems occur during transmission, such as data loss or communication interruption, the result reading module will attempt to resend the data or report the exception to the controller module.

[0073] From a connectivity perspective, the result reading module is directly connected to the storage module, reading task execution result data from the storage module. The storage module stores intermediate and final results at each stage during task execution, and the result reading module accesses and reads data through its interface with the storage module. The result reading module receives control commands from the controller module. Based on the task execution progress and status, the controller module determines when to allow the result reading module to read and output results, providing relevant parameters and information to the result reading module. Simultaneously, the result reading module also provides feedback to the controller module on the status of the data reading and output process, such as whether data was successfully read or output. Finally, the result reading module outputs the task execution results to the task requesting end. It transmits data with the task requesting end through a specific communication interface and protocol, ensuring that the data is accurately received and processed by the task requesting end.

[0074] The result reading module is a crucial link in the data interaction between the data processing device and the task requesting end. It ensures that the data processed internally by the device is successfully returned to the task requesting end, enabling the requesting end to obtain the required calculation results and achieving effective data output and interaction. By verifying and processing the task execution results, the result reading module improves the reliability and accuracy of the output data. This is particularly important for applications that rely on data processing results, ensuring that users receive correct calculation results and avoiding problems and losses caused by data errors. As the final link in the data processing device, the result reading module completes the functionality of the entire system. Working closely with other modules, it completes the entire process from data input, processing to output, enabling the data processing device to operate efficiently and reliably, meeting the needs of different users and application scenarios.

[0075] For example, with Figure 2 Taking the large-bit-width long-sequence polynomial multiplication acceleration circuit architecture shown as an example, multiple modules work together to accelerate polynomial multiplication. The controller module receives task selection signals and other parameter signals, contains a finite state machine, determines the target task based on the signals, and coordinates the work of other modules, serving as the control core of the entire architecture. The initialization module receives input data, performs preprocessing, and temporarily stores the data in the storage module to prepare for subsequent calculations. Two storage modules are used to store input data and intermediate calculation results, acting as data caches to facilitate each module's retrieval of required data. The inversion module performs bit-reversal processing on data in tasks such as number theory transformations to meet specific calculation format requirements. The butterfly calculation module performs butterfly operations in number theory transformations and is a key operation module for implementing polynomial transformations. The multiplication module performs multiplication operations on the input polynomial data to calculate the polynomial product. The modular multiplication module performs modular operations on the results of butterfly calculations or multiplication operations, ensuring the result is within a finite field. The result reading module reads the final calculation result from the storage module and outputs the result.

[0076] exist Figure 2 In this process, input data enters the initialization module, processes it, and then stores it in the storage module. Each computation module (reversal, butterfly calculation, multiplication, modular multiplication) reads data from the storage module, processes it, and then stores the results back into the storage module. Data exchange between modules is achieved through the storage module. The result reading module retrieves the final result from the storage module and outputs it, completing the entire data transmission and processing flow. This architecture and data transmission method accelerate the computation of large-bit-width long-sequence polynomial multiplication.

[0077] As an optional embodiment, the storage module includes a first storage module and a second storage module; the first storage module and the second storage module each occupy one unit of storage space. When the task execution unit selects a corresponding hardware processing module based on the target task to construct a corresponding target task path, it specifically performs the following: the task execution unit selects a corresponding target processing unit from the first storage module, the second storage module, the reversal module, the butterfly calculation module, the multiplication module, and the modular multiplication module based on the target task; combines the selected target processing units into a corresponding data processing link, and uses the combined data processing link as the target task path.

[0078] For example, in a number theory transformation task, the polynomial data to be processed is read from either the first or second storage module. The inversion module performs bit-reversal preprocessing on the data, followed by the core butterfly operation executed by the butterfly computation module. The result is then processed using the modular multiplication module, and finally stored back in the storage module. This process selects the storage module, inversion module, butterfly computation module, and modular multiplication module, combining them to form the data processing chain for the number theory transformation task.

[0079] For example, in a multiplication task, the two polynomials involved in the multiplication operation are read from two storage modules, respectively. The data is then input into the multiplication module for point-by-point multiplication. The multiplication result is then processed modularly by the modular multiplication module, and the final result is stored back into the storage module. Here, the storage module, multiplication module, and modular multiplication module are selected to construct the target task path for the multiplication task, efficiently completing the multiplication calculation.

[0080] Therefore, by setting up two storage modules and each occupying an independent unit of storage space, the task execution unit can read data from different storage modules as needed and combine them with other hardware processing modules to construct task paths, achieving flexible resource allocation. For example, in different polynomial calculation tasks, different types of data can be stored in two separate modules to avoid resource conflicts and improve resource utilization. Selecting target processing units from multiple modules to construct data processing links allows for the customization of exclusive execution paths for different target tasks. For simple multiplication tasks, only the multiplication module and storage module can be selected to construct the link; for complex number theory transformation combination tasks, butterfly calculation modules, inversion modules, etc., can be included in the link to accurately match task requirements and improve execution efficiency. This modular selection and combination method makes it easy to add or modify modules when new task requirements emerge. If new polynomial calculation algorithms or task types emerge in the future, they can be adapted to new requirements simply by expanding on the existing modules, reducing hardware deployment and upgrade costs.

[0081] As an optional embodiment, the controller module is further configured to control the data processing status of the data to be processed in the target task path; the task execution unit, when inputting the data to be processed into the target task path to execute the target task, is specifically configured to: under the control and scheduling of the controller module, the task execution unit loads the data to be processed into the target task path, and switches the hardware processing unit where the data to be processed is located in the target task path to execute the corresponding data processing flow in the target task.

[0082] For example, when the target task is a number theory transformation, the controller module issues instructions to first enter the initialization module. After data preprocessing, the data is temporarily stored in either the first or second storage module. Next, the controller schedules the data to enter the inversion module for bit reversal. Subsequently, the data is switched to the butterfly computation module for butterfly operations, and the result is then processed in the modular multiplication module. Throughout this process, the controller module continuously monitors and controls the data processing status, ensuring that the data is switched accurately between hardware processing units in sequence, thus successfully completing the number theory transformation task.

[0083] For example, in a combined multiplication and number theory transformation task, the controller first guides the data to be processed into the initialization module, and then stores it in the corresponding storage module. Following the multiplication task flow, the data is first switched to the multiplication module for multiplication operations. After processing by the modular multiplication module, the data is then controlled to sequentially enter the inversion module, butterfly calculation module, and modular multiplication module, etc., according to the requirements of the number theory transformation task, thus achieving the coherent execution of the combined task.

[0084] In this way, the controller module's control over the data processing status allows for precise control over the timing and order of data processing in each hardware processing unit, preventing data processing chaos and ensuring that tasks are executed according to the expected process. By flexibly switching hardware processing units within the target task path, the functionality of each module can be fully utilized, reducing data waiting time, accelerating task execution, and improving overall computational efficiency. Regardless of whether the task is simple or complex, this mechanism can adapt to different task requirements through controller scheduling and data processing unit switching, enhancing the device's ability to handle various polynomial computation tasks and improving the system's versatility and flexibility.

[0085] As an optional embodiment, the controller module includes a first state machine; the first state machine is configured to receive a task start signal before determining the target task to be executed by the task execution unit based on the task selection signal; based on the task start signal, switch the initialization module to an initialization memory state to trigger the initialization module to perform an initialization operation on the data to be processed; after receiving an initialization end signal, remain in the initialization memory state and trigger the step of determining the target task to be executed by the task execution unit based on the task selection signal. The initialization module is further configured to perform initialization parsing on the data to be processed, and after initialization is completed, feed back the initialization end signal to the first state machine.

[0086] In this data processing device, the first state machine is initially in the kIdle (idle) state. At this time, it can receive the start signal `poly_start` from the outside. If `poly_start` is 0, it indicates that the task has not started, and the first state machine remains in the kIdle state, waiting for the start command. When `poly_start` becomes 1, the first state machine receives the start signal, and its state transitions from kIdle to kInitMem (initialization memory state). After entering this state, the first state machine controls the initialization module to start working, performing initialization operations on the input data to be processed, such as data format conversion and storage location allocation. During the initialization process, the initialization module continuously processes data. As long as it has not completed initialization, it will report `poly_finish_in=0` to the first state machine, and the first state machine will remain in the kInitMem state. Once initialization is complete, the initialization module will report `poly_finish_in=1` to the first state machine. At this time, although the first state machine is still in the kInitMem state, it will determine the target task to be executed next by the task execution unit based on the received task selection signal `control_signal`. For example, if control_signal represents a number theory transformation task, the first state machine will instruct subsequent modules to perform the corresponding number theory transformation operation.

[0087] In this way, the first state machine determines whether to start the task based on the `poly_start` signal, avoiding accidental task triggering. The system only enters the initialization process after receiving a clear start signal, ensuring the accuracy and reliability of task startup. During initialization, the first state machine determines whether initialization is complete based on the `poly_finish_in` signal. Only after initialization is truly complete will the target task be determined based on the `control_signal`, avoiding subsequent calculation errors due to incomplete initialization and improving system stability. Determining the target task based on the `control_signal` allows the system to flexibly configure tasks according to different needs. This enhances the system's adaptability, enabling it to handle various types of polynomial computation tasks and meet diverse application scenarios.

[0088] As an optional embodiment, when the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is specifically configured to: if the task selection signal is a first task signal, then the controller module determines that the target task is a number theory transformation task (NTT).

[0089] The controller module includes a second state machine; the second state machine is used to sequentially switch the task execution unit from the initialization memory state to the twitch factor loading state, the butterfly calculation state, the reversal state, and the result output state; in the number theory transformation task, the data to be processed includes polynomial coefficients and NTT twitch factors.

[0090] In NTT, the target task path consists of the initialization module, the butterfly calculation module, and the reversal module. In the twitch factor loading state, the initialization module retrieves the NTT twitch factor from the second storage module and performs initialization parsing on the NTT twitch factor. If parsing is complete, the NTT twitch factor parsing results are returned to the second storage module, and a twitch factor parsing completion signal is sent to the second state machine, causing the second state machine to switch to the butterfly calculation state. In the butterfly calculation state, the butterfly calculation module performs butterfly calculations on the polynomial coefficients in the first storage module and the NTT twitch factor parsing results in the second storage module. The intermediate butterfly calculation results are stored in the first storage module, and a butterfly calculation completion signal is sent to the second state machine, causing the second state machine to switch to the reversal state. In the reversal state, the reversal module performs bit-reversal permutations on the intermediate butterfly calculation results in the first storage module to obtain the NTT calculation result. A reversal completion signal is sent to the second state machine, causing the second state machine to switch to the result output state, and the NTT calculation result is output through the result reading module in the result output state.

[0091] In the above embodiments, the controller module determines the target task of the task execution unit using a task selection signal. When the task selection signal is the first task signal, the number theory transformation task (NTT) is determined to be executed. This process is precisely controlled by the second state machine in the controller module, which guides the task execution unit in an orderly manner from the initialization memory state to the rotation factor loading state, the butterfly calculation state, the reversal state, and the result output state.

[0092] For example, when control_signal=2'b00, the circuit needs to perform a number-theoretical transformation task. The state machine will enter the kWaitNTTTF state from the KInitMem state. This state waits for the twiddle factor of the number-theoretical transformation to be initialized. When the initialization module sends ntt_tf_is_avlb=0, it indicates that the twiddle factor of the number-theoretical transformation has not been initialized, and the state machine remains in the kWaitNTTTF state. When ntt_tf_is_avlb=1, the twiddle factor of the number-theoretical transformation is initialized, and the state machine will enter the kPolyNTT state. This state performs the butterfly calculation of the number-theoretical transformation. When the butterfly calculation module sends ntt_btf_finish_in=0, it indicates that the butterfly calculation module has not completed the calculation, and the state machine remains in the kPolyNTT state. When ntt_btf_finish_in=1, the butterfly calculation module completes the calculation, and the state machine returns to normal. The state machine will enter the kReverse state, where the data written back to the first storage module from the butterfly calculation module is reversed. When reverse_finish_in=0 from the reverse module, it indicates that the reverse module has not yet completed the reverse operation, and the state machine remains in the kReverse state. When reverse_finish_in=1, the reverse module has completed the reverse operation, and the state machine will enter the kReadResult state, which outputs the number theory transformation calculation result. When read_finish_in=0 from the result reading module, it indicates that the output is not complete, and the state machine remains in the kReadResult state. When read_finish_in=1, the calculation result has been output, and the state machine will enter the kFinish state. The state machine will then automatically jump to the kIdle state, waiting for the next poly_start signal from the outside. For the above state switching process and related data processing flow, please refer to [link to documentation]. Figure 3 As shown.

[0093] Based on the above example, in the memory initialization state, after the system receives the task start signal, it enters the memory initialization state. The initialization module stores the polynomial coefficients and NTT twiddle factors to be processed into the first and second storage modules, respectively. In the twiddle factor loading state, after the second state machine switches to the twiddle factor loading state, the initialization module retrieves the NTT twiddle factor from the second storage module and parses it. After parsing, the parsing result is returned to the second storage module, and a twiddle factor parsing completion signal is sent to the second state machine, pushing the state machine into the butterfly calculation state. This is similar to the example of waiting for twiddle factor initialization. In the example, the ntt_tf_is_avlb signal is used to determine whether the twiddle factor initialization is complete, while in this embodiment, the parsing completion signal is used to achieve state switching. In the butterfly calculation state, the butterfly calculation module reads the polynomial coefficients from the first storage module and the NTT twiddle factor parsing result from the second storage module, performing butterfly calculation. The intermediate result obtained from the calculation is stored in the first storage module, and a butterfly calculation completion signal is sent to the second state machine, causing the state machine to enter the reverse state. This is similar to the mechanism in the example where the butterfly calculation is judged based on the `ntt_btf_finish_in` signal to determine whether the butterfly calculation is complete, and then the state is switched accordingly. In the reverse state, the reverse module performs a bit-reversal permutation on the intermediate butterfly calculation result in the first storage module to obtain the NTT calculation result, and sends a reverse completion signal to the second state machine, causing the state machine to enter the result output state. This is similar to the example where the reverse_finish_in signal is used to determine whether the reverse operation is complete and switch states. In the result output state, the result reading module outputs the NTT calculation result. For the above state switching process and related data processing flow, please refer to [link to relevant documentation]. Figure 3 As shown.

[0094] In this way, the second state machine provides phased and refined control over the task execution process. Each state transition is based on the completion signal of the previous stage, ensuring orderly task execution and reducing the probability of errors. By clearly defining the operations of each module in different states, efficient data flow between hardware processing units is achieved, avoiding resource idleness and improving hardware resource utilization. This state transition and signal feedback mechanism enables the system to respond promptly to state changes in each module when executing NTT tasks, effectively improving system stability and reliability.

[0095] As an optional embodiment, if there are multiple NTT twitch factors, the initialization module is further configured to load the multiple NTT twitch factors into the second storage module at different times, so as to calculate the multiple NTT calculation results corresponding to the multiple NTT twitch factors respectively.

[0096] As an optional embodiment, when the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is specifically configured to: if the task selection signal is a second task signal, then the controller module determines that the target task is a multiplication task.

[0097] The controller module includes a third state machine; the third state machine is used to sequentially switch the task execution unit from the initialization memory state to the multiplication calculation state and the result output state; in the multiplication task, the data to be processed includes polynomial coefficients.

[0098] In the multiplication task, the target task path consists of the initialization module and the multiplication module. In the multiplication calculation state, the multiplication module is used to perform multiplication calculation on the first polynomial coefficients stored in the first storage module and the second polynomial coefficients stored in the second storage module. The product result is written into the first storage module, and a multiplication calculation completion signal is sent to the third state machine, causing the second state machine to switch to the result output state. In the result output state, the product result is output through the result reading module.

[0099] For example, assuming the task selection signal `control_signal` is used as an external input, when `control_signal` is assigned the value of the second task signal (equivalent to l2'b01 in the circuit logic), the system begins executing the multiplication task. Upon receiving the task start signal, the system enters the memory initialization state. The initialization module receives two sets of polynomial coefficients from the external memory and stores the first set in the first memory module and the second set in the second memory module. During the multiplication calculation state, the third state machine switches the task execution unit to the multiplication calculation state. The multiplication module reads the first polynomial coefficients from the first memory module and the second polynomial coefficients from the second memory module, performing the multiplication operation. During the calculation, the multiplication module continuously processes data. If the multiplication module feeds back `poly_mult_finish_in = 0` to the third state machine, the third state machine keeps the task execution unit in the multiplication calculation state. After the multiplication module completes the calculation, it can send the `poly_mult_finish_in = 1` signal to the third state machine. This is similar to the `poly_mult_finish_in` signal feedback mechanism in the example. Based on this signal, the third state machine switches the task execution unit to the result output state. In the result output state, the result reading module retrieves the product result from the first storage module and outputs the result externally, completing the execution of the entire multiplication task. Subsequent state transitions are the same as when `control_signal = 2'b00`. That is, when the result reading module sends `read_finish_in = 1`, the entire process enters the end state and then automatically returns to the idle state, waiting for the next task start signal.

[0100] Therefore, for multiplication tasks, the complex task is broken down into three stages: initialization, multiplication calculation, and result output. These stages are sequentially switched by a third state machine. Compared to schemes without state machine control, this greatly simplifies the execution flow of multiplication tasks and reduces design complexity. Through signal feedback and state machine state switching, the controller module can monitor the execution status of the multiplication task in real time, achieving precise control over task execution. It can also respond and handle abnormalities in task execution promptly, improving system stability and reliability. For the above state switching process and related data processing flow, please refer to [link to relevant documentation]. Figure 3 As shown.

[0101] As an optional embodiment, when the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is specifically configured to: if the task selection signal is a third task signal, then the task execution unit determines that the target task is the inverse number theory transformation task INTT.

[0102] The controller module includes a fourth state machine; the fourth state machine is used to sequentially switch the task execution unit from the initialization memory state to the inversion state, the twitch factor loading state, the butterfly calculation state, and the result output state; in the number theory transformation task, the data to be processed includes polynomial coefficients and INTT twitch factors.

[0103] In the number theory transformation task, the target task path consists of the initialization module, the butterfly calculation module, and the inversion module. In the inversion state, the inversion module is used to perform bit-reversal permutation on the polynomial coefficients in the first storage module and write the resulting polynomial inversion result back to the first storage module; it sends a inversion completion signal to the fourth state machine, causing the fourth state machine to switch to the twiddle factor loading state; in the twiddle factor loading state, the butterfly calculation module is also used to perform butterfly calculation on the polynomial inversion result in the first storage module and the INTT twiddle factor result in the second storage module to obtain the INTT calculation result; it sends a butterfly calculation completion signal to the fourth state machine, causing the fourth state machine to switch to the result output state, and outputs the INTT calculation result through the result reading module in the result output state.

[0104] For example, assuming the task selection signal `control_signal` is used as an external input, when `control_signal` is assigned the value of the third task signal, which is equivalent to 2'b10 in the circuit logic, the system initiates the inverse number theory transformation task. The controller module receives the task start signal and enters the initialization memory state. The initialization module stores the polynomial coefficients to be processed and the INTT twiddle factor into the first and second memory modules, respectively. The fourth state machine switches the task execution unit to the inversion state, and the inversion module reads the polynomial coefficients from the first memory module and performs a bit-reversal permutation operation. During the operation, if the inversion module feeds back `reverse_finish_in = 0` to the fourth state machine, the fourth state machine maintains the task execution unit in the inversion state; when the inversion operation is complete, the inversion module sends a `reverse_finish_in = 1` signal to the fourth state machine, which is consistent with the feedback mechanism of the `reverse_finish_in` signal in the given example. Based on this, the fourth state machine switches the task execution unit to the twiddle factor loading state. After entering the twiddle factor loading state, the butterfly calculation module reads the polynomial inversion result from the first memory module and the INTT twiddle factor from the second memory module, and performs butterfly calculations. During calculation, if the butterfly calculation module feeds back intt_btf_finish_in = 0 to the fourth state machine, the fourth state machine maintains the task execution unit in this state. When the butterfly calculation module completes the calculation, it sends an intt_btf_finish_in = 1 signal to the fourth state machine, and the fourth state machine switches the task execution unit to the result output state. This signal feedback and state switching mechanism is similar to the example where the intt_btf_finish_in signal controls the butterfly calculation state switching. In the result output state, the result reading module retrieves the INTT calculation result from the first storage module and outputs it externally, completing the inverse number theory transformation task. Subsequent state transitions are the same as when control_signal = 2'b00. When the result reading module sends read_finish_in = 1, the process enters the end state and then automatically returns to the idle state, waiting for the next task start signal. For the above state switching process and related data processing flow, please refer to [link to relevant documentation]. Figure 3 As shown.

[0105] Therefore, by utilizing a fourth state machine, the inverse number theory transformation task is decomposed into multiple stages, including initialization, reversal, rotation factor loading, and result output. Each stage has a clear function, and the state transitions are orderly. Compared to complex, disordered execution schemes, this greatly simplifies the task execution logic and improves the readability and maintainability of the design. Through feedback signals and state machine state transitions, the controller module can monitor the execution status of the inverse number theory transformation task in real time, achieving precise control of the task. When an anomaly occurs during task execution, the system can respond and handle it promptly, significantly improving system stability and reliability. The target task path consists of an initialization module, a butterfly calculation module, and a reversal module, avoiding unnecessary module involvement and reducing resource consumption. The modules cooperate collaboratively during task execution, effectively improving the utilization efficiency of hardware resources.

[0106] Figure 3 This illustrates the working principle of a finite state machine used for at least one task: number theory transformation, inverse number theory transformation, and multiplication. Figure 3 In the state machine, the `kldle` (idle) state is the initial state, waiting for the start signal `poly_start`. When `poly_start` is 0, the state remains in this state; when `poly_start` becomes 1, the state transitions to the `klnitMem` (initialize memory) state, marking task startup. In the `klnitMem` state, the initialization module processes and stores the input data, and then enters subsequent states based on different conditions. During initialization, the initialization module continuously processes data. If initialization is not complete, the initialization module will report `poly_finish_in=0` to the state machine, and the state machine will remain in the `kInitMem` state. Once initialization is complete, the initialization module will report `poly_finish_in=1` to the state machine. At this point, although the state machine is still in the `kInitMem` state, it will determine the target task to be executed next by the task execution unit based on the received task selection signal `control_signal`.

[0107] exist Figure 3In the process, if the condition for entering the kWaitNTTTF state is met (e.g., waiting for the number-theory transform twitch factor initialization related signal to be satisfied), the system switches to this state. If the condition for entering the kPolyMult state is met (e.g., the state switching condition used to trigger the multiplication task), the system switches to this state. If the condition for entering the kReverse state is met (e.g., some data preprocessing is completed), the system switches to the kReverse state. In the kWaitNTTTF (waiting for number-theory transform twitch factor) state, the system waits for the number-theory transform twitch factor initialization to complete. When the relevant signal (e.g., ntt_tf_is_avlb=1) is satisfied, it indicates that the twitch factor initialization is complete, and the system switches to the kPolyNTT state. In the kPolyNTT (performing number-theory transform butterfly calculation) state, the butterfly calculation module performs butterfly operations. When the operation completion signal (e.g., ntt_btf_finish_in=1) appears, the system switches to the kReverse state. In the kReverse (reverse) state, the reversal module performs bit-reversal permutation operations. After the operation is completed (e.g., reverse_finish_in=1), the system enters different states depending on the conditions. If the condition for entering the kWaitINTTTF state is met (e.g., preparing for the inverse number theory transformation, waiting for the inverse twiddle factor initialization), switch to this state. If the condition for entering the kReadResult state is met (e.g., preparing to output the result), switch to the kReadResult state. In the kWaitINTTTF (waiting for the inverse number theory transformation twiddle factor) state, wait for the inverse number theory transformation twiddle factor initialization to complete, and switch to the kPolyINTT state after the condition is met. In the kPolyINTT (performing the inverse number theory transformation butterfly calculation) state, execute the inverse number theory transformation butterfly calculation, and switch to the kReadResult state after completion. In the kReadResult (outputting the result) state, read the calculation result from the result module, and switch to the kFinish state after the result output is complete (e.g., read_finish_in=1). In the kFinish (completed) state, the task execution is complete, and then automatically jump to the kldle state, waiting for the next task start signal. Specific state switching conditions and processes can be found in the relevant descriptions in the previous embodiments, and will not be repeated here.

[0108] Figure 3 The state machine shown coordinates the work of each hardware processing unit in the number theory transformation task through orderly state switching and control of each module, accurately controls the data processing flow and state, ensures the accurate and efficient execution of the number theory transformation task, and realizes complete flow control from data initialization, rotation factor preparation, butterfly calculation, data reversal to result output.

[0109] In existing technologies, number-theoretical transformations, multiplications, and inverse number-theoretical transformations are executed as a single process using a data processing device. When multiplying two polynomials of length N, the required data storage consists of two polynomial coefficients of length N and two twiddle factors of length N, totaling 4N data points. When the data bit width is large (e.g., 255 bits) and the polynomial length is long (e.g., 2×18), the required data storage becomes enormous, exceeding the onboard storage resources of most FPGAs on the market. In this embodiment, the tasks are decoupled, and one task is executed at a time. When performing number-theoretical transformations or inverse number-theoretical transformations, only one polynomial coefficient of length N and one twiddle factor of length N need to be stored; when performing multiplication, two polynomial coefficients of length N are stored, reducing the total data quantity to 2N. This saves 50% of storage space compared to existing technologies. Under the same hardware resource conditions, due to the saving of storage space, this solution can support calculations with twice the sequence length. For example, under certain hardware resources, computations that could only support shorter sequence lengths can now support longer sequence lengths, thus increasing the computational scale.

[0110] Existing technical solutions lack flexibility in computation, requiring a complete process of number theory transformations, multiplication, and inverse number theory transformations. For polynomial multiplications of larger lengths (e.g., 2×30), it is difficult to implement ordinary number theory transformations and inverse number theory transformations on FPGAs, and existing technical solutions cannot support matrix number theory transformations and their inverse transformations.

[0111] In this embodiment, the state transition process of the finite state machine is controlled by a task selection signal to realize any one or more tasks among number-theoretical transformations, multiplication, or inverse number-theoretical transformations. The computation process can be flexibly changed according to requirements. It supports not only ordinary number-theoretical transformations and their inverse transformations, but also matrix number-theoretical transformations and their inverse transformations. Under similar hardware resource conditions, the sequence length of the number-theoretical transformations and their inverse transformations supported by this solution is increased quadratically. For example, the maximum sequence length supported in related technologies was originally 2×15, while the maximum supported sequence length can be increased to 2×30 after adopting the technical solution of this embodiment, greatly expanding the range of polynomial sequence lengths that can be processed and enhancing the applicability and computational power of the solution. Overall, in this embodiment, by decoupling and flexibly controlling tasks, computational efficiency and hardware resource utilization are improved, better meeting the needs of polynomial computation in practical applications.

[0112] Figure 4 This is a flowchart illustrating a data processing method provided in an embodiment of this application. The method is applied to the data processing apparatus described in the preceding embodiments. Figure 4 As shown, the method includes the following steps:

[0113] 401, The data processing device receives a task selection signal from the task request end and determines the target task to be executed by the task execution unit based on the task selection signal;

[0114] 402, The data processing device selects the corresponding hardware processing module based on the target task to construct the corresponding target task path;

[0115] 403, The data processing device receives the data to be processed and inputs the data to be processed into the target task path to start the target task and obtain the task execution result;

[0116] 404, the data processing device outputs the task execution result to the task requesting end.

[0117] In this embodiment of the application, the target task is one or more polynomial computation tasks. Polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks.

[0118] In this embodiment, the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs. The hardware processing modules in the task execution unit include: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module.

[0119] Further optionally, the hardware processing module in the task execution unit includes: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module; wherein, the initialization module is connected to the storage module; the initialization module is used to receive the data to be processed and temporarily store the data to be processed in the storage module; wherein, the storage module is respectively connected to the reversal module, the butterfly calculation module, and the multiplication module, and the butterfly calculation module and the multiplication module are respectively connected to the modular multiplication module; the data processing results of the reversal module, the butterfly calculation module, the multiplication module, and the modular multiplication module are output to the result reading module through the storage module.

[0120] Further optionally, the storage module includes a first storage module and a second storage module; the first storage module and the second storage module each occupy one unit of storage space; the step of selecting the corresponding hardware processing module based on the target task to construct the corresponding target task path includes:

[0121] Based on the target task, a corresponding target processing unit is selected from the first storage module, the second storage module, the reversal module, the butterfly calculation module, the multiplication module, and the modular multiplication module; the selected target processing units are combined into a corresponding data processing link, and the combined data processing link is used as the target task path.

[0122] Further optionally, the method further includes: controlling the data processing state of the data to be processed in the target task path; the step of inputting the data to be processed into the target task path to execute the target task includes: under the control and scheduling of the controller module, loading the data to be processed into the target task path, and switching the hardware processing unit where the data to be processed is located in the target task path to execute the corresponding data processing flow in the target task.

[0123] Further optionally, the controller module includes a first state machine; before determining the target task to be executed by the task execution unit based on the task selection signal, the method further includes: receiving a task start signal through the first state machine; based on the task start signal, switching the initialization module to an initialization memory state to trigger the initialization module to perform an initialization operation on the data to be processed; after receiving an initialization end signal, remaining in the initialization memory state and triggering the step of determining the target task to be executed by the task execution unit based on the task selection signal. After the initialization and parsing of the data to be processed is completed, the method further includes: feeding back the initialization end signal to the first state machine through the initialization module.

[0124] Further optionally, determining the target task to be executed by the task execution unit based on the task selection signal includes: if the task selection signal is a first task signal, then determining the target task as a number theory transformation task (NTT).

[0125] The controller module includes a second state machine; controlling the data processing state of the data to be processed in the target task path includes: using the second state machine to sequentially switch the task execution unit from the initialization memory state to the twitch factor loading state, the butterfly calculation state, the reversal state, and the result output state; in the number theory transformation task, the data to be processed includes polynomial coefficients and NTT twitch factors.

[0126] In NTT, the target task path consists of the initialization module, the butterfly calculation module, and the reversal module. Under the control and scheduling of the controller module, loading the data to be processed into the target task path and switching the hardware processing unit where the data to be processed resides within the target task path includes: in the rotation factor loading state, obtaining the NTT rotation factor from the second storage module through the initialization module and performing initialization parsing on the NTT rotation factor; if parsing is complete, returning the NTT rotation factor parsing results to the second storage module and sending a rotation factor parsing completion signal to the second state machine, causing the second state machine to switch to the butterfly calculation state; In the butterfly calculation state, the butterfly calculation module performs butterfly calculations on the polynomial coefficients in the first storage module and the NTT twitch factor analysis results in the second storage module; the intermediate butterfly calculation results are stored in the first storage module, and a butterfly calculation completion signal is sent to the second state machine, causing the second state machine to switch to the inversion state; in the inversion state, the inversion module performs bit-reversal permutation on the intermediate butterfly calculation results in the first storage module to obtain the NTT calculation result; a inversion completion signal is sent to the second state machine, causing the second state machine to switch to the result output state, and in the result output state, the NTT calculation result is output through the result reading module.

[0127] Further optionally, the method further includes: if there are multiple NTT twitch factors, loading the multiple NTT twitch factors into the second storage module at different times respectively, so as to calculate the multiple NTT calculation results corresponding to the multiple NTT twitch factors respectively.

[0128] Further optionally, determining the target task to be executed by the task execution unit based on the task selection signal includes: if the task selection signal is a second task signal, then determining the target task as a multiplication task.

[0129] The controller module includes a third state machine; controlling the data processing state of the data to be processed in the target task path includes: using the third state machine to sequentially switch the task execution unit from the initialization memory state to the multiplication calculation state and the result output state; in the multiplication task, the data to be processed includes polynomial coefficients.

[0130] In the multiplication task, the target task path consists of the initialization module and the multiplication module. The process of loading the data to be processed into the target task path under the control and scheduling of the controller module, and switching the hardware processing unit where the data to be processed is located within the target task path, includes: in the multiplication calculation state, multiplying the first polynomial coefficients stored in the first storage module with the second polynomial coefficients stored in the second storage module using the multiplication module; writing the product result into the first storage module; sending a multiplication calculation completion signal to the third state machine, causing the second state machine to switch to the result output state; and outputting the product result through the result reading module in the result output state.

[0131] Further optionally, determining the target task to be executed by the task execution unit based on the task selection signal includes: if the task selection signal is a third task signal, then determining the target task as the inverse number theory transformation task INTT.

[0132] The controller module includes a fourth state machine; controlling the data processing state of the data to be processed in the target task path includes: using the fourth state machine to sequentially switch the task execution unit from the initialization memory state to the inversion state, the twitch factor loading state, the butterfly calculation state, and the result output state; in the number theory transformation task, the data to be processed includes polynomial coefficients and INTT twitch factors.

[0133] In the number theory transformation task, the target task path consists of the initialization module, the butterfly calculation module, and the inversion module. Under the control and scheduling of the controller module, loading the data to be processed into the target task path and switching the hardware processing unit where the data to be processed resides within the target task path includes: in the inversion state, performing bit-reversal permutations on the polynomial coefficients in the first storage module using the inversion module, and writing the resulting polynomial inversion result back to the first storage module; sending a inversion completion signal to the fourth state machine, causing the fourth state machine to switch to the twiddle factor loading state; in the twiddle factor loading state, performing a butterfly calculation on the polynomial inversion result in the first storage module and the INTT twiddle factor result in the second storage module using the butterfly calculation module; storing the intermediate butterfly calculation result in the first storage module, and sending a butterfly calculation completion signal to the fourth state machine, causing the fourth state machine to switch to the result output state, and outputting the INTT calculation result through the result reading module in the result output state.

[0134] The above method can achieve various functions in the above device embodiments, which will not be elaborated here.

[0135] In the data processing method provided in this application embodiment, the target task is determined based on the task selection signal, which supports the individual or combined execution of tasks such as number theory transformation, multiplication, and inverse number theory transformation in polynomial calculation tasks. This facilitates the adaptation of various polynomial multiplication task calculation requirements through the task selection signal and dynamically combined hardware processing modules, thereby improving the scalability of the hardware structure and increasing resource utilization.

[0136] Please see Figure 5 , Figure 5 A schematic diagram illustrating an embodiment of the electronic device provided in this application. For example... Figure 5 As shown, this application provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, it implements the functions described in the above-described device embodiment.

[0137] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided in this application. For example... Figure 6 As shown, this embodiment provides a computer-readable storage medium 600 that stores instructions 611 thereon. When the instructions 611 are executed on a computer, the computer performs the functions described in the above-described device embodiment.

[0138] This application also provides a chip loaded with a computer program, which is used to implement the functions described in the above-described device embodiments.

[0139] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should understand that the embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. Although preferred embodiments of this application have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A data processing apparatus, characterized in that, The device is used to process polynomial multiplication tasks with large bit width sequences. The device includes: a controller module, a task execution unit, and a result reading module. The controller module is used to receive a task selection signal from the task request terminal and determine the target task to be executed by the task execution unit based on the task selection signal; the target task is one or more polynomial computation tasks; polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks; The task execution unit is used to select the corresponding hardware processing module based on the target task to construct the corresponding target task path; the hardware processing module in the task execution unit includes: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module; the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs; The task execution unit is also used to receive data to be processed and input the data to be processed into the target task path to start the target task and obtain the task execution result; The result reading module is used to output the task execution result to the task requesting end; Specifically, when the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is used to: if the task selection signal is a first task signal, then the controller module determines that the target task is a number theory transformation task (NTT). When the task selection signal is the first task signal, the hardware processing module of the target task path is connected in series, and the output of the initialization module is directly connected to the input of the butterfly calculation module, and the output of the butterfly calculation module is directly connected to the input of the reversal module. The controller module includes a second state machine; the second state machine is used to sequentially switch the task execution unit from the initialization memory state to the twitch factor loading state, the butterfly calculation state, the reversal state, and the result output state; each state switch of the second state machine is triggered by a signal from a single preceding module, and cross-stage jumps are prohibited during the state switch process; in the number theory transformation task, the data to be processed includes polynomial coefficients and NTT twitch factors; In NTT, the target task path consists of the initialization module, the butterfly calculation module, and the reversal module; In the rotation factor loading state, the initialization module is used to obtain the NTT rotation factor from the second storage module and perform initialization parsing on the NTT rotation factor; if the parsing is completed, the NTT rotation factor parsing result is returned to the second storage module and a rotation factor parsing completion signal is sent to the second state machine, causing the second state machine to switch to the butterfly calculation state; In the butterfly calculation state, the butterfly calculation module is used to perform butterfly calculation on the polynomial coefficients in the first storage module and the NTT twitch factor analysis results in the second storage module; store the obtained intermediate butterfly calculation results in the first storage module, and send a butterfly calculation completion signal to the second state machine, so that the second state machine switches to the reverse state; In the reverse state, the reverse module is used to perform bit reversal permutation on the data during the bit reversal arrangement stage, in the preprocessing or postprocessing of NTT or INTT. The bit reversal permutation of the reverse module completely reverses the binary bits of the index of the intermediate result of the butterfly calculation, and the bit reversal permutation of the reverse module is independent of the butterfly calculation module, serving as a post-processing step in the NTT task. The reverse module is used to perform bit reversal permutation on the intermediate result of the butterfly calculation in the first storage module to obtain the NTT calculation result; send a reverse completion signal to the second state machine to switch the second state machine to the result output state, and output the NTT calculation result through the result reading module in the result output state.

2. The data processing apparatus according to claim 1, characterized in that, The initialization module is connected to the storage module; the initialization module is used to receive the data to be processed and temporarily store the data to be processed in the storage module. The storage module is connected to the inversion module, the butterfly calculation module, and the multiplication module, respectively. The butterfly calculation module and the multiplication module are connected to the modular multiplication module, respectively. The data processing results of the inversion module, the butterfly calculation module, the multiplication module, and the modular multiplication module are output to the read result module through the storage module.

3. The data processing apparatus according to claim 2, characterized in that, The storage module includes a first storage module and a second storage module; the first storage module and the second storage module each occupy one unit of storage space. The task execution unit, when selecting the corresponding hardware processing module based on the target task to construct the corresponding target task path, is specifically used for: The task execution unit selects a corresponding target processing unit from the first storage module, the second storage module, the reversal module, the butterfly calculation module, the multiplication module, and the modular multiplication module based on the target task; combines the selected target processing units into a corresponding data processing link, and uses the combined data processing link as the target task path.

4. The data processing apparatus according to claim 2, characterized in that, The controller module is also used to control the data processing status of the data to be processed in the target task path; The task execution unit, when inputting the data to be processed into the target task path to execute the target task, is specifically used for: Under the control and scheduling of the controller module, the task execution unit loads the data to be processed into the target task path, and switches the hardware processing unit where the data to be processed is located in the target task path to execute the corresponding data processing flow in the target task.

5. The data processing apparatus according to claim 4, characterized in that, The controller module includes a first state machine; the first state machine is configured to receive a task start signal before determining the target task to be executed by the task execution unit based on the task selection signal; based on the task start signal, switch the initialization module to the initialization memory state to trigger the initialization module to perform an initialization operation on the data to be processed; after receiving the initialization end signal, remain in the initialization memory state and trigger the step of determining the target task to be executed by the task execution unit based on the task selection signal; The initialization module is also used to perform initialization parsing on the data to be processed, and after the initialization is completed, to send the initialization completion signal back to the first state machine.

6. The data processing apparatus according to claim 1, characterized in that, If there are multiple NTT twitch factors, the initialization module is also used to load the multiple NTT twitch factors into the second storage module at different times, so as to calculate the multiple NTT calculation results corresponding to the multiple NTT twitch factors respectively.

7. The data processing apparatus according to claim 1, characterized in that, When the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is specifically configured to: if the task selection signal is a second task signal, then the controller module determines that the target task is a multiplication task; The controller module includes a third state machine; the third state machine is used to sequentially switch the task execution unit from the initialization memory state to the multiplication calculation state and the result output state; In the multiplication task, the data to be processed includes polynomial coefficients; In the multiplication task, the target task path consists of the initialization module and the multiplication module; In the multiplication calculation state, the multiplication module is used to perform multiplication calculation on the first polynomial coefficients stored in the first storage module and the second polynomial coefficients stored in the second storage module; write the product result into the first storage module, and send a multiplication calculation completion signal to the third state machine, causing the second state machine to switch to the result output state, and output the product result through the result reading module in the result output state.

8. The data processing apparatus according to claim 1, characterized in that, When the controller module determines the target task to be executed by the task execution unit based on the task selection signal, it is specifically used to: if the task selection signal is a third task signal, then the controller module determines that the target task is the inverse number theory transformation task INTT; The controller module includes a fourth state machine; the fourth state machine is used to sequentially switch the task execution unit from the initialization memory state to the reverse state, the rotation factor loading state, the butterfly calculation state, and the result output state; In the number theory transformation task, the data to be processed includes polynomial coefficients and INTT twitch factors; In the number theory transformation task, the target task path consists of the initialization module, the butterfly calculation module, and the reversal module; In the inverted state, the inverted module is used to perform bit-reversal permutation on the polynomial coefficients in the first storage module and write the resulting polynomial inversion result back to the first storage module; Send a reversal completion signal to the fourth state machine to switch the fourth state machine to the rotation factor loading state; In the twitch factor loading state, the butterfly calculation module is also used to perform butterfly calculation on the polynomial inversion result in the first storage module and the INTT twitch factor result in the second storage module to obtain the INTT calculation result; A butterfly calculation completion signal is sent to the fourth state machine, causing the fourth state machine to switch to the result output state, and the INTT calculation result is output through the result reading module in the result output state.

9. A data processing method, applied to the data processing apparatus as described in any one of claims 1-8, wherein the apparatus is used to process polynomial multiplication tasks of large bit-width long sequences, the data processing method comprising: The data processing device receives a task selection signal from the task request terminal and determines the target task to be executed by the task execution unit based on the task selection signal. The target task is one or more of the following: polynomial computation tasks; polynomial computation tasks include at least: number theory transformation tasks, multiplication tasks, and inverse number theory transformation tasks. The data processing device selects the corresponding hardware processing module based on the target task to construct the corresponding target task path; the hardware processing module in the task execution unit includes: an initialization module, a storage module, a reversal module, a butterfly calculation module, a multiplication module, and a modular multiplication module; the number, type, and connection method of the hardware processing modules in the target task path are related to the task type to which the target task belongs; The data processing device receives the data to be processed and inputs the data to be processed into the target task path to start the target task and obtain the task execution result; The data processing device outputs the task execution result to the task request terminal; The step of determining the target task to be executed by the task execution unit based on the task selection signal includes: if the task selection signal is a first task signal, then the controller module determines that the target task is a number theory transformation task (NTT). When the task selection signal is the first task signal, the hardware processing module of the target task path is connected in series, and the output of the initialization module is directly connected to the input of the butterfly calculation module, and the output of the butterfly calculation module is directly connected to the input of the reversal module. The controller module includes a second state machine; the second state machine sequentially switches the task execution unit from the initialization memory state to the rotation factor loading state, the butterfly calculation state, the reversal state, and the result output state; each state switch of the second state machine is triggered by a signal from a single preceding module, and cross-stage jumps are prohibited during the state switch process; in the number theory transformation task, the data to be processed includes polynomial coefficients and NTT rotation factors; In NTT, the target task path consists of the initialization module, the butterfly calculation module, and the reversal module; In the rotation factor loading state, the NTT rotation factor is obtained from the second storage module through the initialization module, and the NTT rotation factor is initialized and parsed; if the parsing is completed, the NTT rotation factor parsing result is returned to the second storage module, and a rotation factor parsing completion signal is sent to the second state machine, so that the second state machine switches to the butterfly calculation state. In the butterfly calculation state, the butterfly calculation module performs butterfly calculation on the polynomial coefficients in the first storage module and the NTT twitch factor analysis results in the second storage module; the intermediate results of the butterfly calculation are stored in the first storage module, and a butterfly calculation completion signal is sent to the second state machine, causing the second state machine to switch to the reverse state; In the reverse state, the reverse module performs bit reversal permutation on the intermediate butterfly calculation results in the first storage module to obtain the NTT calculation result; a reverse completion signal is sent to the second state machine, causing the second state machine to switch to the result output state, and the NTT calculation result is output through the result reading module in the result output state; the reverse module is used to perform bit reversal permutation on the data during the bit reversal arrangement stage, during the preprocessing or postprocessing of NTT or INTT; the bit reversal permutation of the reverse module completely reverses the binary bits of the index of the intermediate butterfly calculation results, and the bit reversal permutation of the reverse module is independent of the butterfly calculation module, serving as a post-processing step in the NTT task.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for reading and executing the computer program to implement the data processing apparatus according to any one of claims 1-8.

11. A chip, characterized in that, The chip is loaded with a computer program, which is used to implement the data processing device as described in any one of claims 1-8.

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