Charging circuit

Abstract

To provide a charging circuit capable of stably operating in a wide range of charging currents.SOLUTION: A first transistor M1 is connected between an input terminal VIN and an output terminal VOUT. An external current setting resistor RICHG is connected to a current setting terminal ICHG. A second transistor M2 is connected between the input terminal VIN and the current setting terminal VOUT, and the gate is connected to the first transistor M1 and a gate. A constant current feedback circuit 210 feedback controls the gate voltage VG of the first transistor M1 so that a voltage VICHG_S of the current setting terminal ICHG approaches a reference voltage VREF(CC). The constant current feedback circuit 210 is configured such that a phase compensation parameter is variable according to a current ICHG flowing through the first transistor M1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a charging circuit for a secondary battery. [Background technology]

[0002] Battery-powered devices such as mobile phones, smartphones, tablets, notebook computers, and portable audio players are equipped with rechargeable secondary batteries that can be charged by a charging circuit built into the electronic device or by an external charger.

[0003] When the battery voltage is low, the charging circuit operates in CC (Constant Current) mode, charging the battery at a constant current, and when the battery approaches full charge, it operates in CV (Constant Voltage) mode, adjusting the charging current so that the battery voltage approaches the target voltage when fully charged. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-184598 A [Patent Document 2] JP 2015-43648 A Summary of the Invention [Problem to be solved by the invention]

[0005] Designers of electronic devices and chargers want to specify the amount of charging current in CC mode individually according to the type and model of the battery, etc. To meet this requirement, the charging circuit is configured to be able to set the amount of charging current in CC mode.

[0006] The charging circuit has a feedback loop that maintains the charging current in CC mode at a target value, but the stability of this feedback loop is greatly affected by the target value of the charging current. Therefore, if the charging current is configured to be settable over a wide range, it is necessary to ensure stability (i.e., phase margin and gain margin) over a wide current range, which makes the design of the feedback loop difficult.

[0007] The present disclosure has been made in this context, and it is an exemplary purpose of an embodiment of the present disclosure to provide a charging circuit capable of stably operating over a wide range of charging currents. [Means for solving the problem]

[0008] A charging circuit according to an embodiment of the present disclosure includes an input terminal, an output terminal, a first transistor connected between the input terminal and the output terminal, a current setting terminal to which an external current setting resistor is to be connected, a second transistor connected between the input terminal and the current setting terminal and having a gate connected to the gate of the first transistor, and a constant current feedback circuit that feedback controls the gate voltage of the first transistor so that the voltage of the current setting terminal approaches a reference voltage. The constant current feedback circuit is configured such that a phase compensation parameter is variable according to the current flowing through the first transistor.

[0009] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0010] According to an aspect of the present disclosure, a charging circuit can be operated stably over a wide range of charging currents. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of an electronic device including a charging circuit according to an embodiment. [Diagram 2]FIG. 2 is a circuit diagram showing a specific example of the configuration of the charging circuit. [Diagram 3] FIG. 3 is a diagram illustrating adaptive phase compensation in a charging circuit. [Figure 4] FIG. 4 is a circuit diagram of a charging circuit according to an embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing a specific example of the configuration of the charging circuit in FIG. [Figure 6] FIG. 6 is a diagram for explaining adaptive phase compensation based on a decrease in loop gain. [Figure 7] FIG. 11 is a circuit diagram showing another example of the configuration of the charging circuit. [Figure 8] FIG. 8 is a circuit diagram showing a modification of the charging circuit of FIG. [Figure 9] FIG. 9 is a circuit diagram showing another example of the configuration of the charging circuit. [Figure 10] FIG. 10 is a circuit diagram showing another example of the configuration of the charging circuit. [Figure 11] FIG. 11 is a circuit diagram showing another example of the configuration of the charging circuit. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a charging circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified summary of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to limit essential components of the embodiments. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0013] This summary is not an extensive overview of all possible embodiments, and is not intended to identify key or critical elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0014] A charging circuit according to one embodiment includes an input terminal, an output terminal, a first transistor connected between the input terminal and the output terminal, a current setting terminal to which an external current setting resistor is to be connected, a second transistor connected between the input terminal and the current setting terminal and having a gate connected to the gate of the first transistor, and a constant current feedback circuit that feedback controls the gate voltage of the first transistor so that the voltage of the current setting terminal approaches a reference voltage. The constant current feedback circuit is configured such that a phase compensation parameter is variable according to the current flowing through the first transistor.

[0015] A current proportional to the charging current flowing through the first transistor and the output terminal flows through the resistance of the current setting resistor. Therefore, the voltage at the current setting terminal, in other words, the voltage drop Vs of the current setting resistor, is proportional to the charging current I CHG and the resistance value of the current setting resistor R ICHG is proportional to. V S =A×I CHG ×R ICHG The constant current feedback circuit regulates the voltage V S is the reference voltage V REF When the charge current is regulated to I CHG is the target current I CHG(REF) is stabilized to. I CHG(REF) =V REF / (A×R ICHG ) In other words, the charging current I is inversely proportional to the resistance value of the current setting resistor. CHG can be set.

[0016] Here, the current setting resistor generates a pole together with the parasitic capacitance around it. The position of this pole shifts according to the resistance value of the current setting resistor. With this configuration, by changing the phase compensation parameters of the constant current feedback circuit according to the current flowing through the first transistor, in other words, the resistance value of the current setting resistor, it is possible to ensure a phase margin and a gain margin, and to ensure stability over a wide current range.

[0017] In one embodiment, the constant current feedback circuit may include a third transistor having a first terminal connected to the input terminal and a second terminal connected to the gate of the first transistor, a constant current load connected between the second terminal of the third transistor and ground, and a differential amplifier receiving the voltage of the current setting terminal and a reference voltage and having an output node connected to the control terminal of the third transistor. In this configuration, a pole of the first stage in the differential amplifier is formed by a common emitter / common source amplifier stage including the third transistor and the constant current load, a pole of the second stage is formed by the second transistor and a current setting resistor, and a pole of the third stage is formed by the second transistor and a current setting resistor. Stability can be ensured by dynamically changing a phase compensation parameter in the first stage or the second stage according to a shift in the pole of the third stage.

[0018] In one embodiment, the constant current feedback circuit may further include a first resistor and a first capacitor connected in series between the control terminal and the second end of the third transistor. At least one of the resistance value of the first resistor and the capacitance of the first capacitor may be a variable phase compensation parameter. In this case, the position of the zero can be shifted according to the position of the pole determined according to the current setting resistor.

[0019] In one embodiment, the first resistor may include a first resistive element, and a series transistor and a second resistive element connected in series across the first resistive element. The series transistor may change state in response to a current flowing through the first transistor.

[0020] In one embodiment, the constant current feedback circuit may include a third transistor having a first end connected to the input terminal and a second end connected to the gate of the first transistor, a constant current load connected between the second end of the third transistor and ground, a differential amplifier receiving the voltage of the current setting terminal and a reference voltage and having an output node connected to the control terminal of the third transistor, a first resistance element and a first capacitor connected in series between the control terminal and the second end of the third transistor, a P-type transistor and a second resistance element connected directly between both ends of the first resistance element, a fourth transistor having gates and sources commonly connected to the first transistor, a current mirror circuit having an input node connected to the fourth transistor and an output node connected to the P-type transistor, and an impedance circuit connected between the input terminal and the output node of the current mirror circuit. This allows the position of the zero to be set according to the position of the pole determined according to the current setting resistor.

[0021] In one embodiment, the impedance circuit may include a P-type transistor with its gate and drain wired together.

[0022] In one embodiment, the constant current feedback circuit may supply a current proportional to the current flowing through the first transistor to the control terminal of the third transistor, so that the larger the charging current is, i.e., the smaller the current setting resistor is, the larger the mirror current is, and the gain can be reduced, thereby increasing the gain margin.

[0023] In one embodiment, the gain of the differential amplifier may be a variable phase compensation parameter, and the position of the pole, which is determined by the current setting resistor, can be changed depending on the position of the pole, which is determined by the gain of the differential amplifier.

[0024] In one embodiment, the differential amplifier may include a differential input stage and a common-emitter or common-source amplifier stage that amplifies an output of the differential input stage. The constant current feedback circuit may be configured to vary the output impedance of the amplifier stage according to a current flowing through the first transistor.

[0025] In one embodiment, the collector load or drain load of the amplifier stage may be configured to be variable.In one embodiment, the impedance of the common emitter transistor or common source transistor of the amplifier stage may be configured to be variable.

[0026] In one embodiment, the constant current feedback circuit may include a fourth transistor having gates and sources commonly connected to the first transistor. A phase compensation parameter of the constant current feedback circuit may vary according to a current of the fourth transistor. A charging current flowing through the first transistor, in other words, a current according to a resistance value of a current setting resistor, flows through the fourth transistor. Therefore, by referring to the current of the fourth transistor, the phase compensation parameter of the constant current feedback circuit can be suitably controlled.

[0027] In one embodiment, the constant current feedback circuit may include a sense resistor connected in series with the first transistor, and a phase compensation parameter of the constant current feedback circuit may vary according to a voltage drop across the sense resistor.

[0028] In one embodiment, the charging circuit may further include a voltage balance circuit connected between the second transistor and the current setting terminal to bring the voltage of one end of the second transistor closer to the voltage of the output terminal, thereby making it possible to bring the drain-source voltage of the second transistor closer to the drain-source voltage of the first transistor, thereby making it possible to monitor the charging current with high accuracy.

[0029] In one embodiment, the charging circuit may further include a constant voltage feedback circuit that feedback controls the gate voltage of the first transistor so that the voltage of the output terminal approaches the second reference voltage.

[0030] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0031] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected to each other, and a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0032] Similarly, "a state in which component C is provided between components A and B" and "a state in which component C is connected between components A and B" include not only cases in which components A and C, or components B and C, are directly connected to each other, but also cases in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0033] 1 is a block diagram of an electronic device 100 including a charging circuit 200 according to an embodiment. The electronic device 100 includes a battery 102 and the charging circuit 200. The battery 102 is a rechargeable secondary battery, such as a lithium ion battery, a lithium ion polymer battery, a nickel metal hydride battery, or a nickel cadmium battery.

[0034] The charging circuit 200 receives a DC input voltage V IN The charging circuit 200 receives a charging current I CHG to charge the battery 102. The charging circuit 200 is an IC (Integrated Circuit) integrated on a single semiconductor substrate.

[0035] The charging circuit 200 includes a charging current setting terminal (hereinafter, simply referred to as a current setting terminal) ICHG. The current setting terminal ICHG is connected to an external current setting resistor R ICHG The charging current I generated by the charging circuit 200 is CHG is the current setting resistor R ICHG It can be set according to the resistance value of the current setting resistor R ICHG The resistance value of the resistor R is determined by the designer of the electronic device 100 based on the specifications of the battery 102. In other words, the charging circuit 200 does not require a resistor R ICHG It is required that the device operates stably without oscillating even if it is connected to a terminal. In this specification, a "terminal" may be a pin of an IC package, or an electrode of a die (chip) in an IC package.

[0036] In general, the charging circuit 200 detects the voltage V of the battery 102. BAT The mode can be switched between CC (constant current) mode and CV (constant voltage) mode depending on the input voltage, but FIG. 1 shows only the configuration related to the CC mode, and omits the configuration related to the CV mode.

[0037] The charging circuit 200 includes a first transistor M1, a second transistor M2, and a constant current feedback circuit 210. The first transistor M1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is connected between an input terminal VIN and an output terminal VOUT. The first transistor M1 may be a PNP-type bipolar transistor. A current flowing through the first transistor M1 is a charging current I CHG In the CC mode, the charging circuit 200 controls the gate voltage V G By adjusting the charging current I CHG The target current I CHG(REF) The voltage stabilizes to .

[0038] The second transistor M2 is of the same type as the first transistor M1 and is connected between the input terminal VIN and the current setting terminal ICHG. The gate of the second transistor M2 is connected to the gate of the first transistor M1. The second transistor M2 has a charging current I CHG Current I proportional to M2 flows. I M2 =A×I CHG The coefficient A is determined according to the size ratio between the first transistor M1 and the second transistor M2. For example, when the size ratio between the first transistor M1 and the second transistor M2 is 1000:1, A=1 / 1000.

[0039] current I M2 is the current setting resistor R ICHG When a current flows through the current setting terminal ICHG, a voltage drop occurs. ICHG_S It appears as: V ICHG_S =R ICHG ×I M2 =R ICHG ×A×I CHG

[0040] Voltage signal V ICHG_S is fed back to the constant current feedback circuit 210. The constant current feedback circuit 210 receives the voltage V ICHG_S is the reference voltage V REF(CC) The gate voltage V of the first transistor M1 is adjusted so as to approach G is feedback controlled.

[0041] The feedback of the constant current feedback circuit 210 causes V REF(CC) =V ICHG_S Therefore, the charging current I CHG is the target current I CHG(REF) is stabilized to. I CHG(REF) =V REF(CC) / (R ICHG ×A)

[0042] That is, the set value I CHG(REF) is the current setting resistor R ICHG is inversely proportional to the resistance value.

[0043] Current setting resistor R ICHG In general, a semiconductor chip has an ESD protection element (diode) for each terminal, and the parasitic capacitance Cp of this ESD protection element is ICHG This is also one of the causes of the pole generation. CHG If the current is variable in the range of 1 mA to 300 mA, the pole position (frequency) also changes by a factor of 300. Furthermore, when considering fluctuations in the power supply voltage and temperature, the pole frequency changes by a factor of 1000 (for example, from 1 kHz to 1 MHz).

[0044] To ensure the stability of the feedback loop, a zero is usually introduced by phase compensation. However, when the pole changes by a factor of 1000, it is very difficult to ensure the stability of the feedback loop with the same phase compensation.

[0045] Therefore, in this embodiment, adaptive phase compensation is introduced. Specifically, the constant current feedback circuit 210 adjusts the charging current I CHG The phase compensation parameters are adapted to change adaptively in response to the

[0046] As mentioned above, the charging current I CHG is the current setting resistor R ICHG Therefore, the charging current I ICHG is the current setting resistor R ICHG Therefore, the parameter of the phase compensation in the constant current feedback circuit 210 is the charging current I CHG By dynamically and adaptively changing the loop gain and the position of the zero can be changed according to the position of the pole, thereby ensuring a phase margin and a gain margin.

[0047] Specific examples of variable phase compensation parameters will be described later, but examples of phase compensation parameters include changes in circuit constants, operating points, and circuit configurations that contribute to the stability of the feedback loop.

[0048] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram in Fig. 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described in order to aid in understanding the essence and operation of the present disclosure and the present invention and to clarify them, without narrowing the scope of the present disclosure.

[0049] 2 is a circuit diagram showing a specific configuration example of the charging circuit 200. The constant current feedback circuit 210 includes a third transistor M3 and a constant current load CS3.

[0050] The third transistor M3 is a P-channel MOSFET, and a first end (source) thereof is connected to the input terminal VIN. The constant current load CS3 is connected between a second end (drain) of the third transistor M3 and the ground. The connection node between the third transistor M3 and the constant current load CS3 is connected to the gate of the first transistor M1.

[0051] The differential amplifier (error amplifier) ​​212 has a reference voltage V REF(CC) and its inverting input terminal (-) receives the voltage of the current setting terminal ICHG. In this example, a sense terminal ICHG_S having the same potential as the current setting terminal ICHG is provided, and a voltage VCHG_S of the sense terminal ICHG_S is supplied to the inverting input terminal (-) of the differential amplifier 212. The output of the differential amplifier 212 is connected to the control terminal (gate) of the third transistor M3.

[0052] The charging circuit 200 can be considered as a three-stage amplifier. That is, the first stage STG1 is a differential amplifier 212, the second stage STG2 is a common-source amplifier including a third transistor M3 and a constant current load CS3, and the third stage is a common-source amplifier including a second transistor M2 and a current setting resistor R ICHG In this three-stage amplifier, a pole is introduced in each of the first, second, and third stages. A phase compensation circuit 214 is provided in the constant current feedback circuit 210.

[0053] The phase compensation circuit 214 includes a first resistor R1 and a first capacitor C1 connected in series between the control terminal (gate) and the second terminal (drain) of the third transistor M3, in other words, between the input and output of the second amplification stage (M3, CS3).

[0054] The pole that occurs in the third stage (third pole) is the current setting resistor R ICHG is determined by the parasitic capacitance Cp. The parasitic capacitance Cp may include the parasitic capacitance of the ESD (Electro Static Discharge) protection elements 202 and 204 provided on the ICHG terminal and the ICHG_S terminal.

[0055] 3 is a diagram for explaining adaptive phase compensation in the charging circuit 200. In FIG. 3, the first, second, and third poles are plotted with X. The frequency of the third pole varies in the range of, for example, 1 kHz to 1 MHz, and the current setting resistor R ICHG The smaller the resistance of, that is, the lower the charging current I CHG The larger the set value, the higher the frequency of the third pole shifts.

[0056] The zeros introduced by the phase compensation circuit 214 are plotted as circles in FIG. CHG In other words, the current setting resistor R ICHG By changing the circuit constant of the phase compensation circuit 214 in accordance with the third pole, the position of the zero in the first stage can be adaptively set in accordance with the third pole.

[0057] Charging current ICHG When the current is variable in the range of 1mA to 300mA, the current setting resistor R ICHG Since the resistance value of also changes by 300 times, the position (frequency) of the third pole also changes by a range of 300 times. Furthermore, when considering fluctuations in the power supply voltage and temperature, the frequency of the third pole changes by a range of 1000 times (for example, from 1 kHz to 1 MHz).

[0058] In one embodiment, the resistance value of the first resistor R1 can be selected as a variable phase compensation parameter in the constant current feedback circuit 210, and the resistance value of the first resistor R1 is set to a value that is smaller than the charging current I CHG The resistor may be a variable resistor that changes depending on the input voltage.

[0059] 4 is a circuit diagram of a charging circuit 200 according to an embodiment. In this embodiment, the resistance value of the first resistor R1 of the phase compensation circuit 214 is set to a value that is smaller than the charging current I CHG The system is adaptively controlled according to the conditions.

[0060] The constant current feedback circuit 210 includes a fourth transistor M4, a current mirror circuit 230, and an impedance circuit 232 for adaptive phase compensation, in addition to a third transistor M3, a phase compensation circuit 214, and a constant current load CS3.

[0061] The fourth transistor M4 has its gates and sources connected in common to the first transistor M1. Therefore, the fourth transistor M4 is supplied with a charging current I CHG Current I proportional to M4 The current mirror circuit 230 outputs a current I M4 The impedance circuit 232 is connected between the input terminal VIN and the output node of the current mirror circuit 230, and the current I M4 ', more specifically according to the current I M4 This generates a voltage drop ΔV which is positively correlated with

[0062] The first resistor R1 is a variable resistor, and its resistance value is determined by the voltage V N1 =V IN Specifically, the resistance of the first resistor R1 changes according to the voltage V N1 The capacitance varies in the range of Rc2 to Rc1 depending on the Rc2 <R1<Rc1

[0063] The switch SW1 is inserted between the source of the first transistor M1 and the input terminal VIN.

[0064] 4 shows a constant voltage feedback circuit 250 for the CV mode. A differential amplifier 252, a fifth transistor M5, and a phase compensation circuit 254 form the constant voltage feedback circuit 250 together with a constant current load CS3. A feedback terminal VFB is connected to the output voltage V OUT , that is, the feedback voltage V according to the voltage of the battery 102 FB For example, the feedback voltage V FB is the divided voltage of the battery.

[0065] The differential amplifier 252 detects the voltage VFB at the feedback terminal VFB. FB and the target reference voltage V REF(CV) The output of the error amplifier is connected to the gate of the fifth transistor M5. In CV mode, the battery voltage V OUT is the reference voltage V REF(CV) The target voltage V is determined according to OUT(REF) The charging current I CHG is controlled.

[0066] 4 includes a voltage balancing circuit 240. In the configuration of FIG. 2 where the voltage balancing circuit 240 is not provided, the drain voltage of the first transistor M1 is the battery voltage of the output terminal VOUT, while the drain voltage of the second transistor M2 is the voltage V ICHG , i.e. the reference voltage V REF(CC)As a result, the drain-source voltages of the first transistor M1 and the second transistor M2 become unbalanced, and the ratio A of the currents of the first transistor M1 and the second transistor M2 fluctuates. The fluctuation of the ratio A is caused by the charging current I CHG This leads to a decrease in accuracy.

[0067] 4 makes the drain voltage of the second transistor M2 close to the drain voltage of the first transistor M1, thereby making the drain-source voltage of the first transistor M1 and the drain-source voltage of the second transistor M2 equal to each other, and stabilizing the ratio A of the currents of the first transistor M1 and the second transistor M2. CHG can be controlled with high precision.

[0068] FIG. 5 is a circuit diagram showing a specific example of the configuration of the charging circuit 200 of FIG. 4. The impedance circuit 232 includes a P-type transistor 234 with a gate and drain connected, for example. In this example, two P-type transistors 234 are shown, but the number of P-type transistors 234 may be determined according to the voltage drop ΔV to be generated in the impedance circuit 232. The impedance circuit 232 may be configured with resistors, but in that case, the temperature characteristics of the resistance value and process variations will affect the zero position. On the other hand, if the impedance circuit 232 is configured with P-type transistors, more specifically, P-channel MOSFETs, the characteristics of the P-type transistor 234 will follow the characteristics of the other P-type transistors, and the zero position can be stabilized.

[0069] In this configuration example, the first resistor R1 includes a first resistive element R11, a second resistive element R12, and a P-type transistor M11. The second resistive element R12 and the P-type transistor M11 are connected in series between both ends of the first resistive element R11. A voltage V N1 is entered.

[0070] Charging current I CHG is small, in other words, the current setting resistor RI CHGWhen it is large, the current I flowing through the fourth transistor M4 M4 becomes small, and thus the voltage drop ΔV of the P-type transistor 234 is small, and V N1 ≒V IN is obtained. In this case, since the P-type transistor M11 is turned off, the resistance value Rc1 of the first resistor R1 becomes equal to the first resistor element R11. Rc1 = R11 The zero point at this time is located on the lowest frequency side.

[0071] The charging current I CHG When it is large, in other words, when the current setting resistor R ICHG is small, the current I flowing through the fourth transistor M4 M4 becomes large, and thus the voltage drop ΔV of the P-type transistor 234 becomes large. In this case, the gate-source voltage of the P-type transistor M11 becomes large and it enters the full-on state, so the resistance value Rc2 of the first resistor R1 becomes a parallel connection of the first resistor element R11 and the second resistor element R12. / / represents the combined resistance of parallel resistors. Rc2 = R11 / / R12 By reducing the resistance value of the first resistor R1, the zero point shifts to the high-frequency side.

[0072] That is, according to the configuration of FIG. 5, the resistance value of the first resistor R1 can be controlled within the range of Rc2 < R1 < Rc1, and the zero point can be shifted.

[0073] Here, adaptive phase compensation using the shift of the zero point has been described, but other methods can also be used.

[0074] FIG. 6 is a diagram for explaining adaptive phase compensation based on the decrease in loop gain. For simplicity, the Bode diagram of a two-stage amplifier is shown. The solid line shows the case when the second pole ω P2 is low, and the broken line shows the gain characteristics and phase characteristics when the second pole ω P2 is high. When adaptive phase compensation is not performed, the second pole ω P2When is high, at the unity gain frequency, the phase is rotated by 180° and oscillation occurs.

[0075] In contrast, in adaptive phase compensation based on the reduction of loop gain, the second pole ω 2P As the phase margin φ increases, the loop gain is reduced as shown by the dashed line. M can be secured.

[0076] 7 is a circuit diagram showing another example of the configuration of the charging circuit 200. In this example, the output of the current mirror circuit 230 is connected to the gate of the third transistor M3, and the current mirror circuit 230 outputs a charging current I CHG Current I proportional to M4 ' is sunk from the gate of the third transistor M3.

[0077] Fig. 8 is a circuit diagram showing a modification of the charging circuit 200 of Fig. 7. In this modification, the drain of the fourth transistor M4 is connected to the gate of the third transistor M3, and the charging current I CHG Current I proportional to M4 ' is sourced to the gate of the third transistor M3.

[0078] According to the configuration of FIG. 7 or FIG. 8, the charging current I CHG Depending on this, the gain of the second stage can be changed, and thus the loop gain can be changed.

[0079] 9 is a diagram showing another example of the configuration of the charging circuit 200. In the configuration examples shown in FIGS. 4, 5, 7, and 8, the fourth transistor M4 is used to reduce the charging current I CHG and copy the copied current I M4 9, a sense resistor Rs is inserted in series with the first transistor M1, and adaptive phase compensation is realized based on the voltage drop Vcs of the sense resistor Rs.

[0080] In this configuration example, similar to the configuration example in FIG. 5, the charging current I CHG The resistance value of the first resistor R1 is adaptively changed in response to the change.

[0081] The amplifier 260 includes resistors R21 and R22, a transistor M22, and a differential amplifier (error amplifier) ​​262. When an imaginary short occurs in the differential amplifier 262, the voltage drop Rs×I CHG The voltage drop R21 × Ia across resistor R21 is equal to the current Ia flowing through resistor R21. CHG is proportional to. Ia=I CHG ×Rs / R21

[0082] This current Ia flows through the transistor M22 and the resistor R22. Therefore, the output voltage Va of the amplifier 260 is expressed by the following equation, and the charging current I CHG is proportional to. Va=Ia×R22=I CHG ×Rs×R22 / R21

[0083] The resistance value of the first resistor R1 of the phase compensation circuit 214 is controlled in response to the voltage Va. This makes it possible to adaptively shift the pole position.

[0084] 10 is a circuit diagram showing another example of the configuration of the charging circuit 200. The differential amplifier 212 of the constant current feedback circuit 210 includes a differential input stage 216 and an amplification stage 218. The differential input stage 216 receives the voltage signal V ICHG_S and the reference voltage V REF(CC) The amplifier stage 218 is an emitter-common (or source-common) amplifier stage, and amplifies the differential output signal of the amplifier stage 218 in the preceding stage.

[0085] The constant current feedback circuit 210 controls the current I CHGThe output impedance of amplifier stage 218 may be configured to be variable depending on the input / output characteristics of amplifier stage 218. Common-emitter amplifier stage 218 includes a pair of common-emitter transistors Q41, Q42 and a collector load 219 connected to the collectors of the common-emitter transistors. In this example, the impedance (collector impedance) of collector load 219 of amplifier stage 218 is configured to be variable.

[0086] The collector load 219 includes transistors M41 to M43 that form a current mirror circuit, and a variable resistor R41. A fourth transistor M4 and an impedance circuit 232 are provided to control the resistance value of the variable resistor R41. The fourth transistor M4 is connected to the first transistor M1 via a charging current I CHG Current I proportional to M4 flows through the impedance circuit 232, and a current I M4 That is, the charging current I CHG A voltage drop ΔV proportional to the voltage V occurs. The resistance value of the variable resistor R41 changes according to the voltage drop ΔV.

[0087] The collector load of the transistor Q42 is the combined impedance of the transistors M42, M43 and the variable resistor R41. Therefore, the charging current I CHG As a result of the resistance value of the variable resistor R41 changing in response to this, the collector impedance of one of the differential outputs of the amplifier stage 218 changes, and the output impedance of the amplifier stage 218 changes.

[0088] In other words, when the charging current setting value is small, that is, when the resistance value of the current setting resistor R ICHG When the charging current is large, the resistance value of the variable resistor R41 is large, and as the charging current setting value increases, that is, the resistance value R of the current setting resistor ICHG As the charging current I CHG As this increases, the output impedance of the amplifier stage 218 increases, and the pole of the differential amplifier 212 moves to the low-frequency side. This ensures stability.

[0089] 11 is a circuit diagram showing another example of the configuration of the charging circuit 200. The differential amplifier 212 of the constant current feedback circuit 210 includes a differential input stage 216 and an amplification stage 218. The differential input stage 216 receives the voltage signal V ICHG_S and the reference voltage V REF(CC) The amplifier stage 218 is an emitter-common (or source-common) amplifier stage, and amplifies the differential output signal of the amplifier stage 218 in the preceding stage.

[0090] As in FIG. 10, the common-emitter amplifier stage 218 includes a pair of common-emitter transistors Q41 and Q42 and a collector load 219 connected to the collectors of the transistors. The constant current feedback circuit 210 controls the current I CHG The output impedance of the amplifier stage 218 is configured to be variable in response to the input.

[0091] In FIG. 11, the impedance (or transconductance) of the common-emitter transistor Q42 is CHG Since the output impedance of amplifier stage 218 is a combined resistance of the impedance and collector impedance of transistor Q42, the output impedance of amplifier stage 218 changes by changing the impedance of transistor Q42.

[0092] The common-emitter transistor Q42 includes transistors Q42a and Q42b and a variable resistor R42. When the resistance value of the variable resistor R42 changes, the transconductance gm, in other words, the impedance, of the common-emitter transistor Q42 changes.

[0093] In order to control the resistance value of the variable resistor R42, a fourth transistor M4, a current mirror circuit 230, and an impedance circuit 232 are provided. The operations of the fourth transistor M4, the current mirror circuit 230, and the impedance circuit 232 are similar to those in FIG.

[0094] According to the charging circuit 200 of FIG.CHG As this increases, the impedance of the transistor Q42, that is, the output impedance of the amplifier stage 218, increases, and the pole of the differential amplifier 212 moves to the low-frequency side. This ensures stability.

[0095] Fig. 12 is a diagram showing a configuration example of the charging circuit 200. In Fig. 12, the configuration related to adaptive phase compensation is omitted.

[0096] The CC / CV stabilization circuit 270 includes the third transistor M3, constant current load CS3, fifth transistor M5, and phase compensation circuits 214, 254 in FIG. 4, and controls the gate voltage of the first transistor M1 according to the output of the differential amplifier 212 or the output of the differential amplifier 252.

[0097] The controller 280 comprehensively controls the entire charging circuit 200. The reference voltage source 296 includes, for example, a bandgap reference circuit, and generates a reference voltage referenced by each block of the charging circuit 200.

[0098] The sixth transistor M6 has its gates and sources connected in common to the first transistor M1. The sixth transistor M6 has a charging current I CHG Current I proportional to M6 A current I M6 is the resistor R connected to the termination current setting terminal ITEM ITEM The charging current I CHG Voltage V proportional to ITEM The voltage V ITEM is input to a comparator 286 via a buffer 284. The comparator 286 outputs a voltage V ITEM is the threshold voltage V TH Compared with the charging current I CHG is the terminal current I TERM The controller 280 determines whether the charging current I CHG is the terminal current I TERM When it detects that the battery voltage has dropped to 0.5V, charging is stopped.

[0099] The overvoltage comparator 282 detects the voltage VFB at the feedback terminal VFB. FB to a threshold voltage to detect an over-voltage condition. If an over-voltage condition is detected, the controller 280 stops charging.

[0100] When the voltage of the recharge detection terminal VFBRE becomes lower than the threshold voltage, the recharge detection comparator 288 generates a trigger to start recharge. Once the controller 280 receives the trigger to start recharge after the charging is completed, it activates the CC / CV stabilization circuit 270 and starts recharge.

[0101] The oscillator 292 oscillates at a predetermined frequency to generate a clock signal. The controller 280 operates in synchronization with the clock signal CLK. For example, the controller 280 may include a timer 281.

[0102] The UVLO / TSD circuit 294 is IN It generates a trigger for undervoltage lockout depending on the input voltage and generates a trigger for thermal shutdown depending on the temperature.

[0103] The NTC terminal is connected to a thermistor 104 provided in close proximity to the battery 102. A comparator group 290 compares the voltage of the NTC terminal with different threshold voltages to determine the temperature state of the battery 102. The controller 280 can switch the operation state of the charging circuit 200 according to the output of the comparator group 290.

[0104] The LEDCNT terminal is connected to an external LED (light emitting diode) 106. The controller 280 controls the on / off state of the transistor M21 to control the on / off state of the LED 106.

[0105] The switch SW1 includes transistors M31 and M32. The controller 280 controls the gate voltage of the transistor M32 to switch the transistor M31 on and off.

[0106] The transistor M22 is connected to the VFBG pin and controlled by the controller 280. When the transistor M22 is on, the output voltage V OUT When the transistor M22 is off, the VFB and VFBRE terminals receive the output voltage V OUT is entered as is.

[0107] (Modification) The embodiment has been described above. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step, and that such modifications are also within the scope of the present invention. Such modifications will be described below.

[0108] In the embodiment, the resistance value of the resistor R1 of the phase compensation circuit 214 is variable, but the capacitance of the first capacitor C1 may be selected as a variable phase compensation parameter in the constant current feedback circuit 210. The capacitance of the first capacitor C1 is set to a value that is proportional to the charging current I CHG The capacitance may be configured as a variable capacitance that changes depending on the input voltage.

[0109] Alternatively, the first resistor R1 is a variable resistor, the first capacitor C1 is a variable capacitance, and both of them are connected to a charging current I CHG It may be changed depending on the

[0110] In FIG. 7 and FIG. 8, the gain of the second stage STG2 is changed, but the present disclosure is not limited to this. CHG It may be changed depending on the

[0111] Furthermore, when performing the adaptive gain control described with reference to FIGS. 6 to 8, the gain may be controlled according to the voltage drop Vs across the sense resistor Rs, rather than the current flowing through the fourth transistor M4.

[0112] In the above explanation, the transistors indicated as P-channel MOSFET and N-channel MOSFET can be replaced with PNP-type bipolar transistor and NPN-type bipolar transistor, respectively. In that case, the gate, source, and drain should be read as base, emitter, and collector.

[0113] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments without departing from the spirit of the present invention as defined in the claims. [Explanation of symbols]

[0114] VIN input terminal VOUT output terminal 100 Electronic equipment 102 Battery 200 charging circuit 210 Constant current feedback circuit 212 Differential Amplifier 214 Phase compensation circuit 216 Differential Input Stage 218 Amplification stage M1 First transistor M2 Second transistor M3 Third transistor CS3 constant current load M4 4th transistor R1 First resistor C1 First capacitor RICHG Current setting resistor 230 Current Mirror Circuit 232 Impedance Circuit 234 P-type transistor 240 Voltage balance circuit 250 Constant voltage feedback circuit 252 Differential Amplifier 254 Phase compensation circuit 260 Amplifier 280 Controller

Claims

1. An input terminal; An output terminal; a first transistor connected between the input terminal and the output terminal; a current setting terminal to which an external current setting resistor is to be connected; a second transistor connected between the input terminal and the current setting terminal and having a gate connected to a gate of the first transistor; a constant current feedback circuit that feedback controls a gate voltage of the first transistor so that a voltage of the current setting terminal approaches a reference voltage; Equipped with The charging circuit according to claim 1, wherein the constant current feedback circuit is configured such that a phase compensation parameter is variable in response to a current flowing through the first transistor.

2. The constant current feedback circuit includes: a third transistor having a first terminal connected to the input terminal and a second terminal connected to the gate of the first transistor; a constant current load connected between the second end of the third transistor and ground; a differential amplifier receiving the voltage of the current setting terminal and the reference voltage, and having an output node connected to a control terminal of the third transistor; 2. The charging circuit of claim 1, further comprising:

3. The constant current feedback circuit includes: a first resistor and a first capacitor connected in series between the control terminal and the second end of the third transistor; 3. The charging circuit according to claim 2, wherein at least one of a resistance value of the first resistor and a capacitance of the first capacitor is the variable phase compensation parameter.

4. The first resistor is A first resistance element; a series transistor and a second resistive element connected in series across the first resistive element; 4. The charging circuit according to claim 3, wherein the state of the series transistor changes in response to a current flowing through the first transistor.

5. The constant current feedback circuit includes: a third transistor having a first terminal connected to the input terminal and a second terminal connected to the gate of the first transistor; a constant current load connected between the second end of the third transistor and ground; a differential amplifier receiving the voltage of the current setting terminal and the reference voltage, and having an output node connected to a control terminal of the third transistor; a first resistive element and a first capacitor connected in series between the control terminal and the second end of the third transistor; a P-type transistor and a second resistive element connected in series across the first resistive element; a fourth transistor, the gates of which and the sources of which are commonly connected to the first transistor; a current mirror circuit having an input node connected to the fourth transistor and an output node connected to the P-type transistor; an impedance circuit connected between the input terminal and the output node of the current mirror circuit; 2. The charging circuit of claim 1, further comprising:

6. 6. The charging circuit according to claim 5, wherein the impedance circuit includes a P-type transistor having a gate and a drain connected together.

7. 3. The charging circuit according to claim 2, wherein the constant current feedback circuit supplies a current proportional to a current flowing through the first transistor to a control terminal of the third transistor.

8. 3. The charging circuit of claim 2, wherein the gain of the differential amplifier is the variable phase compensation parameter.

9. The differential amplifier is A differential input stage; an amplifier stage of a common emitter type or a common source type for amplifying an output of the differential input stage; Including, 3. The charging circuit according to claim 2, wherein the constant current feedback circuit is configured so that an output impedance of the amplifier stage is variable in response to a current proportional to a current flowing through the first transistor.

10. 10. The charging circuit according to claim 9, wherein a collector load or a drain load of the amplifier stage is configured to be variable.

11. 10. The charging circuit according to claim 9, wherein the impedance of the common-emitter transistor or the common-source transistor of the amplifier stage is variable.

12. The constant current feedback circuit includes: a fourth transistor having gates and sources commonly connected to the first transistor; 2. The charging circuit according to claim 1, wherein the phase compensation parameter of the constant current feedback circuit varies depending on the current of the fourth transistor.

13. The constant current feedback circuit includes: a sense resistor connected in series with the first transistor; 2. The charging circuit according to claim 1, wherein the phase compensation parameter of the constant current feedback circuit varies according to a voltage drop across the sense resistor.

14. 14. The charging circuit according to claim 1, further comprising a voltage balance circuit connected between the second transistor and the current setting terminal, the voltage balance circuit adjusting a voltage of one end of the second transistor to approach a voltage of the output terminal.

15. 15. The charging circuit according to claim 1, further comprising a constant voltage feedback circuit that feedback controls the gate voltage of the first transistor so that the voltage of the output terminal approaches a second reference voltage.

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