Overcurrent protection performance evaluation circuit, switching power supply, and overcurrent protection performance evaluation method

Abstract

To evaluate over-current protection performance with accuracy, without applying a large current or using a test pad.SOLUTION: An over-current protection performance evaluation circuit comprises a first transistor MP2, a second transistor MP3, and a test mode switching unit 10. In a first test mode, with a power transistor MP1 and the first transistor MP2 turned on and the second transistor MP3 turned off, the on-resistance of the power transistor MP1 is measured. In a second test mode, with the power transistor MP1 and the first transistor MP2 turned off and the second transistor MP3 turned on, the potential difference between a source and a drain of the power transistor MP1 is measured when an over-current protection circuit 4 activates over-current protection operation. Each measurement can be performed from terminals connected to the source and drain of the power transistor MP1, and performance evaluation is performed from the measurement results.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an overcurrent protection performance evaluation circuit, a switching power supply, and an overcurrent protection performance evaluation method. [Background technology]

[0002] Some switching power supplies with built-in power transistors are equipped with an overcurrent protection function that switches the power transistor off to suppress the current when the current flowing through the power transistor becomes excessive. There are roughly two types of overcurrent protection. One is a latch type that switches the power transistor off when the current flowing through the power transistor becomes excessive and keeps it off until it is restarted. The other is a pulse-by-pulse type that switches the power transistor off once when the current flowing through the power transistor becomes excessive, but then switches it on again in the next cycle and repeatedly determines whether the current flowing through the power transistor is excessive or not.

[0003] The overcurrent protection value that triggers the implementation of such an overcurrent protection operation varies depending on the specifications of the switching power supply, and the value can reach several amperes or more. In the shipping inspection of a switching power supply, such an overcurrent protection value is one of the evaluation targets as part of quality control, but depending on the inspection environment, there may be no equipment for applying a desired large current. In order to address such a problem, for example, Patent Document 1 discloses a technology related to a test method for evaluating the overcurrent protection value by simulating an overcurrent state in a semiconductor integrated circuit by using a test pad of a semiconductor integrated circuit that constitutes a switching power supply circuit. In this document, in a certain test mode, the drain voltage of the power transistor is changed while the power transistor is in an off state regardless of a PWM signal for performing a switching operation, and the drain voltage of the power transistor when the overcurrent protection operation becomes effective is measured by a monitor pad for monitoring the PWM signal. Furthermore, in another test mode, the on-resistance of the power transistor is measured, and the above-mentioned drain voltage is divided by the on-resistance to calculate the overcurrent protection value. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-254061 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the above Patent Document 1, when measuring the drain voltage for calculating the overcurrent protection value, a monitor pad is required, which increases the chip layout area of ​​the semiconductor integrated circuit. Also, if the number of external terminals of the package is limited depending on the product and test pads or monitor pads cannot be provided as external terminals of the package, it cannot be applied to shipping inspection after packaging.

[0006] At least one embodiment of the present disclosure has been made in consideration of the above-mentioned circumstances, and aims to provide an overcurrent protection performance evaluation circuit, a switching power supply, and an overcurrent protection performance evaluation method that are capable of evaluating overcurrent protection performance with high accuracy without applying a large current or using a test pad. [Means for solving the problem]

[0007] In order to solve the above problem, an overcurrent protection performance evaluation circuit according to at least one embodiment of the present disclosure includes: An overcurrent protection performance evaluation circuit for evaluating the overcurrent protection performance of an overcurrent protection circuit provided in a switching power supply having a built-in power transistor, comprising: The power transistor has a source connected to a first terminal and a drain connected to a second terminal, a first transistor having a gate connected to a gate of the power transistor so that an overcurrent detection current corresponding to a drain current of the power transistor flows; a second transistor having a source and a drain in common with the first transistor; a test mode switching unit for selectively switching between a first test mode and a second test mode for evaluating the overcurrent protection performance; Equipped with The test mode switching unit receives, from the first terminal and the second terminal, in the first test mode, the power transistor and the first transistor are turned on and the second transistor is turned off, so that an on-resistance of the power transistor can be measured; In the second test mode, the power transistor and the first transistor are turned off and the second transistor is turned on, making it possible to measure a potential difference between the source and drain of the power transistor at which an overcurrent protection operation is initiated by the overcurrent protection circuit.

[0008] In order to solve the above problems, a switching power supply according to at least one embodiment of the present disclosure has: The device includes an overcurrent protection performance evaluation circuit according to at least one embodiment of the present disclosure.

[0009] In order to solve the above problem, at least one embodiment of the present disclosure provides an overcurrent protection performance evaluation method, An evaluation method using an overcurrent protection performance evaluation circuit for evaluating the overcurrent protection performance of an overcurrent protection circuit provided in a switching power supply having a built-in power transistor, comprising: The overcurrent protection performance evaluation circuit includes a first transistor configured to allow an overcurrent detection current corresponding to a drain current of the power transistor having a source connected to a first terminal and a drain connected to a second terminal to flow therethrough, and a second transistor having a source and a drain in common with the first transistor; Equipped with executing a first test mode in which the power transistor and the first transistor are turned on and the second transistor is turned off, and an on-resistance of the power transistor is measured from the first terminal and the second terminal; a step of executing a second test mode in which the power transistor and the first transistor are turned off and the second transistor is turned on, and a potential difference between a source and a drain of the power transistor at which an overcurrent protection operation is activated in the overcurrent protection circuit is measured from the first terminal and the second terminal; calculating an overcurrent protection value of the overcurrent protection circuit by dividing the potential difference by the on-resistance; Equipped with. Effect of the Invention

[0010] According to at least one embodiment of the present disclosure, it is possible to provide an overcurrent protection performance evaluation circuit, a switching power supply, and an overcurrent protection performance evaluation method that are capable of evaluating overcurrent protection performance with high accuracy without applying a large current or using a test pad. [Brief description of the drawings]

[0011] [Figure 1] 1 is a circuit diagram of a switching power supply circuit according to an embodiment of the present invention; [Diagram 2] 5 is a flowchart illustrating a method for calculating an overcurrent protection value according to an embodiment. [Diagram 3] 4 is a time chart showing the operating states of each part of the switching power supply circuit when switched from a normal mode to a first test mode. [Figure 4] 5 is a time chart showing the operating states of each part of the switching power supply circuit when switched from a normal mode to a second test mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, some embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of components described as the embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure.

[0013] 1 is a circuit diagram of a switching power supply circuit 1 according to one embodiment. The switching power supply circuit 1 is configured as a circuit capable of supplying power to a load at a predetermined voltage by switching a power transistor MP1 based on a signal from a driver circuit 2, and can be configured as a semiconductor integrated circuit, either in a chip state or after packaging.

[0014] The power transistor MP1 has a source connected to a V+ terminal (first terminal) which is a high potential power supply terminal, a drain connected to an SW terminal (second terminal) which is an output terminal, and a gate connected to the driver circuit 2. The transistor MP2 (first transistor) constituting the overcurrent protection circuit 4 is an overcurrent detection transistor made of a PMOS transistor, and has a source connected to an overcurrent detection resistor R SENSE The comparator COMP1 has an inverting input terminal connected to the source of the transistor MP2 and a non-inverting input terminal connected to the reference voltage source V ROCP is connected to

[0015] The overcurrent protection circuit 4 is configured to detect the current flowing between the source and drain of the power transistor MP1, which is driven by a signal from the driver circuit 2, by replacing it with the current of the transistor MP2. SENSE If the current flowing through the transistor MP2 is I2, the voltage VR1 generated across both ends is expressed by the following equation: VR1 = I2 × R SENSE (1) Here, R SENSE is the overcurrent detection resistor R SENSE is the resistance value.

[0016] The comparator COMP1 is connected to the voltage VR1 expressed by equation (1) and the reference voltage source V ROCP The comparator COMP1 compares the reference voltage V ... ROCP The current value corresponding to the voltage (overcurrent protection value I LIMIT ) is restricted to

[0017] The switching power supply circuit 1 is configured to be able to evaluate the overcurrent protection performance of the overcurrent protection circuit 4 configured as described above. In this embodiment, the overcurrent protection performance of the overcurrent protection circuit 4 is evaluated using an overcurrent protection value I LIMIT Specifically, the switching power supply circuit 1 calculates the overcurrent protection value I LIMIT The test mode switching unit 10 is provided for switching a test mode for performing parameter measurement necessary for calculating the above.

[0018] The test mode switching unit 10 is a circuit for switching between a normal mode in which the switching power supply circuit 1 can normally operate and at least one test mode. In this embodiment, a first test mode and a second test mode are provided as the test modes. The details of each test mode will be described later. In the first test mode, the ON resistance RON of the power transistor MP1 is changed by a factor of 1. MP1The first test mode is a test mode for measuring the potential difference VM2 between the V+ terminal V+ and the SW terminal when the output of the overcurrent protection circuit 4 switches from Low to High.

[0019] A test mode signal for selectively switching the test mode implemented in the switching power supply circuit 1 is input to the test mode switching unit 10. In this embodiment, a first test mode signal TMS1 corresponding to the first test mode and a second test mode signal TMS2 corresponding to the second test mode are respectively input to the test mode switching unit 10 as the test mode signal. The test mode switching unit 10 can switch the circuit configuration corresponding to the normal mode, the first test mode, and the second test mode according to the input states of the first test mode signal TMS1 and the second test mode signal TMS2. Specifically, when the first test mode signal TMS1 and the second test mode signal TMS2 are both Low, the normal mode is selected, when the first test mode signal TMS1 is High and the second test mode signal TMS2 is Low, the first test mode is selected, and when both the first test mode signal TMS1 and the second test mode signal TMS2 are High, the second test mode is selected.

[0020] Such a test mode switching unit 10 includes a transistor MP3 (second transistor). The source of the transistor MP3 is connected to the source of the transistor MP2, the drain of the transistor MP2, and the gate of the transistor MP3 is connected to the output terminal of the NAND circuit M8. The transistor MP3 is a PMOS transistor having approximately the same W / L size as the above-mentioned transistor MP2.

[0021] The circuit configuration of the test mode switching unit 10 shown in FIG. 1 is an example, and the design can be appropriately changed as long as the same functions can be realized.

[0022] Here, the overcurrent protection value I LIMITis the current flowing through the power transistor MP1 when the drain current of the power transistor MP1 is increased and the output of the overcurrent protection circuit 4 changes from low to high, thereby activating the overcurrent protection operation. In the normal mode, the transistor MP3 is in the off state, so that the on-resistance of the transistor MP3 is sufficiently large. The overcurrent protection value I LIMIT is expressed as follows: As shown in equation (2), the overcurrent protection value I LIMIT is the on-resistance RON of the power transistor MP1 MP1 and can be calculated using a potential difference VM2 between the V+ terminal and the SW terminal when the output of the overcurrent protection circuit 4 switches from Low to High, which are measured in each test mode as described later.

[0023] FIG. 2 shows an example of an overcurrent protection value I LIMIT In this method, the first test mode is executed to calculate the on-resistance RON of the power transistor MP1. MP1 In the first test mode executed in step S1, the on-resistance RON of the power transistor MP1 is measured with the power transistors MP1 and MP2 in the on-state and the transistor MP3 in the off-state. MP1 Measurements are taken.

[0024] In the subsequent second test mode, the voltage difference VM2 between the V+ terminal and the SW terminal when the output of the overcurrent protection circuit 4 switches from Low to High is measured (step S2). In the second test mode executed in step S2, the voltage VM2 is measured when the output of the overcurrent protection circuit 4 switches from Low to High with the power transistor MP1 and the transistor MP2 in the OFF state and the transistor MP3 in the ON state.

[0025] Then, the on-resistance RON measured in step S1 MP1Using the potential difference VM2 measured in step S2, the overcurrent protection value I LIMIT is calculated (step S3).

[0026] In FIG. 2, the case where the second test mode is executed after the first test mode is described. In this case, the on-resistance RON of the power transistor MP1 is MP1 Since heat is generated by passing a current to measure the temperature, it is preferable to perform a sufficient cool-down before performing the subsequent second test mode. In another embodiment, the second test mode may be performed before the first test mode, in which case the above-mentioned cool-down is not necessary, which is advantageous for shortening the evaluation time.

[0027] Next, the operation of each part of the switching power supply circuit 1 when the test mode switching unit 10 switches the test mode will be described. Fig. 3 is a time chart showing the operating state of each part of the switching power supply circuit 1 when switching from the normal mode to the first test mode. In Fig. 3, the mode is switched at time t1, and the normal mode is performed before time t1, and the first test mode is performed after time t1.

[0028] In the normal mode before time t1, the first test mode signal TMS1 and the second test mode signal TMS2 are both Low, and the oscillator 12 included in the switching power supply circuit 1 outputs a BLK signal, a MAXD signal, and a CLOCK signal synchronized with the oscillation frequency fosc. The CLOCK signal changes from Low to High at the same time that the BLK signal changes from Low to High, and also switches from High to Low at the same time that the MAXD signal changes from Low to High.

[0029] The CLOCK signal is input from the oscillator 12 to the slope compensation circuit 14. The slope compensation circuit 14 outputs a sawtooth signal that increases at a constant rate of change while the CLOCK signal is High and is Low while the CLOCK signal is Low.

[0030] The output voltage of the switching power supply circuit 1 is input as a feedback signal from the FB terminal to the inverting input terminal of the error amplifier M1. A reference voltage source VREF is connected to the non-inverting input terminal of the error amplifier M1, and the error amplifier M1 amplifies and outputs the difference between the feedback voltage from the FB terminal and the reference voltage source VREF. The output terminal of the error amplifier M1 is connected to the non-inverting input terminal (+ input) of the comparator M2. An adder 16 is connected to the inverting input terminal (- input) of the comparator M2. The adder 16 adds the sawtooth wave signal from the slope compensation circuit 14 and a signal proportional to the current flowing through the power transistor MP1. The comparator M2 compares the signal amplified by the error amplifier M1 with the signal added by the adder 16, and outputs High when the amplified signal from the error amplifier M1 is greater than the input from the adder 16, and outputs Low when the amplified signal from the error amplifier M1 is smaller than the input from the adder 16.

[0031] The NOR circuit M3 is a circuit for holding the output signal low even if the output signal of the comparator M2 goes low while the BLK signal from the oscillator 12 is high. In the normal mode before time t1, the first test mode signal is low, so that the same signal as the output signal of the NOR circuit M3 is input to the R input of the flip-flop circuit RSFF1. In the flip-flop circuit RSFF1, when the BLK signal, which is the S input signal from the oscillator 12, goes from low to high, the QB signal goes from high to low, and when the R input signal goes from low to high, the QB signal goes from low to high.

[0032] In addition, in normal mode before time t1, the current flowing through the power transistor MP1 is the overcurrent protection value I LIMITSince the value of the second test mode signal does not exceed 1, the output of the overcurrent protection circuit 4 remains low, and the Q output of the flip-flop circuit RSFF2 also remains low. The gate voltage of the power transistor MP1 is the same as the QB output signal of the flip-flop circuit RSFF1, and when it is low, the power transistor MP1 and the transistor MP2 are in the on state, and when it is high, they are in the off state. In the normal mode, the second test mode signal is low, and the gate voltage of the transistor MP3 is always high, so that it is always in the off state.

[0033] When the normal mode is switched to the first test mode at time t1, the first test mode signal goes from low to high (at this time the second test mode signal remains low). When the first test mode signal goes high, the R input signal of the flip-flop circuit RSFF1 is held low regardless of the output of the circuit M3. The QB output signal of the flip-flop circuit RSFF1 goes from high to low when the BLK signal goes from low to high, and is held low while the R input signal of the flip-flop circuit RSFF1 remains low. This holds the power transistor MP1 in the on state.

[0034] On the other hand, the transistor MP3 is maintained in the off state because the second test mode signal remains low. In the first test mode, in this state, a current source (not shown) is connected to the SW terminal, which does not affect normal operation, and a current IM1 is caused to flow from the SW terminal to the ground point. At this time, when the voltage VM1 between the V+ terminal and the SW terminal is measured, the on-resistance RON of the power transistor MP1 is MP1 is expressed as follows: Can be derived from TIFF0007636266000002.tif10170.

[0035] In this way, in the first test mode, the test mode switching unit 10 switches the power transistors MP1 and MP2 on and the transistor MP3 off, and the overcurrent protection value I LIMITThe on-resistance RON of the power transistor MP1 required to calculate MP1 can be sought.

[0036] Next, Fig. 4 is a time chart showing the operating states of each part of the switching power supply circuit 1 when the normal mode is switched to the second test mode. In Fig. 4, the mode is switched at time t2, and the normal mode is performed before time t2, and the second test mode is performed after time t2.

[0037] In the second test mode, both the first test mode signal TMS1 and the second test mode signal TMS2 input to the test mode switching unit 10 become High. At this time, the output of the OR circuit M7 is always High regardless of the output of the OR circuit M6, and the gate voltages of the power transistor MP1 and the transistor MP2 are High, so that the power transistor MP1 and the transistor MP2 are always in the off state.

[0038] When the first test mode signal TMS1 goes High, the R input of the flip-flop circuit RSFF1 remains Low regardless of the output of the OR circuit M3. Similarly, the R input of the flip-flop circuit RSFF2 also remains Low. The QB output of the flip-flop circuit RSFF1 changes from High to Low when the BLK signal changes from Low to High, and remains Low while the R input of the flip-flop circuit RSFF1 remains Low. When no current flows through the SW terminal, the output of the overcurrent protection circuit 4 becomes Low, and the Q output of the flip-flop circuit RSFF2 remains Low. When the QB output of the flip-flop circuit RSFF1 is Low and the Q output of the flip-flop circuit RSFF2 is Low, the output of the OR circuit M6 becomes Low. At this time, the output of the NAND circuit M8 becomes Low, and the transistor MP3 becomes ON.

[0039] In the second test mode, in this state, a voltage source (not shown) is connected to the SW terminal, and the voltage of the voltage source is gradually decreased from the voltage of the V+ terminal. Then, the negative input voltage (the voltage of the inverting input terminal of the comparator COMP1) to the overcurrent protection circuit 4 gradually decreases, and at the timing when it falls below the positive input voltage (the voltage of the non-inverting input terminal of the comparator COMP1) (see time t3 in FIG. 4), the output of the overcurrent protection circuit 4 changes from Low to High. Accordingly, the Q output of the flip-flop circuit RSFF2 also changes from Low to High. At the same time, the output of the OR circuit M6 also changes from Low to High, so that the gate voltage of the transistor MP3 becomes High and the transistor is turned off. As a result, the current IM becomes zero, and the voltage difference VM2 between the V+ terminal and the SW terminal at this timing is measured.

[0040] In this way, in the second test mode, the test mode switching unit 10 turns off the power transistor MP1 and the transistor MP2 and turns on the transistor MP3, thereby making it possible to measure the potential difference VM2. The potential difference VM2 measured in this way is calculated based on the on-resistance RON measured in the first test mode described above. MP1 By applying this to the above formula (2), the overcurrent protection value I LIMIT can be sought.

[0041] As described above, according to the embodiment, the first test mode and the second test mode are executed to obtain the overcurrent protection value I LIMIT Therefore, it is possible to accurately derive the overcurrent protection value I without passing current or using a test pad. LIMIT can be evaluated.

[0042] In addition, within the scope of the present disclosure, the components in the above-described embodiments may be replaced with well-known components as appropriate, and the above-described embodiments may be combined as appropriate.

[0043] The contents described in each of the above embodiments can be understood, for example, as follows.

[0044] (1) An overcurrent protection performance evaluation circuit according to one embodiment includes: An overcurrent protection performance evaluation circuit for evaluating the overcurrent protection performance of an overcurrent protection circuit (e.g., the overcurrent protection circuit 4 of the above embodiment) provided in a switching power supply (e.g., the switching power supply circuit 1 of the above embodiment) incorporating a power transistor (e.g., the power transistor MP1 of the above embodiment), The power transistor has a source connected to a first terminal (e.g., the V+ terminal in the above embodiment) and a drain connected to a second terminal (e.g., the SW terminal in the above embodiment), a first transistor (e.g., the transistor MP2 in the above embodiment) having a gate connected to the gate of the power transistor so that an overcurrent detection current corresponding to a drain current of the power transistor flows; A second transistor (e.g., the transistor MP3 in the above embodiment) that shares a source and a drain with the first transistor; a test mode switching unit (e.g., the test mode switching unit 10 in the above embodiment) for selectively switching between a first test mode and a second test mode for evaluating the overcurrent protection performance; Equipped with The test mode switching unit receives, from the first terminal and the second terminal, In the first test mode, the power transistor and the first transistor are turned on and the second transistor is turned off, and the on-resistance of the power transistor (for example, the on-resistance RON MP1 ) can be measured, In the second test mode, the power transistor and the first transistor are turned off and the second transistor is turned on, making it possible to measure a potential difference between the source and drain of the power transistor (e.g., the potential difference VM2 in the above embodiment) at which an overcurrent protection operation is triggered in the overcurrent protection circuit.

[0045] According to the above aspect (1), the first test mode is executed to measure the on-resistance of the power transistor from the first terminal and the second terminal, and the second test mode is executed to measure the source-drain potential difference of the power transistor at which the overcurrent protection operation is triggered in the overcurrent protection circuit from the first terminal and the second terminal. As a result, the overcurrent protection value of the overcurrent protection circuit can be obtained in a pseudo manner without using a test pad, and the overcurrent protection performance can be evaluated simply and accurately.

[0046] (2) In another embodiment, in the above embodiment (1), In the second test mode, the potential difference between the source and drain of the power transistor is Gradual expansion and measuring the potential difference when the overcurrent protection circuit performs the overcurrent protection operation.

[0047] According to the above aspect (2), in the second test mode, the power transistor and the first transistor are turned off and the second transistor is turned on, while the potential difference between the source and drain of the power transistor is Gradual expansion While this is being done, the potential difference can be measured when the overcurrent protection circuit triggers overcurrent protection operation.

[0048] (3) In another embodiment, in the above embodiment (1) or (2), In the second test mode, if the overcurrent protection circuit operates, the second transistor is latched in an off state.

[0049] According to the above aspect (3), by latching the second transistor in the off state when the overcurrent protection circuit operates, it is possible to suitably measure the potential difference when the overcurrent protection operation is triggered by the overcurrent protection circuit in the second test mode.

[0050] (4) In another embodiment, in any one of the above (1) to (3), The second transistor has the same size W (gate width) / L (gate length) as the first transistor.

[0051] According to the above aspect (4), the on-resistances of the transistors MP2 and MP3 are equal, so that the voltage VM2 measured in the second test mode is equal to the voltage at which the output of the overcurrent protection circuit 4 switches from low to high due to the current flowing between the source and drain of the transistor MP2 during the second normal operation. LIMIT can be sought.

[0052] (5) A switching power supply according to one embodiment comprises: The device includes an overcurrent protection performance evaluation circuit according to any one of the above aspects (1) to (4).

[0053] According to the above aspect (5), by including the overcurrent protection performance evaluation circuit having the above configuration, the overcurrent protection performance of the switching power supply can be evaluated simply and accurately.

[0054] (6) A method for evaluating overcurrent protection performance according to one embodiment includes the steps of: An evaluation method using an overcurrent protection performance evaluation circuit for evaluating overcurrent protection performance of an overcurrent protection circuit (e.g., the overcurrent protection circuit 4 of the above embodiment) included in a switching power supply (e.g., the switching power supply circuit 1 of the above embodiment) incorporating a power transistor (e.g., the power transistor MP1 of the above embodiment), comprising: The overcurrent protection performance evaluation circuit includes a first transistor (e.g., the transistor MP2 in the above embodiment) configured to allow an overcurrent detection current corresponding to a drain current of the power transistor having a source connected to a first terminal (e.g., the V+ terminal in the above embodiment) and a drain connected to a second terminal (e.g., the SW terminal in the above embodiment) to flow, and a second transistor (e.g., the transistor MP3 in the above embodiment) sharing a source and a drain with the first transistor, Equipped with The power transistor and the first transistor are turned on, and the second transistor is turned off, so that the on-resistance of the power transistor (for example, the on-resistance RON MP1 ) from the first terminal and the second terminal; and executing a second test mode in which the power transistor and the first transistor are turned off and the second transistor is turned on, and a potential difference between the source and drain of the power transistor at which an overcurrent protection operation is initiated in the overcurrent protection circuit (e.g., the potential difference VM2 in the above embodiment) is measured from the first terminal and the second terminal; calculating an overcurrent protection value of the overcurrent protection circuit by dividing the potential difference by the on-resistance; Equipped with.

[0055] According to the above aspect (6), the first test mode is executed to measure the on-resistance of the power transistor, and the second test mode is executed to measure the source-drain potential difference of the power transistor at which the overcurrent protection operation is triggered in the overcurrent protection circuit. As a result, the overcurrent protection value, which is an index for quantitatively evaluating the overcurrent protection performance of the overcurrent protection circuit, can be obtained in a pseudo manner without using a test pad, thereby making it possible to simply and accurately evaluate the overcurrent protection performance. [Explanation of symbols]

[0056] 1. Switching power supply circuit 2 Driver circuit 4 Overcurrent protection circuit 10 Test mode switching section 12 Oscillators 14 Slope compensation circuit 16 Adder I LIMIT Overcurrent Protection Value TMS1 First test mode signal TMS2 Second test mode signal R SENSE Overcurrent detection resistor

Claims

1. An overcurrent protection performance evaluation circuit for evaluating the overcurrent protection performance of an overcurrent protection circuit provided in a switching power supply having a built-in power transistor, comprising: The power transistor has a source connected to a first terminal and a drain connected to a second terminal, a first transistor having a gate connected to a gate of the power transistor so that an overcurrent detection current corresponding to a drain current of the power transistor flows; a second transistor having a source and a drain in common with the first transistor; a test mode switching unit for selectively switching between a first test mode and a second test mode for evaluating the overcurrent protection performance; Equipped with The test mode switching unit receives, from the first terminal and the second terminal, in the first test mode, the power transistor and the first transistor are turned on and the second transistor is turned off, so that an on-resistance of the power transistor can be measured; an overcurrent protection performance evaluation circuit for evaluating a voltage difference between a source and a drain of the power transistor at which an overcurrent protection operation is activated in the overcurrent protection circuit by turning off the power transistor and the first transistor and turning on the second transistor in the second test mode.

2. 2. The overcurrent protection performance evaluation circuit according to claim 1, wherein in the second test mode, a potential difference between a source and a drain of the power transistor is gradually increased, and the potential difference is measured when the overcurrent protection operation by the overcurrent protection circuit is activated.

3. 3. The overcurrent protection performance evaluation circuit according to claim 1, configured to latch the second transistor in an off state when the overcurrent protection circuit operates in the second test mode.

4. 4 . The overcurrent protection performance evaluation circuit according to claim 1 , wherein the second transistor has the same W / L size as the first transistor.

5. A switching power supply comprising the overcurrent protection performance evaluation circuit according to claim 1 .

6. An evaluation method using an overcurrent protection performance evaluation circuit for evaluating the overcurrent protection performance of an overcurrent protection circuit provided in a switching power supply having a built-in power transistor, comprising: The overcurrent protection performance evaluation circuit includes a first transistor configured to allow an overcurrent detection current corresponding to a drain current of the power transistor having a source connected to a first terminal and a drain connected to a second terminal to flow therethrough, and a second transistor having a source and a drain in common with the first transistor; Equipped with executing a first test mode in which the power transistor and the first transistor are turned on and the second transistor is turned off, and an on-resistance of the power transistor is measured from the first terminal and the second terminal; a step of executing a second test mode in which the power transistor and the first transistor are turned off and the second transistor is turned on, and a potential difference between a source and a drain of the power transistor at which an overcurrent protection operation is activated in the overcurrent protection circuit is measured from the first terminal and the second terminal; calculating an overcurrent protection value of the overcurrent protection circuit by dividing the potential difference by the on-resistance; The method for evaluating overcurrent protection performance comprises:

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