Data receiving circuit, data receiving system and storage device

Abstract

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, the data receiving circuit including a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal, a decision feedback control module configured to generate a second sampling clock signal in response to an enable signal, a decision feedback equalization module configured to perform decision feedback equalization in response to the second sampling clock signal and the feedback signal during a period when the enable signal has a first level value, and stop performing the decision feedback equalization during a period when the enable signal has a second level value, and a second amplification module configured to process the first voltage signal and the second voltage signal, and output a first output signal and a second output signal. The embodiments of the present disclosure are advantageous in reducing the power consumption of the data receiving circuit while improving at least the receiving performance of the data receiving circuit.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on June 23, 2022, bearing application number 202210726556.3 and entitled "Data Receiving Circuit, Data Receiving System, and Storage Device", the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. [Background technology]

[0003] In memory applications, as the signal transmission speed becomes faster and faster, the impact of channel loss on the signal quality becomes greater and the inter-symbol interference becomes more likely to occur. At present, an equalization circuit is usually used to compensate the channel, and the equalization circuit can be selected as a continuous time linear equalizer (CTLE) or a decision feedback equalizer (DFE).

[0004] Although the signal can be compensated for by adding an equalization circuit, adding an equalization circuit to the data receiving circuit increases the power consumption of the entire data receiving circuit. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device that are advantageous in reducing the power consumption of the data receiving circuit while improving at least the receiving performance of the data receiving circuit. [Means for solving the problem]

[0006] According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a data receiving circuit, the data receiving circuit including: a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal via a first node and a second node, respectively; a decision feedback control module configured to generate a second sampling clock signal in response to an enable signal; a decision feedback equalization module connected to the first node and the second node, configured to perform decision feedback equalization based on a feedback signal in response to the second sampling clock signal to adjust the first voltage signal and the second voltage signal during a period when the enable signal has a first level value, and stop performing decision feedback equalization during a period when the enable signal has a second level value, the feedback signal being obtained based on previously received data; and a second amplification module configured to perform an amplification process on a voltage difference between the first voltage signal and the second voltage signal, and output a first output signal and a second output signal via a third node and a fourth node, respectively.

[0007] In some embodiments, the first amplification module includes a first current source connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to the first sampling clock signal; and a comparison unit connected to the fifth node, the first node, and the second node and configured to receive the data signal and the reference signal, compare the data signal and the reference signal when the first current source supplies a current to the fifth node in response to the first sampling clock signal, and output the first voltage signal via the first node and output the second voltage signal via the second node.

[0008] In some embodiments, the first current source includes a first PMOS transistor coupled between the power supply node and the fifth node, a gate of the first PMOS transistor receiving the first sampling clock signal.

[0009] In some embodiments, the comparison unit includes: a third PMOS transistor connected between the fifth node and the first node, where a gate of the third PMOS transistor receives the data signal; and a fourth PMOS transistor connected between the fifth node and the second node, where a gate of the fourth PMOS transistor receives the reference signal.

[0010] In some embodiments, the first amplification module further includes a first reset unit coupled to the first node and the second node and configured to reset the first node and the second node.

[0011] In some embodiments, the first reset unit includes: a first NMOS transistor coupled between the first node and a ground terminal, where a gate of the first NMOS transistor receives the first sampling clock signal; and a second NMOS transistor coupled between the second node and the ground terminal, where a gate of the second NMOS transistor receives the first sampling clock signal.

[0012] In some embodiments, the feedback signal includes a first feedback signal and a second feedback signal that are differential signals with respect to each other, and the decision feedback equalization module includes: a second current source connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the second sampling clock signal; a first decision feedback unit connected to the first node and the sixth node and configured to perform decision feedback equalization on the first node based on the first feedback signal to adjust the first voltage signal when the second current source supplies a current to the sixth node in response to the second sampling clock signal; and a second decision feedback unit connected to the second node and the sixth node and configured to perform decision feedback equalization on the second node based on the second feedback signal to adjust the second voltage signal when the second current source supplies a current to the sixth node in response to the second sampling clock signal.

[0013] In some embodiments, the second current source includes a second PMOS transistor coupled between the power supply node and the sixth node, a gate of the second PMOS transistor receiving the second sampling clock signal.

[0014] In some embodiments, either the first decision feedback unit or the second decision feedback unit includes a switch unit configured to make the sixth node and the seventh node conductive in response to the feedback signal, and an adjustment unit connected between the seventh node and an output node and configured to adjust a magnitude of an equivalent resistance value between the seventh node and the output node in response to a control signal, the output node being one of the first node and the second node, in the first decision feedback unit, the feedback signal is the first feedback signal, the output node is the first node, and the switch unit is responsive to the first feedback signal, and in the second decision feedback unit, the feedback signal is the second feedback signal, the output node is the second node, and the switch unit is responsive to the second feedback signal.

[0015] In some embodiments, the switch unit includes a fifth PMOS transistor connected between the sixth node and the seventh node, a gate of the fifth PMOS transistor receiving the feedback signal.

[0016] In some embodiments, the adjustment unit includes a plurality of transistor groups connected in parallel between the seventh node and the output node, the control signals received by control terminals of different transistor groups are different, and equivalent resistance values ​​of different transistor groups are different.

[0017] In some embodiments, the different transistor groups include: at least one of the transistor groups consists of a single MOS transistor; and at least one of the transistor groups includes at least two MOS transistors connected in series.

[0018] In some embodiments, the second amplification module includes an input unit connected to the first node and the second node and configured to compare the first voltage signal and the second voltage signal and provide a third voltage signal and a fourth voltage signal to an eighth node and a ninth node, respectively, and a latch unit configured to perform amplification and latching on the third voltage signal and the fourth voltage signal, and output the first output signal to the third node and the second output signal to the fourth node.

[0019] In some embodiments, the input unit includes: a third NMOS transistor connected between the eighth node and a ground terminal, where a gate of the third NMOS transistor receives the first voltage signal; and a fourth NMOS transistor connected between the ninth node and the ground terminal, where a gate of the fourth NMOS transistor receives the second voltage signal.

[0020] In some embodiments, the latch unit includes a fifth NMOS transistor connected between the eighth node and the third node, the gate of the fifth NMOS transistor receiving the second output signal; a sixth NMOS transistor connected between the ninth node and the fourth node, the gate of the sixth NMOS transistor receiving the first output signal; a sixth PMOS transistor connected between a power supply node and the third node, the gate of the sixth PMOS transistor receiving the second output signal; and a seventh PMOS transistor connected between the power supply node and the fourth node, the gate of the seventh PMOS transistor receiving the first output signal.

[0021] In some embodiments, the second amplification module further includes a second reset unit coupled to the latch unit and configured to reset the latch unit.

[0022] In some embodiments, the second reset unit includes an eighth PMOS transistor connected between a power supply node and the third node, and a ninth PMOS transistor connected between the power supply node and a fourth node, and a gate of the eighth PMOS transistor and a gate of the ninth PMOS transistor are both responsive to a third sampling clock signal.

[0023] In some embodiments, the decision feedback control module includes a NAND gate circuit, one input terminal of which receives a fourth sampling clock signal, another input terminal of which receives the enable signal, and an output terminal of which outputs the second sampling clock signal.

[0024] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a data receiving system, the data receiving system including a plurality of cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described above and a latch circuit connected to the data receiving circuit, each of the data receiving circuits being connected to a data port to receive the data signal, the data transmission circuit of a previous stage being connected to the decision feedback equalization module of the data transmission circuit of a next stage, the output of the data transmission circuit of the previous stage being used as the feedback signal of the decision feedback equalization module of the data transmission circuit of the next stage, the data transmission circuit of a final stage being connected to the decision feedback equalization module of the data transmission circuit of a first stage, and the output of the data transmission circuit of the final stage being used as the feedback signal of the decision feedback equalization module of the data transmission circuit of the first stage.

[0025] According to some embodiments of the present disclosure, yet another aspect of the embodiments of the present disclosure further provides a storage device, the storage device including a plurality of data ports and a plurality of data receiving systems as described in any one of the preceding paragraphs, each of the data receiving systems corresponding to one of the data ports.

[0026] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0027] The decision feedback control module and the decision feedback equalization module are integrated into the data receiving circuit, and the decision feedback control module is used to generate a second sampling clock signal for controlling the decision feedback equalization module, so as to flexibly control whether the decision feedback equalization module is in an operating state. For example, only when the enable signal is in a first level value period, the decision feedback equalization module performs decision feedback equalization to improve the receiving performance of the data receiving circuit, and when the enable signal is in a second level value period, the decision feedback equalization module stops performing decision feedback equalization, i.e., the decision feedback equalization module is in a non-operating state, so as to reduce the power consumption of the entire data receiving circuit.

[0028] Here, compared with the related art in which the first output signal and the second output signal are adjusted by the decision feedback equalization module to reduce the impact of inter-symbol interference on data reception, and the storage device reduces inter-symbol interference by separately installing a decision feedback equalization equalizer, the embodiment of the present disclosure is advantageous in realizing the adjustment to the signal output by the data receiving circuit using a smaller circuit layout area and lower power consumption, and by flexibly controlling the adjustment capability of the decision feedback equalization module for the first output signal and the second output signal, the impact of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit is reduced, thereby improving the receiving performance of the data receiving circuit, and reducing the impact of inter-symbol interference on the accuracy of the signal output by the data receiving circuit. [Brief description of the drawings]

[0029] [Figure 1] FIG. 2 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a functional block diagram of a data receiving system according to another embodiment of the present disclosure. [Diagram 3] 11A to 11C are other two functional block diagrams of a data receiving circuit according to an embodiment of the present disclosure. [Figure 4] 11A to 11C are other two functional block diagrams of a data receiving circuit according to an embodiment of the present disclosure. [Diagram 5] 2 is a schematic diagram of a circuit structure of a data receiving circuit according to an embodiment of the present disclosure. [Figure 6] 4A and 4B are schematic diagrams of two circuit structures of a first decision feedback unit in a data receiving circuit according to an embodiment of the present disclosure; [Figure 7] 4A and 4B are schematic diagrams of two circuit structures of a first decision feedback unit in a data receiving circuit according to an embodiment of the present disclosure; [Figure 8] FIG. 2 is a schematic diagram of another circuit structure of a data receiving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] One or more embodiments are illustrated by their corresponding drawings, which are not intended to limit the embodiments, and elements with the same reference numbers in the drawings are shown as similar elements, and unless otherwise specified, the drawings do not constitute a limit on scale. In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

[0031] The embodiments of the present disclosure provide a data receiving circuit, a data receiving system and a storage device, in which a decision feedback control module and a decision feedback equalization module are integrated into the data receiving circuit, and the decision feedback control module is used to generate a second sampling clock signal for controlling the decision feedback equalization module, so as to flexibly control whether the decision feedback equalization module is in an operating state. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, i.e., when the enable signal is in a first level value period, the decision feedback equalization module is controlled to perform decision feedback equalization according to the second sampling clock signal output by the decision feedback control module, so as to improve the receiving performance of the data receiving circuit; when it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit, i.e., when the enable signal is in a second level value period, the decision feedback equalization module is controlled to stop decision feedback equalization according to the second sampling clock signal output by the decision feedback control module, so as to reduce the power consumption of the entire data receiving circuit, thus being advantageous to reduce the power consumption of the data receiving circuit while improving the receiving performance of the data receiving circuit.

[0032] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. However, those skilled in the art can understand that in each embodiment of the present invention, many technical details are presented to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can be implemented.

[0033] An embodiment of the present disclosure provides a data receiving circuit, and the data receiving circuit provided by the embodiment of the present disclosure will be described in detail below with reference to the drawings. Fig. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, Figs. 3 and 4 are two other functional block diagrams of a data receiving circuit according to an embodiment of the present disclosure, Fig. 5 is a schematic diagram of a circuit structure of a data receiving circuit according to an embodiment of the present disclosure, Figs. 6 and 7 are schematic diagrams of two circuit structures of a first decision feedback unit in a data receiving circuit according to an embodiment of the present disclosure, and Fig. 8 is a schematic diagram of another circuit structure of a data receiving circuit according to an embodiment of the present disclosure.

[0034] Referring to FIG. 1, the data receiving circuit 100 includes a first amplification module 101 configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ with the reference signal Vref in response to a first sampling clock signal CLK1, and output a first voltage signal and a second voltage signal via a first node n_stg1 and a second node p_stg1, respectively; a decision feedback control module 104 configured to generate a second sampling clock signal CLK2 in response to an enable signal DfeEn; and a second sub-module 105 connected to the first node n_stg1 and the second node p_stg1 and configured to adjust the first voltage signal and the second voltage signal during a period when the enable signal DfeEn has a first level value. 5 , the decision feedback equalization module 103 is configured to perform decision feedback equalization based on a feedback signal fb in response to a sampling clock signal CLK2, and to stop performing the decision feedback equalization during a period in which the enable signal DfeEn has a second level value, where the feedback signal fb is obtained based on previously received data; and a second amplification module 102 configured to perform an amplification process on a voltage difference between a first voltage signal and the second voltage signal, and output a first output signal Vout and a second output signal VoutN via a third node net3 (see FIG. 5 ) and a fourth node net4 (see FIG. 5 ), respectively.

[0035] It should be noted that the data receiving circuit 100 adopts two-stage amplification modules, i.e., the first amplification module 101 and the second amplification module 102 process the data signal DQ and the reference signal Vref, which is advantageous to improve the amplification capability of the data receiving circuit 100 and increase the voltage amplitude of the first output signal Vout and the second output signal VoutN, and facilitate the processing of subsequent circuits.

[0036] Furthermore, the decision feedback control module 104 is used to generate a second sampling clock signal CLK2 for controlling the decision feedback equalization module 103, so as to flexibly control whether the decision feedback equalization module 103 is in an operating state. For example, when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, i.e., when the enable signal DfeEn is in the first level value period, the decision feedback control module 104 generates a second sampling clock signal CLK2 in response to the enable signal DfeEn at this time, and the decision feedback equalization module 103 performs decision feedback equalization based on the second sampling clock signal CLK2 to improve the receiving performance of the data receiving circuit 100; when it is not necessary to take into account the effect of inter-symbol interference on the data receiving circuit 100, i.e., when the enable signal DfeEn is in the second level value period, the decision feedback control module 104 stops the decision feedback equalization based on the second sampling clock signal CLK2 at this time to reduce the power consumption of the entire data receiving circuit 100, which is advantageous in reducing the power consumption of the data receiving circuit 100 while improving the receiving performance of the data receiving circuit 100.

[0037] Here, integrating the decision feedback equalization module 103 into the data receiving circuit 100 is advantageous for realizing the adjustment of the signal output by the data receiving circuit using a smaller circuit layout area and lower power consumption. In addition, it can be understood that the adjustment ability of the decision feedback equalization module 103 provided by an embodiment of the present disclosure for the first output signal Vout and the second output signal VoutN can be adjusted, and when the data signal DQ and / or the reference signal Vref received by the data receiving circuit 100 change, the adjustment ability of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN can be flexibly controlled to reduce the influence of inter-symbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100, so as to improve the receiving performance of the data receiving circuit 100 and reduce the influence of inter-symbol interference on the accuracy of the signal output by the data receiving circuit 100.

[0038] In some embodiments, referring to FIG. 3, the first amplification module 101 includes a first current source 111 connected between a power supply node Vcc (see FIG. 5) and a fifth node net5 and configured to supply a current to the fifth node net5 in response to a first sampling clock signal CLK1, and a comparison unit 121 connected to the fifth node net5, the first node n_stg1, and the second node p_stg1 and configured to receive a data signal DQ and a reference signal Vref, and when the first current source 111 supplies a current to the fifth node net5 in response to the first sampling clock signal CLK1, compare the data signal DQ with the reference signal Vref, output a first voltage signal via the first node n_stg1, and output a second voltage signal via the second node p_stg1.

[0039] It can be seen that the comparison unit 121 controls the difference between the current supplied to the first node n_stg1 and the current supplied to the second node p_stg1 based on the difference between the data signal DQ and the reference signal Vref, and outputs the first voltage signal and the second voltage signal.

[0040] The first amplification module 101 will be described in detail below with reference to FIGS.

[0041] 5 and 8, in some embodiments, the first current source 111 may include a first PMOS transistor MP1 connected between a power supply node Vcc and a fifth node net5, and the gate of the first PMOS transistor MP1 receives the first sampling clock signal CLK1. When the first sampling clock signal CLK1 is at a low level, the gate of the first PMOS transistor MP1 receives the first sampling clock signal CLK1 for conduction, and supplies current to the fifth node net5, so that the comparison unit 121 is in an active state and compares the received data signal DQ with the reference signal Vref.

[0042] In some embodiments, still referring to FIGS. 5 and 8, the comparison unit 121 includes a third PMOS transistor MP3 connected between the fifth node net5 and the first node n_stg1, the gate of which receives the data signal DQ, and a fourth PMOS transistor MP4 connected between the fifth node net5 and the second node p_stg1, the gate of which receives the reference signal Vref.

[0043] It should be noted that since the changes in the level values ​​of the data signal DQ and the reference signal Vref are not synchronized, the conduction time of the third PMOS transistor MP3 receiving the data signal DQ is different from the conduction time of the fourth PMOS transistor MP4 receiving the reference signal Vref, and at the same time, the conduction degree of the third PMOS transistor MP3 is different from the conduction degree of the fourth PMOS transistor MP4. Based on the fact that the conduction degree of the third PMOS transistor MP3 is different from the conduction degree of the fourth PMOS transistor MP4, the shunt capabilities of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 with respect to the current at the fifth node net5 are also different, so that it can be understood that the voltage at the first node n_stg1 is different from the voltage at the second node p_stg1.

[0044] In one example, when the level value of the data signal DQ is lower than the level value of the reference signal Vref, the conductivity of the third PMOS transistor MP3 is greater than the conductivity of the fourth PMOS transistor MP4, so that more current at the fifth node net5 flows through the path in which the third PMOS transistor MP3 is located, and the current at the first node n_stg1 becomes greater than the current at the second node p_stg1, so that the level value of the first voltage signal output by the first node n_stg1 is high and the level value of the second voltage signal output by the second node p_stg1 is low.

[0045] 3 and 4, in some embodiments, the first amplifying module 101 further includes a first reset unit 131 connected to the first node n_stg1 and the second node p_stg1 and configured to reset the first node n_stg1 and the second node p_stg1. In this way, after the data receiving circuit completes receiving the data signal DQ and the reference signal Vref and outputting the first output signal Vout and the second output signal VoutN once, the first reset unit 131 can restore the level values ​​at the first node n_stg1 and the second node p_stg1 to initial values, to facilitate the next data receiving and processing of the subsequent data receiving circuit.

[0046] In some embodiments, referring to FIGS. 5 and 8, the first reset unit 131 includes a first NMOS transistor MN1 connected between a first node n_stg1 and a ground terminal, where the gate of the first NMOS transistor MN1 receives the first sampling clock signal CLK1, and a second NMOS transistor MN2 connected between a second node p_stg1 and a ground terminal, where the gate of the second NMOS transistor MN2 receives the first sampling clock signal CLK1.

[0047] In one example, when the first sampling clock signal CLK1 is at a low level, the first PMOS transistor MP1 is turned on, and at this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off to ensure the normal operation of the data receiving circuit; at the same time, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be used as a load of the first amplification module 101 to increase the amplification gain of the first amplification module 101; when the first sampling clock signal CLK1 is at a high level, the first PMOS transistor MP1 is turned off, and at this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on to pull down the voltage at the first node n_stg1 and the voltage at the second node p_stg1, and realize the reset of the first node n_stg1 and the second node p_stg1.

[0048] In some embodiments, referring to FIG. 3 and FIG. 4, the feedback signal fb includes a first feedback signal fbn and a second feedback signal fbp which are differential signals with respect to each other, and the decision feedback equalization module 103 includes a second current source 133 connected between a power supply node Vcc (see FIG. 5) and the sixth node net6 and configured to supply a current to the sixth node net6 in response to the second sampling clock signal CLK2, and a second current source 133 connected to the first node n_stg1 and the sixth node net6 and configured to supply a current to the sixth node net6 in response to the second sampling clock signal CLK2. , a first decision feedback unit 113 configured to perform decision feedback equalization on the first node n_stg1 based on the first feedback signal fbn so as to adjust the first voltage signal, and a second decision feedback unit 123 connected to the second node p_stg1 and the sixth node net6 and configured to perform decision feedback equalization on the second node p_stg1 based on the second feedback signal fbp so as to adjust the second voltage signal when the second current source 133 supplies current to the sixth node net6 in response to the second sampling clock signal CLK2.

[0049] It can be understood that the current source in the first amplification module 101 is the first current source 111, and the current source in the decision feedback equalization module 103 is the second current source 133. In this way, by using different current sources to supply current to the first amplification module 101 and the decision feedback equalization module 103 respectively, the decision feedback equalization module 103 has an independent second current source 133, and realizes independent control of whether the decision feedback equalization module 103 is in an operating state.

[0050] Here, the second sampling clock signal CLK2 is controlled by the enable signal DfeEn, and when the enable signal DfeEn is in the first level value period, the second current source 133 supplies a current to the sixth node net6 in response to the second sampling clock signal CLK2 at this time, so that the first decision feedback unit 113 performs decision feedback equalization on the first node n_stg1 based on the received first feedback signal fbn to adjust the first voltage signal, and the second decision feedback unit 123 performs decision feedback equalization on the second node p_stg1 based on the received second feedback signal fbp to adjust the second voltage signal. In this way, during the period when the enable signal DfeEn has the first level value, the decision feedback equalization module 103 can perform decision feedback equalization based on the feedback signal fb in response to the second sampling clock signal CLK2 to adjust the first voltage signal and the second voltage signal.

[0051] During the period when the enable signal DfeEn has the second level value, the second current source 133 is in an off state in response to the second sampling clock signal CLK2 at this time, i.e., does not supply current to the sixth node net6, and further prevents current from passing through the first decision feedback unit 113 and the second decision feedback unit 123, thereby realizing the purpose of the decision feedback equalization module 103 stopping the execution of decision feedback equalization, which is also beneficial to reducing the power consumption of the entire data receiving circuit 100.

[0052] Here, the first decision feedback unit 113 is used to adjust the current in the third PMOS transistor MP3 to adjust the voltage at the first node n_stg1, which is equivalent to adjusting the data signal DQ, and the second decision feedback unit 123 is used to adjust the current in the fourth PMOS transistor MP4 to adjust the voltage at the second node p_stg1, which is equivalent to adjusting the reference signal Vref.

[0053] It should be noted that the second amplification module 102 receives the first voltage signal and the second voltage signal, performs an amplification process on the voltage difference between the first voltage signal and the second voltage signal, and outputs the first output signal Vout and the second output signal VoutN, that is, the first output signal Vout and the second output signal VoutN are affected by the first voltage signal and the second voltage signal, and the decision feedback equalization module 103 can adjust the first voltage signal and the second voltage signal according to the feedback signal fb, and can also realize the adjustment of the first output signal Vout and the second output signal VoutN. Furthermore, the adjustment of the first voltage signal and the second voltage signal by the decision feedback equalization module 103 will be described in detail later with reference to a specific circuit diagram.

[0054] In some embodiments, referring to FIGS. 5 and 8, the second current source 133 may include a second PMOS transistor MP2 connected between the power supply node Vcc and the sixth node net6, and the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2.

[0055] In one example, during a period in which the enable signal DfeEn has a first level value, the decision feedback control module 104 generates a second sampling clock signal CLK2 in response to the enable signal DfeEn. When the second sampling clock signal CLK2 is at a low level, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and turns on to supply current to the sixth node net6. Further, the decision feedback equalization module 103 makes a decision feedback equalization based on the feedback signal fb in response to the second sampling clock signal CLK2 at this time. During the period when the enable signal DfeEn has the second level value, the second sampling clock signal CLK2 generated by the decision feedback control module 104 in response to the enable signal DfeEn at this time is at a high level all the time, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and is turned off, so as to not supply current to the sixth node net6, and the decision feedback equalization module 103 stops performing the decision feedback equalization, thereby reducing the power consumption of the entire data receiving circuit 100.

[0056] In some embodiments, with continued reference to FIGS. 5 and 8, the decision feedback control module 104 may include a NAND gate circuit 114, one input terminal of which receives the fourth sampling clock signal CLK4, the other input terminal of which receives the enable signal DfeEn, and an output terminal of which outputs the second sampling clock signal CLK2.

[0057] Note that in one example, the first level value period of the enable signal DfeEn refers to a level value range that causes the decision feedback control module 104 to determine that the enable signal DfeEn is logic level 1, i.e., a high level, and the second level value period of the enable signal DfeEn refers to a level value range that causes the decision feedback control module 104 to determine that the enable signal DfeEn is logic level 0, i.e., a low level.

[0058] In one example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the enable signal DfeEn is in the first level value period, that is, the enable signal DfeEn is at a high level. In this case, the phase of the second sampling clock signal CLK2 output by the NAND gate circuit 114 is opposite to the phase of the fourth sampling clock signal CLK4. When the second sampling clock signal CLK2 is at a low level, the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and turns on to supply current to the sixth node net6. Furthermore, the phase of the first sampling clock signal CLK1 is synchronized with the phase of the second sampling clock signal CLK2, and the first sampling clock signal CLK1 and the second sampling clock signal CLK2 are both at a low level. When the level is high, the decision feedback equalization module 103 and the first amplification module 101 are both in an operating state, and the influence of inter-symbol interference on the data receiving circuit 100 is reduced. When there is no need to consider the influence of inter-symbol interference on the data receiving circuit 100, the enable signal DfeEn is in the second level value period, that is, the enable signal DfeEn is at a low level. In this case, whether the fourth sampling clock signal CLK4 is at a high level or a low level, the second sampling clock signals CLK2 output by the NAND gate circuit 114 are all at a high level, and the gate of the second PMOS transistor MP2 receives the second sampling clock signal CLK2 at this time and is turned off, so as to not supply current to the sixth node net6, that is, the decision feedback equalization module 103 is in a non-operating state.

[0059] 5 and 8, take the case where the NAND gate circuit 114 only includes one NAND as an example, it should be noted that in practical applications, any circuit that can realize NAND gate logic can be the NAND gate circuit 114.

[0060] In some embodiments, referring to FIG. 6 and FIG. 7, either the first decision feedback unit 113 or the second decision feedback unit 123 includes a switch unit 1131 configured to make the sixth node net6 and the seventh node net7 conductive in response to a feedback signal fb, and an adjustment unit 1132 connected between the seventh node net7 and an output node and configured to adjust the magnitude of an equivalent resistance value between the seventh node net7 and the output node in response to a control signal, where the output node is one of the first node n_stg1 and the second node p_stg1, where in the first decision feedback unit 113, the feedback signal is the first feedback signal fbn, the output node is the first node n_stg1, and the switch unit 1131 is responsive to the first feedback signal fbn, and in the second decision feedback unit 123, the feedback signal is the second feedback signal fbp, the output node is the second node p_stg1, and the switch unit 1131 is responsive to the second feedback signal fbp.

[0061] Here, the switch unit 1131 in the first decision feedback unit 113 is turned on or off according to the first feedback signal fbn, and the switch unit 1131 in the second decision feedback unit 123 is turned on or off according to the second feedback signal fbp. Whether it is the first decision feedback unit 113 or the second decision feedback unit 123, only when the switch unit 1131 is turned on, the adjusting unit 1132 is put into an operating state and adjusts the voltage at the first node n_stg1 or the second node p_stg1.

[0062] In some embodiments, with continued reference to FIGS. 6 and 7, the switch unit 1131 may include a fifth PMOS transistor MP5 connected between the sixth node net6 and the seventh node net7, and the gate of the fifth PMOS transistor MP5 receives the feedback signal fb.

[0063] 6 and 7, take the case where the gate of the fifth PMOS transistor MP5 receives the first feedback signal fbn and the output node is the first node n_stg1 as an example. It should be noted that what is shown in FIG. 6 and FIG. 7 is the specific structure of the first decision feedback unit 113, and in actual application, the specific structure of the second decision feedback unit 123 is similar to the specific structure of the first decision feedback unit 113, with the difference being that the gate of the fifth PMOS transistor MP5 in the second decision feedback unit 123 receives the second feedback signal fbp, and the output node is the second node p_stg1, and everything else is the same.

[0064] In one example, when the first feedback signal fbn received by the switch unit 1131 in the first decision feedback unit 113 is at a low level, the fifth PMOS transistor MP5 is turned on, and in this case, the adjustment unit 1132 adjusts the voltage at the first node n_stg1 according to the control signal. In another example, when the second feedback signal fbp received by the switch unit 1131 in the second decision feedback unit 123 is at a low level, the fifth PMOS transistor MP5 is turned on, and in this case, the adjustment unit 1132 adjusts the voltage at the second node p_stg1 according to the control signal.

[0065] 6 and 7, in some embodiments, the regulating unit 1132 includes a plurality of transistor groups connected in parallel between the seventh node net7 and the output node, the control signals received by the control terminals of different transistor groups are different, and the equivalent resistance values ​​of different transistor groups are different. It can be seen that the difference in the equivalent resistance values ​​of different transistor groups makes the equivalent resistance of the entire regulating unit 1132 flexible and controllable, the control signals received by the control terminals of different transistor groups are different, and the number of transistor groups in the on state is selected by the control signal to realize the adjustment of the equivalent resistance of the entire regulating unit 1132, thereby realizing the flexible control of the voltage at the first node n_stg1.

[0066] In one example, referring to FIG. 6, the adjustment unit 1132 may include three single MOS transistors connected in parallel between the seventh node net7 and the first node n_stg1, which are, in order, a first MOS transistor M01, a second MOS transistor M02, and a third MOS transistor M03, where the gate of the first MOS transistor M01 is connected to a first control signal DfeTrim <2> The gate of the second MOS transistor M02 receives the second control signal DfeTrim <1> , and the gate of the third MOS transistor M03 receives the third control signal DfeTrim <0> Receive.

[0067] 7, in some embodiments, the different transistor groups include: at least one transistor group is composed of a single MOS transistor, and at least one transistor group includes at least two MOS transistors connected in series. In this way, several single MOS transistors having the same channel aspect ratios connected in series with each other can be used to configure a transistor group, and the equivalent channel aspect ratio of the transistor group can be adjusted to realize various designs of the adjustment unit 1132. It can be understood that due to the difference in the equivalent channel aspect ratios of the transistor groups, the equivalent resistance of the transistor groups may be different.

[0068] In one example, the adjustment unit may include three transistor groups, a first transistor group, a second transistor group, and a third transistor group, connected in parallel between a seventh node and the first node, where the first transistor group includes a first MOS transistor, a gate of the first MOS transistor receives a first control signal, the second transistor group includes a second MOS transistor, a gate of the second MOS transistor receives a second control signal, the third transistor group includes a third MOS transistor and a fourth MOS transistor connected in series with each other, a first terminal of the fourth MOS transistor is connected to the seventh node, a second terminal of the fourth MOS transistor is connected to the first terminal of the third MOS transistor, the second terminal of the third MOS transistor is connected to the first node, and the gate of the third MOS transistor and the gate of the fourth MOS transistor all receive the third control signal.

[0069] In another example, referring to FIG. 7 , the adjustment unit 1132 may further include a fourth transistor group 43 and a fifth transistor group 53 connected in parallel between the seventh node net7 and the first node n_stg1 in addition to the first transistor group 13, the second transistor group 23, and the third transistor group 33 in the above-mentioned example, where the first transistor group 13 includes a first MOS transistor M01, and the gate of the first MOS transistor M01 is connected to a first control signal DfeTrim <2> The second transistor group 23 includes a second MOS transistor M02, and the gate of the second MOS transistor M02 receives a second control signal DfeTrim <1> the third transistor group 33 includes a third MOS transistor M03 and a fourth MOS transistor M04 connected in series to each other, a first terminal of the fourth MOS transistor M04 is connected to a seventh node net7, a second terminal of the fourth MOS transistor M04 is connected to a first terminal of the third MOS transistor M03, a second terminal of the third MOS transistor M03 is connected to a first node n_stg1, and a gate of the third MOS transistor M03 and a gate of the fourth MOS transistor M04 both receive a third control signal DfeTrim <0> The fourth transistor group 43 includes a fifth MOS transistor M05, and the gate of the fifth MOS transistor M05 receives a fourth control signal DfePerPin <1> The fifth transistor group 53 includes a sixth MOS transistor M06 and a seventh MOS transistor M07 connected in series to each other, a first terminal of the seventh MOS transistor M07 is connected to a seventh node net7, a second terminal of the seventh MOS transistor M07 is connected to a first terminal of the sixth MOS transistor M06, and a second terminal of the sixth MOS transistor M06 is connected to a first node n_stg1. The gates of the sixth MOS transistor M06 and the seventh MOS transistor M07 are both connected to a fifth control signal DfePerPin <0> Receive.

[0070] In the above three examples, the first control signal DfeTrim <2> , second control signal DfeTrim <1> and the third control signal DfeTrim <0> may be common to all data receiving circuits 100, i.e., in the case of different data receiving circuits 100 connected to different DQ ports, the first control signal DfeTrim <2> , second control signal DfeTrim <1> and the third control signal DfeTrim <0> Note that the fourth control signal DfePerPin <1> and the fifth control signal DfePerPin <0> is individually designed based on each DQ port. In the case of different data receiving circuits of each DQ port, for example, in the case of a first data receiving circuit connected to the port DQ1 and a second data receiving circuit connected to the port DQ2, the fourth control signal DfePerPin <1> and the fifth control signal DfePerPin <0> is designed based on the port DQ1, and the fourth control signal DfePerPin <1> and the fifth control signal DfePerPin <0> It can be seen that the fourth control signal DfePerPin is designed based on the port DQ2. Since the data received by different DQ ports will experience different inter-symbol interference, the interference experienced by each data signal DQ in the transmission path will also be different. <1> and the fifth control signal DfePerPin <0> , and is advantageous to specifically adjust for each DQ port through the adjustment unit 1132, so as to further improve the receiving performance of the data receiving circuit, where the DQ port is a port through which the data receiving circuit receives the data signal DQ.

[0071] 6 and 7, in the above embodiment, the different transistor groups may include a first transistor group 13, a second transistor group 23 and a third transistor group 33 connected in parallel with each other, and the equivalent aspect ratio of the channel of the first transistor group 13 is twice that of the channel of the second transistor group 23, and the equivalent aspect ratio of the channel of the second transistor group 23 is twice that of the channel of the third transistor group 33. In this way, the ratio of the equivalent resistance of the first transistor group 13, the equivalent resistance of the second transistor group 23 and the equivalent resistance of the third transistor group 33 is 1:2:4, thereby linearly adjusting the total equivalent resistance of the adjustment unit 1132, thereby realizing linear adjustment of the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

[0072] It should be noted that the above is only an example in which the ratio between the equivalent aspect ratio of the channels of the first transistor group 13 and the equivalent aspect ratio of the channels of the second transistor group 23 is 2, and the ratio between the equivalent aspect ratio of the channels of the second transistor group 23 and the equivalent aspect ratio of the channels of the third transistor group 33 is 2, and in actual applications, the ratio between the equivalent aspect ratio of the channels of the first transistor group 13 and the equivalent aspect ratio of the channels of the second transistor group 23, or the ratio between the equivalent aspect ratio of the channels of the second transistor group 23 and the equivalent aspect ratio of the channels of the third transistor group 33 may be other values, such as 3 or 4.

[0073] In FIG. 6, by controlling the channel aspect ratio of the first MOS transistor M01 to be twice that of the second MOS transistor M02, the equivalent aspect ratio of the channel of the first transistor group 13 becomes twice that of the second transistor group 23. By controlling the channel aspect ratio of the second MOS transistor M02 to be twice that of the third MOS transistor M03, the equivalent aspect ratio of the channel of the second transistor group 23 becomes twice that of the third transistor group 33. In FIG. 7, by controlling the channel aspect ratio of the first MOS transistor M01 to be twice that of the second MOS transistor M02, the equivalent aspect ratio of the channel of the second transistor group 23 becomes twice that of the third transistor group 33. It should be noted that by controlling the channel aspect ratios of the second MOS transistor M02, the third MOS transistor M03, and the fourth MOS transistor M04 to be equal, the channel aspect ratio of the second MOS transistor M02 is twice the equivalent aspect ratio of the channel of the third transistor group 33, i.e., the equivalent aspect ratio of the channel of the second transistor group 23 is twice the equivalent aspect ratio of the channel of the third transistor group 33.

[0074] 7, by controlling the channel aspect ratios of the fifth MOS transistor M05, the sixth MOS transistor M06, and the seventh MOS transistor M07 to be equal, the channel aspect ratio of the fifth MOS transistor M05 is twice the equivalent aspect ratio of the channel of the fifth transistor group 53, i.e., the equivalent aspect ratio of the channel of the fourth transistor group 43 is twice the equivalent aspect ratio of the channel of the fifth transistor group 53. In some embodiments, the channel aspect ratio of the fifth MOS transistor M05 may also be equal to the channel aspect ratio of the second MOS transistor M02.

[0075] In one example, referring to FIG. 6, the channel length of the first MOS transistor M01, the channel length of the second MOS transistor M02, and the channel length of the third MOS transistor M03 may be equal, the channel width of the first MOS transistor M01 may be twice the channel width of the second MOS transistor M02, and the channel width of the second MOS transistor M02 may be twice the channel width of the third MOS transistor M03. It should also be noted that in practical applications, when the channel widths of the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03 are kept the same, the ratio relationship between the equivalent aspect ratios of the channels of the first transistor group 13, the second transistor group 23, and the third transistor group 33 can be realized by adjusting the ratio relationship between the channel lengths of the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03, or by not only adjusting the ratio relationship between the channel widths of the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03, but also adjusting the ratio relationship between the channel lengths of the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03.

[0076] It should be noted that the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06, and the seventh MOS transistor M07 may all be PMOS transistors or NMOS transistors, and that when any one of the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06, and the seventh MOS transistor M07 is a PMOS transistor, the phase of the control signal when the PMOS transistor is in a conductive state is a first phase, and when the MOS transistor is an NMOS transistor, the phase of the control signal when the NMOS transistor is in a conductive state is a second phase, and the first phase is opposite to the second phase.

[0077] In some embodiments, referring to Figures 3 and 4, the second amplification module 102 includes an input unit 112 connected to the first node n_stg1 and the second node p_stg1 and configured to compare the first voltage signal and the second voltage signal and provide a third voltage signal and a fourth voltage signal to the eighth node n_stg2 and the ninth node p_stg2, respectively, and a latch unit 122 configured to perform amplification and latching on the third voltage signal and the fourth voltage signal, output a first output signal Vout to the third node net3 and output a second output signal VoutN to the fourth node net4.

[0078] Here, the input unit 112 is used to compare the first voltage signal and the second voltage signal, and output a third voltage signal and a fourth voltage signal, and the latch unit 122 is used to output a high level signal to the third node net3 and a low level signal to the fourth node net4, or output a low level signal to the third node net3 and a high level signal to the fourth node net4 based on the third voltage signal and the fourth voltage signal.

[0079] In some embodiments, referring to FIGS. 5 and 8, the input unit 112 may include a third NMOS transistor MN3 connected between the eighth node n_stg2 and a ground terminal, where the gate of the third NMOS transistor MN3 receives a first voltage signal, and a fourth NMOS transistor MN4 connected between the ninth node p_stg2 and the ground terminal, where the gate of the fourth NMOS transistor MN4 receives a second voltage signal.

[0080] In one example, when the level value of the first voltage signal output by the first node n_stg1 is higher than the level value of the second voltage signal output by the second node p_stg1, the conductivity of the third NMOS transistor MN3 is greater than the conductivity of the fourth NMOS transistor MN4, so that the voltage at the eighth node n_stg2 is smaller than the voltage at the ninth node p_stg2, and therefore the conductivity of the fifth NMOS transistor MN5 is greater than the conductivity of the sixth NMOS transistor MN6, the voltage at the third node net3 is smaller than the voltage at the fourth node net4, and the conductivity of the seventh PMOS transistor MP7 is greater than the conductivity of the sixth PMOS transistor MP6, and the latch unit 122 forms a positive feedback amplification, and the first output signal Vout output by the third node net3 is at a low level, and the second output signal VoutN output by the fourth node net4 is at a high level.

[0081] 5 and 8, in some embodiments, the latch unit 122 may include a fifth NMOS transistor MN5 connected between the eighth node n_stg2 and the third node net3, where the gate of the fifth NMOS transistor MN5 receives the second output signal VoutN, a sixth NMOS transistor MN6 connected between the ninth node p_stg2 and the fourth node net4, where the gate of the sixth NMOS transistor MN6 receives the first output signal Vout, a sixth PMOS transistor MP6 connected between the power supply node Vcc and the third node net3, where the gate of the sixth PMOS transistor MP6 receives the second output signal VoutN, and a seventh PMOS transistor MP7 connected between the power supply node Vcc and the fourth node net4, where the gate of the seventh PMOS transistor MP7 receives the first output signal Vout.

[0082] 3 and 4, in some embodiments, the second amplifying module 102 further includes a second reset unit 142 connected to the latch unit 122 and configured to reset the latch unit 122. In this way, after the data receiving circuit completes receiving the data signal DQ and the reference signal Vref, and outputting the first output signal Vout and the second output signal VoutN once, the second reset unit 142 can restore the level values ​​at the third node net3 and the fourth node net4 to initial values, so as to facilitate the next data receiving and processing of the subsequent data receiving circuit.

[0083] In some embodiments, referring to FIGS. 5 and 8, the second reset unit 142 may include an eighth PMOS transistor MP8 connected between the power supply node Vcc and the third node net3, and a ninth PMOS transistor MP9 connected between the power supply node Vcc and the fourth node net4, and the gate of the eighth PMOS transistor MP8 and the gate of the ninth PMOS transistor MP9 are both responsive to the third sampling clock signal CLK3.

[0084] In one example, the third sampling clock signal CLK3 and the first sampling clock signal CLK1 have opposite phases, and the third sampling clock signal CLK3 and the fourth sampling clock signal CLK4 may be the same clock signal, or may be different clock signals with the same phase but different amplitudes. In this way, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the enable signal DfeEn is in the first level value period, that is, when the enable signal DfeEn is at high level and the first sampling clock signal CLK1 is at low level, the fourth sampling clock signal CLK4 is at high level, so that the second sampling clock signal CLK2 is at low level and the first PMOS transistor MP1 and the second PMOS transistor MP2 are both conductive, in this case, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off, the third sampling clock signal CLK3 is at high level, and the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both turned off to ensure the normal operation of the data receiving circuit 100. When there is no need to consider the impact of inter-symbol interference on the data receiving circuit 100, the enable signal DfeEn is in the second level value period, i.e., the enable signal DfeEn is at a low level. In this case, whether the first sampling clock signal CLK1 is at a high level or a low level, the second sampling clock signal CLK2 is at a fixed high level, and the second PMOS transistors MP2 are all turned off and do not supply current to the sixth node net6, i.e., the decision feedback equalization module 103 stops performing decision feedback equalization, thereby reducing the power consumption of the entire data receiving circuit 100.Furthermore, regardless of whether or not it is necessary to consider the effect of inter-symbol interference on the data receiving circuit 100, when the first sampling clock signal CLK1 is at a high level, the third sampling clock signal CLK3 is at a low level and the first PMOS transistor MP1 is turned off. In this case, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both conductive, and the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both conductive, pulling down the voltage at the first node n_stg1 and the voltage at the second node p_stg1, pulling up the voltage at the third node net3 and the voltage at the fourth node net4, thereby realizing resetting the first node n_stg1, the second node p_stg1, the third node net3 and the fourth node net4.

[0085] In some embodiments, based on the second reset unit 142 including the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9, the second reset unit 142 may further include a tenth PMOS transistor (not shown) connected between the power supply node Vcc and the eighth node n_stg2, and an eleventh PMOS transistor (not shown) connected between the power supply node Vcc and the ninth node p_stg2, and the gate of the tenth PMOS transistor and the gate of the eleventh PMOS transistor are both responsive to the third sampling clock signal CLK3. In this way, when the data receiving circuit 100 does not need to receive the data signal DQ and the reference signal Vref, the third sampling clock signal CLK3 is at a low level, and the tenth PMOS transistor and the eleventh PMOS transistor are both conductive, thereby pulling up the voltage at the eighth node n_stg2 and the voltage at the ninth node p_stg2 to realize the reset of the eighth node n_stg2 and the ninth node p_stg2.

[0086] 8, in some embodiments, the data receiving circuit 100 (see FIG. 1) may further include an offset compensation module 105 connected to the second amplification module 102 (see FIG. 1) and configured to compensate for an offset voltage of the second amplification module 102. Specifically, the offset compensation module 105 may be connected to an eighth node n_stg2 and a ninth node p_stg2.

[0087] 8, in some embodiments, the offset compensation module 105 may include a first offset compensation unit 115 connected between an eighth node n_stg2 and a ground terminal, and a second offset compensation unit 125 connected between a ninth node p_stg2 and a ground terminal, where the first offset compensation unit 115 is used to compensate a parameter of the third NMOS transistor MN3, the second offset compensation unit 125 is used to compensate a parameter of the fourth NMOS transistor MN4, and the first offset compensation unit 115 and the second offset compensation unit 125 can adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0088] In some embodiments, still referring to FIG. 8, the first offset compensation unit 115 may include at least two transistor groups connected in parallel, each transistor group including a seventh NMOS transistor MN7 and a seventh MOS transistor M7, a first terminal of the seventh NMOS transistor MN7 is connected to an eighth node n_stg2, a gate of the seventh NMOS transistor MN7 is connected to a first node n_stg1, the seventh MOS transistor M7 and the seventh NMOS transistor MN7 are arranged in one-to-one correspondence, the seventh MOS transistor M7 is connected between a second terminal of the seventh NMOS transistor MN7 and a ground terminal, and a gate of the seventh MOS transistor M7 receives a first offset signal Offset_1. It should be noted that for ease of explanation, FIG. 8 shows only one transistor group in the first offset compensation unit 115.

[0089] In this way, by controlling the conductivity of the seventh NMOS transistor MN7 by the first offset signal Offset_1, the equivalent resistance of the entire first offset compensation unit 115 can be adjusted, and the voltage at the eighth node n_stg2 can be further adjusted.

[0090] In some embodiments, the first offset compensation unit 115 includes two transistor groups connected in parallel, one of which is composed of a 71 NMOS transistor (not shown) and a 71 MOS transistor (not shown), and the other of which is composed of a 72 NMOS transistor (not shown) and a 72 MOS transistor (not shown), where the first offset signal Offset_1 includes a third offset signal (not shown) and a fourth offset signal (not shown), the gates of the 71 NMOS transistor and the 72 NMOS transistor are connected to the first node n_stg1, the gate of the 71 MOS transistor receives the third offset signal, and the gate of the 72 MOS transistor receives the fourth offset signal.

[0091] Here, the third offset signal and the fourth offset signal may be different. In this way, the conductivity of the 71st NMOS transistor and / or the 72nd MOS transistor can be controlled based on the third offset signal and the fourth offset signal to flexibly adjust the equivalent resistance of the entire first offset compensation unit 115, and further improve the adjustment effect of the voltage at the eighth node n_stg2.

[0092] In some embodiments, referring to FIG. 5, the second offset compensation unit 125 may include at least two groups of transistor groups connected in parallel, each transistor group including an 8th NMOS transistor MN8 and an 8th MOS transistor M8, a first terminal of the 8th NMOS transistor MN8 is connected to a 9th node p_stg2, a gate of the 8th NMOS transistor MN8 is connected to a second node p_stg1, the 8th MOS transistor M8 is disposed in one-to-one correspondence with the 8th NMOS transistor M8, the 8th MOS transistor M8 is connected between a second terminal of the 8th NMOS transistor MN8 and a ground terminal, and a gate of the 8th MOS transistor M8 receives a second offset signal Offset_2. It should be noted that for ease of explanation, FIG. 5 shows only one group of transistor groups in the second offset compensation unit 125.

[0093] In this way, by controlling the conductivity of the eighth NMOS transistor MN8 by the second offset signal Offset_2, the equivalent resistance of the entire second offset compensation unit 125 can be adjusted, and the voltage at the ninth node p_stg2 can be further adjusted.

[0094] In some embodiments, the second offset compensation unit 125 includes two transistor groups connected in parallel, one of which is composed of an 81st NMOS transistor (not shown) and an 81st MOS transistor (not shown), and the other of which is composed of an 82nd NMOS transistor (not shown) and an 82nd MOS transistor (not shown). Here, the second offset signal Offset_2 includes a fifth offset signal (not shown) and a sixth offset signal (not shown), the gates of the 81st NMOS transistor and the 82nd NMOS transistor are connected to the first node n_stg1, the gate of the 81st MOS transistor receives the fifth offset signal, and the gate of the 82nd MOS transistor receives the sixth offset signal.

[0095] Here, the fifth offset signal and the sixth offset signal may be different. In this way, the conductivity of the 81st NMOS transistor and / or the 82nd MOS transistor can be controlled based on the fifth offset signal and the sixth offset signal to flexibly adjust the equivalent resistance of the entire second offset compensation unit 125, and further improve the adjustment effect of the voltage at the ninth node p_stg2.

[0096] It should be noted that the seventh MOS transistor M7, the seventy-first MOS transistor M7, the seventy-second MOS transistor M8, the eighth MOS transistor M8, the eighth MOS transistor M8, and the eighth MOS transistor M8 can all be PMOS transistors or NMOS transistors. It should be noted that if any of the above MOS transistors is a PMOS transistor, the phase of the first offset signal Offset_1 when the PMOS transistor is controlled to be on is the third phase, and if the MOS transistor is an NMOS transistor, the phase of the second offset signal Offset_2 when the NMOS transistor is controlled to be on is the fourth phase, and the third phase is opposite to the fourth phase.

[0097] In the above description of the high level and the low level, it should be noted that the high level may be a level value equal to or higher than the power supply voltage, and the low level may be a level value equal to or lower than the ground voltage. Furthermore, the high level and the low level are relative, and the range of specific level values ​​included in the high level and the low level can be determined according to a specific device, for example, for an NMOS transistor, the high level refers to a range of gate voltage level values ​​that can turn on the NMOS transistor, and the low level refers to a range of gate voltage level values ​​that can turn off the NMOS transistor, and for a PMOS transistor, the low level refers to a range of gate voltage level values ​​that can turn on the PMOS transistor, and the high level refers to a range of gate voltage level values ​​that can turn off the PMOS transistor.

[0098] In summary, the decision feedback control module 104 is used to generate the second sampling clock signal CLK2 for controlling the decision feedback equalization module 103, and flexibly control whether the decision feedback equalization module 103 is in an operating state. For example, when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, i.e., when the enable signal DfeEn is in the first level value period, the decision feedback control module 104 generates a second sampling clock signal CLK2 in response to the enable signal DfeEn at this time, and the decision feedback equalization module 103 performs decision feedback equalization based on the second sampling clock signal CLK2 to improve the receiving performance of the data receiving circuit 100; when it is not necessary to take into account the effect of inter-symbol interference on the data receiving circuit 100, i.e., when the enable signal DfeEn is in the second level value period, the decision feedback control module 104 stops the decision feedback equalization based on the second sampling clock signal CLK2 at this time to reduce the power consumption of the entire data receiving circuit 100, which is advantageous in reducing the power consumption of the data receiving circuit 100 while improving the receiving performance of the data receiving circuit 100.

[0099] Another embodiment of the present disclosure further provides a data receiving system, and the data receiving system provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. Figure 2 is a functional block diagram of the data receiving system according to another embodiment of the present disclosure.

[0100] Referring to FIG. 2, the data receiving system includes a plurality of cascaded data transmission circuits 120, each of which includes a data receiving circuit 100 according to an embodiment of the present disclosure and a latch circuit 110 connected to the data receiving circuit 100. Each data receiving circuit 100 is connected to a data port and receives a data signal DQ. The data transmission circuit 120 of the previous stage is connected to the decision feedback equalization module 103 (see FIG. 1) of the data transmission circuit 120 of the next stage, and the output of the data transmission circuit 120 of the previous stage is used as the feedback signal fb of the decision feedback equalization module 130 of the data transmission circuit 120 of the next stage. The data transmission circuit 120 of the last stage is connected to the decision feedback equalization module 103 of the data transmission circuit 120 of the first stage, and the output of the data transmission circuit 120 of the last stage is used as the feedback signal fb of the decision feedback equalization module 103 of the data transmission circuit 120 of the first stage.

[0101] Here, the latch circuits 110 and the data receiving circuits 100 are installed in a one-to-one correspondence, and the latch circuits 110 are used to latch and output the signals output by the data receiving circuits 100 corresponding to the latch circuits 110.

[0102] In some embodiments, the data receiving circuit 100 receives data in response to a sampling clock signal, and the data receiving system includes four data receiving circuits 100 cascaded together, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages is 90°. In this way, the period of the sampling clock signal is twice that of the data signal DQ received by the data port, which is advantageous to facilitate clock wiring and save power.

[0103] In FIG. 2 , the data receiving system includes four cascaded data receiving circuits 1000, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages is taken as an example. It should be noted that in actual applications, the number of cascaded data receiving circuits 100 included in the data receiving system is not limited, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages can be appropriately set based on the number of cascaded data receiving circuits 100.

[0104] In some embodiments, the decision feedback equalization module 103 of the current-stage data receiving circuit 100 is connected to the output terminal of the second amplification module 102 of the previous-stage data receiving circuit 100, and uses the first output signal Vout and the second output signal VoutN output by the second amplification module 102 of the previous-stage data receiving circuit 100 as the feedback signal fb of the subsequent-stage data receiving circuit 100. In this way, the output of the data receiving circuit 100 does not need to pass through the latch circuit 110 and is directly transmitted to the next-stage data transmission circuit 120, which is advantageous in reducing data transmission delay.

[0105] In some other embodiments, the decision feedback equalization module 103 of the current data receiving circuit 100 is connected to the output terminal of the previous latch circuit 110, and uses the signal output by the previous latch circuit 110 as the feedback signal fb of the subsequent data receiving circuit 100.

[0106] In summary, the data receiving system provided by another embodiment of the present disclosure can use the decision feedback control module 104 to generate a second sampling clock signal CLK2 for controlling the decision feedback equalization module 103, so as to flexibly control whether the decision feedback equalization module 103 is in an operating state. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the decision feedback equalization module 103 performs decision feedback equalization based on the second sampling clock signal CLK2 to improve the reception performance of the data receiving circuit 100, and when it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit 100, the decision feedback equalization module 103 stops performing decision feedback equalization based on the second sampling clock signal CLK2 to reduce the power consumption of the entire data receiving circuit 100.

[0107] Another embodiment of the present disclosure further provides a storage device, the storage device including a plurality of data ports and a plurality of data receiving systems provided by another embodiment of the present disclosure, each data receiving system corresponding to one data port.

[0108] In this way, when it is necessary to reduce the impact of inter-symbol interference on the storage device, each data port of the storage device can flexibly adjust the data signal DQ received through the data receiving system, and improve the adjustment ability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device; when it is not necessary to consider the impact of inter-symbol interference on the storage device, the decision feedback equalization module 103 stops performing decision feedback equalization based on the second sampling clock signal CLK2, to reduce the power consumption of the storage device.

[0109] In some embodiments, the storage device may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0110] Those skilled in the art can understand that the above embodiments are specific examples for realizing the present disclosure, and in practical application, various changes in form and details can be made without departing from the spirit and scope of the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data receiving circuit, a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal via a first node and a second node, respectively; a decision feedback control module configured to generate a second sampling clock signal in response to the enable signal; a decision feedback equalization module connected to the first node and the second node, configured to perform decision feedback equalization based on a feedback signal in response to the second sampling clock signal to adjust the first voltage signal and the second voltage signal during a period when the enable signal has a first level value, and to stop performing decision feedback equalization during a period when the enable signal has a second level value, the feedback signal being obtained based on previously received data; a second amplification module configured to perform an amplification process on a voltage difference between the first voltage signal and the second voltage signal, and output a first output signal and a second output signal via a third node and a fourth node, respectively; The feedback signal includes a first feedback signal and a second feedback signal, which are mutually differential signals, and the decision feedback equalization module: a second current source connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the second sampling clock signal; a first decision feedback unit coupled to the first node and the sixth node and configured to perform decision feedback equalization on the first node based on the first feedback signal to adjust the first voltage signal when the second current source supplies a current to the sixth node in response to the second sampling clock signal; a second decision feedback unit coupled to the second node and the sixth node and configured to perform decision feedback equalization on the second node based on the second feedback signal to adjust the second voltage signal when the second current source supplies a current to the sixth node in response to the second sampling clock signal.

2. The first amplification module includes: a first current source connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to the first sampling clock signal; a comparison unit coupled to the fifth node, the first node, and the second node, configured to receive the data signal and the reference signal, compare the data signal and the reference signal, and output the first voltage signal via the first node and the second voltage signal via the second node when the first current source supplies a current to the fifth node in response to the first sampling clock signal.

2. The data receiving circuit according to claim 1.

3. The first current source is a first PMOS transistor connected between the power supply node and the fifth node, the gate of the first PMOS transistor receiving the first sampling clock signal; The comparison unit is a third PMOS transistor connected between the fifth node and the first node, the gate of the third PMOS transistor receiving the data signal; a fourth PMOS transistor connected between the fifth node and the second node, the gate of the fourth PMOS transistor receiving the reference signal; The first amplification module further comprises: a first reset unit coupled to the first node and the second node and configured to reset the first node and the second node; 3. The data receiving circuit according to claim 2.

4. The first reset unit is a first NMOS transistor connected between the first node and a ground terminal, the gate of the first NMOS transistor receiving the first sampling clock signal; a second NMOS transistor connected between the second node and the ground terminal, the gate of the second NMOS transistor receiving the first sampling clock signal; 4. The data receiving circuit according to claim 3.

5. The second current source is a second PMOS transistor connected between the power supply node and the sixth node, the gate of the second PMOS transistor receiving the second sampling clock signal; Either the first decision feedback unit or the second decision feedback unit a switch unit configured to conductively connect the sixth node and the seventh node in response to the feedback signal; an adjustment unit connected between the seventh node and an output node and configured to adjust a magnitude of an equivalent resistance value between the seventh node and the output node in response to a control signal, the output node being one of the first node and the second node; In the first decision feedback unit, the feedback signal is the first feedback signal, the output node is the first node, and the switch unit is responsive to the first feedback signal; and in the second decision feedback unit, the feedback signal is the second feedback signal, the output node is the second node, and the switch unit is responsive to the second feedback signal.

2. The data receiving circuit according to claim 1.

6. The switch unit includes: a fifth PMOS transistor connected between the sixth node and the seventh node, the gate of the fifth PMOS transistor receiving the feedback signal; 6. The data receiving circuit according to claim 5.

7. The adjustment unit includes: a plurality of transistor groups connected in parallel between the seventh node and the output node, the control signals received by the control terminals of different transistor groups being different, and equivalent resistance values ​​of different transistor groups being different; 6. The data receiving circuit according to claim 5.

8. The different transistor groups include: At least one of the transistor groups is composed of a single MOS transistor, At least one of the transistor groups includes at least two MOS transistors connected in series.

8. The data receiving circuit according to claim 7.

9. The second amplification module includes: an input unit coupled to the first node and the second node, configured to compare the first voltage signal with the second voltage signal and to provide a third voltage signal and a fourth voltage signal to an eighth node and a ninth node, respectively; a latch unit configured to perform amplification and latching on the third voltage signal and the fourth voltage signal, and to output the first output signal to the third node and the second output signal to the fourth node.

2. The data receiving circuit according to claim 1.

10. The input unit includes a third NMOS transistor and a fourth NMOS transistor; the third NMOS transistor is connected between the eighth node and a ground terminal, the gate of the third NMOS transistor receiving the first voltage signal; the fourth NMOS transistor is connected between the ninth node and the ground terminal, the gate of the fourth NMOS transistor receiving the second voltage signal; the latch unit includes a fifth NMOS transistor, a sixth NMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor; the fifth NMOS transistor is connected between the eighth node and the third node, a gate of the fifth NMOS transistor receives the second output signal; the sixth NMOS transistor is connected between the ninth node and the fourth node, a gate of the sixth NMOS transistor receives the first output signal; the sixth PMOS transistor is connected between a power supply node and the third node, and a gate of the sixth PMOS transistor receives the second output signal; the seventh PMOS transistor is connected between the power supply node and the fourth node, a gate of the seventh PMOS transistor receives the first output signal; The second amplification module further comprises: a second reset unit coupled to the latch unit and configured to reset the latch unit; 10. The data receiving circuit according to claim 9.

11. The second reset unit is an eighth PMOS transistor connected between a power supply node and the third node; a ninth PMOS transistor connected between the power supply node and a fourth node, wherein a gate of the eighth PMOS transistor and a gate of the ninth PMOS transistor are both responsive to a third sampling clock signal; The data receiving circuit according to claim 10.

12. The decision feedback control module: a NAND gate circuit, one input terminal of which receives the fourth sampling clock signal, the other input terminal of which receives the enable signal, and an output terminal of which outputs the second sampling clock signal; 2. The data receiving circuit according to claim 1.

13. 1. A data receiving system, comprising: A data transmission circuit includes a plurality of cascaded data transmission circuits, each of the data transmission circuits includes the data receiving circuit according to any one of claims 1 to 12 and a latch circuit connected to the data receiving circuit, each of the data receiving circuits is connected to a data port to receive the data signal, the data transmission circuit of a previous stage is connected to the decision feedback equalization module of the data transmission circuit of a next stage, and an output of the data transmission circuit of the previous stage is used as the feedback signal of the decision feedback equalization module of the data transmission circuit of the next stage, A data receiving system, wherein the data transmission circuit of a final stage is connected to the decision feedback equalization module of the data transmission circuit of an initial stage, and the output of the data transmission circuit of the final stage is used as the feedback signal of the decision feedback equalization module of the data transmission circuit of the initial stage.

14. 1. A storage device comprising: Multiple data ports and 14. A storage device comprising: a plurality of data receiving systems according to claim 13, each of said data receiving systems corresponding to one of said data ports.

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