Mappings for storing data and metadata

Abstract

To provide a circuit and a method in which data sequences and corresponding metadata are stored in the same sector.SOLUTION: In a computer system 200, a memory device 204 includes a Non-Volatile Memory (NVM) comprising a plurality of sectors, and a memory access circuit 212. The memory access circuit is configured to receive, from a host, a logical address of a block of data, to compute a mapping of the logical address to a data physical address comprising a selected sector among the plurality of sectors and a selected data offset within the same selected sector, to compute a metadata physical address that comprises the selected sector and a metadata offset in the selected sector, and to access the block of data at the data physical address, and the metadata at the metadata physical address.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates generally to non-volatile memory, and more particularly to a method and system for efficiently storing data and metadata in non-volatile memory. [Background technology]

[0002] Non-volatile memory, particularly flash memory, often stores data and corresponding metadata in storage portions called sectors.

[0003] US Patent Application Publication No. 2003 / 0204699 describes a method for embedding integrity metadata. In an exemplary embodiment, a number of integrity metadata segments are determined. Each integrity metadata segment is associated with a segment of user data. The user data is mapped to a number of physical sectors, each physical sector including an integrity metadata segment associated with a segment of user data. In an exemplary embodiment, a common I / O data block size is determined and the data is mapped to a number of 512-byte sectors. The number of 512-byte sectors corresponds to the common I / O data block size plus a required number of one or more additional 512-byte sectors. This creates additional space in each sector to accommodate integrity metadata. The integrity metadata for each sector is mapped to the additional space in each sector.

[0004] US Patent No. 11,294,902 describes a method including a processing entity of a computing system generating a plurality of parity blocks from a plurality of columns of data blocks, a first number of the plurality of parity blocks being generated from a first column of data blocks of the plurality of columns of data blocks, the method further including the processing entity storing the plurality of columns of data blocks in a data section of a memory of a cluster of computing devices of the computing system according to a read / write balancing pattern and a restricted file system. Summary of the Invention [Problem to be solved by the invention]

[0005] Non-Volatile Memory (NVM) devices often store metadata corresponding to stored data blocks (herein referred to as "data strings"). For example, parity signatures such as Cyclic Redundancy Code (CRC) and Error Correcting Code (ECC) are often used to improve the reliability of read data. NVM, such as flash memory, contains sectors, which are the smallest units of storage that can be individually erased.

[0006] One possible implementation is to store the data sequence and the corresponding metadata in separate sectors, allowing a direct mapping of the user's logical address space to the physical address space that defines the addresses in NVM. For example, assuming 4K byte sectors, a 24-bit logical address can be mapped to a sector number and an offset within the sector, where the sector number contains the most significant 12 bits of the logical address and the offset contains the least significant 12 bits.

[0007] However, storing data and metadata in separate sectors means that erasing data also involves erasing the metadata in the sector (which only takes up a small portion of the sector). Because Flash has no way to erase part of a sector, no other data can be stored in that sector, and much of the physical space is lost. [Means for solving the problem]

[0008] Embodiments described herein provide a storage device including: (i) a non-volatile memory (NVM) including a plurality of sectors; and (ii) a memory access circuit configured to receive a logical address of a data block from a host, calculate a mapping from the logical address to a data physical address including a selected sector from the plurality of sectors and a selected data offset within the same selected sector, calculate a metadata offset within the selected sector, access the data block at the data physical address, and access the metadata at the metadata physical address.

[0009] In one embodiment, the memory access circuitry is configured to receive a write command and a data block from a host, and in response, retrieve metadata corresponding to the data block, store the data block in the NVM at a data physical address, and store the metadata in the NVM at a metadata physical address. In another embodiment, the memory access circuitry is configured to receive a read command from the processor, and in response, read the data block stored in the NVM at the data physical address, and read the metadata stored in the NVM at the metadata physical address.

[0010] In some embodiments, the size of each sector is an integer power of 2 in bytes, and the number of data blocks in each sector is (2 m -1)·2 n where m and n represent integer values.

[0011] In an embodiment of the present invention, the memory access circuit performs integer division of a given input as follows: m -1) was designed to calculate (2 m -1) division circuit. And the memory access circuit adds (2 m In an exemplary embodiment, the logical address to data physical address mapping is calculated by applying a (2 −1) division circuit. m-1) The division circuit computes the shift-and-add sum of (i) a given input and (ii) the given input shifted left by an integer multiple of m bits, and repeats the computation of the shift-and-add sum d times, depending on the required precision, and truncates the (d-1)m least significant bits of the sum to obtain the result, such that the result is 2 m If it is equal to -1, the result is 2 m and discarding the m least significant bits to get (2 m -1).

[0012] In an embodiment of the present invention, the memory access circuitry performs a modulo (2 m Modulo (2 -1), designed to calculate m -1) circuit, and the memory access circuit converts the logical address into a modulo (2 m In an exemplary embodiment, the data offset and metadata offset are calculated by applying a modulo (2 −1) circuit. m -1) The circuit receives an input number and recursively (i) splits the input number into a set of m-bit fragments, (ii) adds the m-bit fragments together to obtain an output number that is less than the input number, and (iii) determines whether the output number is greater than or equal to 2 m Repeat steps (i) and (ii) until m is less than 0. In an exemplary embodiment, m is equal to 3.

[0013] According to another embodiment herein, there is further provided a method for accessing a non-volatile memory (NVM) including a plurality of sectors. The method includes: receiving a logical address of a data block from a host; calculating a mapping from the logical address to a data physical address; the data physical address including a selected sector from the plurality of sectors and a selected data offset within the same selected sector; and calculating a metadata physical address including the selected sector and a metadata offset within the selected sector. The data block is accessed at the data physical address and the metadata is accessed at the metadata physical address. Effect of the Invention

[0014] The embodiments of the invention disclosed herein provide circuits and methods whereby a data sequence and corresponding metadata are stored in the same sector. In an embodiment, an NVM storage device includes a memory access circuit (MAC) that efficiently facilitates mapping of logical addresses to physical addresses.

[0015] The present invention can be more fully understood from the following detailed description of the embodiments, taken in conjunction with the drawings, in which: [Brief description of the drawings]

[0016] [Figure 1] 2 is a block diagram that illustrates generally address mapping between logical and physical address spaces, in accordance with one embodiment of the present invention; FIG. [Diagram 2] 1 is a block diagram that illustrates a schematic of a computer system with non-volatile memory (NVM), in accordance with one embodiment of the present invention. [Diagram 3] 4 is a flow chart that illustrates a schematic of a method for storing and retrieving a data string in NVM, in accordance with an embodiment of the present invention. [Figure 4] FIG. 2 is a block diagram that illustrates generally an address mapping circuit, in accordance with one embodiment of the present invention; [Diagram 5] 1 is a block diagram illustrating a schematic configuration of a divide-by-7 circuit according to an embodiment of the present invention. [Figure 6] FIG. 2 is a block diagram illustrating a schematic configuration of a modulo 7 circuit according to an embodiment of the present invention. [Figure 7] 1 is a flow chart that conceptually illustrates a method for efficiently calculating a given number modulo 7, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] NVM devices often store metadata corresponding to stored blocks of data (herein referred to as "data strings"). For example, parity signatures such as Cyclic Redundancy Code (CRC) or Error Correcting Code (ECC) are often used to improve the reliability of read data. NVM, such as flash memory, contains sectors, where a sector is the smallest unit of storage that can be individually erased.

[0018] One possible implementation is to store the data sequence and the corresponding metadata in separate sectors, allowing a direct mapping of the user's logical address space to the physical address space that defines the addresses in NVM. For example, assuming 4K byte sectors, a 24-bit logical address can be mapped to a sector number and an offset within the sector, where the sector number contains the most significant 12 bits of the logical address and the offset contains the least significant 12 bits.

[0019] However, storing data and metadata in separate sectors means that erasing data also involves erasing the metadata in the sector (which only takes up a small percentage of the sector). Because Flash has no way to erase part of a sector, no other data can be stored in that sector, and much of the physical space is lost.

[0020] The embodiments of the invention disclosed herein provide circuits and methods whereby a data sequence and corresponding metadata are stored in the same sector. In an embodiment, an NVM storage device includes a memory access circuit (MAC) that efficiently facilitates mapping of logical addresses to physical addresses.

[0021] In an embodiment, the logical address space is divided into logical pages (groups of data strings and corresponding metadata). The size of each page is close to the size of a physical sector, and the number of data strings in a page is (2 m-1)*2 n where n and m are integers.

[0022] In one exemplary embodiment, the logical address space is divided into logical pages, with each page containing 224=7*32 16-byte data columns. Each logical page is arranged in 4096-byte physical sectors, with the data columns stored at consecutive addresses within the sector. Two bytes of metadata are calculated separately for each 16-byte data row. All metadata is stored immediately after the last data row (starting at an offset of 224*16=3,584 from the beginning of the sector). Together, data and metadata occupy 224*(16+2)=4032 bytes, leaving only 64 unused bytes in each sector.

[0023] In some embodiments, a computer system may include a processor, an NVM storage device, and a random access memory (RAM) shared by the processor and the storage device. The storage device includes memory access circuitry (MAC). To store data in the NVM, assuming the data is initially in the shared RAM, the processor sends a logical address of the data to the MAC. The MAC calculates the beginning of the data string, which includes the logical address, and reads the entire data string from the shared memory. The MAC then obtains metadata corresponding to the data string (e.g., using a parity generation circuit or by requesting the processor to calculate the metadata), calculates physical addresses of the data and metadata, and stores the data and metadata in the same sector of the NVM.

[0024] To read data from the NVM, the processor sends the logical address of the data to the MAC. The MAC calculates the corresponding physical addresses of the data and metadata, and reads the data and metadata. The processor corrects the data (e.g., if the metadata is an ECC code for the data string), saves the data in the shared RAM, and indicates errors if necessary.

[0025] In the embodiment, the number of data columns in a logical page is (2 m-1)*2 n The MAC divides the input number by 2m-1 (2 m -1) Includes a division circuit.

[0026] In another embodiment, the MAC is a modulo (2 m Calculate the division modulo (2 -1) m -1) Equipped with a circuit.

[0027] In an exemplary embodiment, m=3, and the number of data columns in a logical page is 224=7*2 5 where the address mapping involves integer division by 7 and modulo 7 arithmetic.

[0028] Enter 2 valid integers m Divide by -1

[0029] Mathematically, 2 m Dividing by -1 gives us:

number

[0030]

number

[0031]

number

[0032] The definition format of division is shown below in the form of a Python language program. The parameter depth is defined as the number of terms in the inner sum.

number

[0033] The total depth above determines the range within which the algorithm gives the correct answer. This parameter is selected according to the needs of the simulation run. Some results of the numerical simulation are shown in the table below.

[0034] [Table 1]

[0035] NVM devices such as flash memory often store data in sectors. A sector is the smallest entity that can be erased independently. In an embodiment, to facilitate data management, user data and corresponding metadata are stored in the same sector. In one embodiment, a user references data based on a logical page in a logical address space, without regard to where the data is stored. A logical address is translated to the appropriate sector in flash memory, an offset within the sector where the data is stored, and an offset within the sector where the corresponding metadata is stored. An address in flash that includes the sector number and offset is referred to as a physical address. The process of converting from a logical address to a physical address is referred to as address mapping.

[0036] FIG. 1 is a block diagram that illustrates generally an address mapping 100 between a logical address space 102 and a physical address space 104, in accordance with one embodiment of the present invention.

[0037] 1, the physical address space includes 4096-byte sectors 106. Each sector includes 224 16-byte data columns 108, each with a corresponding 2-byte metadata column 110 (64 bytes of the sector are unused).

[0038] A physical sector has 224 data columns, each column is 16 bytes, so there are 3584 bytes of data in a physical sector. The logical address space is contiguous and is mapped to the physical sectors such that the first byte of each 3584-byte page maps to the first byte of the corresponding physical sector, so that logical address n*3584 maps to the first byte of the nth physical sector.

[0039] It should be noted that, although this direct mapping is convenient, the invention is not limited to direct mapping, and other one-to-one mappings may be used in alternative embodiments. For example, in one embodiment, the mapping from logical pages to physical pages may be performed according to a table maintained by wear-leveling flash management software. In another embodiment, the mapping of data strings within a page is scrambled to improve security.

[0040] The configuration of the logical to physical address mapping 100 shown in Figure 1 and described above is an illustrative example, other mapping configurations may be used in alternative embodiments. For example, in one embodiment, the sector size may be 8192 bytes, or any other suitable size, in some embodiments, the number of metadata bytes associated with each data column may be two or more (e.g., four), and in some embodiments, may be one or more.

[0041] In another embodiment, the size and / or number of data columns on each page may be different than 16. In yet another embodiment, metadata for each data column is stored immediately following the data column.

[0042] In some embodiments, the unused space in each of these sectors may be used for additional metadata and / or any other suitable use, in one embodiment, the space may store erase counters for wear leveling.

[0043] Address Mapping

[0044] In the following, we assume that the logical address space and the physical address space are uniform spaces starting from address 0. If this is not the case, for example, if a physical page is mapped to an arbitrary sector, a page number mapping table may be added.

[0045] In the exemplary embodiment described below, the following constants are specified: 1. Sector size = 4,096 bytes (256 16-byte rows). 2. A string of 16 bytes, each containing two metadata bytes. 3. n data columns = 224 (the number of data columns in a sector used for data storage). 4. Sector_data_size (number of bytes stored in a sector) = 16 * n data columns = 3,584.

[0046] The logical address to physical address mapping, which receives the logical address (LA) of a data string and outputs the physical address of metadata corresponding to the data, is defined as follows. 1. Sector = LA / sector data size (integer division) 2. Data offset = LA% sector data size 3. Sector Address = Sector * Sector Size 4. Metadata offset = sector data size + data offset / 8 (8 is the ratio of the size of data and the corresponding metadata).

[0047] FIG. 2 is a block diagram that illustrates generally a computer system 200 with non-volatile memory (NVM), in accordance with one embodiment of the present invention.

[0048] In embodiments, computer system 200 may comprise multiple interconnected integrated circuits (ICs) and discrete devices, while in other embodiments the computer system may be a single IC (e.g., a system on silicon, SoC).

[0049] The computer system 200 includes one or more processors 202 and at least one storage device 204. The storage device includes a non-volatile memory (NVM) (e.g., flash memory) 206 with appropriate read, program, and erase circuitry (not shown). The NVM includes multiple sectors for storing data strings (each data string including, for example, 16 bytes) and for each data string, stores corresponding metadata (e.g., 2 bytes).

[0050] In an embodiment, the metadata includes a parity signature, such as a CRC or ECC, for the corresponding data string. In alternative embodiments, other types of metadata may be stored. According to an exemplary embodiment shown in Figure 2, the storage device 204 includes a parity generation circuit 208 configured to generate a parity signature (e.g., CRC or ECC) for the input data string, and an error detection / correction circuit 210 configured to check and verify the parity signature for the input data string, correct the data string (for error correction metadata), and indicate errors (if any).

[0051] The storage device 204 further comprises a memory access control circuit (MAC) 212 configured to control NVM accesses, including mapping logical address inputs of logical data strings (sent by the processor) to corresponding physical addresses of the data strings, and generating physical addresses of metadata corresponding to the data strings.

[0052] When a processor requests that a data string be stored at location LA, the MAC calculates the sector number for storing the data string and corresponding metadata, calculates offsets for the data string and metadata, generates the metadata (in parity generation circuit 208), and stores the data string and metadata in the same sector at the calculated offset.

[0053] For a read operation, the MAC calculates the sector number for reading the data string and corresponding metadata, calculates the data string and sector offset, and reads the data string and metadata from the NVM. The error detection / correction circuit then verifies and / or corrects the read data string and sends the corrected data string to the processor (or sends the data string and an error indication if an error is detected).

[0054] The configuration of computer system 200 shown in FIG. 2 and described above is an exemplary configuration cited solely for conceptual clarity. In alternative embodiments, other configurations may be used. For example, in some embodiments, the MAC or portions thereof are within the processor. In other embodiments, both the parity generation circuitry 208 and the error detection / correction circuitry 210 may be replaced, with a single parity calculation circuit being used for both parity generation and error detection / correction.

[0055] 3 is a flow chart 300 that generally illustrates a method for storing and retrieving a string of data in NVM, in accordance with one embodiment of the present invention. The flow chart is executed by the MAC 212 (FIG. 2) in response to commands and data received by the storage device from the processor 202. The flow chart begins with a get logical address operation 302, in which the MAC receives a logical address for a string of data from the processor. Next, in a locate sector operation 304, the MAC integer-divides the logical address by the number of data bytes in the sector to obtain a sector number ("sector") (assuming all sectors are numbered starting at 0).

[0056] The MAC then enters offset calculation operation 306 where the MAC calculates the data string offset within the sector by modulo dividing LA by the sector data size and calculates the metadata offset by adding the data string offset divided by 16 to the start of the metadata within the sector (in data sector size).

[0057] At verify read write operation 308, the flow chart is split such that for a read operation, the MAC enters a read data and metadata operation 310, whereas for a write operation, the MAC enters a get data string operation 314.

[0058] In a read data and metadata operation 310, the MAC reads the data string and corresponding metadata from the sector. Then, in a return data operation 312, the MAC returns either (i) the read data string and the metadata, (ii) the read data string corrected based on the metadata, or (iii) the read data string and an error indication (if any), depending on the type of metadata. After operation 312, the flowchart ends.

[0059] The MAC receives the data string from the processor in a get data string operation 314, after which the MAC obtains metadata corresponding to the data string in a get metadata operation 316. In some embodiments, the MAC may include a metadata generation circuit (e.g., the parity generation circuit 208 of FIG. 2), while in other embodiments the MAC obtains the metadata from the processor.

[0060] After operation 316, the MAC enters a store operation 318 to store the data and metadata at the calculated offset within the selected NVM sector. After operation 318, the flowchart ends.

[0061] Efficient Address Mapping

[0062] In an embodiment, the address mapping involves calculating an integer division of the byte address by the logical page size to find the sector number, and calculating a modulo division of the byte address by the logical page size to find the offset within the page to the actual byte of data.

[0063] In the exemplary embodiment presented above, the logical page size is 224*16=512*7 bytes. Denote the logical byte address LA and define it as follows: a = LA / 512 b = LA%512 c = a / 7 (integer division) d = a%7 Sector = c offset = d*512+b Metadata offset = 224*16+offset / 16

[0064] 4 is a block diagram showing an address mapping circuit 400 according to an embodiment of the present invention. The configuration of the address mapping circuit 400 is a direct realization of the address mapping procedure described above. Assume that the input logical address LA includes 25 bits. The divide-by-7 circuit 402 performs integer division of LA[24:9] (the most significant 16 bits) by 7 to generate a 14-bit sector number C, and the modulo-7 circuit 404 performs modulo division of LA[24:9] by 7 to generate a 3-bit D.

[0065] A first concatenation circuit 406 concatenates D with LA[8:0] (the 9 least significant bits of LA) to generate a 12-bit offset of the data string within the sector, and finally, a second concatenation circuit 408 concatenates 224*16 with the most significant 8 bits of the offset (offset[11:4]) to generate the offset of the corresponding metadata within the sector.

[0066] It should be noted that in an embodiment, the concatenated circuits 406 and 408 are simply assemblies of wires and do not include logic gates or other hardware circuitry.

[0067] 5 is a block diagram showing a schematic configuration of a divide-by-7 circuit 500 according to an embodiment of the present invention. According to an embodiment of the present invention, the input of the divide-by-7 circuit is designated X, where X is a 15-bit binary number.

[0068] The configuration of the divide-by-7 circuit 500 is a simple implementation of the divide-by-7 procedure described above for a 15-bit input. The divide-by-7 circuit includes a 5-input adder 502 that generates RES, a 2-input adder 504 that generates RES1, an AND gate 506 that detects RES&7==7, and a multiplexer 508 that selects either RES or RES1 according to the output of the AND gate 506.

[0069] 6 is a block diagram that shows a schematic configuration of a modulo 7 circuit 600 according to an embodiment of the present invention. The input of the modulo 7 circuit is denoted by X, which is a 15-bit binary number. The modulo 7 circuit comprises a 5-input adder 602 that generates RES, a 2-input adder 604 that generates RES1, a 2-input adder 606 that generates RES2, an AND gate 608 that detects RES2&7==7, and a multiplexer 610 that selects either RES2 or 0 according to the output of the AND gate 608. The modulo 7 output is the output of the multiplexer 610 (note that all adders add 3-bit numbers).

[0070] FIG. 7 is a flow chart 700 that outlines a method for efficiently computing a given modulo 7, according to one embodiment of the present invention. The flow chart is executed by the MAC 212 (FIG. 2). The flow chart begins with a get N operation 702, where the MAC receives a number N from a processor. Then, in a fragment operation 704, the MAC splits N into 3-bit fragments. Then, in a sum of fragments operation 706, the MAC accumulates all the fragments to get a new N with fewer bits. Then, in a check N size operation 708, the MAC checks whether the value of N is less than 8. If so, the MAC enters a check operation 710, where if N is equal to 7, the MAC corrects N (sets N to 0) and the flow chart ends.

[0071] At operation 708, if N is greater than or equal to 8 (ie, N is greater than 3 bits), then the MAC returns to operation 704 to further reduce the size of N.

[0072] As explained above, the choice of m=3 in the exemplary embodiments shown in Figures 6 and 7 is by way of example only. In other embodiments, circuits 500 and 600 can be modified for any suitable integer value of m.

[0073] The configurations of the address mapping circuit 400 including the divide-by-7 circuit 500, modulo-7 circuit 600, data storage and retrieval method 300, and modulo-7 method 700 are described as examples and are shown in Figs. 3-7. In other embodiments, other configurations and methods may be used. For example, in some embodiments, X includes more than 17 bits, and as a result, the adders of Figs. 1 and 5 and 6 include more inputs. In one embodiment, a single metadata byte is added to each 16-byte data string (allowing only single-bit error detection). 240 data strings and 240 metadata bytes are stored in a sector (leaving only 16 bytes unused). Since 240=15*16, the divide-by-15 and modulo-15 circuits are arranged and the circuits and methods are modified accordingly (the divide-by-7 and modulo-7 circuits described with reference to Figs. 5 and 6 are added to each 16-byte data string). n It can be extended to cover any divisor equal to -1 (e.g. 7, 15, 31, etc.).

[0074] Configurations of computer system 200 and storage device 204 including MAC 212, divide-by-7 circuit 500, modulo 7 circuit 600, address mapping 100, and methods of flowcharts 300 and 700 are described as examples and are shown in Figures 1 through 7. These example configurations and flowcharts are provided for conceptual understanding purposes only. Any other suitable configurations and flowcharts may be used in alternative embodiments.

[0075] The different sub-units of computing system 200, including memory device 204 and its sub-units, may be implemented using suitable hardware, such as, for example, one or more application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), using software, using hardware, or using a combination of hardware and software elements.

[0076] The processor 202 may comprise one or more general-purpose processors that are programmed with software to perform the functions described herein. The software may be downloaded to the processor in electronic form, for example, over a network or via a host. Alternatively, Alternatively or additionally, it may be provided and / or stored on a non-transitory tangible medium, such as a magnetic, optical, or electronic memory.

[0077] It will be understood that the above-described embodiments are cited by way of example, and the present invention is not limited to what has been specifically shown and described above. Indeed, the scope of the present invention includes both combinations and subcombinations of the various features described above, as well as variations and modifications thereof that would occur to a person skilled in the art upon reading the above specification and that are not disclosed in the prior art. Documents incorporated by reference into this application are considered to be an integral part of the application. However, to the extent that any term is defined in such incorporated documents as to be inconsistent with a definition expressly or impliedly made herein, only the definition in this specification shall be considered. [Industrial Applicability]

[0078] The present invention relates generally to non-volatile memory, and more particularly to a method and system for efficiently storing data and metadata in non-volatile memory. [Explanation of symbols]

[0079] 100: Address mapping 102: Logical address space 104: Physical Address Space 106: Sector 108: Data column 110: Metadata 200: Computer Systems 202: Processor 204: Storage device 206: Non-volatile memory (NVM) 208: Parity generation circuit 210: Error detection / correction circuit 212: Memory Access Control Circuit (MAC) 300, 700: Flowchart 302, 304, 306, 308, 310, 312, 314, 316, 318, 702, 704, 706, 708, 710: Operation 400: Address mapping circuit 402, 500: 7 frequency divider circuit 404: Modulo 7 circuit 406: First connecting circuit 408: Second connecting circuit 502, 602:5 input adder 504, 606:2 input adder 506, 608: AND gate 508, 610: Multiplexer 600: Modulo 7 circuit

Claims

1. a non-volatile memory (NVM) including a plurality of sectors; receiving a logical address of a block of data from the host; calculating a mapping from the logical address to a data physical address including a selected sector from the plurality of sectors and a selected data offset within the same selected sector; Calculating a metadata physical address including the selected sector and a metadata offset within the selected sector; a memory access circuit configured to access a data block at the data physical address and to access the metadata at the metadata physical address; Equipped with A storage device in which the size of each sector, in bytes, is an integer power of 2, and the number of data blocks in each sector is of the form (2 m -1)·2 n , where m and n represent integer values.

2. 2. The storage device of claim 1, wherein the memory access circuitry is configured to receive a write command and the data block from the host, and in response thereto, retrieve the metadata corresponding to the data block, store the data block in the NVM at the data physical address, and store the metadata in the NVM at the metadata physical address.

3. 2. The storage device of claim 1, wherein the memory access circuitry is configured to receive a read command from a processor and, in response thereto, read the data block stored at the data physical address of the NVM and read the metadata stored at the metadata physical address of the NVM.

4. The memory access circuit performs integer division of a given input by (2 ｍ -1) was designed to calculate (2 ｍ -1) Equipped with a division circuit; The memory access circuit assigns the logical address to the ｍ 1) The storage device of claim 1, configured to calculate the mapping of the logical addresses to the data physical addresses by applying a division circuit.

5. The above (2 ｍ -1) The division circuit is Computing a shift-and-add sum of (i) the given input and (ii) the given input shifted left by an integer multiple of m bits; Repeating the calculation of the shift-and-add sum d times according to the required accuracy; truncate the (d-1)m least significant bits of said sum to obtain a result, said result being 2 ｍ If it is equal to -1, the result is 2 ｍ Add up The m least significant bits are truncated to obtain the (2 ｍ 5. The storage device of claim 4, configured to calculate the integer division by -1.

6. The memory access circuitry performs a modulo (2 ｍ Modulo (2 −1), designed to calculate ｍ -1) comprising a circuit; The memory access circuit multiplies the logical address by the modulo (2 ｍ 1) The storage device of claim 1, configured to calculate the data offset and the metadata offset by applying a circuit.

7. The modulo (2 ｍ -1) A circuit receives an input number and recursively (i) divides the input number into a set of m-bit fragments, (ii) adds the m-bit fragments together to obtain an output number that is less than the input number, and (iii) determines whether the output number is greater than or equal to 2 ｍ The storage device of claim 6 , configured to repeat steps (i) and (ii) until the memory capacity is less than 100 Mbps.

8. The storage device of claim 4 , wherein m=3.

9. 1. A method for accessing a non-volatile memory (NVM) comprising a plurality of sectors, comprising: receiving a logical address of a block of data from the host; calculating a mapping from the logical address to a data physical address including a selected sector from the plurality of sectors and a selected data offset within the same selected sector; Calculating a metadata physical address including the selected sector and a metadata offset within the selected sector; accessing the data block at the data physical address and accessing the metadata at the metadata physical address; A method, wherein the size of each sector is an integer power of 2 in bytes, and the number of data blocks in each sector is of the form (2 m -1)·2 n , where m and n represent integer values.

10. 10. The method of claim 9, wherein accessing the data block and the metadata comprises receiving a write command and the data block from the host, and in response, obtaining the metadata corresponding to the data block, storing the data block in the NVM at the data physical address, and storing the metadata in the NVM at the metadata physical address.

11. 10. The method of claim 9, wherein accessing the data block and the metadata includes receiving a read command from a processor and, in response thereto, reading the data block stored in the NVM at the data physical address and reading the metadata stored in the NVM at the metadata physical address.

12. The calculation of the mapping of the logical address to the data physical address is performed by multiplying the logical address by (2 ｍ It was designed to calculate integer division by (2 -1). ｍ The method of claim 9, further comprising:-1) applying a division circuit.

13. Computing a shift-and-add sum of (i) the given input and (ii) the given input shifted left by an integer multiple of m bits; Repeating the calculation of the shift-and-add sum d times according to the required accuracy; truncate the (d-1)m least significant bits of said sum to obtain a result, said result being 2 ｍ If it is equal to -1, the result is 2 ｍ Add up The m least significant bits are truncated to obtain the (2 ｍ 13. The method of claim 12, further comprising calculating the integer division by -1).

14. The calculation of the data offset and the metadata offset is done by multiplying the modulo (2 ｍ Modulo (2 −1), designed to calculate ｍ 10. The method of claim 9, further comprising: 1) applying a circuit to said logical address.

15. A method for implementing the method of the present invention comprising the steps of: receiving an input number; and recursively (i) dividing the input number into a set of m-bit fragments; (ii) adding the m-bit fragments together to obtain an output number that is less than the input number; and (iii) determining whether the output number is less than 2 ｍ Repeating steps (i) and (ii) until modulo (2 ｍ 15. The method of claim 14, comprising calculating:

16. 10. The method of claim 9, wherein m=3.

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