MEMORY SYSTEM AND METHOD

Abstract

To control numbers of bits for values to be written per one memory cell so as to increase performance as much as possible.SOLUTION: A controller of a memory system writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits greater than the first number per memory cell to a plurality of third blocks among a plurality of first blocks included in a flash memory. The controller writes data from a host device to the plurality of second blocks, and transcribes valid data from the plurality of second blocks to the plurality of third blocks. The controller controls the number of second blocks in the plurality of first blocks according to an order of completion of the data writing to each of one or more third blocks that are completed being written, and an amount of valid data stored in each of the one or more third blocks that are completed being written.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present embodiments relate to a memory system and method. [Background technology]

[0002] Conventionally, there is known a memory system in which the number of bits of a value written to each memory cell is variable. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-26448 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment aims to provide a memory system and method for controlling the number of bits of a value written per memory cell to maximize performance. [Means for solving the problem]

[0005] A memory system according to one embodiment is connectable to a host device. The memory system includes a flash memory including a plurality of first blocks, and a controller. Each of the plurality of first blocks includes a plurality of memory cells. Each of the plurality of first blocks can be written in a first mode or a second mode. The first mode is a mode in which a first number of bit values ​​are written per memory cell, and the second mode is a mode in which a second number of bit values ​​are written per memory cell. The second number is greater than the first number. The controller uses a plurality of second blocks that are a part of the plurality of first blocks in the first mode, and uses a plurality of third blocks that are another part of the plurality of first blocks in the second mode. The controller writes data from the host device to the plurality of second blocks sequentially, and executes a first transcription process and a second transcription process. The first transcription process is a process for selecting one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and sequentially writing all valid data in the selected second block to the plurality of third blocks, thereby making the selected second block reusable. The second transcription process is a process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block reusable. The controller When a third block having a minimum amount of valid data stored therein is present among a third number of third blocks for which writing has been completed most recently among the one or more third blocks for which writing has been completed, the number of second blocks among the plurality of first blocks is increased. . [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a memory system according to a first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing an example of the configuration of a memory chip according to the first embodiment. [Diagram 3] FIG. 2 is a schematic diagram showing a circuit configuration of a block BLK according to the first embodiment. [Figure 4] 4A to 4C are diagrams for explaining divisions of the first embodiment in each of the cases of SLC mode, MLC mode, TLC mode, and QLC mode. [Diagram 5] FIG. 4 is a diagram showing an example of a state transition of a block BLK according to the first embodiment. [Figure 6] FIG. 4 is a schematic diagram for explaining a first transcription process and a second transcription process according to the first embodiment. [Figure 7] 5A and 5B are schematic diagrams for explaining an example of a method for determining an increase in a ratio of hot data included in host data according to the first embodiment. [Figure 8] FIG. 11 is a schematic diagram for explaining another example of the method for determining an increase in the ratio of hot data included in host data according to the first embodiment. [Figure 9] 5A and 5B are schematic diagrams for explaining an example of a method for determining an increase in a ratio of cold data included in host data according to the first embodiment. [Figure 10] FIG. 11 is a schematic diagram for explaining another example of the method for determining an increase in the ratio of cold data included in host data according to the first embodiment. [Figure 11] 11 is a flowchart illustrating an example of an execution timing of a first transcription process according to the first embodiment. [Figure 12] 10 is a flowchart illustrating an example of an execution timing of a second transcription process according to the first embodiment. [Figure 13] 5 is a flowchart illustrating a method for controlling the number of SLC blocks according to the first embodiment. [Figure 14] 13 is a schematic diagram for explaining an example of the relationship between the host write amount and the transcription write amount when the rate of hot data included in the host data is relatively high in the memory system according to the second embodiment; [Figure 15] 13 is a schematic diagram for explaining an example of the relationship between the host write amount and the transcription write amount when the ratio of cold data is relatively high in the memory system according to the second embodiment; [Figure 16]10 is a flowchart illustrating a method for controlling the number of SLC blocks according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a memory system and a method according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0008] (First embodiment) FIG. 1 is a schematic diagram showing an example of a configuration of a memory system 1 according to the first embodiment.

[0009] The memory system 1 is connected to a host device 2 via a communication interface 3. The host device 2 is a processor included in an information processing device. The information processing device is a computer such as a laptop personal computer, a mobile phone, a smartphone, a portable music player, or an imaging device. The memory system 1 is, for example, an SSD (Solid State Drive). The standard of the communication interface 3 is not limited to a specific standard.

[0010] The memory system 1 receives an access command (e.g., a write command or a read command) from the host device 2. In response to the write command, the memory system 1 stores user data for which writing is requested. In response to the read command, the memory system 1 transmits user data for which reading is requested to the host device 2.

[0011] The access command includes a logical address. The memory system 1 provides a logical address space to the host device 2. The logical address indicates a location in the address space. The host device 2 uses the logical address to specify a location to write user data or a location to read user data. In other words, the logical address is location information specified by the host device 2.

[0012] The memory system 1 includes a controller 100 and a NAND memory 200. The controller 100 is connected to the NAND memory 200 via a memory bus 300. The NAND memory 200 is an example of a non-volatile memory.

[0013] The controller 100 controls the NAND memory 200 .

[0014] The controller 100 writes data requested to be written by the host device 2 to the NAND memory 200, and reads data requested to be read by the host device 2 from the NAND memory 200 and sends the data to the host device 2. In other words, the controller 100 executes data transfer between the host device 2 and the NAND memory 200.

[0015] Writing data requested to be written by the host device 2 to the NAND memory 200 for the first time after receiving the data from the host device 2 is referred to as host write. Data written to the NAND memory 200 by the host write is referred to as host data. The amount of host data written to the NAND memory 200 per unit time is referred to as the host write amount. The unit time for obtaining the host write amount and the transcription write amount described below can be arbitrarily set by the designer.

[0016] Furthermore, the controller 100 executes a transcription process to transcribe data within the NAND memory 200. The transcription process may also be referred to as garbage collection.

[0017] The transfer process includes a process of reading data from the NAND memory 200 and a process of writing the read data to the NAND memory 200. A process of writing data to the NAND memory 200 as part of the transfer process is referred to as a transfer write. Moreover, data written to the NAND memory 200 by the transfer write is referred to as a transfer data. Moreover, the amount of transfer data written to the NAND memory 200 per unit time is referred to as a transfer write amount. A more detailed explanation of the transfer process will be given later.

[0018] Furthermore, the controller 100 can change the setting of the number of bits of the value written per memory cell. The setting of the number of bits of the value written per memory cell is referred to as a memory mode. The possible memory modes and the method of controlling the memory modes will be described later.

[0019] The controller 100 includes a processor 101, a host interface circuit (host I / F) 102, a RAM (Random Access Memory) 103, a buffer memory 104, a memory interface circuit (memory I / F) 105, and an internal bus 106. The processor 101, the host I / F 102, the RAM 103, the buffer memory 104, and the memory I / F 105 are electrically connected to the internal bus 106.

[0020] The controller 100 may be configured as a system-on-a-chip (SoC). Alternatively, the controller 100 may be configured with multiple chips. The RAM 103 or the buffer memory 104 may be disposed outside the controller 100.

[0021] The host I / F 102 receives access commands, data, and the like from the host device 2. In addition, the host I / F 102 transmits to the host device 2 data read from the NAND memory 200, responses to the access commands, and the like.

[0022] The buffer memory 104 is a memory that functions as a buffer for data transfer between the host device 2 and the NAND memory 200. The buffer memory 104 is configured by a volatile memory such as a static random access memory (SRAM) or a synchronous dynamic random access memory (SDRAM). Note that the type of memory that configures the buffer memory 104 is not limited to these. The buffer memory 104 may be configured by any type of non-volatile memory.

[0023] The memory I / F 105 controls the process of writing data and the like to the NAND memory 200 and the process of reading data and the like from the NAND memory 200 based on instructions from the processor 101.

[0024] The processor 101 is a circuit that can execute a computer program. The processor 101 is, for example, a CPU (Central Processing Unit). The processor 101 comprehensively controls each component of the controller 100 based on a firmware program that has been stored in advance in a predetermined location (for example, the NAND memory 200), thereby realizing the various operations of the controller 100 described above.

[0025] Note that some or all of the processes executed by the processor 101 may be executed by a hardware circuit, or some or all of the processes executed by the processor 101 may be executed by a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0026] The RAM 103 is a memory that can be used by the processor 101 as a cache memory or a working memory. The RAM 103 is configured by a dynamic random access memory (DRAM), an SRAM, or a combination of these. Note that the types of memory that configure the RAM 103 are not limited to these.

[0027] The controller 100 may include any other components instead of or in addition to these components. For example, the controller 100 may include a circuit for encoding data to be written to the NAND memory 200 and for decoding data read from the NAND memory 200. The RAM 103 may be used as a buffer memory, and the buffer memory 104 may be omitted.

[0028] The NAND memory 200 is a NAND type flash memory capable of non-volatilely storing user data, etc. The NAND memory 200 is composed of one or more memory chips 201. Here, the NAND memory 200 is composed of four memory chips 201-0, 201-1, 201-2, and 201-3. The NAND memory 200 is an example of a flash memory.

[0029] 2 is a schematic diagram showing an example of a configuration of a memory chip 201 according to the first embodiment. The memory chip 201 includes a peripheral circuit 210 and a memory cell array 211.

[0030] The memory cell array 211 includes a plurality of blocks BLK (BLK0, BLK1, BLK2, ...). Each block BLK includes a plurality of string units SU (SU0, SU1, SU2, ...). Each string unit SU is a collection of NAND strings in which a plurality of nonvolatile memory cell transistors are connected in series. The number of NAND strings 212 in a string unit SU is arbitrary.

[0031] The peripheral circuit 210 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generating circuit. In response to an instruction from the controller 100, the peripheral circuit 210 executes an operation corresponding to the instruction on the memory cell array 211. The instruction from the controller 100 includes write, read, and erase.

[0032] 3 is a schematic diagram showing a circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. The block BLK has, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings 212.

[0033] Each of the NAND strings 212 includes, for example, 64 memory cell transistors MT (MT0 to MT63) and select transistors ST1 and ST2. The memory cell transistors MT include a control gate and a charge storage layer, and store data in a non-volatile manner. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The memory cell transistors MT may be of a MONOS type that uses an insulating film for the charge storage layer, or may be of an FG type that uses a conductive film for the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 212 is not limited to 64.

[0034] The gates of the select transistors ST1 in each of the string units SU0 to SU3 are connected to the respective select gate lines SGD0 to SGD3. In contrast, the gates of the select transistors ST2 in each of the string units SU0 to SU3 are commonly connected to, for example, a select gate line SGS. The gates of the select transistors ST2 in each of the string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 (not shown) for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 in the same block BLK are commonly connected to the respective word lines WL0 to WL63.

[0035] The drains of the select transistors ST1 of the NAND strings 212 in the string units SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number equal to or greater than 2). The bit lines BL commonly connect one NAND string 212 in each string unit SU across multiple blocks BLK. Furthermore, the sources of the select transistors ST2 are commonly connected to a source line SL.

[0036] That is, a string unit SU is a set of multiple NAND strings 212 each connected to a different bit line BL and connected to the same select gate line SGD. A block BLK is a set of multiple string units SU that share a word line WL. The memory cell array 211 is a set of multiple blocks BLK that share at least one bit line BL.

[0037] The peripheral circuit 210 can collectively write and read data to the memory cell transistors MT connected to one word line WL in one string unit SU. A group of memory cell transistors MT selected collectively during writing and reading is referred to as a memory cell group MCG. A unit of a collection of 1-bit data written to or read from one memory cell group MCG is referred to as a page.

[0038] The erasure by the peripheral circuit 210 is performed in units of blocks BLK, that is, all data stored in one block BLK is erased collectively.

[0039] The configuration of the memory cell array 211 is not limited to the configuration shown in Figures 2 and 3. For example, the memory cell array 211 may have a configuration in which the NAND strings 212 are arranged two-dimensionally or three-dimensionally.

[0040] In writing to the memory cell array 211, the peripheral circuit 210 injects an amount of charge corresponding to the data into the charge storage layer of each memory cell transistor MT constituting the page of the write destination. In reading from the memory cell array 211, the peripheral circuit 210 reads data corresponding to the amount of charge stored in the charge storage layer from each memory cell transistor MT constituting the page of the read destination.

[0041] A value of n (n≧1) bits can be written to each memory cell transistor MT. A mode where n is 1 is called SLC (Single Level Cell) mode. When an n-bit value is written to each memory cell transistor MT, the storage capacity per memory cell group MCG is equal to the size of n pages. A mode where n is 2 is called MLC (Multi Level Cell) mode. A mode where n is 3 is called TLC (Triple Level Cell) mode. A mode where n is 4 is called QLC (Quad Level Cell) mode.

[0042] The threshold voltage of each memory cell transistor MT is controlled within a certain range by the peripheral circuit 210. The controllable range of the threshold voltage is divided into a number of sections equal to the nth power of 2, and a different n-bit value is assigned to each section.

[0043] 4 is a diagram for explaining divisions of the first embodiment in each of the cases of the SLC mode, the MLC mode, the TLC mode, and the QLC mode. As shown in FIG. 4, the range of the threshold voltage (controllable range) is divided into a plurality of divisions 4.

[0044] For example, in SLC mode, the threshold voltage range is divided into two segments 4a, in MLC mode, the threshold voltage range is divided into four segments 4b, in TLC mode, the threshold voltage range is divided into eight segments 4c, and in QLC mode, the threshold voltage range is divided into sixteen segments 4d.

[0045] The more bits of a value stored in one memory cell, the narrower the range of each division 4. Each division 4 is assigned a value with the corresponding number of bits. In SLC mode, the division 4a on the low voltage side is assigned a "1", and the division 4a on the high voltage side is assigned a "0". In MLC mode, the four divisions 4b are assigned "11", "01", "00", and "10", respectively, in order of voltage. In TLC mode, the eight divisions 4c are assigned "111", "101", "001", "011", "010", "110", "100", and "000", respectively, in order of voltage. In QLC mode, the following values ​​are assigned to the 16 divisions 4d in voltage order: "1111", "1011", "0011", "0001", "1001", "1101", "0101", "0111", "0110", "1110", "1010", "1000", "1100", "0100", "0000", and "0010". Note that the method of assigning values ​​to each division 4 is not limited to these examples.

[0046] In writing to the memory cell array 211, the peripheral circuit 210 injects, into the charge storage layer of each memory cell transistor MT constituting the write destination page, an amount of charge corresponding to the division 4 to which the value to be written is assigned. In reading from the memory cell array 211, the peripheral circuit 210 determines the division 4 to which the threshold voltage of each memory cell transistor MT constituting the read destination page belongs, and outputs the value assigned to the division 4 obtained by the determination as read data.

[0047] When erasing the memory cell array 211, the peripheral circuit 210 applies an erase voltage to the substrate side of the memory cell array 211. Then, the peripheral circuit 210 connects all the word lines WL of the block BLK to be erased to the ground potential. Then, the charge stored in the charge storage layer of each memory cell transistor MT in the selected block BLK is discharged. As a result, the state of each memory cell transistor MT in the selected block BLK transitions to a state in which data is considered to have been erased (i.e., section 4 on the lowest voltage side).

[0048] The memory system 1 is configured to be able to set or change the storage mode. More specifically, the processor 101 sets or changes the storage mode of each block BLK between a first mode in which a first number of bit values ​​are written per memory cell, and a second mode in which a second number of bit values ​​(where the second number is greater than the first number) are written per memory cell. In the following description, the first mode is the SLC mode, and the second mode is the TLC mode. Note that the first mode and the second mode are not limited to this example. Also, the minimum unit of storage area in which the storage mode is individually set is not limited to the block BLK. For example, the storage mode may be individually set in units of logical blocks including a plurality of blocks BLK.

[0049] Next, the state transition of the block BLK will be described. Fig. 5 is a diagram showing an example of the state transition of the block BLK according to the first embodiment. The hatched arrows indicate the direction of the state transition of the block BLK, and the solid arrows indicate the direction of data movement.

[0050] The state of a block BLK can be at least an open block, an active block, and a free block. Hereinafter, an open block may mean a block BLK in an open block state. An active lock may mean a block BLK in an active lock state. A free block may mean a block BLK in a free block state.

[0051] An open block is a block BLK in which data is being written but the writing has not been completed, that is, an open block is a block BLK in which there remains an area in which data can be written.

[0052] An active block is a block BLK for which writing has been completed. An active block is also a block BLK that cannot yet be reused. Of the blocks BLK for which writing has been completed, a block BLK in which valid user data is stored is managed as an active block. Reusing refers to transitioning the block BLK to an open block.

[0053] A free block is a block BLK in which no valid data is stored and which can be reused.

[0054] For example, after one block of data BLK is written to an open block, the open block transitions to an active block. The state of the data stored in an active block is either a valid state or an invalid state.

[0055] When certain data (referred to as first data) is stored in an active block, and second data is sent from the host device 2 specifying the same logical address value as the logical address value specified when the first data was sent, the controller 100 writes the second data to an empty page of an open block, and manages the first data stored in the active block as invalid data. Thus, the data stored in the active block may be a mixture of valid data and invalid data.

[0056] Note that the host device 2 sending new data by specifying the same logical address value as the logical address value specified when sending old data to the memory system 1 is referred to as rewrite.

[0057] An active block transitions to a free block through a transcription process. A transcription process is a process in which valid data stored in an active block is transcribed to an open block, and all data stored in the original active block is invalidated. As a result, the original active block transitions to a free block. Note that transcription can also be referred to as transfer, relocation, or movement.

[0058] After the data stored in a free block is erased, the free block transitions to an open block.

[0059] In addition, data being valid means that the location where the data is stored corresponds to any logical address value. Data being invalid means that the location where the data is stored does not correspond to any logical address value. In addition, the "empty" state here means that neither invalid data nor valid data is stored. That is, an empty page is a free area where data can be written. In addition, the correspondence between the location in the block BLK and the logical address value is maintained and updated by the controller 100.

[0060] The host data and the transcription data may both be written to a common open block. Alternatively, an open block to which the host data is written and an open block to which the transcription data is written may be prepared separately. As an example, it is assumed here that the host data and the transcription data are both written to a common open block.

[0061] In a memory system 1 where a host write has never been executed, all blocks BLK except for open blocks are in a free block state. When a host write is started, a transition from an open block to an active block and a transition from a free block to an open block are started. Therefore, the number of active blocks increases and the number of free blocks decreases. When the free blocks are exhausted, a transfer process is started to maintain the number of free blocks at or above an allowable lower limit, for example, one. Through the transfer process, the block BLK that was an active block becomes a new free block.

[0062] In the first embodiment, the transcription process includes a first transcription process and a second transcription process. Fig. 6 is a schematic diagram for explaining the first transcription process and the second transcription process according to the first embodiment.

[0063] 6, some of the blocks BLK included in the NAND memory 200 are used in the SLC mode, and the other blocks BLK are used in the TLC mode. The blocks BLK used in the SLC mode are referred to as SLC blocks. The blocks BLK used in the TLC mode are referred to as TLC blocks.

[0064] The blocks BLK included in the NAND memory 200 are an example of a plurality of first blocks, the group of SLC blocks is an example of a plurality of second blocks, and the group of TLC blocks is an example of a plurality of third blocks.

[0065] Each of the SLC block group and the TLC block group includes an open block and one or more free blocks. In each of the SLC block group and the TLC block group, the number of free blocks is maintained at or above a permitted lower limit. In the example shown in FIG. 6, the permitted lower limit of the number of free blocks is set to 1.

[0066] Additionally, each of the groups of SLC blocks and the groups of TLC blocks may include one or more active blocks.

[0067] Hereinafter, an SLC block in open block state will be referred to as an SLC open block. An SLC block in active block state will be referred to as an SLC active block. An SLC block in free block state will be referred to as an SLC free block. A TLC block in open block state will be referred to as a TLC open block. A TLC block in active block state will be referred to as a TLC active block. A TLC block in free block state will be referred to as a TLC free block.

[0068] The fewer the number of bits of data stored in one memory cell, the shorter the time required to write and read data. In other words, data writing is completed faster in SLC mode than in TLC mode. Therefore, in order to improve the throughput of the memory system 1 as seen from the host device 2, the controller 100 writes host data to an SLC block, more specifically, an SLC open block.

[0069] When the SLC open block is filled with host data, the write to the SLC open block is considered to be completed. When the write to the SLC open block is completed, the SLC open block transitions to an SLC active block, and one of the SLC free blocks transitions to a new SLC open block. Then, when the number of SLC free blocks reaches an allowable lower limit, for example, 1 here, any one of the SLC active blocks is selected, and valid data in the selected SLC active block is moved to a TLC open block by a first transfer process. The selected SLC active block transitions to an SLC free block. In other words, the first transfer process is a process of moving valid data from the SLC active block to the TLC open block to generate an SLC free block.

[0070] When the TLC open block is filled with transcription data, writing to the TLC open block is considered to be completed. When writing to the TLC open block is completed, the TLC open block transitions to a TLC active block, and one of the TLC free blocks transitions to a new TLC open block. Then, when the number of TLC free blocks reaches an allowable lower limit, for example, 1 here, any one of the TLC active blocks is selected, and valid data in the selected TLC active block is moved to the TLC open block by a second transcription process. The selected TLC active block transitions to a TLC free block. In other words, the second transcription process is a process of moving valid data from the TLC active block to the TLC open block to generate a TLC free block.

[0071] In the first transcription process, the SLC active block with the least amount of valid data stored therein is selected as the transcription source SLC active block so that the transcription write amount is as small as possible. Typically, the SLC active block with the least amount of valid data stored therein is selected as the transcription source SLC active block.

[0072] Similarly, in the second transcription process, a TLC active block with as little valid data stored therein as possible is selected as the transcription source TLC active block so as to minimize the transcription write amount. Typically, a TLC active block with the least amount of valid data stored therein is selected as the transcription source TLC active block.

[0073] Hereinafter, when data in block BLK is mentioned, this data means valid data. Similarly, when data to be transferred by a transfer process is mentioned, this data means valid data.

[0074] Execution of the transcription process, i.e., the first transcription process and the second transcription process, affects the performance of the memory system 1. For example, the more frequently the transcription process is executed, the more hardware resources, such as the processor 101 or buses (the internal bus 106 and the memory bus 300), are allocated to the transcription process, and this reduces the throughput as seen from the host device 2. Also, the more frequently the transcription process is executed, the more the number of times write / erase is executed for the NAND memory 200, and this speeds up the degradation of the NAND memory 200. Also, the more the NAND memory 200 deteriorates, the less reliable the data stored in the NAND memory 200 becomes. For these reasons, it is desirable to suppress the frequency of execution of the transcription process as much as possible.

[0075] According to the operation shown in Fig. 6, data written to an SLC block is either transcribed to a TLC block by a first transcription process or invalidated by rewriting. Therefore, the frequency of execution of the first transcription process is affected by the frequency of rewriting of data sent from the host device 2 to the memory system 1. The frequency of rewriting of data sent from the host device 2 to the memory system 1 differs for each data. The state of data that tends to be rewritten in a short period of time is referred to as hot. The state of data that tends not to be rewritten for a long period of time is referred to as cold.

[0076] For example, there is a case where hot data in an SLC block becomes invalid due to a new rewrite before it becomes the target of the first transcription process. The case where data in an SLC block becomes invalid due to a new rewrite before it becomes the target of the first transcription process is referred to as the first case. The more frequently the first case occurs, the more the frequency of execution of the first transcription process is suppressed.

[0077] On the other hand, the first case is less likely to occur for cold data in an SLC block. In other words, the cold data in an SLC block is more likely to be moved to a TLC block by the first transcription process. The case in which data in an SLC block is moved to a TLC block by the first transcription process is referred to as the second case. The more frequently the second case occurs, the more frequently the first transcription process is executed.

[0078] The cold data in the TLC block may be subject to a second transcription process until it is invalidated by a new rewrite. The frequency of the second transcription process varies depending on the ratio of the total amount of cold data stored in the group of TLC blocks to the total capacity of the group of TLC blocks. The higher the ratio of the total amount of cold data stored in the group of TLC blocks to the total capacity of the group of TLC blocks, the higher the frequency of the second transcription process tends to be.

[0079] Increasing the number of SLC blocks increases the frequency of the first case, which reduces the frequency of the first transcription process. However, increasing the number of SLC blocks reduces the total capacity of the TLC block group by three times the capacity of the increased SLC blocks. The reduction in the total capacity of the TLC block group increases the ratio of the total amount of cold data stored in the TLC block group to the number of TLC blocks, which results in a higher frequency of the second transcription process.

[0080] Therefore, if the number of SLC blocks is too large, the frequency of transcription processing cannot be suppressed, and if the number of SLC blocks is too small, the frequency of transcription processing cannot be suppressed. In other words, in order to suppress the frequency of transcription processing, it is necessary to set the number of SLC blocks appropriately.

[0081] Furthermore, the appropriate number of SLC blocks for suppressing the frequency of execution of the transcription process also depends on the relationship between the amount of hot data and the amount of cold data contained in the host data.

[0082] For example, when the host data contains a large proportion of hot data, the benefit of reducing the frequency of execution of the first transfer process by increasing the number of SLC blocks is greater than when the host data contains a small proportion of hot data, and the drawback of increasing the frequency of execution of the second transfer process by reducing the total capacity of the group of TLC blocks is smaller. Therefore, when the host data contains a large proportion of hot data, the frequency of execution of the transfer process can be efficiently suppressed by allocating a larger number of blocks BLK as SLC blocks.

[0083] Conversely, when the proportion of cold data contained in the host data is high, the benefit of reducing the frequency of execution of the first transfer process by increasing the number of SLC blocks is small, and the disadvantage of increasing the frequency of execution of the second transfer process by reducing the total capacity of the group of TLC blocks is large, compared to when the proportion of cold data contained in the host data is low. Therefore, when the proportion of cold data contained in the host data is high, the frequency of execution of the transfer process can be efficiently suppressed by allocating a smaller number of blocks BLK as SLC blocks.

[0084] In the first embodiment, the processor 101 controls the number of SLC blocks so that the frequency of execution of the transcription process can be reduced as much as possible even if the ratio of the amount of hot data and the amount of cold data contained in the host data changes. A method for controlling the number of SLC blocks will be described below. The ratio of the amount of hot data and the amount of cold data contained in the host data is referred to as the data composition ratio.

[0085] When the data composition ratio remains constant for a predetermined time, the block BLK that transitioned to the active block earlier tends to have a smaller amount of valid data stored in it. Therefore, when the data composition ratio remains constant for a predetermined time, the TLC active block that transitioned to the active block the oldest is likely to be selected as the transcription source for the second transcription process.

[0086] However, when the ratio of hot data included in the host data increases, the tendency that the amount of valid data stored in a block BLK that has been transitioned to an active block earlier is broken. When the ratio of hot data included in the host data increases, the amount of hot data transferred to a TLC block by the first transcription process before being rewritten increases. The hot data in a TLC block is invalidated by rewriting at a relatively early timing after the TLC block transitions to an active block. Therefore, the amount of valid data decreases at a high speed in a TLC block to which a lot of hot data has been written by the first transcription process. As a result, there occurs a case where the amount of valid data stored in a TLC block that has been transitioned to an active block relatively recently is less than the amount of valid data stored in a TLC block that has been transitioned to an active block earlier. This case is referred to as the third case.

[0087] When the third case occurs, it can be estimated that the ratio of hot data contained in the host data has increased. Therefore, in the first embodiment, the increase in the ratio of hot data contained in the host data is determined by detecting the occurrence of the third case. That is, when the occurrence of the third case is detected, the processor 101 increases the number of SLC blocks. The processor 101 increases the number of SLC blocks by reducing the amount of blocks BLK allocated to TLC blocks among the multiple blocks BLK included in the NAND memory 200 and increasing the amount of blocks BLK allocated to SLC blocks.

[0088] FIG. 7 is a schematic diagram for explaining an example of a method for determining an increase in the ratio of hot data included in host data according to the first embodiment. Blocks BLK11 to BLK18 shown in this diagram are active blocks included in a group of TLC blocks, i.e., TLC active blocks. Blocks BLK11 to BLK18 are arranged in the order of the timing of transition to active blocks. It can be seen from this diagram that blocks BLK11, BLK12, BLK13, BLK14, BLK15, BLK16, BLK17, and BLK18 transitioned to active blocks in this order. The area of ​​the shaded portion of the rectangle representing blocks BLK11 to BLK18 represents the amount of valid data stored in each block BLK.

[0089] The processor 101 sets the value Rth1 in advance. The value Rth1 is an integer equal to or greater than 2. The value Rth1 is an example of a third number. A method for setting the value Rth1 will be described later. The processor 101 determines whether or not a TLC active block with the smallest amount of valid data stored exists among the Rth1 TLC active blocks that have most recently transitioned to the active block. The existence of a TLC active block with the smallest amount of valid data stored exists among the Rth1 TLC active blocks that have most recently transitioned to the active block corresponds to the third case. Therefore, when a TLC active block with the smallest amount of valid data stored exists among the Rth1 TLC active blocks that have most recently transitioned to the active block, the processor 101 increases the number of SLC blocks. When a TLC active block with the smallest amount of valid data stored does not exist among the Rth1 TLC active blocks that have most recently transitioned to the active block, the processor 101 does not increase the number of SLC blocks.

[0090] 7, the value Rth1 is "3". The three TLC active blocks that have most recently transitioned to active blocks, namely, blocks BLK16 to BLK18, include block BLK17, which is the TLC active block that stores the smallest amount of valid data. Therefore, the processor 101 increases the number of SLC blocks.

[0091] When the ratio of hot data increases rapidly, the TLC block with the smallest amount of stored valid data appears among the TLC blocks that have transitioned to active blocks relatively recently, as in the example shown in Fig. 7. However, when the rate of increase in the ratio of hot data is gradual, the TLC block with the smallest amount of stored valid data does not necessarily appear among the TLC blocks that have transitioned to active blocks relatively recently. A method for determining the increase in the ratio of hot data even when the rate of increase in the ratio of hot data is gradual will be described with reference to Fig. 8.

[0092] FIG. 8 is a schematic diagram for explaining another example of a method for determining an increase in the ratio of hot data included in host data according to the first embodiment. Blocks BLK21 to BLK28 shown in this diagram are active blocks included in a group of TLC blocks, i.e., TLC active blocks. Blocks BLK21 to BLK28 are arranged in the order of the timing of transition to active blocks. It can be seen from this diagram that blocks BLK21, BLK22, BLK23, BLK24, BLK25, BLK26, BLK27, and BLK28 transitioned to active blocks in this order. The area of ​​the shaded parts of the rectangles representing blocks BLK21 to BLK28 represents the amount of valid data stored in each block BLK.

[0093] The processor 101 sets the value Rth1 in advance and obtains the value Ath1 in advance. The value Ath1 is an example of a first threshold value. The value Ath1 may be a fixed value set by a designer, or may be calculated by the processor 101 based on a predetermined calculation. The processor 101 judges whether or not there is a TLC active block in which the amount of valid data stored is less than the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to the active block. If there is a TLC active block in which the amount of valid data stored is relatively small, even if it is not the smallest, among the Rth1 TLC active blocks that have most recently transitioned to the active block, this may correspond to the third case. Therefore, if there is a TLC active block in which the amount of valid data stored is less than the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to the active block, the processor 101 increases the number of SLC blocks. If there is no TLC active block in which the amount of valid data stored is less than the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to active blocks, the processor 101 does not increase the number of SLC blocks.

[0094] 8, the value Rth1 is "3." The three TLC active blocks that have most recently transitioned to active blocks, namely, blocks BLK26 to BLK28, include block BLK27, which is a TLC active block in which the amount of valid data stored is less than the value Ath1. Therefore, the processor 101 increases the number of SLC blocks.

[0095] In addition, the process when there is a TLC active block in which the amount of valid data stored is equal to the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to active blocks is not limited to the above example. When there is a TLC active block in which the amount of valid data stored is equal to or less than the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to active blocks, the processor 101 increases the number of SLC blocks, and when there is no TLC active block in which the amount of valid data stored is equal to or less than the value Ath1 among the Rth1 TLC active blocks that have most recently transitioned to active blocks, the processor 101 does not need to increase the number of SLC blocks.

[0096] When the proportion of cold data contained in the host data increases, the amount of data transcribed to the TLC blocks by the second transcription process increases. This increases the ratio of the total amount of cold data stored in the group of TLC blocks to the total capacity of the group of TLC blocks. When the ratio of the total amount of cold data stored in the group of TLC blocks to the total capacity of the group of TLC blocks increases, the amount of valid data stored in the transcription source of the second transcription process, i.e., the TLC active block that stores the least amount of valid data, increases. This increases the amount of transcription writes required to generate one TLC free block. In other words, the frequency of execution of the second transcription process increases.

[0097] FIG. 9 is a schematic diagram for explaining an example of a method for determining an increase in the proportion of cold data included in host data according to the first embodiment. Blocks BLK31 to BLK38 shown in this diagram are active blocks included in a group of TLC blocks, i.e., TLC active blocks. Blocks BLK31 to BLK38 are arranged in the order of the timing of transition to active blocks. It can be seen from this diagram that blocks BLK31, BLK32, BLK33, BLK34, BLK35, BLK36, BLK37, and BLK38 transitioned to active blocks in this order. The area of ​​the shaded portion of the rectangle representing blocks BLK31 to BLK38 represents the amount of valid data stored in each block BLK.

[0098] The processor 101 obtains the value Ath2 in advance. The value Ath2 is an example of a second threshold value. The value Ath2 may be a fixed value set by a designer, or may be calculated by the processor 101 based on a predetermined calculation. The processor 101 determines whether the amount of valid data stored in the TLC active block that transitioned to the active block oldest is equal to or greater than the value Ath2.

[0099] As described above, when the data composition ratio remains constant for a certain period of time, the block BLK that transitioned to the active block earlier tends to store less valid data. The higher the proportion of cold data, the greater the amount of valid data stored in the TLC active block that stores the least amount of valid data. In other words, when the proportion of cold data increases, the amount of valid data stored in the TLC active block that transitioned to the active block the earliest increases. Based on this tendency, the increase in the proportion of cold data is determined based on whether the amount of valid data stored in the TLC active block that transitioned to the active block the earliest is equal to or greater than a predetermined value, in this example, the value Ath2.

[0100] If the amount of valid data stored in the TLC active block that transitioned to the active block oldest is equal to or greater than the value Ath2, it can be inferred that the proportion of cold data has increased. In such a case, the processor 101 reduces the number of SLC blocks. The processor 101 increases the number of TLC blocks by reducing the amount of blocks BLK allocated to SLC blocks and increasing the amount of blocks BLK allocated to TLC blocks among the multiple blocks BLK included in the NAND memory 200.

[0101] If the amount of valid data stored in the TLC active block that has transitioned to the active block the oldest is less than the value Ath2, it can be inferred that the proportion of cold data has not increased. In such a case, the processor 101 does not reduce the number of SLC blocks.

[0102] 9, the amount of valid data stored in block BLK31, which is the TLC active block that transitioned to the active block oldest, exceeds the value Ath2. Therefore, the processor 101 reduces the number of SLC blocks.

[0103] In addition, the process when the amount of valid data stored in the TLC active block that transitioned to the active block oldest is equal to the value Ath2 is not limited to the above example. When the amount of valid data stored in the TLC active block that transitioned to the active block oldest is equal to the value Ath2, the processor 101 does not need to reduce the number of SLC blocks.

[0104] According to the example shown in Fig. 9, only the TLC active block that transitioned to the active block the oldest was used to determine whether the proportion of cold data increased. Two or more TLC active blocks that transitioned to the active block relatively recently may be used to determine whether the proportion of cold data increased. An example of using two or more TLC active blocks that transitioned to the active block relatively recently to determine whether the proportion of cold data increased will be described with reference to Fig. 10.

[0105] FIG. 10 is a schematic diagram for explaining another example of a method for determining an increase in the proportion of cold data included in host data according to the first embodiment. Blocks BLK41 to BLK48 shown in this diagram are active blocks included in a group of TLC blocks, i.e., TLC active blocks. Blocks BLK41 to BLK48 are arranged in the order of the timing of transition to active blocks. It can be seen from this diagram that blocks BLK41, BLK42, BLK43, BLK44, BLK45, BLK46, BLK47, and BLK48 transitioned to active blocks in this order. The area of ​​the shaded portion of the rectangle representing blocks BLK41 to BLK48 represents the amount of valid data stored in each block BLK.

[0106] The processor 101 obtains the value Ath2 in advance and sets the value Rth2 in advance. The value Rth2 is an integer equal to or greater than 2. The value Rth2 is an example of a fourth number. A method for setting the value Rth2 will be described later. The processor 101 determines whether or not a TLC active block having an amount of valid data stored therein equal to or greater than the value Ath2 exists among the Rth2 TLC active blocks that have transitioned to the active block the earliest. If a TLC active block having an amount of valid data stored therein equal to or greater than the value Ath2 exists among the Rth2 TLC active blocks that have transitioned to the active block the earliest, the processor 101 decreases the number of SLC blocks. If a TLC active block having an amount of valid data stored therein equal to or greater than the value Ath2 does not exist among the Rth2 TLC active blocks that have transitioned to the active block the earliest, the processor 101 does not decrease the number of SLC blocks.

[0107] In addition, the processing when there is a TLC active block in which the amount of valid data stored is equal to the value Ath2 among the Rth2 TLC active blocks that transitioned to the active block earliest is not limited to the above example. When there is a TLC active block in which the amount of valid data stored exceeds the value Ath2 among the Rth2 TLC active blocks that transitioned to the active block earliest, the processor 101 reduces the number of SLC blocks, and when there is no TLC active block in which the amount of valid data stored exceeds the value Ath2 among the Rth2 TLC active blocks that transitioned to the active block earliest, the processor 101 does not have to reduce the number of SLC blocks.

[0108] In this way, processor 101 controls the number of SLC blocks based on the order in which each TLC active block transitioned to an active block, i.e., the order in which writing was completed, and the amount of valid data stored in each TLC active block.

[0109] Next, the operation of the memory system 1 according to the first embodiment will be described with reference to a flowchart.

[0110] FIG. 11 is a flowchart illustrating an example of the execution timing of the first transcription process according to the first embodiment.

[0111] The controller 100 writes the host data to the SLC open block. First, the processor 101 judges whether the SLC open block is full of host data (S101). If the SLC open block is not full of host data (S101: No), that is, if there is still a writable area in the SLC open block, the process of S101 is executed again.

[0112] If an SLC open block is full of host data (S101: Yes), i.e., if there is no writable area remaining in the SLC open block, the processor 101 transitions the SLC open block to an SLC active block (S102) and transitions one of the SLC free blocks to the SLC open block (S103).

[0113] Then, the processor 101 determines whether the number of SLC free blocks has reached the lower limit (S104). If the number of SLC free blocks has not reached the lower limit (S104: No), the control proceeds to S101.

[0114] If the number of SLC free blocks reaches the lower limit (S104: Yes), the controller 100 executes the first transcription process (S105). The controller 100 executes the first transcription process until at least one SLC free block is generated.

[0115] The execution timing of the first transcription process is not limited to the example shown in Fig. 11. In addition to the execution timing shown in Fig. 11, the controller 100 may execute the first transcription process during a period when there is no access from the host device 2.

[0116] FIG. 12 is a flowchart illustrating an example of the execution timing of the second transcription process according to the first embodiment.

[0117] The controller 100 writes the transcription data by the first transcription process and the second transcription process to the TLC open block. First, the processor 101 judges whether the TLC open block is full of transcription data (S201). If the TLC open block is not full of transcription data (S201: No), that is, if there is a writable area remaining in the TLC open block, the process of S201 is executed again.

[0118] If the TLC open block is full of transcription data (S201: Yes), i.e., if there is no writable area remaining in the TLC open block, the processor 101 transitions the TLC open block to a TLC active block (S202) and transitions one of the TLC free blocks to the TLC open block (S203).

[0119] Then, the processor 101 judges whether the number of TLC free blocks has reached the lower limit (S204). If the number of TLC free blocks has not reached the lower limit (S204: No), the control proceeds to S201.

[0120] If the number of TLC free blocks reaches the lower limit (S204: Yes), the controller 100 executes the second transcription process (S205). The controller 100 executes the second transcription process until at least one TLC free block is generated.

[0121] The execution timing of the second transcription process is not limited to the example shown in Fig. 12. In addition to the execution timing shown in Fig. 12, the controller 100 may execute the second transcription process during a period when there is no access from the host device 2.

[0122] Fig. 13 is a flowchart for explaining a method for controlling the number of SLC blocks according to the first embodiment. In the example of the control method shown in Fig. 13, it is determined whether to increase the number of SLC blocks based on the method shown in Fig. 7, and it is determined whether to decrease the number of SLC blocks based on the method shown in Fig. 10. It is possible to adopt the method shown in Fig. 8 instead of the method shown in Fig. 7. It is also possible to adopt the method shown in Fig. 9 instead of the method shown in Fig. 10.

[0123] First, the processor 101 sets values ​​Rth1 and Rth2 (S301).

[0124] For example, the processor 101 obtains each of the values ​​Rth1 and Rth2 by multiplying the total number of TLC active blocks by a constant greater than 0 and less than 1. The constant by which the total number of TLC active blocks is multiplied may be prepared separately for each of the values ​​Rth1 and Rth2, or may be used commonly for the values ​​Rth1 and Rth2. The decimal places of the value obtained by multiplying the total number of TLC active blocks by the constant are rounded up or down.

[0125] Alternatively, each of the values ​​Rth1 and Rth2 may be a fixed value. The designer stores each of the values ​​Rth1 and Rth2 in a predetermined area (for example, the NAND memory 200) in advance. In S301, the processor 101 may read each of the values ​​Rth1 and Rth2.

[0126] Next, the processor 101 determines whether or not there is a TLC active block with the smallest amount of valid data stored therein among the Rth1 TLC active blocks that have most recently transitioned to the active block (S302).

[0127] If there is a TLC active block that stores the smallest amount of valid data among the Rth1 TLC active blocks that have most recently transitioned to active blocks (S302: Yes), the processor 101 increases the number of SLC blocks (S303).

[0128] In S303, the processor 101 increases the number of SLC blocks by a predetermined number. The processor 101 increases the number of SLC blocks, for example, by changing a predetermined number of TLC free blocks to SLC free blocks. When the TLC free blocks are insufficient, the processor 101 can generate a predetermined number of TLC free blocks by executing a second transcription process. Note that the method of increasing the number of SLC blocks is not limited to this. The number of SLC blocks increased by one processing of S303 may be fixed or variable.

[0129] After the process of S303, the processor 101 executes the process of S306, which will be described later.

[0130] If there is no TLC active block with the smallest amount of valid data stored among the Rth1 TLC active blocks that most recently transitioned to active blocks (S302: No), the processor 101 determines whether there is a TLC active block with the amount of valid data stored that is equal to or greater than the value Ath2 among the Rth2 TLC active blocks that most recently transitioned to active blocks (S304).

[0131] If there is a TLC active block having an amount of valid data stored therein that is equal to or greater than Ath2 among the Rth2 TLC active blocks that transitioned to an active block oldest (S304: Yes), the processor 101 reduces the number of SLC blocks (S305).

[0132] In S305, the processor 101 reduces the number of SLC blocks by a predetermined number. The processor 101 reduces the number of SLC blocks, for example, by changing a predetermined number of SLC free blocks to TLC free blocks. When there is a shortage of SLC free blocks, the processor 101 can generate a predetermined number of SLC free blocks by executing a first transcription process. Note that the method of reducing the number of SLC blocks is not limited to this. The number of SLC blocks reduced by one processing of S305 may be fixed or variable.

[0133] After S303 or S305, the processor 101 determines whether or not the host write amount after the change in the number of SLC blocks has reached the value Ath3 (S306).

[0134] The processor 101 controls the number of SLC blocks based on the order of when each TLC active block transitioned to an active block and the amount of valid data stored in each TLC active block. However, for a while after the number of SLC blocks is changed, the order of when each TLC active block transitioned to an active block and the amount of valid data stored in each TLC active block may continue to be inappropriate for determining whether to increase or decrease the number of SLC blocks. Therefore, after changing the number of SLC blocks, the processor 101 postpones the determination of whether to increase or decrease the number of SLC blocks for a while.

[0135] S306 corresponds to a process of stopping the determination of the increase or decrease in the number of SLC blocks. The value Ath3 is a threshold value for specifying the period for which the determination of the increase or decrease in the number of SLC blocks is stopped based on the host write amount. The designer can set the value Ath3 in any manner. The value Ath3 is an example of the first amount.

[0136] The method of defining the period during which the determination of the increase or decrease in the number of SLC blocks is suspended is not limited to the method using the host write amount. The processor 101 may suspend the determination of the increase or decrease in the number of SLC blocks until the elapsed time after the change in the number of SLC blocks reaches a predetermined value.

[0137] If the host write amount after the change in the number of SLC blocks has not reached the value Ath3 (S306: No), the processor 101 executes the determination process of S306 again. If the host write amount after the change in the number of SLC blocks has reached the value Ath3 (S306: Yes), the processor 101 executes the process of S301.

[0138] If there is no TLC active block having the amount of valid data stored therein equal to or greater than the value Ath2 among the Rth2 TLC active blocks that transitioned to the active block oldest (S304: No), the processor 101 executes the process of S302.

[0139] In the example shown in Fig. 13, processor 101 makes a decision to increase the number of SLC blocks (e.g., the process of S302) and then makes a decision to decrease the number of SLC blocks (e.g., the process of S304). Processor 101 may make a decision to decrease the number of SLC blocks (e.g., the process of S304), and if the number of SLC blocks is not decreased, may make a decision to increase the number of SLC blocks (e.g., the process of S302). In this way, the order of the processes shown in Fig. 13 may be changed as appropriate.

[0140] Furthermore, processor 101 may execute a determination to increase the number of SLC blocks (e.g., the process of S302) and a determination to decrease the number of SLC blocks (e.g., the process of S304), and if the number of SLC blocks is neither increased nor decreased, may suspend the determination of whether to increase or decrease the number of SLC blocks for a period of time. Processor 101 may suspend (postpone) the next determination until the host write amount reaches the value Ath3, regardless of whether the number of SLC blocks has been increased or decreased.

[0141] As described above, according to the first embodiment, the controller 100 controls the number of SLC blocks based on the order in which each TLC active block transitioned to an active block, i.e., the order in which writing was completed, and the amount of valid data stored in each TLC active block.

[0142] Therefore, even if the data composition ratio changes, it is possible to effectively suppress the frequency of execution of the transfer process by appropriately changing the number of SLC blocks. If the frequency of execution of the transfer process is suppressed, the performance of the memory system 1 is improved. In other words, according to the first embodiment, the memory system 1 can control the number of bits of a value written per memory cell so as to maximize the performance.

[0143] Furthermore, according to the first embodiment, the controller 100 increases the number of SLC blocks, for example, when a TLC active block having the smallest amount of valid data stored therein is present among the Rth1 TLC active blocks that have most recently transitioned to an active block.

[0144] Therefore, even if the ratio of hot data contained in the host data increases, the frequency of execution of the transcription process can be suppressed by appropriately increasing the number of SLC blocks.

[0145] Alternatively, according to the first embodiment, the controller 100 increases the number of SLC blocks when, for example, among the Rth1 TLC active blocks that have most recently transitioned to active blocks, there is a TLC active block in which the amount of valid data stored is less than Ath1.

[0146] Therefore, even if the ratio of hot data contained in the host data increases, the frequency of execution of the transcription process can be suppressed by appropriately increasing the number of SLC blocks.

[0147] Also, according to the first embodiment, the controller 100 reduces the number of SLC blocks, for example, when the amount of valid data stored in the TLC active block to which the oldest active block has transitioned exceeds Ath2.

[0148] Therefore, even if the ratio of cold data contained in the host data increases, the frequency of execution of the transcription process can be suppressed by appropriately reducing the number of SLC blocks.

[0149] Alternatively, according to the first embodiment, the controller 100 reduces the number of SLC blocks, for example, when there is a TLC active block having an amount of valid data stored therein that exceeds Ath2 among the Rth2 TLC active blocks that transitioned to an active block earliest.

[0150] Therefore, even if the ratio of cold data contained in the host data increases, the frequency of execution of the transcription process can be suppressed by appropriately reducing the number of SLC blocks.

[0151] Furthermore, according to the first embodiment, the controller 100 stops determining whether to increase or decrease the number of SLC blocks until the host write amount reaches Ath3 after increasing or decreasing the number of SLC blocks, thereby stopping control of the number of second blocks.

[0152] Therefore, during a period that is not suitable for determining whether to increase or decrease the number of SLC blocks, it is possible to stop control of the number of second blocks.

[0153] Second Embodiment In the second embodiment, the number of SLC blocks is controlled based on a comparison between the host write amount and the transcription write amount. The memory system of the second embodiment will be described below. The functions of the memory system of the second embodiment and the components of the memory system are the same as those of the first embodiment, except for the function of controlling the number of SLC blocks. In the following, the memory system and the components of the memory system are given the same names and symbols as those of the first embodiment.

[0154] In the second embodiment, the host write amount is an example of a first amount, and the transcription write amount is an example of a second amount.

[0155] 14 is a schematic diagram for explaining an example of the relationship between the host write amount and the transcription write amount when the ratio of hot data included in the host data is relatively high in the memory system 1 according to the second embodiment. In this figure, a group of SLC blocks and a group of TLC blocks included in the NAND memory 200 are displayed. Note that the display of SLC free blocks and TLC free blocks is omitted. The hollow arrows indicate the flow of hot data, and the filled arrows indicate the flow of cold data.

[0156] Hot data and cold data are written to the SLC open blocks. Not only cold data but also some hot data are written to the TLC open blocks by the first transcription process. In the group of TLC blocks, most of the hot data is invalidated by rewriting before it is targeted for the second transcription process. Thus, in the example shown in FIG. 14, only cold data is written to the TLC open blocks in the second transcription process.

[0157] The smaller the host write amount, the longer it takes from when one SLC open block is set until the SLC open block is filled with host data. Therefore, the smaller the host write amount, the lower the frequency of execution of the first transcription process. Conversely, the smaller the transcription write amount, the longer it takes from when one TLC open block is set until the TLC open block is filled with transcription data. Therefore, the smaller the transcription write amount, the lower the frequency of execution of the second transcription process. In view of these trends, when the transcription write amount is small compared to the host write amount, it can be considered that there is room to reduce the number of TLC blocks.

[0158] 14, when the host write amount is regarded as W1, the transcription write amount by the first transcription process and the transcription write amount by the second transcription process are both 0.2×W1. Therefore, the transcription write amount, that is, the sum of the transcription write amount by the first transcription process and the transcription write amount by the second transcription process, is 0.4×W1, which is smaller than the host write amount. In such a case, the processor 101 increases the number of SLC blocks.

[0159] 15 is a schematic diagram for explaining an example of the relationship between the host write amount and the transcription write amount when the ratio of cold data is relatively high in the memory system 1 according to the second embodiment. In this diagram, a group of SLC blocks and a group of TLC blocks included in the NAND memory 200 are displayed. Note that the display of SLC free blocks and TLC free blocks is omitted. The hollow arrows indicate the flow of hot data, and the filled arrows indicate the flow of cold data.

[0160] 15, if the host write amount is considered to be W2, the transcription write amount by the first transcription process is 0.6×W2, and the transcription write amount by the second transcription process is 0.5×W2. Therefore, the transcription write amount is 1.1×W2, which is larger than the host write amount. In such a case, the processor 101 reduces the number of SLC blocks.

[0161] In the example described with reference to Figures 14 and 15, if the transcription write amount is less than the host write amount, the number of SLC blocks is increased, and if the transcription write amount is greater than the host write amount, the number of SLC blocks is decreased. If the transcription write amount is equal to the host write amount, the processing is arbitrary. If the transcription write amount is equal to the host write amount, the number of SLC blocks may be increased, the number of SLC blocks may be decreased, or the number of SLC blocks may not be changed.

[0162] In addition, the method of determining whether to increase or decrease the number of SLC blocks is not limited to a simple comparison between the transcription write amount and the host write amount. In order to prevent the number of SLC blocks from fluctuating finely, the processor 101 may increase the number of SLC blocks when the transcription write amount is smaller than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is larger than a constant C1 (where C1 is a positive real number), and may decrease the number of SLC blocks when the transcription write amount is larger than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is larger than a constant C2 (where C2 is a positive real number). C2 may be the same as or different from C1. When the transcription write amount is smaller than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is equal to the constant C1, the processing is arbitrary. When the transcription write amount is larger than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is equal to the constant C2, the processing is arbitrary. The constant C1 is an example of a first value. The constant C2 is an example of the second value.

[0163] 16 is a flowchart for explaining a method for controlling the number of SLC blocks according to the second embodiment. In the example shown in this figure, the number of SLC blocks is controlled by comparison using the constants C1 and C2 described above.

[0164] The processor 101 monitors the host write amount and the transcription write amount. The processor 101 judges whether the transcription write amount is less than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is greater than a constant C1 (S401). If the transcription write amount is less than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is greater than the constant C1 (S401: Yes), the processor 101 increases the number of SLC blocks by a process similar to the process of S303 in the first embodiment (S402).

[0165] If the transcription write amount is not less than the host write amount or the difference between the transcription write amount and the host write amount is not greater than a constant C1 (S401: No), the processor 101 judges whether the transcription write amount is greater than the host write amount and the difference between the transcription write amount and the host write amount is greater than a constant C2 (S403). If the transcription write amount is greater than the host write amount and the difference between the transcription write amount and the host write amount is greater than a constant C2 (S403: Yes), the processor 101 reduces the number of SLC blocks by a process similar to the process of S305 in the first embodiment (S404).

[0166] If the transcription write amount is not greater than the host write amount, or the magnitude of the difference between the transcription write amount and the host write amount is not greater than the constant C2 (S403: No), the processor 101 executes the process of S401.

[0167] After the process of S402 or S404, the processor 101 determines whether or not the host write amount since the change in the number of SLC blocks has reached the value Ath3, similar to the process of S306 in the first embodiment (S405). If the host write amount since the change in the number of SLC blocks has not reached the value Ath3 (S405: No), the processor 101 executes the determination process of S405 again. If the host write amount since the change in the number of SLC blocks has reached the value Ath3 (S405: Yes), the processor 101 executes the process of S401.

[0168] In the example shown in Fig. 16, processor 101 makes a decision to increase the number of SLC blocks (e.g., the process of S401) and then makes a decision to decrease the number of SLC blocks (e.g., the process of S403). Processor 101 may make a decision to decrease the number of SLC blocks (e.g., the process of S403), and may make a decision to increase the number of SLC blocks (e.g., the process of S401) if the number of SLC blocks is not to be decreased. In this way, the order of the processes shown in Fig. 16 may be changed as appropriate.

[0169] Furthermore, processor 101 may execute a determination to increase the number of SLC blocks (e.g., the process of S401) and a determination to decrease the number of SLC blocks (e.g., the process of S403), and if the number of SLC blocks is neither increased nor decreased, may suspend the determination of whether to increase or decrease the number of SLC blocks for a period of time. Processor 101 may suspend (postpone) the next determination until the host write amount reaches the value Ath3, regardless of whether the number of SLC blocks has been increased or decreased.

[0170] As described above, according to the second embodiment, the controller 100 controls the number of SLC blocks based on a comparison between the host write amount and the transcription write amount.

[0171] When the data composition ratio changes, the relationship between the host write amount and the transcription write amount may change. With the above configuration, even if the data composition ratio changes, it is possible to efficiently suppress the execution frequency of the transcription process by appropriately changing the number of SLC blocks. When the execution frequency of the transcription process is suppressed, the performance of the memory system 1 is improved. In other words, according to the second embodiment, the memory system 1 can control the number of bits of the value written per memory cell so as to maximize the performance.

[0172] Furthermore, according to the second embodiment, for example, when the transcription write amount is less than the host write amount, the controller 100 increases the number of SLC blocks, and when the transcription write amount is greater than the host write amount, the controller 100 decreases the number of SLC blocks.

[0173] Therefore, even if the data configuration ratio changes, the frequency of execution of the transcription process can be suppressed by appropriately changing the number of SLC blocks.

[0174] Furthermore, according to the second embodiment, for example, when the transcription write amount is smaller than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is larger than a constant C1, the controller 100 increases the number of SLC blocks. When the transcription write amount is larger than the host write amount and the magnitude of the difference between the transcription write amount and the host write amount is larger than a constant C2, the controller 100 decreases the number of SLC blocks.

[0175] Therefore, even if the data composition ratio changes, the frequency of execution of the transcription process can be suppressed by appropriately changing the number of SLC blocks. Also, it is possible to prevent the number of SLC blocks from fluctuating in a short period of time.

[0176] Furthermore, according to the second embodiment, the controller 100 stops determining whether to increase or decrease the number of SLC blocks until the host write amount reaches Ath3 after increasing or decreasing the number of SLC blocks, thereby stopping control of the number of second blocks.

[0177] Therefore, during a period that is not suitable for determining whether to increase or decrease the number of SLC blocks, it is possible to stop control of the number of second blocks.

[0178] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0179] 1 memory system, 2 host device, 3 communication interface, 4, 4a-4 division, 100 controller, 101 processor, 102 host I / F, 103 RAM, 104 buffer memory, 105 memory I / F, 106 internal bus, 200 NAND memory, 201 memory chip, 210 peripheral circuit, 211 memory cell array, 212 NAND string, 300 memory bus.

Claims

1. 1. A memory system connectable to a host device, comprising: a flash memory including a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from the host device sequentially into the second blocks; a first transcription process is executed to select one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and to make the selected second block reusable by sequentially writing all valid data in the selected second block to the plurality of third blocks; performing a second transcription process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block available for reuse; increasing the number of second blocks among the plurality of first blocks when a third block having a minimum amount of valid data stored therein is present among a third number of third blocks for which writing has been completed most recently among the one or more third blocks for which writing has been completed; A controller; A memory system comprising:

2. A memory system connectable to a host device, comprising: a flash memory including a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from the host device sequentially into the second blocks; a first transcription process is executed to select one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and to make the selected second block reusable by sequentially writing all valid data in the selected second block to the plurality of third blocks; performing a second transcription process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block available for reuse; increasing the number of second blocks among the plurality of first blocks when a third block in which an amount of valid data stored therein is less than a first threshold value is present among a third number of third blocks in which writing has been completed most recently among the one or more third blocks in which writing has been completed; A controller; A memory system comprising:

3. A memory system connectable to a host device, comprising: a flash memory including a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from the host device sequentially into the second blocks; a first transcription process is executed to select one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and to make the selected second block reusable by sequentially writing all valid data in the selected second block to the plurality of third blocks; performing a second transcription process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block available for reuse; reducing the number of second blocks among the plurality of first blocks when an amount of valid data stored in the third block for which writing has been completed earliest among the one or more third blocks for which writing has been completed exceeds a second threshold value; A controller; A memory system comprising:

4. A memory system connectable to a host device, comprising: a flash memory including a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from the host device sequentially into the second blocks; a first transcription process is executed to select one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and to make the selected second block reusable by sequentially writing all valid data in the selected second block to the plurality of third blocks; performing a second transcription process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block available for reuse; reducing the number of second blocks among the plurality of first blocks when a third block having an amount of valid data stored therein that exceeds a second threshold value is present among a fourth number of third blocks for which writing has been completed earliest among the one or more third blocks for which writing has been completed; A controller; A memory system comprising:

5. the controller stops controlling the number of second blocks from the time when the number of second blocks among the plurality of first blocks is increased or decreased until an amount of data written to the plurality of second blocks reaches a first amount; The memory system according to any one of claims 1 to 4.

6. 1. A memory system connectable to a host device, comprising: a flash memory including a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from the host device sequentially into the second blocks; a first transcription process is executed to select one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and to make the selected second block reusable by sequentially writing all valid data in the selected second block to the plurality of third blocks; performing a second transcription process for selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby making the selected third block available for reuse; controlling the number of second blocks among the plurality of first blocks based on a comparison between a first data amount, which is an amount of data written to the plurality of second blocks per unit time, and a second data amount, which is an amount of data written to the plurality of third blocks per unit time; A controller; A memory system comprising:

7. The controller: If the second amount of data is less than the first amount of data, increasing the number of second blocks among the plurality of first blocks; If the second amount of data is greater than the first amount of data, reducing the number of second blocks among the plurality of first blocks.

7. The memory system of claim 6.

8. The controller: When the second data amount is smaller than the first data amount and the magnitude of the difference between the second data amount and the first data amount is greater than a first value, increasing the number of second blocks among the plurality of first blocks; When the second data amount is greater than the first data amount and the magnitude of the difference between the second data amount and the first data amount is greater than a second value, reducing the number of second blocks among the plurality of first blocks.

7. The memory system of claim 6.

9. the controller stops controlling the number of second blocks from the time when the number of second blocks among the plurality of first blocks is increased or decreased until an amount of data written to the plurality of second blocks reaches a first amount; 9. The memory system according to claim 7 or 8.

10. 1. A method of controlling a memory system including a flash memory having a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from a host device sequentially into the second blocks; selecting one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and sequentially writing all valid data in the selected second block to the plurality of third blocks, thereby executing a first transcription process to make the selected second block reusable; selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby executing a second transcription process to make the selected third block available for reuse; increasing the number of second blocks among the plurality of first blocks when a third block in which an amount of valid data stored therein is less than a first threshold value is present among a third number of third blocks in which writing has been completed most recently among the one or more third blocks in which writing has been completed; The method includes:

11. A method for controlling a memory system having a flash memory having a plurality of first blocks, each of the plurality of first blocks having a plurality of memory cells, each of the plurality of first blocks being writable in a memory mode selected from a first mode and a second mode, the first mode being a mode in which a first number of bit values ​​are written per memory cell, the second mode being a mode in which a second number of bit values ​​are written per memory cell, the second number being greater than the first number, using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from a host device sequentially into the second blocks; selecting one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and sequentially writing all valid data in the selected second block to the plurality of third blocks, thereby executing a first transcription process to make the selected second block reusable; selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby executing a second transcription process to make the selected third block available for reuse; reducing the number of second blocks among the plurality of first blocks when a third block having an amount of valid data stored therein that exceeds a second threshold value is present among a fourth number of third blocks for which writing has been completed earliest among the one or more third blocks for which writing has been completed; The method includes:

12. 1. A method of controlling a memory system including a flash memory having a plurality of first blocks, each of the plurality of first blocks including a plurality of memory cells, each of the plurality of first blocks being writable in a first mode and a second mode, the first mode being a mode in which a value of a first number of bits is written per memory cell, the second mode being a mode in which a value of a second number of bits is written per memory cell, the second number being greater than the first number; using a plurality of second blocks that are a part of the plurality of first blocks in the first mode; using a plurality of third blocks which are another part of the plurality of first blocks in the second mode; writing data from a host device sequentially into the second blocks; selecting one second block from one or more second blocks for which writing has been completed among the plurality of second blocks, and sequentially writing all valid data in the selected second block to the plurality of third blocks, thereby executing a first transcription process to make the selected second block reusable; selecting one third block from one or more third blocks for which writing has been completed among the plurality of third blocks, and writing all valid data in the selected third block to a third block for which writing has not been completed among the plurality of third blocks, thereby executing a second transcription process to make the selected third block available for reuse; controlling the number of second blocks among the first blocks based on a comparison between a first data amount, which is an amount of data written to the second blocks per unit time, and a second data amount, which is an amount of data written to the third blocks per unit time; The method includes:

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