3D memory device and memory system

Abstract

To provide a 3D memory device and a memory system to improve I / O speed, throughput, and memory density.SOLUTION: A 3D memory device includes a 3D NAND memory array, an on-die SRAM, and a plurality of peripheral circuits coupled to the 3D NAND memory array and formed on the same chip as the on-die SRAM, and the plurality of peripheral circuits include: page buffers coupled to the on-die SRAM; and a controller that is coupled to the on-die SRAM and the page buffer, loads program data into the page buffer, caches program data in the on-die SRAM as a backup copy of the program data, transmits the backup copy in the on-die SRAM to the page buffer in response to a status where programming of the program data from the page buffer to the 3D NAND memory array is failed, and programs the backup copy in the page buffer into the 3D NAND memory array.SELECTED DRAWING: Figure 8

Description

[Background technology]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for manufacturing the same.

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and manufacturing techniques become more difficult and expensive. As a result, the memory density of planar memory cells approaches an upper limit.

[0003] 3D memory architectures can address density limitations in planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] Disclosed herein are embodiments of a 3D memory device having static random access memory (SRAM) and a method of operating the same.

[0005] In one example, a 3D memory device includes a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N-2)th batch of program data, where N is an integer greater than or equal to 2, program an (N-1)th batch of program data into respective pages in the 3D NAND memory array, and cache the Nth batch of program data in respective spaces in the on-die cache as a backup copy of the Nth batch of program data.

[0006] In another example, a system for performing cache program operations on a 3D memory device includes a host, a storage unit having multiple pages of NAND memory cells and coupled to the host, a cache unit coupled on the same chip as the storage unit and configured to cache multiple batches of program data between the host and the storage unit, and a control unit coupled to the cache unit and the host. The control unit is configured to check a status of an (N-2)th batch of program data programmed from the host to the storage unit, where N is an integer equal to or greater than 2. The control unit is also configured to program the (N-1)th batch of program data into respective pages of the storage unit and cache the Nth batch of program data in respective spaces within the cache unit as a backup copy of the Nth batch of program data.

[0007] In yet another example, a method for performing a cache program operation on a 3D memory device includes checking a status of an (N-2)th batch of program data programmed from a host to a storage unit, where N is an integer equal to or greater than 2. The method can also include programming the (N-1)th batch of program data into respective pages in the 3D NAND memory array and caching the Nth batch of program data in respective spaces in on-die static random access memory (SRAM) cells as a backup copy of the Nth batch of program data. [Brief description of the drawings]

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. [Figure 1A] 1 illustrates a schematic diagram of a cross section of an exemplary 3D memory device having SRAM, according to some embodiments. [Figure 1B] 1 illustrates a schematic diagram of a cross section of another exemplary 3D memory device having SRAM, according to some embodiments. [Diagram 2] 1 illustrates a schematic plan view of an exemplary semiconductor structure having peripheral circuitry and SRAM in accordance with some embodiments. [Diagram 3] 1 illustrates a cross-sectional view of an exemplary 3D memory device having SRAM, according to some embodiments. [Figure 4] 1 illustrates a cross-sectional view of another exemplary 3D memory device having SRAM, according to some embodiments. [Figure 5A] 1 illustrates a manufacturing process for forming an exemplary semiconductor structure having peripheral circuitry and SRAM according to some embodiments. [Figure 5B] 1 illustrates a manufacturing process for forming an exemplary semiconductor structure having peripheral circuitry and SRAM according to some embodiments. [Figure 5C] 1 illustrates a manufacturing process for forming an exemplary semiconductor structure having peripheral circuitry and SRAM according to some embodiments. [Figure 6A] 1 illustrates a manufacturing process for forming an exemplary semiconductor structure having a 3D NAND memory string, according to some embodiments. [Figure 6B] 1 illustrates a manufacturing process for forming an exemplary semiconductor structure having a 3D NAND memory string, according to some embodiments. [Figure 7A] 1 illustrates a manufacturing process for forming an exemplary 3D memory device having SRAM, according to some embodiments. [Figure 7B] 1 illustrates a manufacturing process for forming an exemplary 3D memory device having SRAM, according to some embodiments. [Figure 8] 1 illustrates a schematic block diagram of an example system having a 3D memory device with SRAM, according to some embodiments. [Figure 9A]1 illustrates a schematic block diagram of an exemplary system having a 3D memory device that uses SRAM as an on-die cache, according to some embodiments. [Figure 9B] 1 illustrates a schematic block diagram of an exemplary system having a 3D memory device that uses SRAM as an on-die data buffer, in accordance with some embodiments. [Figure 10] 1 is a flowchart of an exemplary method for operating a 3D memory device having SRAM, according to some embodiments. [Figure 11] 1 is a flowchart of another exemplary method for operating a 3D memory device having SRAM, according to some embodiments. [Figure 12] 1 is a flowchart of an exemplary method for forming a 3D memory device having SRAM, according to some embodiments.

[0009] An embodiment of the present disclosure will be described with reference to the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to one skilled in the art that the present disclosure can also be used in a variety of other applications.

[0011] It should be noted that references herein to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to achieve such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0012] Generally, terms may be understood, at least in part, from their use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, also depending at least in part on the context.

[0013] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with an intermediate feature or layer between, and "above" or "over" not only means "above" or "over" something, but also can include the meaning "above" or "over" something without an intermediate feature or layer between (i.e., directly on top of something).

[0014] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0016] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a uniform or non-uniform region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along tapered surfaces. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers above, on, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0017] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" can refer to a value of a given quantity that varies within a range of, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0018] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the sides of the substrate.

[0019] In conventional 3D memory devices, peripheral circuits formed outside the memory array device on the same plane can occupy a large area of ​​the device chip, resulting in poor array efficiency, large die size, and high cost. Also, the thermal budget associated with processing the memory array device limits the performance requirements of the peripheral circuits, making it difficult to achieve the high input / output (I / O) speeds of 3D memory devices. Furthermore, in memory technologies, operations based on caching and / or buffering of program data often require additional memory space. Certain operations that require additional memory space to be implemented are difficult in conventional 3D memory architectures.

[0020] For example, cache program operations are commonly used in solid-state drives of memory devices to improve the performance (e.g., speed) of sequential programming. In cache program operations, program data is written sequentially to memory cells while being cached / buffered in a cache to enable faster programming. Due to considerations such as volume and cost, cache space is often not formed in memory packages such as embedded multimedia cards (eMMC) or universal flash storage (UFS). In such memory packages, cache program operations are often not enabled. As a result, high-speed sequential programming in these memory packages may be limited. In another example, memory devices may use a significant amount of resources (e.g., data buffers and data buses) to buffer and transmit program data. This may slow down other operations (e.g., buffering and / or transmitting data for other operations). The overall performance of the memory device may be limited.

[0021] Various embodiments according to the present disclosure provide a 3D memory device having on-chip static random access memory (SRAM) with improved I / O speed, throughput, and memory density. The on-die SRAM cells are formed on the same chip as the peripheral circuitry of the 3D memory device. The SRAM cells can be located in areas not occupied by the peripheral circuitry (e.g., spare space adjacent to the peripheral circuitry), thus eliminating the need to form extra space. The on-die SRAM can enable fast read and write operations on memory cells of the 3D memory device. In one embodiment, the on-die SRAM is used as a cache for cache program operations. In another embodiment, the on-die SRAM is used as a data buffer for coarse and fine programming of memory cells, freeing up buffering space in the main buffer of the system. Thus, the on-die SRAM enables fast sequential programming in the 3D memory device, freeing up more space in the main buffer for other operations.

[0022] FIG. 1A illustrates a schematic diagram of a cross section of an exemplary 3D memory device 100 with SRAM, according to some embodiments. The 3D memory device 100 represents an example of a non-monolithic 3D memory device. The term "non-monolithic" means that the components of the 3D memory device 100 (e.g., peripheral circuits / SRAM and 3D NAND memory) can be formed separately on different substrates and then bonded to form a 3D memory device. The 3D memory device 100 can include a first semiconductor structure 102 that includes peripheral circuits and an array of SRAM cells. Both the peripheral circuits and the SRAM cell array can be implemented in advanced logic processes (e.g., technology nodes of 90 nm, 80 nm, 65 nm, 55 nm, 45 nm, 40 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, etc.) to achieve high speed. In some embodiments, the peripheral circuitry and the SRAM cell array in the first semiconductor structure 102 use complementary metal-oxide-semiconductor (CMOS) technology.

[0023] In some embodiments, the peripheral circuits include any suitable digital, analog, and / or mixed-signal peripheral circuits used to facilitate operation of the 3D memory device 100. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The SRAM is integrated on the same die of the logic circuit (e.g., the peripheral circuit), thus allowing for wider buses and faster operation speeds. A memory controller for the SRAM may be incorporated as part of the peripheral circuits. In some embodiments, each SRAM cell includes multiple transistors for stringing a bit of data as a positive of negative charge, as well as one or more transistors for controlling access thereto. In one example, each SRAM cell has six transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), e.g., four transistors for storing a bit of data and two transistors for controlling access to the data.

[0024] The 3D memory device 100 may also include a second semiconductor structure 104 that includes an array of 3D NAND memory strings. That is, the second semiconductor structure 104 may be a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. In some embodiments, depending on the NAND technology (e.g., the number of levels / tiers in the memory stack), a 3D NAND memory string typically consists of 32 to 256 NAND memory cells. The 3D NAND memory strings may be organized into pages, which are then organized into blocks, with each 3D NAND memory string connected to a separate line called a bit line (BL). All cells having the same position in the 3D NAND memory string may be connected through their control gates by a word line (WL). In some embodiments, a plane includes a certain number of blocks connected through the same bit line. The second semiconductor structure 104 may include one or more planes, and the peripheral circuitry required to perform all read / write / erase operations may be included in the first semiconductor structure 102.

[0025] As shown in FIG. 1A, the 3D memory device 100 further includes a bond interface 106 between the first semiconductor structure 102 and the second semiconductor structure 104 in the vertical direction. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (in some embodiments, in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process for fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104. Furthermore, in contrast to a long-distance chip-to-chip data bus on a circuit board, a large number of interconnects (e.g., bond contacts via hybrid junctions) can be formed through the bond interface 106 to provide a direct and short electrical connection between the first semiconductor structure 102 and the second semiconductor structure 104, thereby eliminating chip interface delays and achieving high-speed I / O throughput while reducing power consumption. Data transfer between the array of 3D NAND memory strings in the second semiconductor structure 104 and the array of SRAM cells in the first semiconductor structure 102 may be performed via interconnects (e.g., junction contacts via hybrid junctions) via the junction interface 106. Additionally, vertical integration of the first semiconductor structure 102 and the second semiconductor structure 104 may enable smaller chip sizes and higher memory cell densities.

[0026] It is understood that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Figure 1B shows a schematic diagram of a cross section of another exemplary 3D memory device 101 with SRAM, according to some embodiments. Unlike the 3D memory device 100 of Figure 1A, in which the second semiconductor structure 104 including an array of 3D NAND memory strings is on top of the first semiconductor structure 102 including an array of peripheral circuits and SRAM cells, in the 3D memory device 100 of Figure 1B, the first semiconductor structure 102 including the array of peripheral circuits and SRAM cells is on top of the second semiconductor structure 104 including the array of 3D NAND memory strings. Nevertheless, according to some embodiments, a junction interface 106 is formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101 in a vertical direction, and the first semiconductor structure 102 and the second semiconductor structure 104 are joined in a vertical direction by a junction (e.g., a hybrid junction). Data transfer between the array of 3D NAND memory strings in the second semiconductor structure 104 and the array of SRAM cells in the first semiconductor structure 102 can be performed via an interconnection via the junction interface 106 (e.g., a junction contact via a hybrid junction).

[0027] FIG. 2 illustrates a schematic plan view of an exemplary semiconductor structure 200 having peripheral circuits and an SRAM, according to some embodiments. The semiconductor structure 200 may be an example of the first semiconductor structure 102. The semiconductor structure 200 may include peripheral circuits for controlling and sensing the 3D NAND memory, including a word line driver 202, a page buffer 204, and any other suitable circuits. The semiconductor structure 200 may further include an SRAM 206 on the same die as the peripheral circuits and fabricated using the same logic process as the peripheral circuits. FIG. 2 illustrates an exemplary layout of the peripheral circuits (e.g., word line driver 202, page buffer 204) and the SRAM 206, where the peripheral circuits (e.g., word line driver 202, page buffer 204) and the SRAM 206 are formed in different regions on the same plane. For example, the SRAM 206 may be formed outside the peripheral circuits (e.g., word line driver 202, page buffer 204). It is understood that the layout of the semiconductor structure 200 is not limited to the exemplary layout of FIG. 2. In some embodiments, the peripheral circuits (e.g., word line driver 202 and page buffer 204) and SRAM 206 are formed in non-overlapping regions of the same plane. In some embodiments, on a plane, SRAM 206 is formed in space not used to form peripheral circuits. In some embodiments, the peripheral circuits (e.g., word line driver 202 and page buffer 204) and SRAM 206 (e.g., array of SRAM cells) are stacked on top of each other, i.e., on different planes. For example, SRAM 206 (e.g., array of SRAM cells) may be formed above or below the peripheral circuits (e.g., word line driver 202, page buffer 204) to further reduce the chip size.

[0028] 3 illustrates a cross-sectional view of an exemplary 3D memory device 300 having an SRAM, according to some embodiments. As an example of the 3D memory device 100 described above with respect to FIG. 1A, the 3D memory device 300 is a non-monolithic 3D memory device including a first semiconductor structure 302 and a second semiconductor structure 304 stacked on the first semiconductor structure 302. The first semiconductor structure 302 and the second semiconductor structure 304 are bonded at a bond interface 306 therebetween. As shown in FIG. 3, the first semiconductor structure 302 can include a substrate 308, which can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0029] The first semiconductor structure 302 of the 3D memory device 300 can include a device layer 310 on top of a substrate 308. Note that x and y axes have been added to FIG. 3 to further illustrate the spatial relationships of components within the 3D memory device 300. The substrate 308 includes two sides (e.g., top and bottom) that extend laterally (horizontally or widthwise) in the x direction. As used herein, whether one component (e.g., layer or device) is "on," "above," or "below" another semiconductor device (e.g., the 3D memory device 300) is determined in the y direction (vertically or thickness direction) relative to the substrate (e.g., substrate 308) of the semiconductor device when the substrate is positioned on the bottom surface of the semiconductor device in the y direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0030] In some embodiments, the device layer 310 includes peripheral circuitry 312 on the substrate 308 and an array of SRAM cells 314 on the substrate 308 and outside of the peripheral circuitry 312. In some embodiments, the peripheral circuitry 312 includes a plurality of peripheral transistors 316 that form any suitable digital, analog, and / or mixed signal peripheral circuitry used to facilitate operation of the 3D memory device 300, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references. The peripheral transistors 316 may be formed "on" the substrate 308, with all or a portion of the peripheral transistors 316 formed in the substrate 308 (e.g., below the top surface of the substrate 308) and / or directly on the substrate 308. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the peripheral transistors 316) may also be formed in the substrate 308.

[0031] In some embodiments, each SRAM cell 314 includes multiple SRAM transistors 318 (e.g., MOSFETs). In some embodiments, the SRAM cell 314 is a 6T cell consisting of four MOSFETs for storing one bit of data and two MOSFETs for controlling access to the data. It is understood that the SRAM cell 314 may be of any suitable configuration, such as more or less than six transistors (e.g., more or less transistors per bit). In some embodiments, the SRAM transistors 318 are formed "on" the substrate 308, where all or a portion of the SRAM transistors 318 are formed in the substrate 308 (e.g., below the top surface of the substrate 308) and / or directly on the substrate 308. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the SRAM transistors 318) may also be formed in the substrate 308. As shown in FIG. 3, the SRAM transistors 318 and the peripheral transistors 316 may be formed in the same plane, e.g., different regions on the substrate 308. That is, the SRAM transistors 318 may be formed outside of the area in which the peripheral circuitry 312 is formed on the substrate 308. In some embodiments, two access MOSFETs (e.g., MOSFETs that control access of data) are controlled by word lines, and four storage MOSFETs (e.g., MOSFETs that store bits of data) are coupled to bit lines and controlled by the two access MOSFETs. For ease of illustration, FIG. 3 shows only a limited number of SRAM transistors 318 and their connections to bit lines 319. Electrode contacts 320 may be connected to the electrodes of the MOSFETs and to a common plate 321, e.g., a common ground. It is understood that the configuration of FIG. 3, e.g., the layout of the SRAM transistors and the connections between the SRAM transistors 318 and the bit lines 319, do not reflect the actual layout and electrical connections between the SRAM transistors and other components (e.g., word lines, bit lines, and ground).

[0032] In some embodiments, the first semiconductor structure 302 of the 3D memory device 300 further includes an interconnect layer 322 over the device layer 310 to transfer electrical signals between the peripheral circuitry 312 and the array of SRAM cells 314. The interconnect layer 322 may include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 322 may further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and via contacts may be formed. That is, the interconnect layer 322 may include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in the interconnect layer 322 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer 322 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0033] As shown in FIG. 3, the first semiconductor structure 302 of the 3D memory device 300 may further include a bonding layer 324 at the bonding interface 306 and over the interconnect layer 322 and the device layer 310 (including the peripheral circuitry 312 and the array of SRAM cells 314). The bonding layer 324 may include a plurality of bonding contacts 326 and a dielectric that electrically insulates the bonding contacts 326. The bonding contacts 326 may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 324 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 326 and the surrounding dielectric in the bonding layer 324 may be used for hybrid bonding.

[0034] Similarly, as shown in FIG. 3, the second semiconductor structure 304 of the 3D memory device 300 can also include a bonding layer 328 at the bonding interface 306 and over the bonding layer 324 of the first semiconductor structure 302. The bonding layer 328 can include a plurality of bonding contacts 330 and a dielectric that electrically insulates the bonding contacts 330. The bonding contacts 330 can include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 328 can be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 330 and the surrounding dielectric in the bonding layer 328 can be used for hybrid bonding.

[0035] As described above, the second semiconductor structure 304 can be bonded in a face-to-face manner on top of the first semiconductor structure 302 at the bonding interface 306. In some embodiments, the bonding interface 306 is disposed between the bonding layers 324 and 328 as a result of a hybrid bond (also known as a "metal / dielectric hybrid bond") that is a direct bonding technique (e.g., forming a bond between the surfaces without using an intermediate layer such as a solder or adhesive) and can simultaneously obtain a metal-metal bond and a dielectric-dielectric bond. In some embodiments, the bonding interface 306 is where the bonding layers 324 and 328 meet and bond. In practice, the bonding interface 306 can be a layer having a certain thickness that includes the top surface of the bonding layer 324 of the first semiconductor structure 302 and the bottom surface of the bonding layer 328 of the second semiconductor structure 304.

[0036] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 further includes an interconnect layer 332 on top of the bonding layer 328 to transfer electrical signals. The interconnect layer 332 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer 332 can further include one or more ILD layers in which interconnect lines and via contacts can be formed. The interconnect lines and via contacts in the interconnect layer 332 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 332 can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0037] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 includes a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings 338 on the interconnect layer 332 and the bonding layer 328. According to some embodiments, each 3D NAND memory string 338 extends vertically through multiple pairs, each including a conductor layer 334 and a dielectric layer 336. The stacked and interleaved conductor layers 334 and dielectric layers 336 are also referred to herein as memory stacks 333. According to some embodiments, the interleaved conductor layers 334 and dielectric layers 336 in the memory stacks 333 alternate in the vertical direction. In other words, each conductor layer 334 can be flanked on both sides by two dielectric layers 336, and each dielectric layer 336 can be flanked on both sides by two conductor layers 334, except for the one at the top or bottom of the memory stack 333. The conductor layers 334 can each have the same thickness or different thicknesses. Similarly, the dielectric layers 336 can each have the same or different thicknesses. The conductor layer 334 can include a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, a silicide, or any combination thereof. The dielectric layer 336 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0038] In some embodiments, each 3D NAND memory string 338 is a "charge trap" type NAND memory string including a semiconductor channel 342 and a memory film 340. In some embodiments, the semiconductor channel 342 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 340 is a composite dielectric layer including a tunnel layer, an accumulation layer (also known as a "charge trap / accumulation layer"), and a blocking layer. Each 3D NAND memory string 338 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 342, the tunnel layer, the accumulation layer, and the blocking layer of the memory film 340 are arranged in this order along a direction from the center of the pillar toward the outer surface. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The accumulation layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the blocking layer can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). In another example, the blocking layer can include a high-k dielectric layer, such as an aluminum oxide (Al2O3) layer, a hafnium oxide (HfO2) layer, or a tantalum oxide (TA2O5) layer.

[0039] In some embodiments, the 3D NAND memory string 338 further includes a plurality of control gates (each part of a word line). Each conductor layer 334 in the memory stack 333 can function as a control gate for each memory cell of the 3D NAND memory string 338. In some embodiments, each 3D NAND memory string 338 includes two plugs 344 and 346 at each end in the vertical direction. The plugs 344 can include a semiconductor material, such as single crystal silicon, epitaxially grown from the semiconductor layer 348. The plugs 344 can function as a channel controlled by a source select gate of the 3D NAND memory string 338. The plugs 344 are at the top end of the 3D NAND memory string 338 and can contact the semiconductor channel 342. As used herein, the "top" of a component (e.g., 3D NAND memory string 338) is the end farther from substrate 308 in the y-direction, and the "bottom" of a component (e.g., 3D NAND memory string 338) is the end closer to substrate 308 in the y-direction when substrate 308 is disposed on the lowest plane of 3D memory device 300. Another plug 346 can include a semiconductor material (e.g., polysilicon) or a conductive material (e.g., metal). In some embodiments, plug 346 includes an opening filled with titanium / titanium nitride (Ti / TiN as a barrier layer) and tungsten (as a conductor). By covering the top of 3D NAND memory string 338 during fabrication of 3D memory device 300, plug 346 can function as an etch stop layer that prevents etching of dielectrics filled in 3D NAND memory string 338, such as silicon oxide and silicon nitride. In some embodiments, plug 346 functions as a drain of 3D NAND memory string 338.

[0040] In some embodiments, the first semiconductor structure 302 further includes a semiconductor layer 348 disposed over the memory stack 333 and the 3D NAND memory string 338. The semiconductor layer 348 can be a thinned substrate on which the memory stack 333 and the 3D NAND memory string 338 are formed. In some embodiments, the semiconductor layer 348 includes single crystal silicon on which the plugs 344 can be epitaxially grown. In some embodiments, the semiconductor layer 348 can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 348 can also include isolation regions and doped regions (e.g., functioning as an array common source for the 3D NAND memory strings 338, not shown). The isolation regions (not shown) can extend through the entire thickness or a portion of the thickness of the semiconductor layer 348 to electrically isolate the doped regions. In some embodiments, a pad oxide layer including silicon oxide is disposed between the memory stack 333 and the semiconductor layer 348.

[0041] It is understood that the 3D NAND memory string 338 is not limited to a "charge trap" type 3D NAND memory string, but may be a "floating gate" type 3D NAND memory string in other embodiments. The semiconductor layer 348 can include polysilicon as a source plate of the "floating gate" type 3D NAND memory string.

[0042] 3, the second semiconductor structure 304 of the 3D memory device 300 can further include a pad-out interconnect layer 350 on the semiconductor layer 348. The pad-out interconnect layer 350 includes interconnects, such as contact pads 352, in one or more ILD layers. The pad-out interconnect layer 350 and the interconnect layer 332 can be formed on either side of the semiconductor layer 348. In some embodiments, the interconnects in the pad-out interconnect layer 350 can transfer electrical signals between the 3D memory device 300 and external circuitry, such as for pad-out purposes.

[0043] In some embodiments, the second semiconductor structure 304 further includes one or more contacts 354 extending through the semiconductor layer 348 to electrically connect the pad-out interconnect layer 350 to the interconnect layers 332 and 322. As a result, the array of SRAM cells 314 can be electrically connected to the array of 3D NAND memory strings 338 via the interconnect layers 322 and 332 and the junction contacts 326 and 330. Furthermore, the peripheral circuitry 312, the array of SRAM cells 314, and the array of 3D NAND memory strings 338 can be electrically connected to external circuitry via the contacts 354 and the pad-out interconnect layer 350.

[0044] FIG. 4 illustrates a cross-sectional view of another exemplary 3D memory device 400 with SRAM, according to some embodiments. Similar to the 3D memory device 300 described above in FIG. 3, the 3D memory device 400 represents an example of a non-monolithic 3D memory device in which a first semiconductor structure 402 including 3D NAND memory strings and a second semiconductor structure 404 including peripheral circuits and SRAM cells are formed separately and bonded in a face-to-face manner at a bonding interface 406. Unlike the 3D memory device 300 described above in FIG. 3, in which the first semiconductor structure 302 including peripheral circuits and SRAM cells is below the second semiconductor structure 304 including 3D NAND memory strings, the 3D memory device 400 of FIG. 4 includes a second semiconductor structure 404 including peripheral circuits and SRAM cells disposed above the first semiconductor structure 402 including 3D NAND memory strings. It is understood that details of similar structures (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 300 and 400 will not be repeated below.

[0045] The first semiconductor structure 402 of the 3D memory device 400 may include a substrate 408 and a memory stack 410 including interleaved conductor layers 412 and dielectric layers 414 on the substrate 408. In some embodiments, an array of 3D NAND memory strings 416 each extend vertically through the interleaved conductor layers 412 and dielectric layers 414 in the memory stack 410 on the substrate 408. Each 3D NAND memory string 416 may include a semiconductor channel 420 and a memory membrane 418. Each 3D NAND memory string 416 further includes two plugs 422 and 424 at its lower and upper ends, respectively. The 3D NAND memory string 416 may be a "charge trap" type 3D NAND memory string or a "floating gate" type 3D NAND memory string. In some embodiments, a pad oxide layer including silicon oxide is disposed between the memory stack 410 and the substrate 408.

[0046] In some embodiments, the first semiconductor structure 402 of the 3D memory device 400 also includes an interconnect layer 426 over the memory stack 410 and the 3D NAND memory string 416 to transfer electrical signals to and from the 3D NAND memory string 416. The interconnect layer 426 can include a plurality of interconnects including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 426 also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the first semiconductor structure 402 of the 3D memory device 400 further includes a bonding layer 428 at the bonding interface 406 and over the interconnect layer 426 and the memory stack 410. The bonding layer 428 can include a plurality of bonding contacts 430 and a dielectric that surrounds and electrically insulates the bonding contacts 430.

[0047] 4, the second semiconductor structure 404 of the 3D memory device 400 includes another bonding layer 432 at the bonding interface 406 and above the bonding layer 428. The bonding layer 432 can include a plurality of bonding contacts 434 and a dielectric that surrounds and electrically insulates the bonding contacts 434. In some embodiments, the second semiconductor structure 404 of the 3D memory device 400 also includes an interconnect layer 436 above the bonding layer 432 to transfer electrical signals. The interconnect layer 436 can include a plurality of interconnects, including interconnect lines and via contacts.

[0048] The second semiconductor structure 404 of the 3D memory device 400 may further include a device layer 438 over the interconnect layer 436 and the bonding layer 432. In some embodiments, the device layer 438 includes a peripheral circuit 442 over the interconnect layer 436 and the bonding layer 432, and an array of SRAM cells 444 over the interconnect layer 436 and the bonding layer 432 and outside the peripheral circuit 442. In some embodiments, the peripheral circuit 442 includes a plurality of peripheral transistors 446 that form any suitable digital, analog, and / or mixed signal peripheral circuitry used to facilitate operation of the 3D memory device 400, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references. The peripheral transistors 446 may be formed “on” the semiconductor layer 440, with all or a portion of the peripheral transistors 446 formed in and / or directly above the semiconductor layer 440. Isolation regions (eg, shallow trench isolation (STI)) and doped regions (eg, source and drain regions of peripheral transistor 446) may also be formed in semiconductor layer 440.

[0049] In some embodiments, each SRAM cell 444 includes multiple SRAM transistors 448 (e.g., MOSFETs). In some embodiments, the SRAM cell 444 is a 6T cell consisting of four MOSFETs for storing one bit of data and two MOSFETs for controlling access to the data. It is understood that the SRAM cell 444 may be of any suitable configuration, such as more or less than six transistors (e.g., more or less transistors per bit). In some embodiments, the SRAM transistors 448 are formed "on" the semiconductor layer 440, with all or a portion of the SRAM transistors 448 formed in and / or immediately above the semiconductor layer 440. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the SRAM transistors 448) may also be formed in the semiconductor layer 440. As shown in FIG. 4, the SRAM transistors 448 and the peripheral transistors 446 may be formed in the same plane, e.g., different regions on the semiconductor layer 440. That is, the SRAM transistors 448 may be formed outside of the area on the semiconductor layer 440 where the peripheral circuitry 442 is formed. In some embodiments, two access MOSFETs (e.g., MOSFETs that control access of data) are controlled by word lines, and four storage MOSFETs (e.g., MOSFETs that store bits of data) are coupled to bit lines and controlled by the two access MOSFETs. For ease of illustration, FIG. 4 shows only a limited number of SRAM transistors 448 and their connections to bit lines 449. Electrode contacts 450 may be connected to the electrodes of the MOSFETs and to a common plate 451, e.g., a common ground. It is understood that the configuration of FIG. 4, e.g., the layout of the SRAM transistors and the connections between the SRAM transistors 448 and the bit lines 449, do not reflect the actual layout and electrical connections between the SRAM transistors and other components (e.g., word lines, bit lines, and ground).

[0050] In some embodiments, the second semiconductor structure 404 further includes a semiconductor layer 440 disposed over the device layer 438. The semiconductor layer 440 may be a thinned substrate on which the peripheral transistors 446 and the SRAM transistors 448 are formed. In some embodiments, the semiconductor layer 440 includes single crystal silicon. In some embodiments, the semiconductor layer 440 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 440 may also include isolation regions and doped regions.

[0051] As shown in FIG. 4, the second semiconductor structure 404 of the 3D memory device 400 can further include a pad-out interconnect layer 452 on the semiconductor layer 440. The pad-out interconnect layer 452 includes interconnects, such as contact pads 454, in one or more ILD layers. In some embodiments, the interconnects in the pad-out interconnect layer 452 can transfer electrical signals between the 3D memory device 400 and an external circuit, for example, for pad-out purposes. In some embodiments, the second semiconductor structure 404 further includes one or more contacts 456 extending through the semiconductor layer 440 to electrically connect the pad-out interconnect layer 452 to the interconnect layers 436 and 426. As a result, the array of SRAM cells 444 can be electrically connected to the array of 3D NAND memory strings 416 via the interconnect layers 426 and 436 and the junction contacts 430 and 434. Additionally, the peripheral circuitry 442, the array of SRAM cells 444, and the array of 3D NAND memory strings 416 can be electrically connected to external circuitry via contacts 456 and pad-out interconnect layers 452.

[0052] Figures 5A-5C illustrate a fabrication process for forming an exemplary semiconductor structure having peripheral circuitry and SRAM, according to some embodiments. Figures 6A-6C illustrate a fabrication process for forming an exemplary semiconductor structure having 3D NAND memory strings, according to some embodiments.

[0053] 7A and 7B illustrate a fabrication process for forming an exemplary 3D memory device with SRAM, according to some embodiments. FIG. 12 is a flow chart of an exemplary method 1200 for forming a 3D memory device with SRAM, according to some embodiments. Examples of 3D memory devices illustrated in FIGS. 5-7 and 12 include the 3D memory device 300 illustrated in FIG. 3 and the 3D memory device 400 illustrated in FIG. 4. FIGS. 5-7 and 12 are described together. It is understood that the operations illustrated in the method 1200 are not exhaustive and that other operations can be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 12.

[0054] A first semiconductor structure is formed including a peripheral circuit, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts, as shown in Figures 5A-5C. A second semiconductor structure is formed including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts, as shown in Figures 6A and 6B. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the first bonding contacts contact the second bonding contacts at a bonding interface, as shown in Figures 7A and 7B.

[0055] Referring to FIG. 12, method 1200 begins at operation 1202, where an array of peripheral circuits and SRAM cells are formed on a first substrate. The first substrate may be a silicon substrate. In some embodiments, a plurality of transistors are formed on the first substrate to form the array of peripheral circuits and SRAM cells. As shown in FIG. 5A, a plurality of transistors (e.g., peripheral transistor 504 and SRAM transistor 506) are formed on a silicon substrate 502. The transistors 504 and 506 may be formed by a plurality of processes, including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 502, for example, by ion implantation and / or thermal diffusion to function as source and / or drain regions of the transistors 504 and 506. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 502 by wet / dry etching and thin film deposition.

[0056] 5B, bit lines 507 and common plates 509 are also formed to connect the SRAM transistors 506. This forms a device layer 510 that includes peripheral circuitry (having peripheral transistors 504) and an array of SRAM cells (each having multiple SRAM transistors 506).

[0057] The method 1200 proceeds to operation 1204, as shown in FIG. 12, where a first interconnect layer is formed over the peripheral circuitry and the array of SRAM cells. The first interconnect layer may include a first plurality of interconnects in one or more ILD layers. As shown in FIG. 5C, an interconnect layer 512 may be formed over a device layer 510 including peripheral circuitry (having peripheral transistors 504) and an array of SRAM cells (each having an SRAM transistor 506). The interconnect layer 512 may include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the device layer 510. In some embodiments, the interconnect layer 512 includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in the interconnect layer 512 may include conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 5C may be collectively referred to as an interconnect layer 512.

[0058] The method 1200 proceeds to operation 1206, as shown in FIG. 12, where a first bonding layer is formed on the first interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As shown in FIG. 5C, a bonding layer 514 is formed on the interconnect layer 512. The bonding layer 514 can include a plurality of bonding contacts 516 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 512 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The bonding contacts 516 can then be formed through the dielectric layer to contact the interconnects in the interconnect layer 512 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, a bonding layer, and / or a seed layer prior to depositing the conductor.

[0059] The method 1200 continues to operation 1208, as shown in FIG. 12, where a memory stack is formed on a second substrate. The second substrate can be a silicon substrate. As shown in FIG. 6A, an interleaved sacrificial layer (not shown) and a dielectric layer 608 are formed on a silicon substrate 602. The interleaved sacrificial layers and the dielectric layer 608 can form a dielectric stack (not shown). In some embodiments, each sacrificial layer includes a layer of silicon nitride and each dielectric layer 608 includes a layer of silicon oxide. The interleaved sacrificial layers and the dielectric layer 608 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the memory stack 604 can be formed by replacing the sacrificial layer with a conductor layer 606 using a gate replacement process, e.g., wet / dry etching of the sacrificial layer selective to the dielectric layer 608, and filling the resulting recess with the conductor layer 606. As a result, the memory stack 604 can include interleaved conductor layers 606 and dielectric layers 608. In some embodiments, each conductor layer 606 comprises a metal layer, such as a layer of tungsten. It is understood that the memory stack 604 may be formed in other embodiments by alternately depositing conductor layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer comprising silicon oxide is formed between the memory stack 604 and the silicon substrate 602.

[0060] The method 1200 proceeds to operation 1210, where an array of 3D NAND memory strings is formed, extending vertically through the memory stack, as shown in FIG. 6A. As shown in FIG. 6A, 3D NAND memory strings 610 are formed on a silicon substrate 602, each of which extends vertically through the interleaved conductor layers 606 and dielectric layers 608 of the memory stack 604. In some embodiments, a fabrication process for forming the 3D NAND memory strings 610 includes forming a channel hole in the silicon substrate 602 through the memory stack 604 using dry etching and / or wet etching, such as deep reactive ion etching (DRIE), and then epitaxially growing a plug 612 from the silicon substrate 602 to the bottom of the channel hole. In some embodiments, the fabrication process for forming the 3D NAND memory string 610 also includes subsequently filling the channel hole with multiple layers, such as the memory film 614 (e.g., tunnel layer, accumulation layer, and blocking layer) and the semiconductor layer 616, using a thin film deposition process, such as ALD, CVD, PVD, or any combination thereof. In some embodiments, the fabrication process for forming the 3D NAND memory string 610 further includes forming another plug 618 at the top of the channel hole by etching a recess at the top end of the 3D NAND memory string 610, and then filling the recess with a semiconductor material, using a thin film deposition process, such as ALD, CVD, PVD, or any combination thereof.

[0061] The method 1200 proceeds to operation 1212, as shown in FIG. 12, where a second interconnect layer is formed over the array of 3D NAND memory strings. The second interconnect layer may include a second plurality of interconnects in one or more ILD layers. As shown in FIG. 6B, an interconnect layer 620 may be formed over the memory stack 604 and the array of 3D NAND memory strings 610. The interconnect layer 620 may include MEOL and / or BEOL interconnects in the multiple ILD layers to make electrical connections with the 3D NAND memory strings 610. In some embodiments, the interconnect layer 620 includes multiple ILD layers and interconnects formed therein with multiple processes. For example, the interconnects in the interconnect layer 620 may include conductive material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include a dielectric material deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in FIG. 6B may be collectively referred to as interconnect layer 620.

[0062] The method 1200 proceeds to operation 1214, as shown in FIG. 12, where a second bonding layer is formed on the second interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As shown in FIG. 6B, a bonding layer 622 is formed on the interconnect layer 620. The bonding layer 622 can include a plurality of bonding contacts 624 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 620 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The bonding contacts 624 can then be formed through the dielectric layer to contact the interconnects in the interconnect layer 620 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, a bonding layer, and / or a seed layer prior to depositing the conductor.

[0063] The method 1200 proceeds to operation 1216, as shown in FIG. 12, where the first substrate and the second substrate are bonded in a face-to-face manner such that the first bonding contacts meet the second bonding contacts at the bonding interface. The bonding can be a hybrid bond. In some embodiments, the first substrate (e.g., the first semiconductor structure) on which the peripheral circuitry and the SRAM cells are formed is disposed on the second substrate (e.g., the second semiconductor structure) on which the 3D NAND memory strings are formed after bonding. In some embodiments, the second substrate (e.g., the second semiconductor structure) on which the 3D NAND memory strings are formed is disposed on the first substrate (e.g., the first semiconductor structure) on which the peripheral circuitry and the SRAM cells are formed after bonding.

[0064] As shown in FIG. 7A, the silicon substrate 602 and the components formed thereon (e.g., the 3D NAND memory string 610) are flipped upside down. The downward bonding layer 622 is bonded to the upward bonding layer 514, i.e., face-to-face, thereby forming a bonding interface 702 (as shown in FIG. 7B). In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a thermal treatment, is applied to the bonding surfaces prior to bonding. Although not shown in FIG. 7A, the silicon substrate 502 and the components formed thereon (e.g., the device layer 510) can be flipped upside down and the downward bonding layer 514 can be bonded to the upward bonding layer 622, i.e., face-to-face, thereby forming the bonding interface 702. After bonding, the bonding contacts 624 in the bonding layer 622 and the bonding contacts 516 in the bonding layer 514 can be aligned in contact with each other, thereby electrically connecting the device layer 510 (e.g., the peripheral circuitry and the SRAM cells therein) to the 3D NAND memory string 610. It is understood that in a bonded device, the 3D NAND memory string 610 may be either above or below the device layers 510 (e.g., the peripheral circuitry and the SRAM cells therein). Nevertheless, after bonding, a bond interface 702 may be formed between the 3D NAND memory string 610 and the device layers 510 (e.g., the peripheral circuitry and the SRAM cells therein), as shown in FIG.

[0065] The method 1200 proceeds to operation 1218, as shown in Figure 12, where the first substrate or the second substrate is thinned to form a semiconductor layer. In some embodiments, the first substrate of the first semiconductor structure that overlies the second substrate of the second semiconductor structure after bonding is thinned to form a semiconductor layer. In some embodiments, the second substrate of the second semiconductor structure that overlies the first substrate of the first semiconductor structure after bonding is thinned to form a semiconductor layer.

[0066] As shown in FIG. 7B, a substrate on top of the bonded 3D memory device (e.g., silicon substrate 402 shown in FIG. 7A) is thinned, so that the thinned top substrate can function as a semiconductor layer 704, e.g., a monocrystalline silicon layer. The thickness of the thinned substrate can be about 200 nm to about 5 μm, e.g., 200 nm to 5 μm, or about 150 nm to about 50 μm, e.g., 150 nm to 50 μm. The silicon substrate 402 can be thinned by a process including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. It is understood that when the silicon substrate 502 is the substrate on top of the bonded 3D memory device, another semiconductor layer can be formed by thinning the silicon substrate 502.

[0067] The method 1200 proceeds to operation 1220, as shown in FIG. 12, where a pad-out interconnect layer is formed on the semiconductor layer. As shown in FIG. 7B, the pad-out interconnect layer 706 is formed on the semiconductor layer 704 (thinned top substrate). The pad-out interconnect layer 706 can include interconnects, such as pad contacts 708, formed in one or more ILD layers. The pad contacts 708 can include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding and thinning, contacts 710 are formed that extend vertically through the semiconductor layer 704, for example, by wet / dry etching followed by deposition of a conductive material. The contacts 710 can contact interconnects in the pad-out interconnect layer 706.

[0068] FIG. 8 illustrates a schematic block diagram of an exemplary system 850 having a 3D memory device with on-die SRAM, according to some embodiments. FIG. 9A illustrates a schematic block diagram of a system 920 having a 3D memory device with on-die SRAM as a cache, according to some embodiments. FIG. 9B illustrates a schematic block diagram of a system 930 having a 3D memory device with on-die SRAM as a data buffer, according to some embodiments. FIG. 10 is a flow chart of an exemplary method 1000 for operating a 3D memory device with on-die SRAM as a cache, according to some embodiments. FIG. 11 is a flow chart of an exemplary method 1100 for operating a 3D memory device with on-die SRAM as a data buffer, according to some embodiments. Examples of systems illustrated in FIGS. 9A and 9B are described in conjunction with FIGS. 10 and 11, respectively. It is understood that the operations illustrated in methods 1000 and 1100 are not exhaustive and other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that shown in FIGS.

[0069] FIG. 8 illustrates a system 850 having an SRAM used as a cache or data buffer, according to some embodiments. The system 850 can have a host 810, an I / O 802, an SRAM 804, a page buffer 806, and a 3D NAND memory 808. In some embodiments, the SRAM 804 is formed on the same chip as the page buffer 806 and the 3D NAND memory 808, as described in detail above. In some embodiments, the SRAM 804, the page buffer 806, and the 3D NAND memory 808 form a 3D memory device 800. The SRAM 804 can be referred to as an on-die SRAM or an on-NAND SRAM. Data, e.g., program data and control instructions, may be transmitted bidirectionally between the host 810 and the I / O 802, between the I / O 802 and the SRAM 804, between the SRAM 804 and the page buffer 806, and between the 3D NAND memory 808 and the page buffer 806. The data transmission 812 between the host 810 and the page buffer 806 can be enabled or disabled depending on the functionality of the SRAM 804. For example, if the SRAM 804 serves as a cache in the 3D memory device 800, the data transmission 812 can be a bidirectional data transmission between the host 810 and the page buffer 806, and if the SRAM 804 serves as a data buffer in the 3D memory device 800, the data transmission 812 can be disabled. That is, if the SRAM 804 serves as a cache, the data transmission 812 allows the 3D memory device 800 to program the 3D NAND memory 808 using program data from the host 810 and simultaneously allow the host 810 to extract the program data from the page buffer 806, and if the SRAM 804 serves as a data buffer, the 3D memory device 800 sequentially buffers the program data from the host 810 in the SRAM 804 and programs the buffered program data into the 3D NAND memory 808.

[0070] The host 810 can be any suitable device that generates data, such as one or more processors. In some embodiments, the host 810 includes a central processing unit (CPU), a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU (accelerated processing unit), a GPGPU (general purpose computing on GPU)), or any other suitable processor. The input / output circuitry 802 can be a high-speed, high-throughput input / output circuitry as part of the peripheral circuitry. In some embodiments, the host 810 includes a system controller (e.g., a controller that controls various operations of the system 850) and / or a memory controller (e.g., a controller that controls various operations of the 3D memory device 800). Any suitable type of data generated by the host 810 is transferred to the SRAM 804 of the 3D memory device 800 via the I / O 802. The host 810 and the 3D memory device 800 may be part of any suitable apparatus, such as a virtual reality (VR) / augmented reality (AR) device (e.g., a VR headset, etc.), a handheld device (e.g., a dumbphone or smartphone, tablet, etc.), a wearable device (e.g., glasses, wristwatch, etc.), an automobile control station, a games console, a television set, a laptop computer, a desktop computer, a netbook computer, a media center, a set-top box, a global positioning system (GPS), a printer, or any other suitable device.

[0071] In some embodiments, the SRAM 804 includes a plurality of SRAM cells arranged in an array or any pattern. Details of the SRAM cells can be found in the description of Figures 3-5C and therefore will not be repeated here. The SRAM 804 can be connected to a page buffer 806 that includes a plurality of buffering sections connected to respective pages in the 3D NAND memory 808.

[0072] The SRAM 804 can be used as a fast on-die cache for the 3D memory device 800 to improve sequential programming. FIG. 9A illustrates a system 920 in which the SRAM 804 functions as a fast on-die cache. For ease of illustration, the I / O 802 is omitted from FIG. 9A. In some embodiments, data is programmed into the 3D NAND memory 808 in pages, and the SRAM 804 is illustrated as multiple cache units 904 (i.e., 904-1, ..., 904-K), each configured to cache program data for programming a page in the 3D NAND memory 808. The 3D NAND memory 808 is organized into multiple planes, each representing memory cells formed by word lines and intersecting memory strings. 908 (i.e., 908-1, ..., 908-M). The plane 908 can include multiple pages of memory cells. K and M may each be a positive integer and may or may not be the same as each other. During operation, multiple cache units 904 can cache the same batch of program data in the page buffer 806 simultaneously. The cache units 904 further input the cached program data into the page buffer 806, which then inputs the cached program data into respective pages in the plane 908. In some embodiments, the host 810 transmits batches of program data, e.g., (N-3)th, (N-2)th, (N-1)th, Nth, (N+1)th, and (N+2)th, to the SRAM 804 and / or page buffer 806 sequentially (e.g., one batch immediately followed by another).

[0073] 10, method 1000 begins at operation 1002, where 3D memory device 800 receives control instructions from host 810 to condition 3D memory device 800 for a cache program operation. In some embodiments, 3D memory device 800 initializes SRAM cells of SRAM 804 in accordance with the control instructions, e.g., erases data in / empties the SRAM cells, so that SRAM 804 is ready to receive program data.

[0074] In operation 1004, the 3D memory device 800 programs the (N-1)th batch of program data into the respective pages. At the same time, the 3D memory device 800 caches the Nth batch of program data in a respective space (e.g., cache unit) in the SRAM 804 and checks the status of the (N-2)th batch of program data. The SRAM 804 can cache multiple batches of program data. In some embodiments, the SRAM caches up to three batches of program data, e.g., the (N-2)th, (N-1)th, and Nth batches of program data shown in FIG. 9A. Each batch of program data (e.g., the (N-2)th batch, the (N-1)th batch, and the Nth batch) can include one or more pages of program data in a respective plane. For example, each batch of program data can include K pages of program data, and each page of program data can be cached in a respective cache unit (e.g., 904-1, ..., 904-K). The cached batches of program data may be backup copies of the respective program data, which can be programmed into the 3D NAND memory 808 as needed, for example, if programming of the respective program data into the 3D NAND memory 808 fails, as described in more detail below.

[0075] In some embodiments, checking the status of the (N-2)th batch of program data, programming the (N-1)th batch of program data, and caching the Nth batch of program data are performed simultaneously or over time. For example, these operations may begin and complete at approximately the same time or may have overlapping operation times. In some embodiments, when the 3D memory device 800 is programming the (N-1)th batch of program data from the page buffer 806 to the 3D NAND memory 808, the 3D memory device 800 is caching the Nth batch of program data from the host 810 and checking the status of the (N-2)th batch of program data. The 3D memory device 800 may program the (N-1)th batch of program data by sending a copy of the (N-1)th batch of program data from the page buffer 806. The copy of the (N-1)th batch of program data may be formed by buffering the (N-1)th batch of program data from the host 810 (e.g., prior to caching the Nth batch of program data) or by buffering a backup copy of the (N-1)th batch of program data from the SRAM 804. In some embodiments, the 3D memory device 800 programs the (N-1)th batch of program data by loading a copy of the (N-1)th batch of program data from the page buffer 806 into the 3D NAND memory 808 when caching the Nth batch of program data from the host 810 into the SRAM 804. The copy of the (N-1)th batch of program data may be formed, for example, by buffering the (N-1)th batch of program data via data transmission 812 from the host 810 before programming begins. In some embodiments, the backup copy of the (N-1)th batch of program data is cached in the SRAM 804 when the 3D memory device 800 is checking the status of the (N-3)th batch of program data.In some embodiments, when the (N-2)th batch of program data is being programmed into each page in the 3D NAND memory 808, the (N-1)th batch of program data is cached from the host 810 to the SRAM 804 to form a backup copy of the (N-1)th batch of program data.

[0076] In some embodiments, checking the status of the (N-2)th batch of program data includes determining whether the programming of the (N-2)th batch of program data was successful. In some embodiments, if the programming of the (N-2)th batch of program data fails, the 3D memory device 800 retrieves a backup copy of the (N-2)th batch of program data from the SRAM 804, buffers the backup copy of the (N-2)th batch of program data in the page buffer 806, and programs the backup copy of the (N-2)th batch of program data into the respective pages in the 3D NAND memory 808. In some embodiments, the SRAM 804 maintains the backup copy of the (N-2)th batch of program data when checking the status of the programming of the (N-2)th batch of program data, and deletes the backup copy of the (N-2)th batch of program data when the programming of the (N-2)th batch of program data was successful. The SRAM 804 may then have space to cache another batch of program data (e.g., the (N+1)th batch of program data).

[0077] The Nth batch of program data may be cached in SRAM 804 to form a backup copy of the Nth batch of program data as the (N-1)th batch of program data is programmed into 3D NAND memory 808. The backup copy of the Nth batch of program data in SRAM 804 may be maintained until it is determined that the Nth batch of program data has been successfully programmed into 3D NAND memory 808. In some embodiments, the host 810 reads the Nth batch of program data from SRAM 804, e.g., for further processing and / or storage, before the Nth batch of program data is deleted from SRAM 804. For example, the host 810 may store the read Nth batch of program data in another location. In some embodiments, the host 810 deletes the copy of the Nth batch of program data from the host after the Nth batch of program data is cached in SRAM 804. In some embodiments, the 3D memory device 800 checks the status of the (N-1)th batch of program data as the Nth batch of program data is programmed into the respective page in 3D NAND memory 808. Meanwhile, the 3D memory device 800 may cache the (N+1)th batch of program data in each space in the SRAM 804. In some embodiments, the host 810 reads the program data from the page buffer 806 for further processing.

[0078] In some embodiments, the 3D memory device 800 sequentially repeats operation 1004 for subsequent batches of program data. In operation 1006, the 3D memory device 800 programs the Nth batch of program data into the respective pages. During this operation, the 3D memory device 800 also caches the (N+1)th batch of program data into the respective spaces in the SRAM 804 and checks the status of the (N-1)th batch of program data. In operation 1008, the 3D memory device 800 programs the (N+1)th batch of program data into the respective pages. During this operation, the 3D memory device 800 also caches the (N+2)th batch of program data into the respective spaces in the SRAM 804 and checks the status of the Nth batch of program data.

[0079] In some embodiments, the 3D memory device 800 may sequentially cache multiple batches of program data and program the cached program data into the 3D NAND memory 808. For example, the 3D memory device 800 may sequentially cache a backup copy of the (N-2)th batch of program data, a backup copy of the (N-1)th batch of program data, and a backup copy of the Nth batch of program data in the SRAM 804. The 3D memory device 800 may then sequentially program the (N-2)th batch of program data, the (N-1)th batch of program data, and the backup copy of the Nth batch of program data into respective pages of the 3D NAND memory 808 via the page buffer 806. In some embodiments, the 3D memory device 800 checks the status of the (N-2)th batch of program data after it has been programmed. If the programming is successful, the 3D memory device 800 can delete the backup copy of the (N-2)th batch of program data from the SRAM 804, and if the programming is unsuccessful, the 3D memory device 800 can reprogram the 3D NAND memory 808 (e.g., repeatedly as necessary) using the backup copy of the (N-2)th batch of program data until the status is successful. The SRAM 804 can then have space to cache the next batch of program data (e.g., the (N+1)th batch of program data). In some embodiments, the host 810 deletes the copies of the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data after these batches of program data are cached in the SRAM 804.

[0080] The 3D NAND memory 808 can include a multi-level cell (MLC) NAND memory device, where the number of pages corresponds to the number of bits stored in the memory cells. In some embodiments, the 3D NAND memory 808 includes a triple-level cell (TLC) NAND memory device packed into a RAM-less application environment, such as eMMC or UFS. In one example, the SRAM 804 has at least 648 kB of storage space to cache three batches of program data for a TLC NAND memory device with four planes.

[0081] The SRAM 804 may also be used as an on-die data buffer for the 3D memory device 800. FIG. 9B illustrates a system 930 in which the SRAM 804 functions as an on-die data buffer. For ease of illustration, the I / O 802 is omitted from FIG. 9B. In some embodiments, program data is programmed into the 3D NAND memory 808 in pages, and the SRAM 804 is illustrated as a plurality of data buffer units 914 (i.e., 914-1, ..., 914-L), each configured to buffer program data for programming a page in the 3D NAND memory 808. The 3D NAND memory 808 may be illustrated as a plurality of planes 908 (i.e., 908-1, ..., 908-M). M and L may each be a positive integer and may or may not be the same as each other. In operation, the plurality of data buffer units 914 may provide storage space for buffering program data before the program data is sent to the page buffer 806. This allows the program data stored in the host 810 and programmed into the 3D NAND memory 808 to be stored in the same chip as the 3D memory device 800, freeing up the main cache / buffer of the host 810 for storing this program data. The SRAM 804 also reduces the bandwidth on the data bus (e.g., between the 3D memory device 800 and the host 810) for transmitting this program data during program operations. Instead, data transmission and processing can be performed in the 3D memory device 800. Resources in the host 810 used to store, process, and transmit program data can be used for other purposes / operations. As shown in FIG. 9B, the 3D memory device 800 receives program data corresponding to different word lines from the host 810. The program data corresponding to the word lines are shown as WL0, ..., WLP. The program data can be transmitted from the host 810 to the SRAM 804 sequentially, in groups, or in any pattern before being buffered in the page buffer 806.The illustration of the program data WL0, . . . , WLP in 9B in each data buffer unit 914 is merely to illustrate the program data for programming a page and does not indicate sequential operation of the program data.

[0082] 11, method 1100 begins at operation 1102, where the 3D memory device 800 receives control instructions from a host 810 to condition the 3D memory device 800 for a first pass program and a second pass program on memory cells of a page in the 3D NAND memory 808. In some embodiments, the 3D memory device 800 initializes SRAM cells of the SRAM 804 in accordance with the control instructions, e.g., erases data in the SRAM cells / empties the SRAM cells, so that the SRAM 804 is ready to receive program data.

[0083] In operation 1104, the 3D memory device 800 buffers in the SRAM 804 the first program data for the first pass program and the second program data for the second pass program. In some embodiments, the word lines correspond to respective program data including the first program data and the second program data for programming the memory cells formed by the word lines and the intersecting memory strings. That is, for example, WL0 refers to the first program data and the second program data for programming the memory cells formed by WL0 (i.e., word line 0 and the intersecting memory cells). In some embodiments, the amount of program data buffered in the SRAM 804 is determined based on the storage capacity of the SRAM 804. Thus, the program data corresponding to WL0, ..., WLP can represent a portion or the entirety of the program data to be programmed into the 3D NAND memory 808. In some embodiments, the first pass program is a coarse program and the second pass program is a fine program.

[0084] The first and second program data for programming memory cells formed by one or more word lines can be buffered in the SRAM 804 in any suitable order before being loaded into the page buffer 806 for programming. For example, the first and second program data for programming memory cells formed by the first and second word lines can be buffered from the host 810 simultaneously (e.g., before performing a first pass program with the first program data) or can be buffered separately (e.g., the second program data can be buffered after the first pass program is completed). In various embodiments of the present disclosure, the first and second program data are each buffered in the SRAM 804 before being sent to the page buffer 806. In some embodiments, the first and second program data for programming memory cells in all planes of the 3D NAND memory 808 are buffered and stored in the SRAM 804 before being loaded into the page buffer 806.

[0085] In operation 1106, the 3D memory device 800 sequentially performs a first pass program using the first program data on the memory cells formed by the first word line and the second word line. The 3D memory device 800 may retrieve the buffered first program data from the SRAM 804 and send it to the page buffer 806 before being programmed into the respective memory cells in the 3D NAND memory 808. As described in this disclosure, memory cells formed by or corresponding to a word line refer to memory cells formed by the word line and a memory string intersecting the word line. In some embodiments, the memory cells are programmed in pages, e.g., the first pass program may be performed on all memory cells formed by the memory string and the first word line before being performed on the memory cells formed by the memory string and the second word line.

[0086] The memory cells being programmed may be MLC. For example, each memory cell being programmed may be a quad level cell (QLC) having four threshold voltage states (e.g., lower page data (LP), middle page data (MP), upper page data (UP), and extra page data (XP)) for storing 24 bits of data. The first program data and the second program data for programming each memory cell may be configured to program the memory cell to a desired threshold voltage state. Table 1 shows an example page map of a QLC in a page being programmed. Table 1 shows the program order of memory cells in a first pass program and a second pass program. In Table 1, string 0-string 5 refer to six memory strings intersecting with a word line, represented using "WL#".

[0087] [Table 1]

[0088] In some embodiments, Table 1 shows the order in which pass programs (e.g., first or second pass programs) are performed. For example, the 3D memory device 800 may sequentially program the memory cells formed by memory strings 0 through 5 and word lines (e.g., word lines 0, 1, 2, or 3) by sequentially programming four threshold voltage states (i.e., LP, MP, UP, and XP) to each memory cell. After the memory cells in each page formed by a memory string and one word line are programmed, the 3D memory device 800 proceeds to program the memory cells formed by the memory string and the next word line. In this operation, the first pass program is sequentially performed on the memory cells formed by strings 0 through 5 using the first and second word lines (e.g., WL0 and WL1) according to the order provided in Table 1.

[0089] In operation 1108, the 3D memory device 800 retrieves the second program data from the SRAM 804 and, once the first pass program is completed, executes a second pass program on the memory cells formed by the first word lines using the second program data. In some embodiments, once the first pass program is completed on the memory cells formed by the first and second word lines and all memory strings (e.g., string 0 through string 5), the 3D memory device 800 automatically begins executing the second pass program, e.g., without receiving permission from the host 810. Table 2 illustrates an exemplary order of memory cells in a page being programmed with a first pass program (e.g., a coarse program, denoted as "first" in Table 2) and a second pass program (e.g., a fine program, denoted as "second" in Table 2).

[0090] [Table 2]

[0091] As shown in Table 2, the 3D memory device 800 may sequentially perform a first pass program on memory cells formed by strings 0 to 5 using the first and second word lines (e.g., WL0 and WL1, as described in operation 1106) before sequentially performing a second pass program on memory cells formed by strings 0 to 5 using the first word line. In some embodiments, data (e.g., program data and / or control instructions) for performing the first and second pass programs are transmitted within the 3D memory device 800 without occupying data buses within the host 810 and between the host 810 and the 3D memory device 800. In some embodiments, the order shown in Table 2 is predetermined before the first and second pass programs are performed. The 3D memory device 800 may repeat the operations described above for memory cells formed by other word lines, for example, memory cells corresponding to WL2 and WL3, until programming of the memory cells is completed.

[0092] The 3D NAND memory 808 may include a multi-level cell (MLC) NAND memory device, where the number of pages corresponds to the number of bits stored in the memory cells. In one example, the SRAM 804 has at least 3.4 MB of storage space to buffer the first and second program data of the memory cells formed by two word lines in a QLC NAND memory device having four planes.

[0093] In some embodiments, a 3D memory device includes a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N-2)th batch of program data, where N is an integer greater than or equal to 2, program an (N-1)th batch of program data into respective pages in the 3D NAND memory array, and cache the Nth batch of program data in respective spaces in the on-die cache as a backup copy of the Nth batch of program data.

[0094] In some embodiments, the controller is configured to simultaneously check the status of the (N-2)th batch of program data, program the (N-1)th batch of program data, and cache the Nth batch of program data.

[0095] In some embodiments, in response to a status that the (N-2)th batch of program data has failed, the controller is further configured to retrieve a backup copy of the (N-2)th batch of program data from an on-die cache and program the backup copy of the (N-2)th batch of program data into a respective page within the 3D NAND memory array.

[0096] In some embodiments, the controller is further configured to read the Nth batch of program data from the on-die cache and transmit the Nth batch of read program data to the host.

[0097] In some embodiments, the controller is further configured to cache the (N-1)th batch of program data from the host to the on-die cache as a backup copy of the (N-1)th batch of program data when the (N-2)th batch of program data is being programmed into the respective page in the 3D NAND memory array.

[0098] In some embodiments, the controller is further configured to check a status of the (N-1)th batch of program data, program the Nth batch of program data into respective pages in the 3D NAND memory array, and cache the (N+1)th batch of program data into respective spaces in the on-die cache.

[0099] In some embodiments, to program respective batches of program data into respective pages in the 3D NAND memory array, the controller is configured to obtain buffered copies of the respective batches of program data from respective page buffers, and to program the buffered copies of the respective batches of program data into respective pages in the 3D NAND memory array.

[0100] In some embodiments, the controller is further configured to buffer each batch of program data in a respective page buffer before the respective batch of program data is programmed into a respective page.

[0101] In some embodiments, the controller is further configured to sequentially cache the backup copy of the (N-2)th batch of program data and the backup copy of the (N-1)th batch of program data in the on-die cache before caching the backup copy of the Nth batch of program data, and sequentially program the backup copies of the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data into their respective pages.

[0102] In some embodiments, the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data each include program data for multiple pages in the memory array.

[0103] In some embodiments, the 3D memory device includes a multi-level cell (MLC) NAND memory device. The number of pages may correspond to the number of bits stored in the memory cells.

[0104] In some embodiments, the controller is further configured to remove a copy of the Nth batch of program data from the host after the Nth batch of program data is cached in the on-die cache.

[0105] In some embodiments, the 3D memory device is packaged in at least one of eMMC or UFS.

[0106] In some embodiments, a system for performing a cache program operation on a 3D memory device includes a host, a storage unit having multiple pages of NAND memory cells and coupled to the host, a cache unit coupled on the same chip as the storage unit and configured to cache multiple batches of program data between the host and the storage unit, and a control unit coupled to the cache unit and the host. The control unit is configured to check a status of an (N-2)th batch of program data programmed from the host to the storage unit, where N is an integer equal to or greater than 2. The control unit is also configured to program the (N-1)th batch of program data into respective pages of the storage unit and cache the Nth batch of program data in respective spaces within the cache unit as a backup copy of the Nth batch of program data.

[0107] In some embodiments, the cache unit includes on-die SRAM cells.

[0108] In some embodiments, the control unit is configured to simultaneously check the status of the (N-2)th batch of program data, program the (N-1)th batch of program data, and cache the Nth batch of program data.

[0109] In some embodiments, in response to a status that the (N-2)th batch of program data has failed, the control unit is further configured to retrieve a backup copy of the (N-2)th batch of program data from the cache unit and program the backup copy of the (N-2)th batch of program data into a respective page of the storage unit.

[0110] In some embodiments, the control unit is further configured to read the Nth batch of program data from the cache unit and transmit the Nth batch of read program data to the host.

[0111] In some embodiments, the control unit is further configured to cache the (N-1)th batch of program data from the host to the cache unit as a backup copy of the (N-1)th batch of program data when the (N-2)th batch of program data is programmed into the respective page of the storage unit.

[0112] In some embodiments, the control unit is further configured to check a status of the (N-1)th batch of program data, program the Nth batch of program data into respective pages of the storage unit, and cache the (N+1)th batch of program data into respective spaces in the cache unit.

[0113] In some embodiments, to program respective batches of program data into respective pages of the storage unit, the control unit is configured to obtain buffered copies of the respective batches of program data from respective buffer units coupled to the storage units, and to program the buffered copies of the respective batches of program data into the respective pages of the storage unit.

[0114] In some embodiments, the control unit is further configured to buffer each batch of program data in a respective buffer unit before the respective batch of program data is programmed into the respective page.

[0115] In some embodiments, the control unit is further configured to sequentially cache the backup copy of the (N-2)th batch of program data and the backup copy of the (N-1)th batch of program data from the host into the cache unit before caching the backup copy of the Nth batch of program data, and sequentially program the backup copies of the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data from the cache unit into their respective pages.

[0116] In some embodiments, the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data each include multiple pages of program data.

[0117] In some embodiments, the storage unit includes a multi-level cell (MLC) NAND memory device, and the number of the plurality of pages corresponds to the number of bits stored in the memory cells.

[0118] In some embodiments, the control unit is further configured to delete a copy of the Nth batch of program data from the host after the Nth batch of program data is cached in the cache unit.

[0119] In some embodiments, a method for performing a cache program operation on a 3D memory device includes checking a status of an (N-2)th batch of program data programmed from a host to a storage unit, where N is an integer equal to or greater than 2. The method can also include programming the (N-1)th batch of program data into respective pages in the 3D NAND memory array and caching the Nth batch of program data in respective spaces in on-die static random access memory (SRAM) cells as a backup copy of the Nth batch of program data.

[0120] In some embodiments, checking the status of the (N-2)th batch of program data, programming the (N-1)th batch of program data, and caching the Nth batch of program data are performed simultaneously.

[0121] In some embodiments, in response to a status that the (N-2)th batch of program data has failed, the method further includes obtaining a backup copy of the (N-2)th batch of program data from the on-die SRAM cells and programming the backup copy of the (N-2)th batch of program data into a respective page in the 3D NAND memory array.

[0122] In some embodiments, the method further includes reading the Nth batch of program data from the on-die SRAM cells and transmitting the Nth batch of read program data to the host.

[0123] In some embodiments, the method further includes caching the (N-1)th batch of program data from the host to on-die SRAM cells as a backup copy of the (N-1)th batch of program data when the (N-2)th batch of program data is being programmed into the respective page in the 3D NAND memory array.

[0124] In some embodiments, the method further includes checking a status of the (N-1)th batch of program data, programming the Nth batch of program data into respective pages in the 3D NAND memory array, and caching the (N+1)th batch of program data into respective spaces in the on-die SRAM cells.

[0125] In some embodiments, programming the respective batches of program data to respective pages in the 3D NAND memory array includes obtaining buffered copies of the respective batches of program data from respective page buffers, and programming the buffered copies of the respective batches of program data to respective pages in the 3D NAND memory array.

[0126] In some embodiments, the method further includes buffering each batch of program data in a respective page buffer before the respective batch of program data is programmed into a respective page.

[0127] In some embodiments, the method further includes caching the backup copy of the (N-2)th batch of program data and the backup copy of the (N-1)th batch of program data from the host to on-die SRAM cells before caching the backup copy of the Nth batch of program data, and sequentially programming the (N-2)th batch of program data, the (N-1)th batch of program data, and the backup copies of the Nth batch of program data into respective pages in order from the on-die SRAM cells.

[0128] In some embodiments, the (N-2)th batch of program data, the (N-1)th batch of program data, and the Nth batch of program data each include multiple pages of program data.

[0129] In some embodiments, the 3D memory device is an MLC NAND memory device, and the number of pages corresponds to the number of bits stored in the memory cells.

[0130] In some embodiments, the method further includes deleting a copy of the Nth batch of program data from the host after the Nth batch of program data is cached in the on-die SRAM cells.

[0131] The foregoing description of specific embodiments reveals the general nature of the present disclosure, so that others may easily modify and / or adapt such specific embodiments to various applications by applying knowledge within the skill of those of ordinary skill in the art without departing from the general concept of the present disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It should be understood that the expressions or terms used herein are intended to be descriptive rather than limiting, as the terms or terms used herein would be interpreted by those of ordinary skill in the art in light of the teaching and guidance.

[0132] The embodiments of the present disclosure are described above with functional components illustrating implementation of specified functions and their relationships. The boundaries of these functional components are arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0133] The Summary and Abstract sections may describe one or more exemplary embodiments of the disclosure, but not all, contemplated by the inventors, and are therefore not intended to be in any way limiting of the scope of the disclosure and the appended claims.

[0134] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. a three dimensional (3D) NAND memory array; an on-die static random access memory (SRAM); a plurality of peripheral circuits coupled to the 3D NAND memory array and formed on the same chip as the on-die SRAM; The plurality of peripheral circuits include a page buffer coupled to the on-die SRAM; a controller coupled to the on-die SRAM and the page buffer, loading program data into the page buffer and caching the program data in the on-die SRAM as a backup copy of the program data; and a controller configured to, in response to a status that programming of the program data from the page buffer to the 3D NAND memory array has failed, send the backup copy of the program data in the on-die SRAM to the page buffer and program the backup copy of the program data in the page buffer into the 3D NAND memory array. 3D memory device.

2. The controller is further configured to cache the same program data in the on-die SRAM as the backup copy of the program data while loading the program data into the page buffer.

10. The 3D memory device of claim 1 .

3. a first semiconductor structure including the plurality of peripheral circuits and the on-die SRAM; a second semiconductor structure including the 3D NAND memory array; The first semiconductor structure and the second semiconductor structure are bonded via a bonding interface.

10. The 3D memory device of claim 1 .

4. Further comprising a device layer including a plurality of transistors; the page buffer includes a portion of the plurality of transistors; The on-die SRAM includes another portion of the plurality of transistors.

10. The 3D memory device of claim 1 .

5. The controller is configured to program first program data configured for a first pass program and second program data configured for a second pass program into the 3D NAND memory array.

10. The 3D memory device of claim 1 .

6. The controller is configured to sequentially program the first program data and the second program data into the 3D NAND memory array.

6. The 3D memory device of claim 5.

7. the on-die SRAM is configured to cache multiple batches of program data simultaneously, comprising an (N-2)th batch of program data and an (N-1)th batch of program data, where N is an integer greater than or equal to 2, the (N-2)th batch of program data being cached in the on-die SRAM as a backup copy of the (N-2)th batch of program data, and the (N-2)th batch of program data and the (N-1)th batch of program data being sequentially programmed into the 3D NAND memory array; The controller: Checking a status of programming the (N-2)th batch of program data into the 3D NAND memory array; configured to program the (N-2)th batch of program data into the 3D NAND memory array based on the backup copy of the (N-2)th batch of program data in the on-die SRAM in response to the status that programming of the (N-2)th batch of program data has failed.

10. The 3D memory device of claim 1 .

8. The controller is configured to delete the backup copy of the (N-2)th batch of program data in the on-die SRAM in response to the status that the programming of the (N-2)th batch of program data was successful.

8. The 3D memory device of claim 7.

9. an (N-2)th batch of program data, an (N-1)th batch of program data, and an Nth batch of program data, where N is an integer equal to or greater than two, being programmed, in that order, into the 3D NAND memory array; While programming the (N-1)th batch of program data into the 3D NAND memory array, the controller is configured to cache the Nth batch of program data in the on-die SRAM as a backup copy of the Nth batch of program data along with a backup copy of the (N-2)th batch of program data and a backup copy of the (N-1)th batch of program data in the on-die SRAM.

10. The 3D memory device of claim 1 .

10. while programming the (N-1)th batch of program data into the 3D NAND memory array, the controller is configured to check a status of programming the (N-2)th batch of program data into the 3D NAND memory array; configured to, in response to the status that programming of the (N-2)th batch of program data has failed, send the backup copy of the (N-2)th batch of program data in the on-die SRAM to the page buffer and program the backup copy of the (N-2)th batch of program data in the page buffer into the 3D NAND memory array.

10. The 3D memory device of claim 1 .

11. the 3D NAND memory array comprises a plurality of pages; The on-die SRAM comprises a plurality of cache units, each corresponding to one of the plurality of pages, and each of the plurality of cache units is configured to cache a portion of the program data for programming one of the plurality of pages in the 3D NAND memory array.

10. The 3D memory device of claim 1 .

12. caching the same batch of program data simultaneously in said multiple cache units; The controller is configured to simultaneously load the same batch of program data from each of the plurality of cache units into the page buffer.

12. The 3D memory device of claim 11.

13. a host coupled to the 3D memory device and configured to sequentially transmit multiple batches of program data to the page buffer; The controller: sequentially loading the batches of program data into the page buffer as buffered copies of the batches of program data; configured to sequentially program the batches of program data into the 3D NAND memory array based on the buffered copies of the batches of program data.

10. The 3D memory device of claim 1 .

14. the on-die SRAM is disposed between the host and the page buffer; The controller: sequentially caching the batches of program data in the on-die SRAM as backup copies of the batches of program data; configured to program a batch of the plurality of batches of program data into the 3D NAND memory array based on a backup copy of the batch of program data in response to determining that programming of the batch of program data is unsuccessful based on a buffered copy corresponding to the batch.

14. The 3D memory device of claim 13.

15. an (N-2)th batch of program data, an (N-1)th batch of program data, and an Nth batch of program data, where N is an integer equal to or greater than two, being programmed, in that order, into the 3D NAND memory array; The controller, in parallel, Checking a status of programming the (N-2)th batch of program data into the 3D NAND memory array; programming the (N-1)th batch of program data into the 3D NAND memory array; configured to cache the Nth batch of program data in the on-die SRAM as a backup copy of the Nth batch of program data along with a backup copy of the (N-2)th batch of program data in the on-die SRAM and a backup copy of the (N-1)th batch of program data.

10. The 3D memory device of claim 1 .

16. In response to the status that programming of the (N-2)th batch of program data based on the buffered copy of the (N-2)th batch of program data has failed, the controller is configured to program the (N-2)th batch of program data based on the backup copy of the (N-2)th batch of program data.

16. The 3D memory device of claim 15.

17. In response to the status that the programming of the (N-2)th batch of program data is successful, the controller is configured to delete the backup copy of the (N-2)th batch of program data in the on-die SRAM.

16. The 3D memory device of claim 15.

18. The controller is configured to obtain the program data from a host and to send the program data to the page buffer and to the on-die SRAM, respectively.

10. The 3D memory device of claim 1 .

19. a first semiconductor structure comprising a three dimensional (3D) NAND memory array; a second semiconductor structure having a plurality of peripheral circuits and an on-die static random access memory (SRAM), the first semiconductor structure and the second semiconductor structure being bonded via a bonding interface to couple the 3D NAND memory array to the plurality of peripheral circuits and the on-die SRAM; The plurality of peripheral circuits include a page buffer coupled to the on-die SRAM; a controller coupled to the on-die SRAM and the page buffer, loading a first batch of program data into the page buffer and caching the first batch of program data in the on-die SRAM as a backup copy of the first batch of program data along with a backup copy of a second batch of program data in the on-die SRAM; and a controller configured to, in response to a status that programming of the first batch of program data from the page buffer to the 3D NAND memory array has failed, send the backup copy of the first batch of program data in the on-die SRAM to the page buffer and program the backup copy of the first batch of program data in the page buffer into the 3D NAND memory array. 3D memory device.

20. The host, a memory device coupled to the host, a three dimensional (3D) NAND memory array; an on-die static random access memory (SRAM); a memory device coupled to the 3D NAND memory array and including a plurality of peripheral circuits formed on the same chip as the on-die SRAM; The plurality of peripheral circuits include a page buffer coupled to the on-die SRAM and configured to receive from the host a number of batches of program data to be sequentially programmed into the 3D NAND memory array; a controller coupled to the on-die SRAM and the page buffer, loading a batch of the plurality of batches of program data into the page buffer and caching the batch of program data in the on-die SRAM as a backup copy of the batch of program data; and a controller configured to, in response to a status that programming of the batch of program data from the page buffer to the 3D NAND memory array has failed, send the backup copy of the batch of program data in the on-die SRAM to the page buffer and program the backup copy of the batch of program data in the page buffer into the 3D NAND memory array. Memory system.

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