Memory loop

Abstract

To provide a memory circuit capable of being made compact and reducing the number of transistors.SOLUTION: A memory circuit includes: a bistable circuit having first to fourth FETs; first and second switches, one end of which is connected to first and second memory nodes respectively; first and second non-volatile memory elements, one end of which is connected to the other end of the first and second switches, and the other end of which is connected to a control line, respectively; and a control circuit that turns off the first and second switches when writing or reading the bistable circuit and turns on the first and second switches when performing a storing operation for non-volatilely storing data from the bistable circuit to the first and second non-volatile memory elements and when performing a restore operation for restoring the data from the first and second non-volatile memory elements to the bistable circuit.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a memory circuit. [Background technology]

[0002] Pseudo non-volatile static random access memory (SRAM) (VNR-SRAM) or ultra-low voltage (ULV) retention static random access memory (SRAM) (ULVR-SRAM) is known that uses an inverter composed of a complementary metal oxide semiconductor (CMOS) without using a non-volatile memory element (see, for example, Patent Document 1). VNR-SRAM uses a dual mode inverter that can switch between a Schmitt trigger (ST) mode that allows ULV retention and a boosted inverter (BI) mode that can achieve circuit performance equivalent to that of SRAM at normal voltage. This ULV retention SRAM can be used for so-called power gating (PG).

[0003] Also, a memory circuit using a memory cell (NV-SRAM) having a bistable circuit and a nonvolatile memory element is known (for example, Patent Document 2). In the NV-SRAM, data from the bistable circuit is stored in the nonvolatile memory element to reduce power consumption, and when necessary, the data from the nonvolatile memory element is restored to the bistable circuit, making the data unavailable.

[0004] Furthermore, studies are being conducted to speed up neural network processing by combining an SRAM for storing coefficients such as weighting coefficients of the neural network with a calculation circuit for product-sum or evaluation functions (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2016 / 158691 [Patent Document 2] International Publication No. 2009 / 028298 [Non-patent literature]

[0006] [Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, pp,983-994, 2018. Summary of the Invention [Problem to be solved by the invention]

[0007] In the VNR-SRAM of Patent Document 1, ULV retention is used to reduce standby power consumption without losing the memory contents of the cell. However, in the VNR-SRAM, 14 or 10 transistors are used in one memory cell (hereinafter referred to as a 14T cell and a 10T cell, respectively). This causes a first problem that the memory cell becomes larger or the cell area increases. In addition, reducing the number of transistors, such as in the 10T cell, reduces the stability (noise margin) of ULV retention.

[0008] Furthermore, the NV-SRAM of Patent Document 2 uses a nonvolatile memory element in the memory cell, which allows the power supply to the memory cell to be cut off during standby, thereby reducing standby power consumption. However, one memory cell uses eight transistors in addition to the nonvolatile memory element. This poses a second problem in that it is difficult to miniaturize the memory cell or the cell area increases.

[0009] In view of the first or second object, an object of the present invention is to provide a memory circuit that can be miniaturized or that has a reduced number of transistors. [Means for solving the problem]

[0010] The present invention relates to a semiconductor device including a first FET having a channel of a first conductivity type, the source of which is connected to a power supply line, the drain of which is connected to a first storage node, and the gate of which is connected to a second storage node; a second FET having a channel of the first conductivity type, the source of which is connected to the power supply line, the drain of which is connected to the second storage node, and the gate of which is connected to the first storage node; a third FET having a channel of a second conductivity type opposite to the first conductivity type, the one of which is connected to the first storage node, the other of which is connected to a first control line, and the gate of which is connected to a word line; a fourth FET of the second conductivity type channel, one of whose source and drain is connected to the second storage node, the other of whose source and drain is connected to a second control line, and a gate of which is connected to the word line; a first switch having one end connected to the first storage node, a second switch having one end connected to the second storage node, a first nonvolatile storage element having one end connected to the other end of the first switch and the other end connected to a third control line; and a second nonvolatile storage element having one end connected to the other end of the second switch and the other end connected to the third control line. a control circuit that turns off the first switch and the second switch during a write operation for volatilely writing data to the bistable circuit and a read operation for reading data from the bistable circuit, and turns on the first switch and the second switch during a store operation for nonvolatilely storing data from the bistable circuit to the first nonvolatile memory element and the second nonvolatile memory element and a restore operation for restoring data from the first nonvolatile memory element and the second nonvolatile memory element to the bistable circuit, wherein the control circuit executes the store operation. a first store operation is performed in which the word line is set to a first voltage, the first control line and the second control line are set to a second voltage, and the third control line is set to a third voltage, and a second store operation is performed in which the word line is set to a fourth voltage, the first control line and the second control line are set to a fifth voltage, and the third control line is set to a sixth voltage, when the first conductivity type is N-type, the first voltage is lower than the fourth voltage, the second voltage and the fifth voltage are higher than a voltage of the power supply line, and the third voltage is lower than the sixth voltage, and when the first conductivity type is P-type, the first voltage is higher than the fourth voltage,The second voltage and the fifth voltage are lower than the voltage of the power supply line, and the third voltage is higher than the sixth voltage.

[0011] In the above configuration, when the first conductivity type is N-type, the fourth voltage can be lower than the fifth voltage, and when the first conductivity type is P-type, the fourth voltage can be higher than the fifth voltage.

[0012] In the above configuration, the control circuit can be configured, when performing the restore operation, to set the voltage of the word line to be higher than the lower of the voltages of the first memory node and the second memory node during the write operation, and lower than the higher of the voltages of the first memory node and the second memory node.

[0013] Another aspect of the present invention relates to a bistable circuit comprising: a first FET of a channel of a first conductivity type, the source of which is connected to a power supply line, the drain of which is connected to a first storage node, and the gate of which is connected to a second storage node; a second FET of the channel of the first conductivity type, the source of which is connected to the power supply line, the drain of which is connected to the second storage node, and the gate of which is connected to the first storage node; a third FET of a channel of a second conductivity type opposite to the first conductivity type, the one of whose source and drain is connected to the first storage node, the other of whose source and drain is connected to a first control line, and the gate of which is connected to a first word line; a fourth FET of the channel of the second conductivity type, the one of whose source and drain is connected to the second storage node, the other of whose source and drain is connected to a second control line, and the gate of which is connected to a second word line; and a fifth FET of the channel of the second conductivity type, the one of whose source and drain is connected to the second storage node, the other of whose source and drain is connected to a fourth control line, and the gate of which is connected to a third word line; a second switch, a first nonvolatile storage element having one end connected to the other end of the first switch and the other end connected to a third control line, a second nonvolatile storage element having one end connected to the other end of the second switch and the other end connected to the third control line, and turning off the first switch and the second switch during a write operation for volatilely writing data to the bistable circuit and a read operation for reading data from the bistable circuit, and turning off the first switch and the second switch during a store operation for nonvolatilely storing data from the bistable circuit to the first nonvolatile storage element and the second nonvolatile storage element and and a control circuit which turns on the first switch and the second switch during a restore operation of restoring data from the second nonvolatile memory element and the second nonvolatile memory element to the bistable circuit, wherein the control circuit turns on the third FET using the first word line, writes data to the bistable circuit using the first control line, turns on the fourth FET using the second word line, reads data from the bistable circuit using the second control line, turns on the fifth FET using the third word line, and reads data from the bistable circuit using the fourth control line.

[0014] In the above configuration, when the first conductivity type is N-type, the control circuit can be configured to make the voltage of the first word line when reading data from the bistable circuit higher than the voltage of the first word line when writing data to the bistable circuit and lower than the higher of the voltage of the second word line and the voltage of the third word line when reading data from the bistable circuit, and when the first conductivity type is P-type, to make the voltage of the first word line when reading data from the bistable circuit lower than the voltage of the first word line when writing data to the bistable circuit and higher than the lower of the voltage of the second word line and the third word line when reading data from the bistable circuit.

[0015] Yet another aspect of the present invention includes a first FET having a channel of a first conductivity type, the channel having a source connected to a power supply line, a drain connected to a first storage node, and a gate connected to a second storage node; a second FET having a channel of the first conductivity type, the source connected to the power supply line, the drain connected to the second storage node, and a gate connected to the first storage node; a third FET having a channel of a second conductivity type opposite to the first conductivity type, the one of its source and drain connected to the first storage node, the other of its source and drain connected to a first control line, and a gate connected to a first word line; and a fourth FET having the channel of the second conductivity type, the one of its source and drain connected to the second storage node, the other of its source and drain connected to a second control line, and a gate connected to the first word line. a fifth FET of the second conductivity type having a channel of the second conductivity type, one of a source and a drain connected to the second storage node, the other of the source and the drain connected to a fourth control line, and a gate connected to a second word line; a sixth FET of the second conductivity type channel, one of a source and a drain connected to the first storage node, the other of the source and the drain connected to a fifth control line, and a gate connected to the second word line; a first switch having one end connected to the first storage node, a second switch having one end connected to the second storage node, a first nonvolatile storage element having one end connected to the other end of the first switch and the other end connected to a third control line, and a second nonvolatile storage element having one end connected to the other end of the second switch and the other end connected to the third control line; and a control circuit which turns on the first switch and the second switch during a store operation of nonvolatilely storing data from the first path to the first nonvolatile memory element and the second nonvolatile memory element and during a restore operation of restoring data from the first nonvolatile memory element and the second nonvolatile memory element to the bistable circuit, wherein the control circuit turns on the third FET and the fourth FET using the first word line, writes data to the bistable circuit and reads data from the bistable circuit using the first control line and the second control line, turns on the fifth FET and the sixth FET using the second word line, and writes data to the bistable circuit and reads data from the bistable circuit using the fourth control line and the fifth control line. Effect of the Invention

[0016] According to the present invention, it is possible to provide a memory circuit that can be miniaturized or that has a reduced number of transistors. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a circuit diagram showing a loop of memory cells in a first comparative example. [Diagram 2] FIG. 2 is a circuit diagram showing a cross-coupled memory cell in the first comparative example. [Diagram 3]FIG. 3 is a circuit diagram showing a loop of memory cells in the second comparative example. [Figure 4] FIG. 4 is a circuit diagram showing a cross-coupled memory cell in the second comparative example. [Diagram 5] FIG. 5 is a circuit diagram showing a loop of memory cells in the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a cross-coupled memory cell in the first embodiment. [Figure 7A] FIG. 7A is a block diagram of a memory array according to the first embodiment. [Figure 7B] FIG. 7B is a diagram illustrating the power switches and the selection circuit according to the first embodiment. [Figure 7C] FIG. 7C is a block diagram illustrating another example of the memory array according to the first embodiment. [Figure 8] 8(a) and 8(b) are diagrams showing SNM and standby power with respect to WLP and WFB in the VDD retention state in the first embodiment. [Figure 9] 9(a) and 9(b) are diagrams showing SNM and standby power with respect to VWL in the VDD retention state and in read in the read / write state in Example 1 and Comparative Example 3. In FIG. [Figure 10] 10(a) to 10(c) are diagrams showing SNM in the VDD retention state and the read / write state in Example 1 and Comparative Examples 2 and 3. FIG. [Figure 11] FIG. 11 is a diagram showing the transfer characteristics of the inverter circuit in the ULV retention state in the first embodiment. [Figure 12] 12(a) and 12(b) are circuit diagrams of a bistable circuit in the first embodiment. [Figure 13] 13(a) and 13(b) are diagrams showing butterfly curves of the bistable circuits in the ULV retention state of Example 1 and Comparative Examples 2 and 3. [Figure 14]FIG. 14(a) is a diagram showing SNM in the ULV retention state of Example 1 and Comparative Examples 2 and 3, and FIG. 14(b) is a diagram showing SNM and standby power with respect to VVDD in the ULV retention state of Example 1. [Figure 15] FIG. 15 is a diagram showing the standby power in Example 1 and Comparative Example 3. In FIG. [Figure 16] FIG. 16 is a circuit diagram showing a loop of memory cells in the first modification of the first embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a cross-coupled memory cell in the first modification of the first embodiment. [Figure 18] FIG. 18 is a circuit diagram showing a loop of memory cells in the second modification of the first embodiment. [Figure 19] FIG. 19 is a circuit diagram showing a cross-coupled memory cell in the second modification of the first embodiment. [Figure 20] FIG. 20 is a diagram showing butterfly curves of the bistable circuits in the ULV retention state of the first embodiment and the second modification thereof. [Figure 21] 21(a) and 21(b) are diagrams showing the voltages of the header PS·PDFB·Type 1 and the footer PS·PUFB·Type 1, respectively. [Figure 22] FIG. 22 is a circuit diagram of a memory cell of the virtual power supply system in the second embodiment. [Diagram 23] FIG. 23 is a diagram illustrating a power switch and a selection circuit in a virtual power supply system according to the second embodiment. [Figure 24] FIG. 24 is a circuit diagram of a memory cell of the virtual ground system in the second embodiment. [Diagram 25] FIG. 25 is a diagram illustrating a power switch and a selection circuit in the virtual ground system according to the second embodiment. [Figure 26] FIG. 26 is a block diagram of a memory array in the second embodiment. [Figure 27] 27(a) to 27(c) are diagrams showing the operation of a memory cell in the second embodiment. [Figure 28]28(a) to 28(c) are diagrams showing the operation of a memory cell in the second embodiment. [Figure 29] FIG. 29 is a diagram illustrating the operation of a memory cell in the second embodiment. [Diagram 30] FIG. 30 is a diagram showing SNM and standby power for the WLP in the hold state in simulation 3. In FIG. [Diagram 31] FIG. 31 is a diagram showing SNM with respect to VWL during a read operation and in a hold state in simulation 3. In FIG. [Diagram 32] 32(a) and 32(b) are diagrams showing the currents Im1 and SNM, respectively, versus the voltage VSR of the H-store operation in simulation 3. FIG. [Diagram 33] 33(a) and 33(b) are diagrams showing the currents Im2 and SNM, respectively, versus the voltage Vc of the L-store operation in simulation 3. [Diagram 34] 34(a) and 34(b) are diagrams showing SNM versus voltage VSR of FF and FS, respectively, in the restore operation in simulation 3. FIG. [Diagram 35] FIG. 35(a) is a diagram showing the SNM in Example 2, and FIG. 35(b) is a diagram showing the standby power in Example 2 and Comparative Example 3. [Diagram 36] FIG. 36 is a circuit diagram of a memory cell according to a first modification of the second embodiment. [Figure 37] FIG. 37 is a diagram illustrating a BNN model in the third embodiment. [Figure 38] FIG. 38 is a block diagram of an arithmetic circuit for performing an n-to-1 connection arithmetic operation in the third embodiment. [Figure 39] FIG. 39(a) is a block diagram of an arithmetic circuit that performs 1-to-n connection calculations in the third embodiment, and FIG. 39(b) is a block diagram of an accumulator. [Diagram 40] FIG. 40 is a block diagram of a BNN device in the third embodiment. [Diagram 41]FIG. 41 is a flowchart showing the n-to-1 connection processing performed by the processor 52 in the third embodiment. [Diagram 42] FIG. 42 is a flowchart showing the process of the 1-to-n connection performed by the processor 62 in the third embodiment. [Diagram 43] FIG. 43 is a diagram showing the process with respect to time in the third embodiment. [Diagram 44] FIG. 44 is a block diagram illustrating an example of a memory according to the second embodiment. [Diagram 45] FIG. 45 is a block diagram of a BNN device in the first modified example of the third embodiment. [Diagram 46] FIG. 46 is a diagram illustrating an example of a memory according to the first modification of the third embodiment. [Figure 47] FIG. 47 is a circuit diagram showing an example of a 2R1W type NV-SRAM memory cell in the second modification of the third embodiment. [Figure 48] FIG. 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in the second modification of the third embodiment. [Figure 49] FIG. 49(a) is a diagram showing SNM versus VWWL of a 2R1W type NV-SRAM memory cell during a read operation of the second modification of the third embodiment, and FIG. 49(b) is a diagram showing SNM versus VWWL of a 2R1W type ULVR-SRAM memory cell during a read operation. [Figure 50] FIG. 50 is a circuit diagram showing an example of a 2RW NV-SRAM memory cell in the second modification of the third embodiment. [Figure 51] FIG. 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in the second modification of the third embodiment. [Figure 52] FIG. 52 is a diagram illustrating an example of a 2R1W type memory according to the second modification of the third embodiment. [Figure 53] FIG. 53 is a diagram illustrating an example of a 2RW type memory according to the second modification of the third embodiment. [Figure 54] FIG. 54 is a diagram showing a process with respect to time in the modified example of the third embodiment. [Figure 55]55(a) to 55(c) are diagrams showing normalized processing time versus the number of layers m. [Figure 56] FIG. 56 is a circuit diagram of an NV-SRAM memory cell according to the fourth modification of the third embodiment. [Figure 57] FIG. 57 is a circuit diagram of a ULVR-SRAM memory cell according to the fourth modification of the third embodiment. [Figure 58] FIG. 58 is a block diagram of a BNN device in the fourth modification of the third embodiment. [Figure 59] 59(a) and 59(b) are block diagrams of the vicinity of the power switch of Comparative Example 4 and Modification 5 of Example 3, respectively. [Figure 60] FIG. 60 is a circuit diagram of a 6T cell in the fifth modification of the third embodiment. [Figure 61] 61(a) and 61(b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Figures 1 and 2: Comparative Example 1 Figures 3 and 4: Comparative Example 2 FIG. 5 to FIG. 7C: Example 1 FIG. 8(a) to FIG. 10(c): Simulation 1, Comparative Examples 2 and 3, Example 1 11 to 15: Simulation 2, Comparative Examples 2 and 3, Example 1 16-17: Modification 1 of the first embodiment 18 to 20: Modification 2 of the first embodiment FIG. 21: Example 1 and its modifications FIG. 22 to FIG. 29: Example 2 Figures 30 to 35(b): Simulation 3, Example 2 FIG. 36: Modification 1 of the second embodiment Figures 37 to 44: Example 3 Figures 45-46: Modification 1 of the third embodiment Figures 47 to 53: Modification 2 of the third embodiment Figures 54 to 55(c): Simulations of Example 3 and its Modifications 1 to 3 Figures 56 to 58: Modification 4 of the third embodiment FIG. 59(a) to FIG. 61(b): Modification 5 of the third embodiment

[0019] Before describing the examples, a comparative example will be described.

[0020] [Comparative Example 1] In Comparative Example 1, the conductivity type of the feedback transistor and the connection destination of the gate are different from those in Patent Document 1. Figures 1 and 2 are circuit diagrams of a memory cell 10 in Comparative Example 1. Figure 1 is a circuit diagram with a loop display, and Figure 2 is a circuit diagram with a cross-couple display. Although Figures 1 and 2 show the same circuit, the loop display in Figure 1 is easier to understand for explaining the operation, and the cross-couple display in Figure 2 is easier to understand for explaining the circuit area, etc.

[0021] 1 and 2, the inverter circuits 14 and 16 include FETs m1 to m3 and m1a to m3a. The FETs m1, m2 and m3a are N-channel MOSFETs, and the FETs m1a, m2a and m3 are P-channel MOSFETs.

[0022] FETs m1, m2, m1a, and m2a are connected in series between a ground line 15b and a power line 15a (virtual power line). The gates of FETs m1, m2, m1a, and m2a are connected to an input node N1. An output node N2 is between FETs m2 and m2a. FETs m1 and m2 are drivers of inverter circuits 14 and 16, and FETs m1a and m2a are loads.

[0023] FET m3 is connected between an intermediate node N3 between FET m1 and m2 and a bias node N4, and FET m3a is connected between an intermediate node N3a between FET m1a and m2a and a bias node N4a. The gates of FET m3 and m3a are connected to the input node N1. FET m3 and m3a are feedback transistors FBTr.

[0024] The storage nodes Q1 and Q2 are connected to the bit lines BL and BLB, respectively, via a FETm5. The gate of the FETm5 is connected to the word line WL. The FETm5 is an N-channel FET and a pass transistor.

[0025] The driver 26 includes inverters 27a and 27b. The inverter 27a outputs a signal VFN obtained by inverting a control signal VCTRL to a bias node N4, and the inverter 27b outputs a signal VFP obtained by inverting the signal VFN to a bias node N4a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c to a virtual power supply voltage VVDD and supplies it to the power supply line 15a. The power switch 30 switches the virtual power supply voltage VVDD according to a control signal from a control circuit (not shown).

[0026] In the memory cell according to Comparative Example 1, the mode of the inverter circuits 14 and 16 can be changed between ST mode and BI mode by the control signal VCTRL. When the control signal VCTRL is at a high level (VVDDH, for example, 1.2 V), the inverter circuits 14 and 16 are in the BI mode. When the control signal VCTRL is at a low level (VGND, for example, 0 V), the inverter circuits 14 and 16 are in the ST mode.

[0027] The ST mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have hysteresis, and the BI mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have substantially no hysteresis. In the ST mode, if the virtual power supply voltage VVDD-VGND applied to the inverter circuits 14 and 16 is a normal voltage (e.g., 1.2V), the leakage current becomes large. In the BI mode, even if the voltage VVDD-VGND is a normal voltage, the leakage current is smaller than in the ST mode. Note that substantially no hysteresis means that there is no intentional hysteresis like in the ST mode, and unintentional hysteresis is allowed.

[0028] In the BI mode, the memory cell 10 functions as a normal SRAM cell. In the ST mode, the bistable circuit 12 retains data even if the voltage (VVDD-VGND) is set to, for example, 0.2 V, which is an ultralow voltage (ULV).

[0029] Table 1 shows the state in Comparative Example 1. [Table 1]

[0030] The state in which data is read from and written to the memory cell 10 is the read / write state. In the read / write state, the control signal VCTRL is at high level H. This puts the inverter circuits 14 and 16 into the BI mode. The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2V). The voltage (VVDD-VGND) becomes VH (e.g., 1.2V). By setting the voltage VWL of the word line WL of the memory cell 10 to be read or written to a high level (e.g., 1.2V), the FET m5 turns on, and data can be read from or written to the bistable circuit 12.

[0031] During normal operation, the state in which data is held is the VDD retention state. In the VDD retention state, the control signal VCTRL is at high level H, and the inverter circuits 14 and 16 are in the BI mode. The virtual power supply voltage VVDD is VVDDH (e.g., 1.2 V), and the voltage (VVDD-VGND) is VH (e.g., 1.2 V). Since no read or write is being performed, the voltage VWL of the word line WL is at a low level (e.g., 0 V), and the FET m5 is off.

[0032] The state in which data in the memory cell 10 is held at an ultra-low voltage is the ULV retention state. In the ULV retention state, the control signal VCTRL is at a low level L, and the inverter circuits 14 and 16 are in the ST mode. The power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2 V). The voltage (VVDD-VGND) becomes VL (e.g., 0.2 V) lower than VH. The voltage VWL is at a low level (e.g., 0 V), and the FET m5 is off.

[0033] [Comparative Example 2] 3 and 4 are circuit diagrams of the memory cell 10 in Comparative Example 2. Fig. 3 is a circuit diagram showing a loop, and Fig. 4 is a circuit diagram showing a cross-coupled.

[0034] 3 and 4, the second comparative example does not include FETs m2a and m3a and a driver 26. The other configurations are the same as those of the first comparative example.

[0035] Table 2 shows the state in Comparative Example 2. [Table 2]

[0036] As shown in Table 2, the voltage of the bias node N4 is constant at VFN (e.g., 0.2V) regardless of the mode. In the read / write state, the power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2V) in response to a control signal from a control circuit (not shown). The virtual power supply voltage (VVDD-VGND) applied to the bistable circuit 12 becomes VH (e.g., 1.2V). At this time, the inverter circuits 14 and 16 are in the BI mode. The voltage VWL of the word line WL is at a high level (e.g., 1.2V). In the VDD retention state, the virtual power supply voltage VVDD is VVDDH (e.g., 1.2V), the voltage (VVDD-VGND) is VH (e.g., 1.2V), and the inverter circuits 14 and 16 are in the BI mode. The voltage VWL of the word line WL is at a low level (0V).

[0037] In the ULV retention state, the power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2V). The voltage (VVDD-VGND) becomes VL (e.g., 0.2V) lower than VH. At this time, the inverter circuits 14 and 16 are in the ST mode. The voltage VWL is at a low level (e.g., 0V). As in the comparative example 1, power consumption can be suppressed in the ULV retention state.

[0038] A type in which a FETm3 is provided as a feedback transistor FBTr between N-channel FETs m1 and m2 is called pull-down feedback PDFB. A type in which a FETm3a is provided as a feedback transistor FBTr between P-channel FETs m1a and m2a is called pull-up feedback PUFB. A type in which both FETs m3 and m3a are provided is called pull-up pull-down feedback PUPDFB. Comparative Example 1 is PUPDFB, and Comparative Example 2 is PDFB.

[0039] When FBTr and the FET to which FBTr are connected have different conductivity type channels, they are called different conductivity type channel FBTr. In comparative example 2 which is PDFB, FETm3 which is FBTr has a P-type channel, and FETm1 and m2 to which FETm3 is connected have N-type channels. Therefore, when FBTr is a P-type channel in PDFB, it is a different conductivity type channel FBTr. When FBTr is an N-type channel in PUFB, it is a different conductivity type channel FBTr. When FBTr and the FET to which FBTr are connected have the same conductivity type channels, they are called same conductivity type channel FBTr. When FBTr is an N-type channel in PDFB, and when FBTr is a P-type channel in PUFB, it is a same conductivity type channel FBTr.

[0040] In the different conductivity type channel FBTr, the gate is connected to the input node of the same inverter circuit or the output node of the other inverter circuit. In the same conductivity type channel FBTr, the gate is connected to the output node of the same inverter circuit or the input node of the other inverter circuit. Comparative Examples 1 and 2 are different conductivity type channel FBTr. Patent Document 1 discloses a same conductivity type channel FBTr.

[0041] A system in which a power switch 30 is provided between the power line 15a and the power supply 15c, the power switch 30 sets a virtual power supply voltage VVDD, and the voltage VVDD-VGND is used as the power supply voltage for the memory cell 10 is called a header PS. A system in which a power switch 30 is provided between the ground line 15b and the ground, the power switch 30 sets a virtual ground voltage VVGND, and the voltage VDD-VVGND is used as the power supply voltage for the memory cell 10 is called a footer PS. A system in which a power switch 30 is provided both between the power line 15a and the power supply 15c and between the ground line 15b and the ground, the power switch 30 sets a virtual power supply voltage VVDD and a virtual ground voltage VVGND, and the voltage VVDD-VVGND is used as the power supply voltage for the memory cell 10 is called a dual PS. Comparative examples 1 and 2 are header PSs.

[0042] A method of switching between ST mode and BI mode by providing a driver 26 and applying high and low levels to bias nodes N4 and N4a by a control signal VCTRL is called Type 2. A method of not providing a driver 26 and setting bias node N4 to a constant voltage (constant bias) is called Type 1. Comparative Example 1 is Type 2, and Comparative Example 2 is Type 1.

[0043] In summary, Comparative Example 1 includes PUPDFB, a different conductivity type channel FBTr, a header PS, and Type 2. Comparative Example 2 includes PDFB, a different conductivity type channel FBTr, a header PS, and Type 1.

[0044] It will be explained that the different conductivity type channel FBTr improves the operational stability (eg, noise margin) of the bistable circuit 12 in the ULV retention state compared to the same conductivity type channel FBTr.

[0045] For example, in Comparative Example 2, when FETm3 is an N-type channel (i.e., the same conductivity type channel), the gates of FETm3 of the inverter circuits 14 and 16 are connected to the output nodes N2 of the inverter circuits 14 and 16, respectively. In the ULV retention state, for example, when the storage nodes Q1 and Q2 are at low and high levels, respectively, the FETm3 of the inverter circuit 14 turns on, and the intermediate node N3 is charged from the bias node N4 of the voltage VFN. However, since the FETm3 is an N-type channel and the threshold voltage Vth of the FETm3 is positive, the charging potential from the bias node N4 is insufficient. This may reduce the feedback effect of the FETm3, which is an FBTr, and the operational stability of the bistable circuit in the ULV retention state may decrease.

[0046] On the other hand, when FETm3 is a P-type channel (i.e., a channel of a different conductivity type) as in Comparative Example 2, for example, when the storage nodes Q1 and Q2 are at low level and high level, respectively, FETm3 of the inverter circuit 14 is turned on. The intermediate node N3 is charged from the bias node N4 whose voltage is VFN. Since FETm3 is a P-type channel and a voltage sufficiently low to the source and drain is applied to the gate of FETm3, the intermediate node N3 can be pulled up to VFN. This allows the feedback effect of FETm3 to be sufficiently generated. Therefore, the operational stability of the bistable circuit in the ULV retention state can be improved.

[0047] Next, it will be described how Comparative Example 2 becomes Type 1. In Comparative Example 2, VFN is a constant bias of about VVDDL. When VVDDH is applied to the power supply line 15a, VFN is sufficiently lower than VVDDH, so the inverter circuits 14 and 16 are in the BI mode. When VVDDL is applied to the power supply line 15a, VFN is higher than VGND and is equal to or close to VVDDL, so the inverter circuits 14 and 16 are in the ST mode. In this way, the PDFB·Header PS does not require the driver 26. Similarly, the PUFB·Footer PS does not require the driver 26.

[0048] In Comparative Example 1, the number of transistors in the memory cell 10 is 14, and a driver 26 is provided. This increases the circuit area as shown in FIG. 2. Feedback is applied by FBTr (FETs m3 and m3a) on both the pull-up side and the pull-down side of the inverter circuits 14 and 16, respectively, so the noise margin in the ULV retention state increases. This allows VVDDL to be set to, for example, 0.15V, which may reduce power consumption.

[0049] In Comparative Example 2, the number of transistors in the memory cell 10 is 10, and the driver 26 is not required. This allows the circuit area to be reduced as shown in FIG. 4. However, since feedback is applied only by the pull-down side FBTr (FETm3), the noise margin in the ULV retention state is smaller than that of Comparative Example 1. As a result, VVDDL becomes, for example, 0.2 V. Therefore, power consumption is greater than that of Comparative Example 1. EXAMPLES

[0050] Example 1 is an example of PDFB, different conductivity type channel FBTr, header PS, type 1. In Example 1, FETm1a which is a load in Comparative Example 2 and FETm5 which is a pass transistor are combined into one FETm4. This allows the number of transistors in the memory cell 10 to be reduced to eight, which is further reduced from Comparative Example 2. Furthermore, the noise margin in ULV retention can be increased.

[0051] [Memory cell description] Fig. 5 and Fig. 6 are circuit diagrams of a memory cell in Example 1. Fig. 5 is a circuit diagram showing a loop, and Fig. 6 is a circuit diagram showing a cross-coupled.

[0052] As shown in Figures 5 and 6, the memory cell 10 mainly includes inverter circuits 14 and 16. The inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12. The inverter circuits 14 and 16 each include FETs m1 to m4. The FETs m1 and m2 are N-channel MOSFETs, and the FETs m3 and m4 are P-channel MOSFETs. The FETs m1 to m4 are, for example, normally-off transistors.

[0053] In FETm1, the source is connected to the ground line 15b to which the ground voltage VGND is applied, the drain is connected to the intermediate node N3, and the gate is connected to the input node N1. In FETm2, the source is connected to the intermediate node N3, the drain is connected to the output node N2, and the gate is connected to the input node N1. FETs m1 and m2 are drivers.

[0054] In the FETm3, one of the source and the drain is connected to the intermediate node N3, the other of the source and the drain is connected to the bias node N4, and the gate is connected to the input node N1. The FETm3 is a feedback transistor FBTr.

[0055] In FETm4, one of the source and drain is connected to the output node N2, the other of the source and drain is connected to the control line CTRL1 or CTRL2, and the gate is connected to the word line WL. FETm4 functions as a pass transistor in the read / write state and functions as a load in the VDD retention state and ULV retention state.

[0056] The input node N1 of the inverter circuit 14 and the output node N2 of the inverter circuit 16 are connected to a storage node Q1, and the input node N1 of the inverter circuit 16 and the output node N2 of the inverter circuit 14 are connected to a storage node Q2. The storage nodes Q1 and Q2 are complementary nodes. The storage node Q1 is connected to a control line CTRL1 via a FETm4 of the inverter circuit 16, and the storage node Q2 is connected to a control line CTRL2 via a FETm4 of the inverter circuit 14.

[0057] The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power line 15a (virtual power line). The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power line 15a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage VVDD and supplies it to the power line 15a.

[0058] [Memory array description] FIG. 7A is a block diagram of a memory array in the first embodiment. As shown in FIG. 7A, the memory array 22 is divided into a plurality of blocks 24 each having a memory cell 10. The number of blocks 24 can be designed as appropriate. A plurality of memory cells 10 are arranged in a matrix in n columns in the memory array 22. In the memory array 22, word lines WL extend in the row direction, and control lines CTRL1 and CTRL2 extend in the column direction. The word lines WL and the control lines CTRL1 and CTRL2 are connected to each memory cell 10. In FIG. 7A, the control lines CTRL1 and CTRL2 in columns 1 to n are indicated as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.

[0059] A control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22. The control circuit 28 controls the power switch 30 and the peripheral circuit 38.

[0060] The power switch 30 outputs a virtual power supply voltage VVDD obtained from the voltage VDD of the power supply 15c, for example, by a voltage divider circuit, in accordance with a control signal from the control circuit 28. The voltage VVDD-VGND is the voltage applied to the bistable circuit 12. The peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge circuit 33, and a read / write circuit 34. In FIG. 7A, the selection circuits 32 and 32a in FIG. 5 and FIG. 6 will be described as the selection circuit 32b. The same applies to the following similar figures.

[0061] When the memory cell 10 holds data, the selection circuit 32b switches the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n to connect the power supply line 15a. When reading or writing data from the memory cell 10, the selection circuit 32b switches the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n to connect the bit lines BL1 and BLB1 to BLn and BLBn, respectively. The WL decoder 31 selects the word line WL based on the row address. A column address is input to the read / write circuit 34. The read / write circuit 34 selects the bit lines BL and BLB corresponding to the column to be selected from the bit lines BL1 and BLB1 to BLn and BLBn based on the column address. The precharge circuit 33 precharges the bit lines BL and BLB. The read / write circuit 34 writes data to the bistable circuit 12 of the selected memory cell 10 or reads data from the bistable circuit 12, and outputs the data to the bus 25.

[0062] Another example of the peripheral circuit will be described with reference to Figs. 7B and 7C. Fig. 7B is a diagram showing the power switch and the selection circuit in the first embodiment. As shown in Fig. 7B, the power switch 30 includes FETs PS1 and PS2. The FETs PS1 and PS2 are P-channel FETs. The FET PS1 is connected between the power supply 15cH and the power supply line 15a, and the FET PS2 is connected between the power supply 15cL and the power supply line 15a. The power supply 15cH and the power supply 15cL are supplied with power supply voltages VDDH and VDDL, respectively.

[0063] Signals VPS1 and VPS2 are input to the gates of FETPS1 and PS2, respectively. When the signals VPS1 and VPS2 are at low and high levels, respectively, FETPS1 and PS2 are turned on and off, respectively, and the virtual power supply voltage VVDD becomes VDDH. The virtual power supply voltage VVDD becomes VDDH in the read / write state and the VDD retention state, and the voltage VVDD-VGND is, for example, 1.2V. When the signals VPS1 and VPS2 are at high and low levels, respectively, FETPS1 and PS2 are turned off and on, respectively, and the virtual power supply voltage VVDD becomes VDDL. The virtual power supply voltage VVDD becomes VDDL in the ULV retention state, and the voltage VVDD-VGND is, for example, 0.2V. When the signals VPS1 and VPS2 are both at high levels, both FETPS1 and PS2 are turned off, and the virtual power supply voltage VVDD is shut off. The virtual power supply voltage VVDD is shut off in the shutdown state.

[0064] A precharge / selection circuit 33a is provided between the power supply line 15a and the control lines CTRL1 and CTRL2. The precharge / selection circuit 33a includes FETs M10 to M12. The FET M10 is connected between the power supply line 15a and the control line CTRL1. The FET M11 is connected between the power supply line 15a and the control line CTRL2. The FET M12 is connected between the control lines CTRL1 and CTRL2. The FETs M10 to M12 are P-channel FETs. A selection signal Sel is input to the gates of the FETs M10 to M12. A selection circuit 32b is provided between the control lines CTRL1 and CTRL2 and the bit lines BL and BLB connected to the read / write circuit 34. The selection circuit 32b includes transfer gates M13 and M14. The transfer gate M13 is connected between the bit line BL and the control line CTRL1. The transfer gate M14 is connected between the bit line BLB and the control line CTRL2. Selection signals Sel' and complementary signals SelB' of Sel' are input to transfer gates M13 and M14.

[0065] Fig. 7C is a block diagram showing another example of the memory array in the embodiment 1. As shown in Fig. 7C, a precharge / selection circuit 33a is provided between the power switch 30 and the memory array 22. The precharge / selection circuit 33a includes the FETs M10 to M12 shown in Fig. 7B, and the selection circuit 32b includes the transfer gates M13 and M14 shown in Fig. 7B.

[0066] When the selection signal Sel is at a low level, the FETs M10 to M12 are turned on, and the virtual power supply voltage VVDD is supplied to the control lines CTRL1 and CTRL2. When the selection signal Sel is at a high level, the FETs M10 to M12 are turned off. When the FETs M10 to M12 are off and the selection signal Sel' is at a high level, the transfer gates M13 and M14 are turned on, and the control lines CTRL1 and CTRL2 function as the bit lines BL and BLB. When the FETs M10 to M12 are on and the selection signal Sel' is at a low level, the transfer gates M13 and M14 are turned off, and the control lines CTRL1 and CTRL2 are disconnected from the bit lines BL and BLB. As described above, the precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and the selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.

[0067] 7A and 7C controls the power switch 30 to make the voltage VL (0.2V) of the voltage VVDD-VGND in Table 3 of Example 1 lower than the voltage VH (1.2V) in the read / write state (second state) in the ULV retention state in which the bistable circuit 12 retains data. This makes it possible to reduce power consumption in the ULV retention state.

[0068] Table 3 shows the state in the first embodiment. [Table 3]

[0069] The bias node N4 is a constant voltage VFN (e.g., 0.2V). In the read / write state, the selection circuit 32b connects the bit line BL (bit lines BL and BLB in FIG. 5 and FIG. 6) to the control line CTRL (control lines CTRL1 and CTRL2 in FIG. 5 and FIG. 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2V). The voltage VVDD-VGND is VH (e.g., 1.2V). In the read state, the bit lines BL and BLB are approximately VVDDH. In the write state, one of the bit lines BL and BLB is approximately VVDDH, and the other is approximately VGND. The high level of the storage nodes Q1 and Q2 is approximately VVDDH, and the low level is approximately VGND. The inverter circuits 14 and 16 are in the BI mode.

[0070] The voltage VWL of the word line WL of the memory cell 10 to be read or written is set to voltage V1 (e.g., 0.25 V). Voltage V1 is set to a voltage at which FET m4 is turned on when memory nodes Q1 and Q2 are at both high and low levels. This makes it possible to read and write data from and to the memory cell 10.

[0071] In the VDD retention state, the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2 V). The voltage VVDD-VGND becomes VH (e.g., 1.2 V). The inverter circuits 14 and 16 are in the BI mode.

[0072] The voltage VWL of the word line WL is set to a voltage V2 (for example, 1.1 V). Since the voltage V2 is slightly lower than VVDDH, FETm4 is slightly turned on whether the storage nodes Q1 and Q2 are at a high level or a low level. This causes FETm4 to function as a load for the inverter circuits 14 and 16. In the VDD retention state, the data in the bistable circuit 12 is held.

[0073] In the ULV retention state, the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2 V). The voltage VVDD-VGND becomes VL (e.g., 0.2 V). The inverter circuits 14 and 16 enter the ST mode.

[0074] The voltage VWL of the word line WL is set to a voltage V3 (for example, 0.2 V). When the voltage V3 is applied to the gate, the FETm4 turns off whether the storage nodes Q1 and Q2 are at a high level or a low level, but the leakage current of the FETm4 causes the FETm4 to function as a load for the inverter circuits 14 and 16. In the ULV retention state, the data of the bistable circuit 12 is held at an ultra-low voltage. This makes it possible to suppress power consumption due to the leakage current.

[0075] [Simulation 1] Simulation 1 is a simulation of SNM (Static Noise Margin) and standby power during reading in the VDD retention state and in the read / write state.

[0076] The simulation was performed for Example 1, Comparative Example 2, and Comparative Example 3, which is an SRAM cell using six transistors (6T). The simulation conditions are as follows.

[0077] The channel width W / length L of each FET in the first embodiment is as follows: FETm1, m2 (driver): 100nm / 60nm FETm3 (feedback transistor): WFB / 60nm FETm4 (pass transistor / load): WLP / 60nm The voltages in the first embodiment are as follows. VVDDH=1.2V VGND=0V VFN=0.2V VWL=1.1V or 0.25V

[0078] The channel width W / length L of each FET in Comparative Example 2 is as follows. FETm1, m2 (driver): 165nm / 60nm FETm1a (load): 100nm / 60nm FETm3 (feedback transistor): 120nm / 60nm FETm5 (pass transistor): 100nm / 60nm The voltages in Comparative Example 2 are as follows. VVDDH=1.2V VGND=0V VFN=0.2V The channel width W / length L of each FET in Comparative Example 3 is as follows. Driver: 150nm / 60nm Load: 100nm / 60nm Pass transistor: 100nm / 60nm The voltages in Comparative Example 3 are as follows. VVDD=1.2V VGND=0V

[0079] In the first embodiment, a virtual power supply voltage VVDD is supplied to the memory cell 10 from the control lines CTRL1 and CTRL2. Therefore, the noise margin and standby power are determined by the size of FETm4 and the voltage VWL of the word line WL in the VDD retention state. In addition, since VFN is a constant bias, even in the BI mode, a weaker feedback is applied by FETm3 than in the ST mode. Therefore, the noise margin can be designed by the size of FETm3.

[0080] Therefore, the size of FETm4 (channel width WLP) and the size of FETm3 (channel width WFB) were changed to simulate the SNM (Static Noise Margin) and standby power in the VDD retention state. Standby power is equivalent to the sum of the leakage currents of each FET when data is being held. In addition, the voltage VWL of the word line WL was changed to simulate the SNM and standby power in the VDD retention state. SNM is the noise margin; if the SNM is small, the data in the bistable circuit 12 is more likely to be inverted due to noise, etc., and if the SNM is large, the data in the bistable circuit 12 is less likely to be inverted due to noise, etc. The target SNM was set to 80 mV or more as an indicator of SNM.

[0081] 8(a) and 8(b) are diagrams showing SNM and standby power for WLP and WFB in the VDD retention state in the first embodiment. TT of SNM is SNM when the threshold voltages of PFET and NFET are typical. FF of SNM is SNM when the threshold voltages of PFET and NFET are both shifted 3σ toward the Fast (F) side (lower) from the typical value due to process fluctuation. SS of SNM is SNM when the threshold voltages of PFET and NFET are both shifted 3σ toward the Slow (S) side (higher) from the typical value due to process fluctuation. FS and SF of SNM are SNM when one of the threshold voltages of PFET and NFET is shifted 3σ toward the F side from the typical value and the other is shifted 3σ toward the S side from the typical value. If the SNMs of TT, FF, SS, FS, and SF are ensured, the SNM can be ensured even if the threshold voltages of PFET and NFET vary within the range of ±3σ. In Comparative Example 3, the channel width W of the pass transistor is constant.

[0082] As shown in FIG. 8(a), when WFB=230 nm and VWL=1.1 V, WLP is changed from 100 nm to 300 nm. As WLP increases, SNM increases. When WLP is 100 nm or more, all SNMs are 80 mV or more. As SNM increases, standby power increases. The standby power of Example 1 becomes smaller than that of Comparative Example 3 (6T) when WLP is 110 nm or less. Therefore, WLP is set to 110 nm.

[0083] As shown in FIG. 8(b), when WLP=110 nm and VWL=1.1 V, WFB is changed from 100 nm to 300 nm. As WFB increases, SNM increases. When WFB is 230 nm or more, all SNMs are 80 mV or more. The standby power of Example 1 is independent of WFB and is smaller than that of Comparative Example 3 at all WFBs. For the above reasons, WFB is set to 230 nm.

[0084] 9(a) and 9(b) are diagrams showing SNM and standby power versus VWL in the VDD retention state and read / write state in Example 1 and Comparative Example 3. FIG. 9(b) is an enlarged view of the vicinity of VWL of 1.1V in FIG. 9(a). The goal was to set SNM at 80mV or more. SNM=80mV is indicated by a dashed line.

[0085] As shown in Fig. 9(a), when WLP = 110 nm and WFB = 230 nm, VWL is changed from 0 V to 1.2 V. SNM peaks at around VWL = 0.7 V, and SNM decreases when VWL is smaller than 0.7 V, and decreases when VWL is larger than 0.7 V. As VWL decreases, the standby power increases.

[0086] 9(b), when VWL is 1.1 V or higher, the standby power of Example 1 is smaller than that of Comparative Example 3. When VWL is 1.15 V or lower, all SNMs are 80 mV or higher. Therefore, VWL in the VDD retention state was set to 1.1 V.

[0087] In the read / write state, VWL is lowered to turn on FETm4. However, it is preferable for SNM to be large. As shown in FIG. 9(a), when VWL is 0.25V or higher, all SNMs are 80mV or higher. Therefore, VWL is set to 0.25V.

[0088] SNM in the read / write state and the VDD retention state was simulated for Example 1 and Comparative Examples 2 and 3. In Example 1, WLP=110 nm, WFP=230 nm, VWL=1.1 V in the VDD retention state, and VWL=0.25 V in the read / write state.

[0089] Figures 10(a) to 10(c) are diagrams showing SNM in the VDD retention state and the read / write state in Example 1 and Comparative Examples 2 and 3. Figure 10(a) shows the SNM in the VDD retention state, Figure 10(b) shows the SNM during reading in the read / write state, and Figure 10(c) shows the SNM during writing in the read / write state.

[0090] As shown in FIG. 10(a), in the VDD retention state, the SNM of Example 1 is smaller than those of Comparative Examples 2 and 3, but all SNMs are greater than 80 mV. As shown in FIG. 10(b), in the read state, the SNM of Example 1 is almost the same as those of Comparative Examples 2 and 3, and all SNMs are greater than 80 mV. As shown in FIG. 10(c), in the write state, the SNM of Example 1 is greater than those of Comparative Examples 2 and 3, and all SNMs are greater than 80 mV. As described above, in Example 1, all SNMs are greater than 80 mV. Also, the SNM of TT is greater than 100 mV. Thus, in Example 1, sufficient noise margins can be secured in the read / write state and the VDD retention state. The optimization of VWL in FIG. 9(a) and FIG. 9(b) is performed in the read state of the VDD retention state and the read / write state, but the SNM can also be increased in the write state of the read / write state as shown in FIG. 10(a) to FIG. 10(c).

[0091] [Simulation 2] Simulation 2 is a simulation of the transfer characteristics of the inverter circuits 14 and 16, the butterfly curve of the bistable circuit 12, the SNM, and the standby power in the ULV retention state.

[0092] Unless otherwise specified, the channel width W / length L of each FET and each voltage are the same as in Simulation 1. In Example 1, WLP=110 nm, WFP=230 nm. In Comparative Example 3, VVDD=0.2 V.

[0093] For the first embodiment, the voltage VWL of the word line WL was changed and the transfer characteristics of the inverter circuits 14 and 16 in the ULV retention state were simulated.

[0094] FIG. 11 is a diagram showing the transfer characteristics of the inverter circuit in the ULV retention state of the first embodiment, and shows the output voltage Vout (output node N2) with respect to the input voltage Vin (voltage at input node N1) of the inverter circuits 14 and 16.

[0095] As shown in Figure 11, in a forward sweep where Vin is increased, increasing VWL causes the threshold voltage at which the output voltage Vout shifts from a high level to a low level to shift toward a higher Vin. In a backward sweep where Vin is decreased, increasing VWL causes the threshold voltage at which the output voltage Vout shifts from a low level to a high level to shift toward a lower Vin. In a backward sweep, increasing VWL causes the threshold voltage to shift even further toward a lower Vin.

[0096] Figures 12(a) and 12(b) are circuit diagrams of the bistable circuit in Example 1. The circuit of the bistable circuit 12 is a circuit diagram in the ULV retention state in Figures 5 and 6, and is displayed so that the principle can be easily understood. The input voltage Vin and the output voltage Vout of the inverter circuit 14 in Figures 12(a) and 12(b) will be described.

[0097] The forward sweep will be described with reference to FIG. 12(a). In the initial state, the input voltage Vin is at a low level (for example, 0V), and the output voltage Vout is at a high level (for example, 0.2V). In this state, in the inverter circuit 14, FETs m1 and m2 are off, and FET m3 is on. FET m4 is off when VWL=0.2V, but a leakage current flows. When VWL is lower than 0.2V, FET m4 is on. Therefore, the output node N2 is charged from the VVDDL of the control line CTRL1 by the leakage current or on-current of FET m4 as indicated by the dotted arrow 92, and the intermediate node N3 is charged by the VFN of the bias node N4 as indicated by the dotted arrow 93.

[0098] When the input voltage Vin becomes high, in order to make the output voltage Vout a low level, discharge is performed from the output node N2 to the intermediate node N3 as indicated by a solid line arrow 90. However, unless discharge is performed from the intermediate node N3 to the ground line 15b as indicated by a solid line arrow 91, discharge from the output node N2 to the intermediate node N3 is not possible. For this reason, the output node N2 discharges after the intermediate node N3 discharges, and the threshold voltage at which the output voltage Vout becomes a low level shifts toward the higher Vin side.

[0099] Referring to FIG. 12(b), the backward sweep will be described. In the initial state, the input voltage Vin is at a high level (for example, 0.2V), and the output voltage Vout is at a low level (for example, 0V). In this state, in the inverter circuit 14, FETs m1 and m2 are on, and FETs m3 and m4 are off. Therefore, the intermediate node N3 is discharged to the ground line 15b as indicated by the dotted arrow 95. Although FET m4 is off when VWL=0.2V, a leakage current flows. When VWL is lower than 0.2V, FET m4 is weakly turned on. Since the discharge via FET m2 indicated by the dotted arrow 94 is faster than the charge via FET m4 indicated by the dotted arrow 96, the output node N2 is discharged to the intermediate node N3.

[0100] When the input voltage Vin becomes low, FETm1 turns off and FETm3 turns on, so that the intermediate node N3 is charged by VFN of the bias node N4, as indicated by the solid arrow 97. When FETm2 turns off and FETm4 turns off or weakly on, the output node N2 is charged by VVDDL of the control line CTRL1, as indicated by the dotted arrow 96. However, since the output node N2 is charged with a current close to the off current of FETm4, the charging depends on VWL. As a result, the threshold voltage at which the output voltage Vout becomes high shifts to the lower side of Vin when VWL is increased. In particular, VWL is applied to the gate of FETm4. For this reason, the magnitude of the current indicated by the dotted arrow 96 depends on VWL. When VWL is high, the current of FETm4 is small, so the threshold voltage shifts to the lower side of Vin.

[0101] Simulations were performed on butterfly curves in the bistable circuits 12 of Example 1 and Comparative Examples 2 and 3. In Example 1, VWL=0.2V.

[0102] 13(a) and 13(b) are diagrams showing butterfly curves of the bistable circuits in the ULV retention state of Example 1 and Comparative Examples 2 and 3. In Fig. 13(a), the operating point is when Q1 is at a low level and Q2 is at a high level, and in Fig. 13(b), the operating point is when Q1 is at a high level and Q2 is at a low level.

[0103] 13(a) and 13(b), in the 6T-SRAM of Comparative Example 3, the lobe of the butterfly curve is narrow and the noise margin is small. In Comparative Example 2, the lobe on the operating point side is wide and the noise margin is large. In Example 1, the lobe on the operating point side is even wider than in Comparative Example 2 and the noise margin is even larger than in Comparative Example 2.

[0104] SNM in the ULV retention state of Example 1 and Comparative Examples 2 and 3 was simulated.

[0105] FIG. 14(a) is a diagram showing the SNM in the ULV retention state in Example 1, Comparative Examples 2 and 3. As shown in FIG. 14(a), in Comparative Example 3, all SNMs are smaller than 80 mV, and the noise margin is small. In Comparative Example 2, all SNMs are 80 mV or more, and the noise margin is large. In Example 1, all SNMs are 130 mV or more, and the noise margin is larger than that of Comparative Example 2. If a practical SNM is 80 mV, in Example 1, VVDD can be made lower than 0.2 V. If VVDD is 0.2 V, SNM is 130 mV or more, and the bistable circuit 12 becomes more stable than when VVDD is lowered to less than 0.2 V.

[0106] In the ULV retention state of Example 1, VVDD was changed and SNM and standby power were simulated.

[0107] FIG. 14(b) is a diagram showing SNM and standby power with respect to VVDD in the ULV retention state in the first embodiment. As shown in FIG. 14(b), in the first embodiment, VVDD is changed from 0.1 to 0.2V. As VVDD increases, SNM increases and standby power increases. When VVDD is 0.15V or more, all SNMs are 80mV or more. Therefore, VVDD (i.e., VVDDL) in the ULV retention state can be set to 0.15V.

[0108] For Example 1 and Comparative Example 3, the standby power for each VVDD was simulated.

[0109] 15 is a diagram showing the standby power in Example 1 and Comparative Example 3. The numbers indicate the reduction rate of the standby power with respect to the standby power when VVDD=1.2 V in Comparative Example 3.

[0110] As shown in Fig. 15, in the normal state where read / write is performed, VVDD = 1.2V in Comparative Example 3. At this time, the standby power is about 4.4nW. In Comparative Example 3, in the sleep state where no read or write is performed and data is retained, VVDD = 0.8V. At this time, the reduction rate of standby power is 44%.

[0111] In the first embodiment, in the VDD retention state, VVDD=1.2V. At this time, the reduction rate of standby power is 7%. In the ULV retention state, if VVDD=0.2V, the reduction rate of standby power is 95%. Furthermore, if VVDD=0.15V, the reduction rate of standby power is 97%.

[0112] In Comparative Example 2, the number of transistors in the memory cell 10 is 10, but in Example 1, the number of transistors in the memory cell 10 can be reduced to 8. This makes it possible to reduce the circuit area as shown in a comparison between FIG. 4 and FIG. 6. Furthermore, as shown in FIG. 14(a), the noise margin in the ULV retention state can be made larger than that of Comparative Example 2. If the noise margin is the same as that of Comparative Example 2, VVDDL can be made lower than that of Comparative Example 2. This makes it possible to further reduce standby power.

[0113] [Modification 1 of Example 1] Modification 1 of the first embodiment is an example of PUFB, a different conductivity type channel FBTr, a footer PS, and type 1. Figs. 16 and 17 are circuit diagrams of a memory cell 10 in modification 1 of the first embodiment. Fig. 16 is a circuit diagram showing a loop, and Fig. 17 is a circuit diagram showing a cross-couple. Note that in the PUFB·footer PS, the state is the VSS retention state, not the VDD retention state, but is referred to as the VDD retention state here to match with the first embodiment.

[0114] 16 and 17, the inverter circuits 14 and 16 each include FETs m1a to m4a. The FETs m1a and m2a are P-channel MOSFETs, and the FETs m3a and m4a are N-channel MOSFETs.

[0115] In the FETm1a, the source is connected to the power supply line 15a to which the power supply voltage VDD is applied. The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the ground line 15b (virtual ground line). The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the ground line 15b. The power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground line 15b. A constant bias VFP is applied to the bias node N4. The other circuit configurations are the same as those of the circuits in FIG. 5 and FIG. 6 of the first embodiment in which the FETs m1 to m4 are replaced with FETs m1a to m4a, respectively.

[0116] Table 4 shows the state in the first modification of the first embodiment. [Table 4]

[0117] The bias node N4 is a constant voltage VFP (e.g., 1.0V). In the read / write state, the selection circuits 32 and 32a connect the bit lines BL and BLB to the control lines CTRL1 and CTRL2, respectively. The power switch 30 sets the virtual ground voltage VVGND to VVGNDL (e.g., 0V). The virtual power supply voltage VDD-VVGND applied to the bistable circuit 12 is VH (e.g., 1.2V). In the read state, the bit lines BL and BLB can be set to approximately VVGNDL. In the write state, one of the bit lines BL and BLB can be set to approximately VVGNDL, and the other can be set to approximately VDD. The high level of the storage nodes Q1 and Q2 is approximately VDD, and the low level is approximately VVGNDL. The inverter circuits 14 and 16 are in the BI mode. The voltage VWL of the word line WL of the memory cell 10 to be read or written is set to voltage V1 (e.g., 0.9V).

[0118] In the VDD retention state, the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 sets the virtual ground voltage VVGND to VVGNDL (e.g., 0V). The voltage VDD-VVGND becomes VH (e.g., 1.2V). The inverter circuits 14 and 16 are in the BI mode. The voltage VWL of the word line WL is set to voltage V2 (e.g., 0.1V).

[0119] In the ULV retention state, the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 sets the virtual ground voltage VVGND to VVGNDH (e.g., 1.0 V). The voltage VDD-VVGND becomes VL (e.g., 0.2 V). The inverter circuits 14 and 16 are in the ST mode. The voltage VWL of the word line WL is set to voltage V3 (e.g., 1.0 V). In the ULV retention state, the data of the bistable circuit 12 is held at an ultra-low voltage. This makes it possible to suppress power consumption due to leakage current.

[0120] [Modification 2 of Example 1] The second modification of the first embodiment is an example of PDFB, a same-conductivity-type channel FBTr, a header PS, and Type 1. Figures 18 and 19 are circuit diagrams of a memory cell 10 in the second modification of the first embodiment. Figure 18 is a circuit diagram showing a loop, and Figure 19 is a circuit diagram showing a cross-coupled.

[0121] As shown in Figures 18 and 19, in the inverter circuits 14 and 16, the FETm3 is an N-channel FET. The gate of the FETm3 in the inverter circuit 14 is connected to the output node N2 of the inverter circuit 14 or the input node N1 of the inverter circuit 16, and the gate of the FETm3 in the inverter circuit 16 is connected to the output node N2 of the inverter circuit 16 or the input node N1 of the inverter circuit 14. The other circuit configurations are the same as those in Figures 5 and 6 of the first embodiment. As in Figure 7B, a part of the selection circuits 32 and 32a may be a precharge / selection circuit 33a provided between the power switch 30 and the control lines CTRL1 and CTRL2, and another part of the selection circuits 32 and 32a may be a selection circuit 32b provided between the read / write circuit 34 and the control lines CTRL1 and CTRL2.

[0122] A butterfly curve in the ULV retention state of the modified example 2 of the embodiment 1 was simulated. The simulation conditions were almost the same as those of the simulation 2 of the embodiment 1. VVDD was set to 0.2 V. In the modified example 2 of the embodiment 1, the noise margin is largest when VWL=0.1 V, so VWL=0.1 V was set.

[0123] Fig. 20 is a diagram showing butterfly curves of the bistable circuits in the ULV retention state of the first embodiment and its modified example 2. In Fig. 20, the operating point is when Q1 is at a low level and Q2 is at a high level. The butterfly curves of the first embodiment are the same as those in Fig. 13(a).

[0124] As shown in FIG. 20, in the second modification of the first embodiment, the opening on the operating point side is smaller than the opening on the operating point side of the first embodiment. In this way, when the feedback transistor (FETm3) has the same conductivity type channel as FETm1 and m3, the noise margin is smaller than that of a different conductivity type channel. The opening on the operating point side is wider than that of the third comparative example in FIG. 13(a). Therefore, power consumption can be suppressed more than the third comparative example by ULV retention. Furthermore, the circuit area can be reduced more than the second comparative example.

[0125] According to the first embodiment and its modified examples, in the inverter circuit 14 (first inverter circuit) and the inverter circuit 16 (second inverter circuit), the source of the FETm1 (first FET) (or FETm1a) is connected to the ground line 15b (or the power supply line 15a), the drain is connected to the intermediate node N3, and the gate is connected to the input node N1. In a PDFB such as the first embodiment and its modified example 2, the ground line 15b corresponds to the power supply line, and in a PUFB such as the modified example 1 of the first embodiment, the power supply line 15a corresponds to the power supply line.

[0126] In FETm2 (second FET) (or FETm2a), the source is connected to the intermediate node N3, and the drain is connected to the output node N2. In FETm3 (third FET) (or FETm3a), one of the source and the drain is connected to the intermediate node N3, and the other of the source and the drain is connected to the bias node N4. In FETm4 (fourth FET) (or FETm4a), one of the source and the drain is connected to the output node N2, and the other of the source and the drain is connected to the control line CTRL1 or CTRL2. The conductivity type (second conductivity type) of FETm4 (or m4a) is opposite to the conductivity type (first conductivity type) of FETm1 and m2 (or FETm1a and m2a).

[0127] At a storage node Q1 (first storage node), the input node N1 of the inverter circuit 14 and the output node N2 of the inverter circuit 16 are connected, and at a storage node Q2 (second storage node), the output node N2 of the inverter circuit 14 and the input node N1 of the inverter circuit 16 are connected. In this way, the bistable circuit 12 is formed.

[0128] The gates of FETm4 (or FETm4a) of the inverter circuits 14 and 16 are connected to the word line WL. The gates of FETm3 (or FETm3a) of the inverter circuit 14 are connected to any one of the input node N1 and output node N2 of the inverter circuit 14, and the input node N1 and output node N2 of the inverter circuit 16. The gates of FETm3 (or FETm3a) of the inverter circuit 16 are connected to any one of the input node N1 and output node N2 of the inverter circuit 16, and the input node N1 and output node N2 of the inverter circuit 14.

[0129] With the circuit configuration described above, the load and pass transistors of the inverter circuits 14 and 16 can be shared by FETm4 (or FETm4a). This allows the circuit area to be reduced compared to Comparative Example 2. In addition, the noise margin in the ULV retention state is wider than that of Comparative Example 3 due to FETm3 (or FETm3a) which is an FBTr. This allows the power consumption to be reduced.

[0130] In the first embodiment and its first modification, FETm3 (or FETm3a) is a second conductivity type channel opposite to the first conductivity type channel of FETm1 and m2 (or FETm1a and m2a). That is, FBTr is a different conductivity type channel. At this time, the gate of FETm3 (or FETm3a) of the inverter circuit 14 is connected to the input node N1 of the inverter circuit 14 or the output node N2 of the inverter circuit 16, and the gate of FETm3 (or FETm3a) of the inverter circuit 16 is connected to the input node N1 of the inverter circuit 16 or the output node N2 of the inverter circuit 14.

[0131] As a result, as in Simulation 2 of Example 1, the noise margin in the ULV retention state can be made larger than that of Comparative Example 2. In addition, by lowering VVDDL, power consumption can be suppressed.

[0132] As in the second modification of the first embodiment, the FET m3 has the same first conductivity type channel as the FETs m1 and m2. That is, the FBTr has the same conductivity type channel. At this time, the gate of the FET m3 of the inverter circuit 14 is connected to the output node N2 of the inverter circuit 14 or the input node N1 of the inverter circuit 16, and the gate of the FET m3 of the inverter circuit 16 is connected to the output node N2 of the inverter circuit 16 or the input node N1 of the inverter circuit 14.

[0133] This makes it possible to increase the noise margin in the ULV retention state compared to Comparative Example 3. In addition, by lowering VVDDL, power consumption can be suppressed.

[0134] 7A and 7C controls the power switch 30 (power supply circuit) to make the voltage VL (first voltage) of the voltage VVDD-VGND in Table 3 of the first embodiment and the voltage VVDD-VVGND in Table 4 of the first modified example of the first embodiment lower than the voltage VH (second voltage) in the read / write state (second state) in the ULV retention state (first state) in which the bistable circuit 12 retains data. This makes it possible to suppress power consumption in the ULV retention state.

[0135] In addition, the voltage VL corresponds to the voltage VVDD-VGND between the ground line 15b and the control lines CTRL1 and CTRL2 in the ULV retention state in the first embodiment, and corresponds to the voltage VDD-VVGND between the power supply line 15a of the voltage VDD and the control lines CTRL1 and CTRL2 in the ULV retention state in the first modification of the first embodiment. The voltage VH corresponds to the voltage between the storage nodes Q1 and Q2 in the read / write state.

[0136] The voltage VL may be smaller than the voltage VH, but from the viewpoint of ensuring SNM in the ULV retention state and suppressing power consumption, the voltage VL is preferably 1 / 2 or less of the voltage VH, more preferably 1 / 4 or less, even more preferably 1 / 5 or less, and even more preferably 1 / 6 or less. In particular, from the viewpoint of suppressing power consumption, it is preferably about 1 / 10. The voltage VL is greater than 0V.

[0137] The control circuit 28 controls the selection circuit 32b to connect the bit lines BL and BLB for reading or writing data from the bistable circuit 12 to the control lines CTRL1 and CTRL2 in the read / write state. That is, the control lines CTRL1 and CTRL2 are set to the bit lines BL and BLB. This allows data to be read or written from the bistable circuit 12 via the control lines CTRL1 and CTRL2.

[0138] In the case of PDFB (i.e., when the first conductivity type is N type) as in the first embodiment and its second modification, FETm4 is P type. For this reason, in order to turn on FETm4 in the read / write state, the voltage VWL of the word line WL is generally set to the voltage VGND (e.g., 0 V) ​​of the ground line 15b. However, when VWL is set to 0 V as in FIG. 9(a), the SNM becomes small.

[0139] Therefore, in the read / write state, the control circuit 28 makes the voltage VWL of the word line WL of the power switch 30 higher than the voltage of the ground line 15b. For example, in the first embodiment and its second modification, VWL=0.25V for VGND=0V. This makes it possible to prevent the SNM from becoming smaller than the target 80mV, as shown in FIG. 9(a).

[0140] In the case of PUFB (i.e., when the first conductivity type is P type) as in the first modification of the first embodiment, the control circuit 28 makes the voltage VWL of the word line WL lower than the voltage VDD of the power supply line 15a. For example, in the first modification of the first embodiment, VWL=0.9V for VDD=1.2V. This makes it possible to suppress the SNM from becoming smaller, similar to PDFB.

[0141] In the VDD retention and read / write states, if VWL is too close to the voltage of the ground line 15b (or the power line 15a), the SNM in the read will not increase. Therefore, the difference between the voltage of the ground line 15b (or the power line 15a) and VWL is preferably 1 / 10 or more of VH, more preferably 1 / 5 or more, and even more preferably about 1 / 2 as shown in FIG. 9(a).

[0142] In the ULV retention state, when VWL becomes high, FETm4 does not turn on, and the operating speed decreases. Therefore, the difference between the voltage of the ground line 15b (or the power line 15a) and VWL is preferably 1 / 2 or less of the voltage VH, more preferably 1 / 4 or less, and even more preferably 1 / 5 or less. In the first embodiment, the difference between the voltage of the ground line 15b and VWL is set to about 1 / 6, with priority given to speed performance.

[0143] In the ULV retention state, in FIG. 12(a) and FIG. 12(b), it is preferable that FETm4 is turned off when the output node N2 is at a low level (for example, GND=0V) and that FETm4 is turned on when the output node N2 is at a high level (for example, VVDDL=0.2V). Therefore, it is preferable that VWL is equal to or higher than VGND and equal to or lower than VVDDL. That is, it is preferable that the control circuit 28 sets the voltage between the word line WL and the ground line 15b (or the power supply line 15a) to the voltage VL or lower than the voltage VL. For example, in the first embodiment, VL=0.2V and VWL-VGND=0.2V. In the first modification of the first embodiment, VL=0.2V and VDD-VWL=0.2V. In the second modification of the first embodiment, VWL-VGND=0.1V and VL=0.2V.

[0144] As shown in Fig. 11, in the first embodiment, if VWL is too close to VGND, the noise margin becomes small. Therefore, the voltage between the word line WL and the ground line 15b (or the power supply line 15a) is preferably 1 / 4 or more of the voltage VL, and more preferably 1 / 2 or more. In Fig. 11, the voltage between the word line WL and the ground line 15b (or the power supply line 15a) may be the voltage VL so that the noise margin is maximized when VWL=0.2V.

[0145] In the case of PDFB (i.e., when the first conductivity type is N type) as in the first embodiment and its modified example 2, FETm4 is P type. For this reason, in the VDD retention state in which the voltage between the ground line 15b and the control lines CTRL1 and CTRL2 is VVDD-VGND=VH (e.g., 1.2 V), it is common to set the voltage VWL of the word line WL to VVDD (e.g., 1.2 V) to turn off FETm4. However, when VWL is set to 1.2 V as in FIG. 9(b), SNM becomes small.

[0146] Therefore, in the VDD retention state (third state), the control circuit 28 makes the voltage between the word line WL and the ground line 15b smaller than VH. For example, in the first embodiment and its second modification, VWL-VGND=1.1V for VH=1.2V. This makes it possible to prevent the SNM from becoming smaller, as shown in FIG. 9(b).

[0147] In the case of PUFB (i.e., when the first conductivity type is P type) as in the first modification of the first embodiment, the control circuit 28 makes the voltage between the word line WL and the power supply line 15a smaller than VH. For example, in the first modification of the first embodiment, VH=1.2V and VDD-VWL=1.1V. This makes it possible to suppress the SNM from becoming smaller.

[0148] If VWL is too close to the voltage of the ground line 15b (or the power line 15a), the SNM does not increase. Therefore, the difference between the voltage of the ground line 15b (or the power line 15a) and VWL is preferably 49 / 50 or less of VH, more preferably 19 / 20 or less, and even more preferably 9 / 10 or less.

[0149] 9(b), the lower the VWL, the higher the standby power. Therefore, the difference between the voltage of the ground line 15b (or the power line 15a) and VWL is preferably ½ or more of the voltage VH, more preferably ¾ or more, and even more preferably ⅓ or more.

[0150] In any of the ULV retention state, VDD retention state, and read / write state, a constant bias VFN or VFP is supplied to the bias node N4. This eliminates the need for the driver 26, and reduces the circuit area. Consider the preferable range of the voltages VFN and VFP supplied to the bias node N4.

[0151] 21(a) and 21(b) are diagrams showing the voltages of the header PS·PDFB·Type 1 and the footer PS·PUFB·Type 1. In FIG. 21(a), VVDDH and VVDDL relative to VGND are shown vertically, and in FIG. 21(b), VVGNDL and VVGNDH relative to VDD are shown vertically.

[0152] 21(a), in the header PS, in the read / write state and the VDD retention state, VVDDH is supplied to the power supply line 15a and VGND is supplied to the ground line 15b. At this time, if VFN is set to a constant bias of about VVDDL, VFN is sufficiently lower than VVDDH, so the inverter circuits 14 and 16 are in the BI mode. In the ULV retention state, VVDDL is supplied to the power supply line 15a and VGND is supplied to the ground line 15b. At this time, if VFN is set to about VVDDL, VFN is higher than VGND, so the inverter circuits 14 and 16 are in the ST mode.

[0153] The constant voltage VFN should be smaller than VVDDH and larger than VGND. That is, VFN should be between the voltages of storage nodes Q1 and Q2 in the read / write state (range 40 in FIG. 21(a)). If the constant voltage VFN is too close to VVDDH, the inverter circuits 14 and 16 are unlikely to enter the BI mode when the virtual power supply voltage VVDD is set to VVDDH. If the constant voltage VFN is too close to VGND, the inverter circuits 14 and 16 are unlikely to enter the ST mode when the virtual power supply voltage VVDD is set to VVDDL. Therefore, in order to automatically switch the mode of the bistable circuit 12 by the virtual power supply voltage VVDD, the constant voltage VFN is preferably equal to or lower than the voltage at the midpoint between VVDDH and VGND (i.e., equal to or lower than (VVDDH-VGND) / 2), more preferably equal to or lower than the voltage obtained by adding half the voltage difference between VVDDL and VGND to VVDDL (i.e., equal to or lower than VVDDL+(VVDDL-VGND) / 2), and further preferably between (VVDDH-VGND) / 2 and the voltage at the midpoint between VVDDL and VGND (i.e., about (VVDDL-VGND) / 2) (range 41 in FIG. 21(a)), and preferably between VVDDL+(VVDDL-VGND) / 2 and about (VVDDL-VGND) / 2 (range 42 in FIG. 21(a)). Furthermore, about VVDDL is preferable.

[0154] As shown in Fig. 21(b), in the footer PS, in the read / write state and the VDD retention state, VVGNDL is supplied to the ground line 15b and VDD is supplied to the power supply line 15a. At this time, if VFP is set to a constant bias of about VVGNDH, VFP is sufficiently higher than VVGNDL, so the inverter circuits 14 and 16 are in the BI mode. In the ULV retention state, VVGNDH is supplied to the ground line 15b and VDD is supplied to the power supply line 15a. At this time, if VFP is set to about VVGNDH, VFP is lower than VDD, so the inverter circuits 14 and 16 are in the ST mode.

[0155] The constant voltage VFP should be greater than VVGNDL and less than VDD. That is, VFP should be between the voltages of storage nodes Q1 and Q2 in the read / write state (range 40 in FIG. 21(b)). If the constant voltage VFP is too close to VVGNDL, the inverter circuits 14 and 16 are unlikely to enter the BI mode when the virtual ground voltage VVGND is set to VVGNDL. If the constant voltage VFP is too close to VDD, the inverter circuits 14 and 16 are unlikely to enter the ST mode when the virtual ground voltage VVGND is set to VVGNDH. Therefore, in order to automatically switch the mode of the bistable circuit 12 by the virtual ground voltage VVGND, the constant voltage VFP is preferably equal to or higher than the voltage at the midpoint between VDD and VVGNDL (i.e., equal to or higher than (VDD-VVGNDL) / 2), more preferably equal to or higher than the voltage obtained by subtracting 1 / 2 of the voltage difference between VDD and VVGNDH from VVGNDH (i.e., equal to or higher than VVGNDH-(VDD-VVGNDH) / 2), and further preferably between (VDD-VVGNDL) / 2 and the voltage at the midpoint between VDD and VVGNDH (i.e., about VVGNDH+(VDD-VVGNDH) / 2) (range 41 in FIG. 21(b)), and preferably between about VVGNDH-(VDD-VVGNDH) / 2 and VVGNDH+(VDD-VVGNDH) / 2 (range 42 in FIG. 21(b)). Furthermore, about VVGNDH is preferable.

[0156] In the first embodiment and its modified examples, the type 1 in which the driver 26 is not provided has been described as an example, but the type 2 in which the driver 26 is provided may also be used. The combinations of PDFB and PUFB, the different conductivity type channels and the same conductivity type channels, and the header PS, footer PS, and dual PS can be set arbitrarily.

[0157] Although an SRAM cell has been described as an example, the bistable circuit of the first embodiment and its modified examples may be used in a flip-flop circuit such as a master-slave flip-flop circuit. In the master-slave flip-flop circuit, a switch such as a pass gate that turns on and off in synchronization with a clock signal may be provided in the loop of the bistable circuit 12. EXAMPLES

[0158] The second embodiment is an example in which the memory cell has a nonvolatile memory element. [Explanation of virtual power supply memory cell] Fig. 22 is a circuit diagram of a memory cell of a virtual power supply system using a virtual power supply voltage VVDD in Example 2. As shown in Fig. 22, in the virtual power supply system, a power switch 30 is provided between a power supply line 15a (virtual power supply line) and a power supply 15c. A memory cell 10 mainly includes inverter circuits 14 and 16, FETs M5 and M6, and spin-transfer torque magnetic tunnel junction elements (STT-MTJ: hereinafter simply referred to as ferromagnetic tunnel junction elements) MTJ1 and MTJ2 as nonvolatile memory elements.

[0159] The inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12. The inverter circuit 14 includes FETs M2 and M4. The inverter circuit 16 includes FETs M1 and M3. The FETs M1, M2, M5, and M6 are N-channel MOSFETs, and the FETs M3 and M4 are P-channel MOSFETs.

[0160] In the FETs M1 (first FET) and M2 (second FET), the sources are connected to the ground line 15b to which the ground voltage VGND is applied, the drains are connected to the storage nodes Q1 (first storage node) and Q2 (second storage node), respectively, and the gates are connected to the storage nodes Q2 and Q1, respectively. The storage nodes Q1 and Q2 are complementary nodes. The FETs M1 and M2 are drivers.

[0161] In FETs M3 (third FET) and M4 (fourth FET), one of the source and drain is connected to storage nodes Q1 and Q2, the other of the source and drain is connected to control lines CTRL1 (first control line) and CTRL2 (second control line), and the gate is connected to a word line WL. FETs M3 and M4 function as pass transistors during read and write operations, and function as loads during hold, store, and restore operations.

[0162] A FET M5 and a ferromagnetic tunnel junction element MTJ1 are connected between a storage node Q1 and a control line CTRL0, and a FET M6 and a ferromagnetic tunnel junction element MTJ2 are connected between a storage node Q2 and a control line CTRL0. In the FET M5 (first switch) and the FET M6 (second switch), one of the source and the drain is connected to the storage nodes Q1 and Q2, respectively, and the other of the source and the drain is connected to the ferromagnetic tunnel junction elements MTJ1 and MTJ2, respectively. The gate is connected to a switch line SR.

[0163] The ferromagnetic tunnel junction elements MTJ1 (first nonvolatile memory element) and MTJ2 (second nonvolatile memory element) each have a free layer 17, a tunnel insulating film 18, and a pinned layer 19. The free layer 17 is connected to a control line CTRL0, and the pinned layer 19 is connected to FETs M5 and M6. The free layer 17 and the pinned layer 19 are made of a ferromagnetic material. When the magnetization directions of the free layer 17 and the pinned layer 19 are parallel (parallel state), the resistance values ​​of MTJ1 and MTJ2 are low. When the magnetization directions of the free layer 17 and the pinned layer 19 are antiparallel (antiparallel state), the resistance values ​​of MTJ1 and MTJ2 are higher than in the parallel state. MTJ1 and MTJ2 store data according to the magnetization states (i.e., resistance values) of MTJ1 and MTJ2. Although an MTJ will be used as an example of a nonvolatile memory element, the nonvolatile memory element may also be a giant magnetoresistance (GMR) element, a variable resistance element such as that used in a ReRAM (Resistance Random Access Memory), or a phase change element such as that used in a PRAM (Phase change RAM).

[0164] The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power supply line 15a. The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power supply line 15a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage VVDD and supplies it to the power supply line 15a.

[0165] FIG. 23 is a diagram showing a power switch and a selection circuit in a virtual power supply method using a virtual power supply voltage of the second embodiment. As shown in FIG. 23, the memory cell 10 is an NV-SRAM cell. Other circuit configurations are the same as those of FIG. 7B. In the second embodiment, the virtual power supply voltage VVDD becomes VDDH during a store operation and a restore operation, and the voltage VVDD-VGND is, for example, 1.2V. The virtual power supply voltage VVDD becomes VDDL during a hold state, and the voltage VVDD-VGND is, for example, 1.0V. The FETs M10 to M12 are turned off during a read operation and a write operation.

[0166] [Explanation of virtual ground memory cell] Fig. 24 is a circuit diagram of a virtual ground memory cell 10 in Example 2. As shown in Fig. 24, in the virtual ground system, a power switch 30 is provided between a ground line 15b (virtual ground line) and a ground 15d. FETs M1a to M6a are provided instead of FETs M1 to M6. FETs M1a, M2a, M5a, and M6a are P-channel FETs, and FETs M3a and M4a are N-channel FETs.

[0167] The sources of FETs M1a and M2a are connected to the power supply line 15a. The pin layers 19 of MTJ1 and MTJ2 are connected to the control line CTRL0, and the free layers 17 are connected to FETs M5 and M6. The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the ground line 15b. The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the ground line 15b. The power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground line 15b. The other configurations are the same as those in FIG. 22 of the virtual power supply method, and therefore description thereof will be omitted.

[0168] FIG. 25 is a diagram showing a power switch and a selection circuit in the virtual ground system of the second embodiment. As shown in FIG. 25, the selection circuit 32b connects either the bit lines BL and BLB connected to the read / write circuit 34 or the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 includes FETs PS1a and PS2a. The FETs PS1a and PS2a are N-channel FETs. The FET PS1a is connected between the ground 15dL and the ground line 15b, and the FET PS2a is connected between the ground 15dH and the ground line 15b. The grounds 15dL and 15dH are supplied with the ground voltages VGNDL and VGNDH, respectively.

[0169] Signals VPS1 and VPS2 are input to the gates of FETPS1a and PS2a, respectively. When the signals VPS1 and VPS2 are at high and low levels, respectively, FETPS1a and PS2a are turned on and off, respectively, and the virtual ground voltage VVGND is VGNDL. The virtual ground voltage VVGND is VGNDL during a store operation and a restore operation, and VDD-VVGND is, for example, 1.2V. When the signals VPS1 and VPS2 are at low and high levels, respectively, FETPS1a and PS2a are turned off and on, respectively, and the virtual ground voltage VVGND is VGNDH. The virtual ground voltage VVGND is VGNDH during a hold state, and VDD-VVGND is, for example, 1.0V. When the signals VPS1a and VPS2a are both at low levels, both FETPS1a and PS2a are turned off, and the virtual ground voltage VVGND is cut off. The virtual ground voltage VVGND is cut off during a shutdown state.

[0170] The precharge / selection circuit 33a includes FETs M10 to M12. FET M10 is connected between the power supply 15c and the control line CTRL1. FET M11 is connected between the power supply 15c and the control line CTRL2. FET M12 is connected between the control lines CTRL1 and CTRL2. A selection signal Sel is input to the gates of FETs M10 to M12. When the selection signal Sel is at a low level, the FETs M10 to M12 are turned on, and a power supply voltage VDD is applied to the control lines CTRL1 and CTRL2. The FETs M10 to M12 are turned on during a precharge for a read operation. When the selection signal Sel is at a high level, the FETs M10 to M12 are turned off, and the selection circuit 32b connects the control lines CTRL1 and CTRL2 to the bit lines BL and BLB or the ground line 15b.

[0171] The memory array and operation of the second embodiment will be described below using the virtual power supply system as an example.

[0172] [Memory array description] FIG. 26 is a block diagram of a memory array in the second embodiment. As shown in FIG. 26, the memory array 22 is divided into a plurality of blocks 24 each having a memory cell 10. The number of blocks 24 can be designed as appropriate. A plurality of memory cells 10 are arranged in a matrix in the memory array 22. In the memory array 22, word lines WL and switch lines SR extend in the row direction, and control lines CTRL0 to CTRL2 extend in the column direction. The word lines WL, switch lines SR, and control lines CTRL0 to CTRL2 are connected to each memory cell 10. In FIG. 26, the control lines CTRL1 and CTRL2 in columns 1 to n are indicated as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.

[0173] A control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22. The control circuit 28 controls the power switch 30 and the peripheral circuit 38. The peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge / selection circuit 33a, a read / write circuit 34, an SR decoder 35, and a column decoder 36.

[0174] In read and write operations, the selection circuit 32b connects the bit lines BL1, BLB1 to BLn and BlBn to the control lines CTRL11, CTRL21 to CTRL1n and CTRL2n, respectively. The WL decoder 31 selects the word line WL based on the row address. The read / write circuit 34 selects the bit lines BL and BLB corresponding to the selected column from the bit lines BL1, BLB1 to BLn and BLBn based on the column address. The precharge / select circuit 33a precharges the bit lines BL and BLB. The read / write circuit 34 writes data to the bistable circuit 12 of the selected memory cell 10 or reads data from the bistable circuit 12, and outputs the data to the bus 25.

[0175] In the store and restore operations, the selection circuit 32b connects the power supply line 15a to the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n. In the store operation, the SR decoder 35 selects the switch line SR based on the row address. The column decoder 36 selects the control line CTRL0 based on the column address. In the memory cell 10 selected by the WL decoder 31 and the column decoder 36, the data of the bistable circuit 12 is stored in a non-volatile manner in the ferromagnetic tunnel junction elements MTJ1 and MTJ2.

[0176] [Explanation of operation] 27(a) to 29 are diagrams showing the operation of a memory cell in Example 2. H indicates a high level, L indicates a low level, and the values ​​in parentheses indicate examples of voltages.

[0177] As shown in FIG. 27(a), a case will be described in which the voltages of the storage nodes Q1 and Q2 in the bistable circuit 12 are set to H (for example, 1.2V) and L (for example, 0V), respectively. During a read operation to read data from the bistable circuit 12, the control circuit 28 causes the selection circuit 32b to function as the control lines CTRL1 and CTRL2 as the bit lines BL and BLB. For example, the control circuit 28 turns off the FETs M10 to M12 in FIG. 23 and turns on the transfer gates M13 and M14. The control circuit 28 sets the word line WL to L (for example, 0V), turns off the FETs M5 and M6 (for example, sets the switch line SR to L (for example, 0V)), and sets the control line CTRL0 to L (for example, 0V). The read / write circuit 34 sets the control lines CTRL1 and CTRL2 to H (for example, 1.2V) and reads data from the bistable circuit.

[0178] As shown in FIG. 27(b), a write operation for writing data to the bistable circuit 12 will be described by taking as an example a case where the voltage of the storage node Q1 is rewritten from H to L and the voltage of the storage node Q2 is rewritten from L to H. The control circuit 28 causes the selection circuit 32b to function the control lines CTRL1 and CTRL2 as bit lines BL and BLB. The control circuit 28 sets the word line WL to L, turns off the FETs M5 and M6, and sets the control line CTRL0 to L. The read / write circuit 34 sets the bit lines BL and BLB to L (e.g., 0V) and H (e.g., 1.2V), respectively. As a result, L and H are written to the storage nodes Q1 and Q2, respectively.

[0179] As shown in FIG. 27(c), when the bistable circuit 12 is in a hold state in which data is volatilized, the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply a voltage VDDH (for example, 1.2V) to the control lines CTRL1 and CTRL2 as H. For example, the control circuit 28 turns on the FETs M10 to M12 in FIG. 23, turns off the transfer gates M13 and M14, turns on the FET PS1, and turns off the FET PS2. The control circuit 28 sets the word line WL to H (for example, 1.2V), turns off the FETs M5 and M6, and sets the control line CTRL0 to L. As a result, the storage nodes Q1 and Q2 are maintained at H and L, respectively. As described above, in the read operation, write operation, and hold state, the FETs M5 and M6 are turned off, so that the influence of the MTJ1 and MTJ2 does not reach the bistable circuit 12.

[0180] The operation of storing data of the bistable circuit 12 in a non-volatile manner in MTJ1 and MTJ2 will be described. In the store operation, an H-store operation (first store operation) is performed to set one of MTJ1 and MTJ2 to a high resistance, and an L-store operation (second store operation) is performed to set the other of MTJ1 and MTJ2 to a low resistance. Either the H-store operation or the L-store operation may be performed first. A hold state may be set between the H-store operation and the L-store operation.

[0181] As shown in FIG. 28(a), an example will be described in which storage nodes Q1 and Q2 are H and L, respectively. During an H-store operation, control circuit 28 causes power switch 30 and selection circuit 32b to apply voltage VDDH as H to control lines CTRL1 and CTRL2. Control circuit 28 sets word line WL to L, turns on FETs M5 and M6 (for example, sets voltage VSR to 0.7V), and sets control line CTRL0 to L. This causes current Im1 to flow from storage node Q1 to control line CTRL0 via MTJ1. Therefore, MTJ1 is in an anti-parallel state and has high resistance.

[0182] As shown in FIG. 28(b), during an L-store operation, the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply a voltage VDDH to the control lines CTRL1 and CTRL2 as H. The control circuit 28 sets the word line WL to H' (e.g., 0.8V), turns on the FETs M5 and M6 (e.g., sets the voltage VSR to 0.7V), and sets the control line CTRL0 to Vc (e.g., 0.5V). This causes a current Im2 to flow from the control line CTRL0 to the storage node Q2 via MTJ2. Therefore, MTJ2 is in a parallel state and has a low resistance.

[0183] As shown in FIG. 28(a) and FIG. 28(b), when FETs M1 and M2 are N-type channels, the voltage VWL (first voltage) of the word line WL in the H-store operation (first store operation) is lower than the voltage VWL (fourth voltage) in the L-store operation (second store operation), and the voltage Vc (third voltage) of the control line CTRL0 in the H-store operation is lower than the voltage Vc (sixth voltage) in the L-store operation. The voltages (second and fifth voltages) of the control lines CTRL1 and CTRL2 in the H-store operation and L-store operation are higher than the voltage VGND of the ground line 15b. This allows data in the bistable circuit 12 to be stored in the MTJ1 and MTJ2. Note that, as shown in FIG. 24, when FETs M1a and M2a are P-type channels, the first voltage is higher than the fourth voltage, and the third voltage is higher than the sixth voltage. The second and fifth voltages are lower than the voltage VDD of the power supply line 15a.

[0184] As shown in FIG. 28(c), after the store operation, the power supply is shut down (the voltage VVDD-VGND is set to 0V) to set the shutdown state. In the shutdown state, the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply the voltage VGND (for example, 0V) to the control lines CTRL1 and CTRL2 as L. The control circuit 28 sets the word line WL to L, turns off the FETs M5 and M6, and sets the control line CTRL0 to L. In this way, the control circuit 28 shuts down the power supply to the memory cell 10. In the shutdown state, the MTJ1 and MTJ2 are maintained at high resistance and low resistance, respectively. The power supplies of the control circuit 28 and the peripheral circuit 38 may or may not be shut down.

[0185] As shown in FIG. 29, an example will be described in which MTJ1 and MTJ2 are high resistance and low resistance, respectively. During a restore operation to restore data of MTJ1 and MTJ2 to the bistable circuit 12, the control circuit 28 raises the control lines CTRL1 and CTRL2 to H' (for example, 1.0 V) from L to the power switch 30 and the selection circuit 32b. The control circuit 28 sets the word line WL to L' (for example, 0.1 V), turns on FETs M5 and M6 (for example, voltage VSR is set to 0.7 V), and sets the control line CTRL0 to L. A current Im3 flows from the control line CTRL1 to MTJ1 via FETs M3 and M5. Similarly, a current Im4 flows from the control line CTRL2 to MTJ2 via FETs M4 and M6. Since MTJ1 and MTJ2 are high resistance and low resistance, respectively, the current Im4 is larger than Im3. As a result, the voltage of the storage node Q2 decreases faster than the voltage of the storage node Q1. Therefore, the storage nodes Q1 and Q2 are stabilized at H and L, respectively. This completes the restore operation. After the restore operation, the bistable circuit 12 volatilely holds the data by going into a hold state. Also, a read operation and a write operation are performed.

[0186] As shown in Figures 27(a) and 27(b), the control circuit 28 turns off FETs M5 and M6 during a write operation in which data is volatilely written to the bistable circuit 12 and during a read operation in which data is read from the bistable circuit 12. As shown in Figures 28(a), 28(b), and 29, the control circuit 28 turns on FETs M5 and M6 during a store operation in which data is nonvolatilely stored from the bistable circuit 12 to MTJ1 and MTJ2 and during a restore operation in which data is restored from MTJ1 and MTJ2 to the bistable circuit 12. This makes it possible to suppress the influence of MTJ1 and MTJ2 on the bistable circuit 12 during a write operation and a read operation.

[0187] [Simulation 3] A simulation was performed to determine the appropriate channel width and voltage in Example 2. In Simulation 3, the following steps S1 to S5 were performed to determine each channel width and voltage. First, by analogy with Comparative Example 3 (6T-SRAM), the channel width of each FET was set as follows. The channel length of each FET was 60 nm. FETM1, M2: WDRV=150nm FETM3,M4: WLP=100nm FETs M5, M6: WSR = 100 nm

[0188] [Step S1] In step S1, the channel width WLP of FETs M3 and M4 was determined from the SNM in the hold state of the 4T cells (FETs M1 to M4) of the bistable circuit 12 of the second embodiment. FIG. 30 is a diagram showing the SNM and standby power with respect to the WLP in the hold state in simulation 3. The channel width WDRV of FETs M1 and M2 is 150 nm, the voltage VWL of the word line WL is 1.2 V, and the voltage VDDH of the control lines CTRL1 and CTRL2 is 1.2 V. The SNM is illustrated for TT, SS, SF, FS, and FF. As for the standby power, the simulation result of the second embodiment (4T cell) is indicated by a solid line, and the simulation result of the third comparative example (6T cell) is indicated by a dashed line.

[0189] As shown in Figure 30, as the WLP increases, the SNM increases, but the standby power also increases. When the WLP is 105 nm or more, all SNMs are 80 mV or more. When the WLP is 110 nm or more, the standby power exceeds that of Comparative Example 3. For these reasons, the WLP was decided to be 105 nm.

[0190] [Step S2] In step S2, the voltage VWL of the word line WL in the read operation, write operation, and hold state was determined from the SNM in the read operation and hold state of the 4T cell. Figure 31 is a diagram showing the SNM with respect to the VWL in the read operation and hold state in simulation 3. The channel width WDRV of FETM1 and M2 is 150 nm, the channel width WLP of FETM3 and M4 is 105 nm, and the voltage VDDH of the control lines CTRL1 and CTRL2 is 1.2 V. The SNM is illustrated for TT, SS, SF, FS, and FF. A VWL of around 0 V corresponds to a read operation and a write operation that turns on FETM3 and M4, and a VWL of around 1.2 V corresponds to a hold state that turns off FETM3 and M4.

[0191] As shown in Figure 31, SNM depends on VWL. As VWL increases from 0V, SNM becomes larger, and as VWL decreases from 1.2V, SNM becomes larger. SNM becomes largest when VWL is 0.7V to 0.8V. Since SNM is 80mV or more when VWL=0V and 1.2V, the VWL for read and write operations was determined to be 0V, and the VWL for the hold state was determined to be 1.2V.

[0192] [Step S3] In step S3, the current Im1 (see FIG. 28(a)) in the H-store operation was designed. The current Im1 was targeted to be 1.2 times the threshold current Ic at which MTJ1 and MTJ2 switch from a parallel state to an anti-parallel state. In the store operation, the control lines CTRL1 and CTRL2 are H (1.2V) to hold the data in the bistable circuit 12. The voltage Vc of the control line CTRL0 is set to 0V to flow the current Im1 from the storage node Q1 of H to MTJ1. FETs M5 and M6 are turned on. FET M3 is turned on so that the storage node Q1 does not become L. For this reason, the voltage VWL of the word line WL is set to 0V.

[0193] 32(a) and 32(b) are diagrams showing the current Im1 and SNM, respectively, versus the voltage VSR for the H-store operation in Simulation 3. As shown in FIG. 32(a), as the voltage VSR increases, the current Im1 increases. When the voltage VSR is 0.7V or higher, the current Im1 is 1.2Ic or higher. As shown in FIG. 32(b), as the voltage VSR increases, the SNM decreases. When the voltage VSR is 0.95V or higher, the SNM falls below 80mV. The voltage VSR was set to 0.7V so that the SNM was 80mV or higher and the current Im1 was around 1.2Ic.

[0194] [Step S4] In step S4, the current Im2 (see FIG. 28(b)) in the L-store operation was designed. The current Im2 was targeted to be 1.2 times or more the threshold current Ic at which MTJ1 and MTJ2 switch from the antiparallel state to the parallel state. To retain the data of the bistable circuit 12, the control lines CTRL1 and CTRL2 are H (1.2V). To pass the current Im2 from the control line CTRL0 to the L storage node Q2 via MTJ2, the voltage Vc of the control line CTRL0 is made higher than L. To turn on the FETs M5 and M6, the voltage VSR is set to 0.7V, the same as the H-store operation. The voltage VWL of the word line WL and the voltage Vc of the control line CTRL0 were changed.

[0195] 33(a) and 33(b) are diagrams showing currents Im2 and SNM, respectively, versus voltage Vc in an L-store operation in simulation 3. Since SF is the smallest, SF is shown as SNM. As shown in FIG. 33(a), as the voltage Vc of the control line CTRL0 increases, the current Im2 increases, and as the voltage VWL of the word line WL increases, the current Im2 increases. The reason that the current Im2 decreases as the voltage VWL decreases is that when the voltage VWL is near 0V, FET M4 is completely on, causing the voltage of storage node Q2 to increase.

[0196] As shown in FIG. 33(b), when the voltage VWL is increased from 0V, the SNM increases, but when the voltage VWL is 0.4V or higher, the SNM decreases. When the VWL is 0.9V, the SNM decreases below 80mV. This is because when the voltage VWL increases, the FET M4 turns off and data cannot be maintained. When the voltage VWL is set to 0.5V to 0.8V, the current Im2=1.2Ic and the SNM of 100mV or more can be achieved by appropriately selecting the voltage Vc. The voltage VWL was set to 0.8V and the voltage Vc to 0.5V. In this way, by setting the voltage VWL for the L-store operation higher than the voltage VWL for the H-store operation, the decrease in SNM during the L-store operation can be suppressed.

[0197] Also, the voltage VWL during the L-store operation is preferably such that FETs M3 and M4 are slightly turned on. Therefore, when FETs M1 and M2 are N-channel, the voltage VWL during the L-store operation is preferably lower than the voltages of the control lines CTRL1 and CTRL2. Also, when FETs M1a and M2a are P-channel, the voltage VWL during the second store operation is preferably higher than the voltages of the control lines CTRL1 and CTRL2. This allows the SNM to be increased. The voltage VWL during the second store operation is preferably greater than or equal to VGND+1 / 4 (VDD-VGND) and less than or equal to VDD-1 / 4 (VDD-VGND).

[0198] [Step S5] In step S5, the voltage VSR of the switch line SR and the voltage VWL of the word line WL in the restore operation are determined. In the restore operation, the voltage Vc of the control line CTRL0 is set to 0V, and the voltages of the control lines CTRL1 and CTRL2 are raised. Data is restored to the bistable circuit 12 without raising the voltages of the control lines CTRL1 and CTRL2 to the voltage VDDH (1.2V). Therefore, the restore operation is terminated when the voltages of the control lines CTRL1 and CTRL2 are raised to 1.0V. After the restore operation, for example, when a hold state is set, the voltages of the control lines CTRL1 and CTRL2 are raised to VDDH (1.2V). This allows the voltage VSR to be 0V and the voltage VWL to be 1.0V or higher when the voltages of the control lines CTRL1 and CTRL2 are 1.0V or higher, thereby reducing power consumption.

[0199] 34(a) and 34(b) are diagrams showing SNM versus voltage VSR of FF and FS in the restore operation in simulation 3. The SNM is when the voltages of the control lines CTRL1 and CTRL2 are 1.0V. As shown in FIG. 34(a) and FIG. 34(b), when the voltage VSR of the switch line SR is increased in a state in which FETs M3 and M4 are off (for example, VWL=0.8V), the voltage of the H storage node Q1 decreases, and SNM decreases. By lowering the voltage VWL of the word line WL and turning on FETs M3 and M4, a current flows from the control line CTRL1 to the H storage node Q1, the H of the storage node Q1 can be maintained, and SNM increases. If the voltage VWL is lowered too much, the voltage of the L storage node Q2 increases, and SNM decreases. Taking these factors into consideration, the voltage VSR is determined to be 0.7V, the same as in the store operation, and the voltage VWL is determined to be 0.1V.

[0200] When a restore operation is performed, the voltage VWL of the word line WL is higher than the lower voltage VDD (e.g., 0V) of the storage nodes Q1 and Q2 during a write operation, and lower than the higher voltage VGND (e.g., 1.2V) of the storage nodes Q1 and Q2. This allows the SNM to be increased as shown in Figures 34(a) and 34(b). The voltage VWL during a restore operation is preferably lower than VGND+1 / 4 (VDD-VGND) when FETs M1 and M2 are N-type channels, and is preferably higher than VDD-1 / 4 (VDD-VGND) when FETs M1a and M2a are P-type channels.

[0201] Table 5 shows the channel width and voltages of each FET determined based on the above steps S1 to S5. [Table 5]

[0202] In Table 5, the voltage VWL of the word line WL in the read operation, write operation, H-store operation, and L-store operation is the voltage VWL in the accessed memory cell 10. The voltage VWL in the non-accessed memory cell 10 is 1.2 V (high level) at which the FETs M3 and M4 are turned off.

[0203] In Table 5, during the hold state, read operation, and write operation, the voltage VSR applied to the switch line SR is -0.2V, which is lower than L. This is to suppress the leakage current of FETM5 and M6. The voltage VSR may be any voltage that turns off FETM5 and M6. To suppress the leakage current of FETM5 and M6 during the hold state, read operation, and write operation, the voltage Vc of the control line CTRL0 may be made higher than L. For example, the voltage Vc may be 0.05V. The voltage VSR may be made lower than L and the voltage Vc may be made higher than L.

[0204] The voltage VSR in the H-store operation, L-store operation, and restore operation may be set to a level at which FETs M5 and M6 are turned on. The voltage VWL of the word line WL in the hold state may be set to a level at which FETs M3 and M4 are turned off, and the voltage VWL in the read operation, write operation, H-store operation, and restore operation may be set to a level at which FETs M3 and M4 are turned on. The channel width and each voltage are not limited to the examples in Table 5 and can be set as appropriate.

[0205] Using the values ​​in Table 5, SNM in each state and operation was simulated. Figure 35(a) is a diagram showing SNM in Example 2. As shown in Figure 35(a), the SNM of FS in the hold state is the smallest. The SNM is 80mV or more in all states and at all corners of the operation. In TT, the SNM is 100mV or more in all states and operations.

[0206] The standby power in Example 2 was simulated and compared with that in Comparative Example 3 (6T cell) described in Fig. 15. Fig. 35(b) is a diagram showing the standby power in Example 2 and Comparative Example 3.

[0207] 35(b), in Comparative Example 3, the reduction rate of the sleep state with VVDD=0.8V compared to normal operation with VVDD=1.2V is 44%. The reduction rate of the standby power when VVDD=1.2V in Example 2 compared to VVDD=1.2V in Comparative Example 3 is 11%. Furthermore, the reduction rate of the standby power in the shutdown state with VVDD=1.2V in Example 2 is 99.99%.

[0208] As described above, in the second embodiment, the FETs M1 and M2 are FETs with a first conductivity type channel, the FETs M3 and M4 are FETs with a second conductivity type channel opposite to the first conductivity type, and the FETs M3 and M4 are used as a pass transistor and a load. This allows the standby power to be reduced and the number of transistors to be reduced to six, making it possible to reduce the size.

[0209] [Modification 1 of Example 2] FIG. 36 is a circuit diagram of a memory cell according to the first modification of the second embodiment. As shown in FIG. 36, in the first modification of the second embodiment, FETM5 and MTJ1 are connected between the storage node Q1 and the control line CTRL0 in FIG. 6 of the first embodiment, and FETM6 and MTJ2 are connected between the storage node Q2 and the control line CTRL0. In this manner, the bistable circuit 12 may be the bistable circuit of the first embodiment and its modifications. As in FIG. 7B and FIG. 23, a precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and a selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.

[0210] When the access interval to the memory cell 10 is short, data is ULV-retained in the bistable circuit 12, and when the access interval is long, data is stored in MTJ1 and MTJ2 and then shut down, thereby further reducing power consumption. EXAMPLES

[0211] Example 3 is an application example to a binary neural network (BNN) such as BinaryNET or XNOR-NET. BNNs can be realized with low power consumption and small memory without much deterioration in inference accuracy, and are expected to be applied to edge computing. In edge computing, learning and inference are not always performed, but data such as weights stored in the BNN device must be held in memory. Therefore, reducing the standby power consumption of the memory becomes an issue. By using ULVR-SRAM or NV-SRAM in the memory part of the BNN device (BNN accelerator), it is possible to reduce the standby power consumption of the memory.

[0212] Fig. 37 is a diagram showing a BNN model in Example 3. Below, a BNN model using the Batch Normalization Free Technique (Y. Yonekawa and H. Nakahara, "On-chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA", 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 98-105, 2017) is shown.

[0213] As shown in FIG. 37, three layers, X, Y and Z, are taken as an example. The number of layers may be four or more. The X layer has nodes x1 to xn, the Y layer has nodes y1 to yn, and the Z layer has nodes z1 to zn. Each of the nodes x1 to xn, y1 to yn and z1 to zn is 1 bit. The output of each node x1 to xn in the X layer is multiplied by a 1-bit weight w1i to wni (i is an integer from 1 to n) and input to the node yi. Furthermore, an integer bias W0i is input from the node l to the node yi. The output of the node yi is obtained by passing the sum of these through an evaluation function. The data of all the nodes yi is obtained by performing the above calculation for all i (integers from 1 to n). The output of the node yj in the Y layer is multiplied by a 1-bit weight w'j1 to w'jn (j is an integer from 1 to n) and input to each node zk (k is an integer from 1 to n). Node zj receives an integer bias W'j0 from node l. The above calculation is performed for all j (integers from 1 to n), and each node zj adds up the respective inputs. After this calculation is complete, the sum is passed through an evaluation function to obtain the output of each node zk (k = 1 to n). Each piece of data in the weighting matrices w11 to wnn and w'11 to w'nn is 1 bit, and each piece of data in the integer bias columns W01 to W0n and W'10 to W'n0 is an integer (multi-bit). The same applies if there are layers after the Z layer.

[0214] In the third embodiment, the calculation for calculating the Y layer from the X layer is performed by performing a calculation corresponding to the solid line from the nodes x1 to xn to the node y1, then performing a calculation corresponding to the dashed line from the nodes x1 to xn to the node y2, and then performing a calculation corresponding to the dotted line from the nodes x1 to xn to the node y3. After that, the calculation is performed sequentially for the nodes y4 to yn. This is called an n-to-1 connection. The calculation for calculating the Z layer from the Y layer is performed by performing a calculation for the solid line from the node y1 to the nodes z1 to zn, then performing a calculation for the dashed line from the node y2 to the nodes z1 to zn, and then performing a calculation for the dotted line from the node y3 to the nodes z1 to zn. This is called a 1-to-n connection. The calculations for the solid line and dashed line of the 1-to-n connection can be performed in parallel with the calculations for the dashed line and dotted line of the n-to-1 connection, respectively.

[0215] FIG. 38 is a block diagram of a calculation circuit that performs calculation of n-to-1 connection in the third embodiment. As shown in FIG. 38, the calculation circuit 50 includes a memory 51 and a processing unit 52. The processing unit 52 includes an XNOR circuit 53, a counter 54, an adder 55, an evaluation unit 56, and an output unit 57. The input unit 48 is an n-bit latch circuit, and holds data of nodes x1 to xn. The XNOR circuit 53 obtains data of nodes x1 to xn from the input unit 48, obtains weight sequence w1i to wni from the memory 51, and performs an XNOR operation on the data of nodes x1 to xn and the weight sequence w1i to wni. The counter 54 performs bit counting of the output of the XNOR circuit 53 and calculates the sum. That is, it calculates the number of bits of 1 in the output of n XNOR circuits 53. The adder 55 obtains an integer bias W0i from the memory 51 and adds it to the output of the counter 54. An evaluation unit 56 compares the output of the adder 55 with an evaluation function f, and outputs a 1-bit result as data of node yi to an output unit 57. The output unit 57 is a 1-bit latch circuit, and holds the data of node yi.

[0216] Fig. 39(a) is a block diagram of a calculation circuit that performs calculations for 1-to-n connections in the third embodiment. As shown in Fig. 39(a), the calculation circuit 60 includes a memory 61 and a processing unit 62. The processing unit 62 includes an XNOR circuit 63, an accumulator 64, an adder 65, an evaluation unit 66, and an output unit 67. The XNOR circuit 63 obtains the data of node yi from the output unit 57, obtains the weight sequence w'i1 to w'in from the memory 61, and performs an XNOR operation on the data of node yi and the weight sequence w'i1 to w'in.

[0217] FIG. 39(b) is a block diagram of the accumulator. As shown in FIG. 39(b), the accumulator 64 includes an adder 64c and a latch circuit 64d. The adder 64c adds the output of the latch circuit 64d and the output of the XNOR circuit 63. The latch circuit 64d holds the output of the adder 64c. The latch circuit 64d is reset in advance, and when i changes from 1 to n, it sequentially adds up the outputs of the XNOR circuit 63 at each i. Then, when i=n, ​​it outputs the numerical value of the calculation result to the adder 65. In this way, the accumulator 64 accumulates the outputs of i=1 to n for each of the n outputs of the XNOR circuits 63.

[0218] 39(a), the adder 65 obtains the integer bias sequence W'10 to W'n0 from the memory 61 and adds it to the output sequence of the accumulator 64. The evaluation unit 66 compares the output sequence of the adder 65 with an evaluation function f, and outputs 1-bit results to the output unit 67 as data of nodes z1 to zn. The output unit 67 is an n-bit latch circuit, and holds the data of nodes z1 to zn.

[0219] FIG. 40 is a block diagram of a BNN device in the third embodiment. As shown in FIG. 40, memories 51 (first memory) and 61 (second memory) are in a matrix form. The memory 51 stores an integer bias sequence W01 to W0n and a weight matrix w11 to wnn. The weights w11 to wnn are each stored in a memory cell 10 (first memory cell). In the memory 51, a plurality of weights w1i to wni corresponding to one node yi are stored in the same row, and a plurality of weights (for example, w11 to wn1 and w12 to wn2) corresponding to different nodes yi are stored in different rows. A plurality of memory cells 10 in the same row are respectively connected to a plurality of bit lines BL (first bit lines) extending in the column direction. Each integer bias (W01 to W0n) is multi-bit and is stored in the memory cell 10.

[0220] The memory 61 stores integer bias columns W'10 to W'n0 and weight matrices w'11 to w'nn. The weights w'11 to w'nn are each stored in a memory cell 10' (second memory cell). In the memory 61, a plurality of weights w'i1 to w'in corresponding to one second node yi are stored in the same row, and a plurality of weights (e.g. w'11 to w'1n and w'21 to w'2n) corresponding to different second nodes yi are stored in different rows. The plurality of memory cells 10' in the same row are respectively connected to a plurality of second bit lines BL' extending in the column direction. Each integer bias (W'10 to W'n0) is multi-bit and is stored in a memory cell 10'.

[0221] By storing the weight matrix in the memories 51 and 61 as described above, the processing unit 52 can obtain a plurality of first weights w1i to wni from the memory 51 via a plurality of bit lines BL when processing the node yi. Also, the processing unit 62 can obtain a plurality of weights w'i1 to w'in from the memory 61 via the second bit line BL' when processing the node yi. This allows the processing units 52 and 62 to perform processing efficiently. The memory cells 10 and 10' may be 6T-SRAM cells, or may be the memory cells 10 of the first and second embodiments and their modifications. At least a part of the processing units 52 and 62 may be realized as a dedicated circuit. At least a part of the processing units 52 and 62 may be realized by a processor working in cooperation with software. In this case, at least a part of the processing units 52 and 62 becomes a processor.

[0222] In the arithmetic circuit 50, XNOR circuits 53 are provided corresponding to the columns of weight matrices w11 to wnn, and perform an XNOR operation on the output data of nodes x1 to xn of the input unit 48 and the weight columns w1i to wni. A counter 54 counts the output bits of the XNOR circuit 53. The adder 55, evaluation unit 56, and output unit 57 are the same as those described in FIG.

[0223] In the arithmetic circuit 60, the XNOR circuit 63 to the output unit 67 are provided corresponding to the columns of the weight matrices w'11 to w'nn. The XNOR circuit 63 performs an XNOR operation on the output data of node yi of the output unit 57 and the weight columns w'i1 to w'in. The accumulator 64 to the output unit 67 perform this for each column. The other operations are the same as those explained in Figure 39(a). When there are four or more layers, the nodes z1 to zn of the output unit 67 become the input data string for the n-to-1 connection processing of the next layer.

[0224] FIG. 41 is a flowchart showing the process of n-to-1 connection performed by the processing unit 52 in the third embodiment. As shown in FIG. 41, the processing unit 52 sets i to 1 (step S10). The processing unit 52 acquires the weight sequence w1i to wni from the memory 51 (step S12). The processing unit 52 calculates the XNOR of the data of the nodes x1 to xn and the weight sequence w1i to wni (step S14). The processing unit 52 performs bit counting of the calculation result of each XNOR and calculates the sum (step S16). The processing unit 52 acquires the weight W0i from the memory 51 and adds it to the sum in step S16 (step S18). The processing unit 52 compares the result of step S18 with the evaluation function f to calculate and hold the data of 1 bit of the node yi (step S20). The processing unit 52 judges whether i=n (step S22). If No, the processing unit 52 sets i=i+1 and proceeds to step S12 (step S24). If the answer is Yes, the n-to-1 connection process ends. The processing unit 52 may include a control circuit that controls the operation of each circuit, and the control circuit may execute steps S10 to S24.

[0225] FIG. 42 is a flowchart showing the process of 1-to-n connection performed by the processing unit 62 in the third embodiment. As shown in FIG. 42, the processing unit 62 sets i to 1 (step S30). The processing unit 62 acquires the weight sequence w′i1 to w′in from the memory 61 (step S32). The processing unit 62 acquires the data of the node yi from step S20 of FIG. 41, and calculates the XNOR of the data of the node yi and the weight sequence w′i1 to w′in (step S34). The processing unit 62 accumulates each of the n XNOR calculation results (step S36). The processing unit 62 judges whether i=n (step S38). If No, the processing unit 62 sets i=i+1 and returns to step S32 (step S40). If Yes in step S38, the processing unit 62 acquires the weights W′10 to W′n0 from the memory 61, and adds them to each of the n results of step S36 (step S42). The processing unit 62 calculates and holds 1-bit data for each of the nodes z1 to zn by comparing each of the n results of step S42 with the evaluation function f (step S44). After that, the 1-to-n connection process ends. The data for the nodes z1 to zn becomes an input data string when making an n-to-1 connection in the next layer. The processing unit 62 may include a control circuit that controls the operation of each circuit, and the control circuit may execute steps S30 to S44.

[0226] FIG. 43 is an explanatory diagram showing the processing operation of the third embodiment along the time axis. In FIG. 43, the processing operation of the third embodiment is illustrated so as to be compared with the processing operations of Case 1 and Case 2 described later. Processes 71 to 74 show calculations between layers. For example, process 71 is a process of calculating each node y1 to yn of the Y layer from each node x1 to xn of the X layer in FIG. 37, and process 72 is a process of calculating each node z1 to zn of the Z layer from each node y1 to yn of the Y layer. Process 73 is a process of calculating each node of a subsequent layer from each node z1 to zn of the Z layer. Process 74 is a process of a subsequent stage. Process 70 shows a process corresponding to one node. In the n-to-1 connection process, the process of calculating one node yi from n nodes x1 to xn corresponds to process 70. In the 1-to-n connection process, the process of calculating n nodes z1 to zn from one node yi corresponds to process 70. Each of the processes 71 to 74 executes n processes 70 sequentially.

[0227] In case 1, processes 71 to 74 are all n-to-1 connection processes or all 1-to-n connection processes. In this case, processes 71 to 74 cannot be processed in parallel. In case 2, processes 71 and 73 are 1-to-n connection processes, and processes 72 and 74 are n-to-1 connection processes. In this case, processes 71 and 72 cannot be processed in parallel. Processes 72 and 73 can be processed in parallel.

[0228] In the third embodiment, processes 71 and 73 are n-to-1 connection processes, and processes 72 and 74 are 1-to-n connection processes. In this case, the (i+1)th process 70 of process 71 and the i-th process of process 72 can be processed in parallel. Therefore, processes 70 and 71 can be processed in the time it takes for n+1 processes 70. After process 72 ends, process 73 is started. The (i+1)th process 70 of process 73 and the i-th process of process 74 can be processed in parallel.

[0229] As described above, in case 2, the processing time can be reduced more than in case 1, but in embodiment 3, the processing time can be reduced even more than in case 2.

[0230] The memory array 22 in Fig. 7A of the first embodiment or the memory array 22 in Fig. 26 of the second embodiment can be used for the memories 51 and 61 of the third embodiment. This makes it possible to reduce power consumption.

[0231] FIG. 44 is a block diagram showing an example of a memory in the third embodiment. As shown in FIG. 44, power switches PS1 to PSn are provided for each row of memories 51 and 61. Furthermore, a power switch control circuit 58 is provided to control the power switches PS1 to PSn to different states independently. This allows virtual power supply voltages VVDD1 to VVDDn to be set for each row. During n-to-1 connection processing and 1-to-n connection processing, the power switch control circuit 58 supplies a first power supply voltage to a row in which data to be processed is stored so that the data can be read. The power switch control circuit 58 sets the other rows to a ULV retention state when the memory array of the first embodiment is used for memories 51 and 61, and to a shutdown state when the memory array of the second embodiment is used.

[0232] For example, when the processing unit 52 performs the ith process in FIG. 41, or when the processing unit 62 performs the ith process in FIG. 42, the power switch control circuit 58 sets the virtual power supply voltage VVDDi supplied to the ith row of the memory 51 or 61 to a first power supply voltage that allows data to be read from the memory cell 10 or 10', and sets the virtual power supply voltage VVDD supplied to rows other than the ith row to a second power supply voltage that is lower than the first power supply voltage and allows the memory cell 10 or 10' to hold data, or shuts down the power supply voltage. When the memory array of the first embodiment is used for the memory 51 or 61, the second power supply voltage is a voltage that results in a ULV retention state. When the memory array of the second embodiment is used for the memory 51 or 61, the power supply voltage is shut down. The power switch control circuit 58 may supply the second power supply voltage to at least some of the rows other than the ith row, or shut down the power supply voltage.

[0233] The power consumption of the memories 51 and 61 can be suppressed by the control of the power switch control circuit 58. This can reduce the power consumption of the entire neural network. The control of the power switches PS1 to PSn is not limited to the above-mentioned control, and power may be supplied so that the rows adjacent to the row performing the n-to-1 connection process and the 1-to-n connection process can also be in a state in which data can be read out, taking into consideration the recovery time from the ULV retention state of the memories 51 and 61 until data can be read out, and the recovery time from the shutdown state until data can be read out in the memory array of the second embodiment. Each of the virtual power supply voltages VVDD1 to VVDDn may have multiple stages. In this case, power switches corresponding to the number of virtual power supply voltages are provided. In FIG. 44, a power switch is provided for each row, but a power switch may be provided for each of multiple rows. Although the virtual power supply method has been described as an example, a virtual ground method may also be used.

[0234] In FIG. 44, an example was described in which power consumption is reduced by controlling the power switches PS1 to PSn in both the n-to-1 connection processing and the 1-to-n connection processing of the neural network processing. In the fourth invention of the present application, power consumption may be reduced by controlling the power switches PS1 to PSn in at least one of the n-to-1 connection processing and the 1-to-n connection processing. In addition, in a processing device having an inference device trained by deep learning in which the n-to-1 connection processing and the 1-to-n connection processing are repeated in multiple layers, power consumption can be reduced by controlling the power switches PS1 to PSn in at least one layer of either the n-to-1 connection processing or the 1-to-n connection processing. All of these are included in the embodiment of the fourth invention of the present application.

[0235] The power consumption of the BNN device was simulated for the case where the 6T cell of Comparative Example 3 and the ULVR-SRAM cell of Example 1 were used for the memory cells 10 and 10' in the memories 51 and 61. When the memory cells 10 and 10' are 6T cells, the power consumption of the memory can be reduced by 50% to 60% when the power supply voltage is set to 70% of the normal state and the sleep state is set. When the memory cells 10 and 10' are ULVR-SRAM cells of Example 1, the power consumption of the memory can be reduced by 90% to 95% compared to the normal state of the 6T cell. In this way, the power consumption of the BNN device can be reduced by using the ULVR-SRAM cell of Example 1 or the NV-SRAM cell of Example 2 for the memory cells 10 and 10'. Also, the ULVR-SRAM cell described in Patent Document 1 or the NV-SRAM cell described in Patent Document 2 may be used for the memory cells 10 and 10'. This allows the standby power to be reduced.

[0236] According to the third embodiment, as shown in step S14 of FIG. 41, the processing unit 52 (first processing unit) performs weighting on a plurality of first data corresponding to a plurality of first nodes x1 to xn in the X layer (first layer) using a plurality of first weights w1i to wni, and then performs addition as shown in step S18, thereby calculating data of one second node yi among a plurality of second data corresponding to a plurality of second nodes y1 to yn in the Y layer (second layer) as shown in steps S16, S18, and S20. The processing unit 52 performs this processing for the plurality of second nodes y1 to yn to calculate a plurality of second data. As shown in step S32 of FIG. 42, the processing unit 62 (second processing unit) performs a processing for a plurality of second nodes y1 to yn to calculate a portion of each of a plurality of third data corresponding to a third node z1 to zn in the Z layer (third layer) by weighting data of one second node yi among a plurality of second nodes y1 to yn using a plurality of second weights w′i1 to w′in. As in steps S36 and S44, the processing unit 62 calculates data of the multiple third nodes z1 to zn by adding a part of the data of the multiple third nodes z1 to zn for the multiple second nodes y1 to yn for each of the multiple third nodes z1 to zn. Then, the processing unit 52 processes another second node yi+1 of the multiple second data in parallel with the processing of one second node yi of the multiple second data performed by the processing unit 62. This makes it possible to reduce the processing time of the processing device as shown in FIG.

[0237] The data of nodes x1 to xn, y1 to yn and z1 to zn, and the weights w11 to wnn and weights w'11 to w'nn are each 1 bit. This makes it possible to process the BNN. In the BNN, the processing unit 52 performs weighting by performing an XNOR operation on the data of the multiple first nodes x1 to xn and the multiple first weights w1i to wni, and the processing unit 62 performs weighting by performing an XNOR operation on the data of the second node yi and the multiple second weights w'i1 to w'in. This makes it possible to perform weighting in the BNN.

[0238] [Modification 1 of Example 3] Fig. 45 is a block diagram of a BNN device in a first modified example of the third embodiment. As shown in Fig. 45, in the first modified example of the third embodiment, in a processing unit 52, XNOR circuits 53a and 53b, counters 54a and 54b, adders 55a and 55b, evaluation units 56a and 56b, and output units 57a and 57b are provided for each of a plurality of rows of the memory 51. The processing unit 52 processes processes corresponding to a plurality of rows of the memory 51 in parallel. In a processing unit 62, XNOR circuits 63a and 63b are provided for each of a plurality of rows of the memory 61. The processing unit 62 processes processes corresponding to a plurality of rows of the memory 61 in parallel.

[0239] FIG. 46 is a diagram showing an example of a memory in the first modified example of the third embodiment. In FIG. 46, peripheral circuits other than the sense amplifiers 44a and 44b are omitted. As shown in FIG. 46, the memories 51 and 61 have memory cells 10a and 10b arranged in a matrix. Bit lines BL1 and BLB1 and bit lines BL2 and BLB2 extend in the column direction. Of the memory cells 10a and 10b in the same column, the memory nodes Q1 and Q2 (see FIG. 1, FIG. 22, etc.) of the memory cell 10a are connected to the bit lines BL1 and BLB1, respectively, and are not connected to the bit lines BL2 and BLB2. The memory nodes Q1 and Q2 of the memory cell 10b are connected to the bit lines BL2 and BLB2, respectively, and are not connected to the bit lines BL1 and BLB1.

[0240] A plurality of sense amplifiers 44a and 44b are provided in one column. Bit lines BL1 and BLB1 are connected to the sense amplifier 44a, and bit lines BL2 and BLB2 are connected to the sense amplifier 44b. The sense amplifiers 44a and 44b read data from the memory cells 10a and 10b selected by the word line WL, respectively. The sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively. That is, when performing one process to be processed in parallel, the processing units 52 and 62 obtain weights from the memories 51 and 61 via BL1 and BLB1, and when performing another process to be processed in parallel, they obtain weights from the memories 51 and 61 via the bit lines BL2 and BLB2. This allows the weight columns of multiple rows to be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b) without using a multiport cell described later in the second modification of the third embodiment. The memory cell 10 may be a 6T cell such as that in Comparative Example 3, or may be the memory cell 10 in Examples 1 and 2 and their modifications.

[0241] [Modification 2 of Example 3] The second modification of the third embodiment is an example in which multiport cells are used for the memories 51 and 61. As the multiport cells, a 2R1W type having one write port and two read ports and a 2RW type having two write ports and two read ports will be described.

[0242] Fig. 47 is a circuit diagram showing an example of a 2R1W NV-SRAM memory cell in the second modification of the third embodiment. As shown in Fig. 47, WWL, RWL1, and RWL2 are provided as word lines. WWL is a write word line, and RWL1 and RWL2 are read word lines. Control lines CTRL1 to CTRL3 are provided.

[0243] The gate of FETM3 is connected to WWL, one of its source and drain is connected to storage node Q1, and the other of its source and drain is connected to control line CTRL1. The gate of FETM41 is connected to RWL1, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2. The gate of FETM42 is connected to RWL2, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL3. The other configurations are the same as those of the second embodiment, and therefore description thereof will be omitted.

[0244] Table 6 shows the voltages on each line in each state and operation. [Table 6]

[0245] In Table 6, the voltages of the word lines WWL, RWL1 and RWL2 in the write operation, read operation 1 and read operation 2 are the voltages in the accessed memory cell 10. The voltages of the word lines WWL, RWL1 and RWL2 in the memory cells 10 that are not accessed are 1.2V.

[0246] As shown in Table 6, in the hold state, the voltages of WWL, RWL1, RWL2, and CTRL1 to CTRL3 are 1.2V (high level), and FETs M3, M41, and M42 are off. During a write operation, the voltage of WWL of the cell 10 to be written to is set to 0V (low level). This turns on the FET M3 of the cell to be written to. The voltages of the word lines RWL1 and RWL2 are 1.2V, and FETs M41 and M42 are off. By setting the voltage of the control line CTRL1 to 1.2V or 0V, the storage node Q1 becomes H or L. This causes data to be written to the cell 10.

[0247] During read operation 1, the voltage of RWL1 of the cell 10 to be read is set to 0V. This turns on FET M41 of the cell 10 to be read. The voltage of RWL2 is 1.2V and FET M42 is off. The voltage of WWL is 0.7V, which turns on FET M3 slightly. By setting the voltage of control line CTRL2 to floating (FL) from 1.2V, data at storage node Q2 is read from control line CTRL2. The voltages during read operation 2 are the same as those in read operation 1. The other operations are the same as those in embodiment 2.

[0248] Fig. 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 48, WWL, RWL1, and RWL2 are provided as word lines. Control lines CTRL1 to CTRL3 are provided.

[0249] The gate of FETm4 is connected to WWL, one of its source and drain is connected to storage node Q1, and the other of its source and drain is connected to control line CTRL1. The gate of FETm41 is connected to RWL1, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2. The gate of FETm42 is connected to RWL2, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL3. The other configurations are the same as those in the first embodiment, and description thereof will be omitted.

[0250] Table 7 shows the voltage on each line in each state and operation. [Table 7]

[0251] As shown in Table 7, in the hold state, the voltages of the word lines WWL, RWL1, and RWL2 are 1.1V, the voltages of CTRL1 to CTRL3 are 1.2V, and FETs m4, m41, and m42 are off. In a write operation, the voltage of WWL of the memory cell 10 to be written to is set to 0.3V. This turns on FET m3 of the memory cell 10 to be written to. The voltages of the word lines RWL1 and RWL2 are 1.1V, and FETs m41 and m42 are off. By setting the voltage of the control line CTRL1 to 1.2V or 0V, the storage node Q1 becomes H or L. This causes data to be written to the memory cell 10.

[0252] During read operation 1, the voltage of RWL1 of the memory cell 10 to be read is set to 0.3V. This turns on FETm41 of the memory cell 10 to be read. The voltage of RWL2 is 1.1V and FETm42 is off. The voltage of WWL is 0.6V and FETm4 is slightly turned on. The voltage of control line CTRL2 is made floating (FL) from 1.2V, so that data of storage node Q2 is read from control line CTRL2. Read operation 2 is the same as read operation 1. The voltages of word lines WWL, RWL1 and RWL2 of memory cells 10 not to be accessed are 1.1V. The other operations are the same as in Example 1.

[0253] For the 2R1W type NV-SRAM cell and the 2R1W type ULVR-SRAM cell, we simulated SNM versus the voltage VWWL of the word line WWL during read operations 1 and 2. For the 2R1W type NV-SRAM memory cell, we set WLP=105nm, WDRV=150nm, and the voltage VRWL of the word lines RWL1 and RWL2=0V. For the 2R1W type ULVR-SRAM memory cell, we set VVDD=1.2V, BI mode, WLP=110nm, and WFB=230nm.

[0254] FIG. 49(a) is a diagram showing SNM versus VWWL of a 2R1W NV-SRAM memory cell in a read operation of the second modified example of the third embodiment, and FIG. 49(b) is a diagram showing SNM versus VWWL of a 2R1W ULVR-SRAM memory cell in a read operation. As shown in FIG. 49(a) and FIG. 49(b), when the voltage VWWL of the word line WWL is increased, SNM is reduced. In a read operation, the word line WWL for writing is not selected, and FETM3 and FETm4 are turned off. However, when FETM3 and FETm4 are completely turned off, SNM is reduced. Therefore, the voltage VWWL (e.g., 0.6V) of the word line WWL for writing in read operations 1 and 2 is made higher than the voltage VWWL (e.g., 0.3V) in the write operation. Furthermore, the voltage VWWL (e.g., 0.6V) in the read operation 1 is made lower than the voltage (e.g., 1.2V) of the word line RWL1 for read operation 2. The same applies to the read operation 2. This makes it possible to increase SNM.

[0255] Fig. 50 is a circuit diagram showing an example of a 2RW NV-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 50, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2, and CTRL2' are provided as control lines.

[0256] The gate of FETM31 (third FET) is connected to WL1 (first word line), one of the source and drain is connected to the storage node Q1 (first storage node), and the other of the source and drain is connected to the control line CTRL1 (first control line). The gate of FETM32 (fifth FET) is connected to WL2 (second word line), one of the source and drain is connected to the storage node Q1, and the other of the source and drain is connected to the control line CTRL1' (fourth control line). The gate of FETM41 (fourth FET) is connected to WL1, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2 (second control line). The gate of FETM42 (sixth FET) is connected to WL2, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2' (fifth control line). The other configurations are the same as those in the second embodiment, and therefore will not be described.

[0257] Table 8 shows the voltages on each line in each state and operation. [Table 8]

[0258] As shown in Table 8, in the hold state, the voltages of the word lines WL1, WL2, and the control lines CTRL1, CTRL1', CTRL2, and CTRL2' are 1.2V (high level), and FETs M31, M32, M41, and M42 are off. In the write operation 1 and read operation 1, WL1, CTRL1, and CTRL2 are used to write and read data via FETs M31 and M41. WL2, CTRL1', and CTRL2' are set to 1.2V, and FETs M32 and M42 are turned off. Write operation 2 and read operation 2 are the same as write operation 1 and read operation 1. The voltages of the word lines WL1 and WL2 of the memory cells 10 that are not accessed are 1.2V. Other operations are the same as those in the second embodiment.

[0259] Fig. 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 51, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2, and CTRL2' are provided as control lines.

[0260] The gate of FETm41 (third FET, fourth FET) is connected to WL1 (first word line), one of the source and drain is connected to storage nodes Q1 and Q2, and the other of the source and drain is connected to control lines CTRL1 (first control line) and CTRL2 (second control line). The gate of FETm42 (fifth FET, sixth FET) is connected to WL2 (second word line), one of the source and drain is connected to storage nodes Q1 and Q2, and the other of the source and drain is connected to control lines CTRL1' (third control line) and CTRL2' (fourth control line). The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0261] Table 9 shows the voltage on each line in each state and operation. [Table 9]

[0262] As shown in Table 9, in the hold state, the voltages of WL1 and WL2 are 1.1V, the voltages of CTRL1, 2, 1' and 2' are 1.2V, and FETm41 and m42 are off. In write operation 1 and read operation 1, WL1, CTRL1 and CTRL2 are used to write and read data via FETm41. The voltage of WL2 is set to 1.1V, the voltages of CTRL1' and CTRL2' are set to 1.2V, and FETm42 is turned off. Write operation 2 and read operation 2 are the same as write operation 1 and read operation 1. The voltages of word lines WL1 and WL2 of memory cells 10 that are not accessed are 1.1V. Other operations are the same as those in the second embodiment.

[0263] FIG. 52 is a diagram showing an example of a 2R1W type memory in the second modification of the third embodiment. In FIG. 52, peripheral circuits other than the sense amplifiers 44a and 44b are omitted. As shown in FIG. 52, the memories 51 and 61 have memory cells 10 arranged in a matrix. The memory cells 10 are 2R1W type NV-SRAM cells or 2R1W type ULVR-SRAM cells. The control line CTRL2 is connected to the sense amplifier 44a, and the control line CTRL3 is connected to the sense amplifier 44b. The sense amplifier 44a reads data from the memory cell 10 selected by the word line RWL1, and the sense amplifier 44b reads data from the memory cell 10 selected by the word line RWL2. The sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively. This allows weighted columns of multiple rows to be output in parallel to the XNOR circuits 53a and 53b (or 63a and 63b) from the memory 51 or 61. The memory cell 10 may be a 6T cell.

[0264] FIG. 53 is a diagram showing an example of a 2RW type memory in the second modification of the third embodiment. In FIG. 53, peripheral circuits other than the sense amplifiers 44a and 44b are omitted. As shown in FIG. 53, the memory cell 10 is a 2RW type NV-SRAM cell or a 2RW type ULVR-SRAM cell. The control lines CTRL1 and CTRL2 are connected to the sense amplifier 44a, and the control lines CTRL1' and CTRL2' are connected to the sense amplifier 44b. The sense amplifier 44a reads data from the memory cell 10 selected by the word line WL1, and the sense amplifier 44b reads data from the memory cell 10 selected by the word line WL2. The other configurations are the same as those in FIG. 52. The sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively. This allows the weighted columns of multiple rows to be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b). The memory cell 10 may be a 6T cell.

[0265] FIG. 54 is a diagram showing processing over time in a modification of the third embodiment. Case 1, case 2, and embodiment 3 are the same as FIG. 43, and description thereof will be omitted. In modifications 1 and 2 of the third embodiment, processing for two rows of memories 51 and 61 can be performed in parallel. This allows processing 71 to be processed in parallel with processing 71a and 71b. Similarly, processing 72a and 72b can be processed in parallel, processing 73a and 73b can be processed in parallel, and processing 74a and 74b can be processed in parallel. Therefore, the processing time can be shortened compared to the third embodiment.

[0266] In the third modification of the third embodiment, the processes for four rows of memories 51 and 61 are performed in parallel. This allows the process 71 to be processed in parallel with processes 71a to 71d. Similarly, the processes 72a to 72d can be processed in parallel, the processes 73a to 73d can be processed in parallel, and the processes 74a to 74d can be processed in parallel. This allows the processing time to be further reduced compared to the first and second modifications of the third embodiment.

[0267] The processing time was simulated for Example 3 and its modified examples. The number of nodes in the input X layer and each of the other layers was set to n, and the number of layers excluding the X layer was set to m (m is an even number). Figures 55(a) to 55(c) are diagrams showing the normalized processing time T / t0 with respect to the number of layers m. t0 is a value for normalization. Figures 55(a) to 55(c) are for n=256, n=512, and n=1024, respectively. As shown in Figures 55(a) to 55(c), regardless of n, Example 3 has a shorter processing time than Case 1 and Case 2. In Modifications 1 and 2 of Example 3, the processing time is about 1 / 2 of Example 3. In Modification 3 of Example 3, the processing time is about 1 / 4 of Example 3.

[0268] According to the first to third modifications of the third embodiment, the processor 52 processes in parallel at least two of the second nodes y1 to yn, and the processor 62 processes in parallel at least two of the second nodes y1 to yn. This can reduce the processing time as shown in FIG. 54.

[0269] As shown in Figures 47, 48, 50 and 51, each of the memory cells 10 has a pair of complementary storage nodes Q1 and Q2, and at least one of the pair of storage nodes Q1 and Q2 is connected to control lines CTRL2 (first bit line) and CTRL3 or CTRL2' (second bit line) extending in parallel in the column direction. When performing one of the parallel processing of second data, the processing unit 52 obtains a plurality of first weights from the memory 51 via the first bit line, and when performing another processing, obtains a plurality of first weights from the memory 51 via the second bit line. This allows the processing unit 52 to execute two processes in parallel.

[0270] 47, 48, 50 and 51, when performing one of the parallel processes of the second data, the processing unit 62 acquires a plurality of first weights from the memory 61 via the control line CTRL2 (third bit line), and when performing another process, acquires a plurality of first weights from the memory 61 via the control line CTRL3 or CTRL2' (fourth bit line). This allows the processing unit 62 to execute two processes in parallel.

[0271] 47, when memory cells 10 and 10' are 2R1W type NV-SRAM memory cells, the other of the source and drain of FET M3 is connected to a first control line CTRL1, and the gate is connected to a first word line WWL. The other of the source and drain of FET M41 is connected to a second control line CTRL2, and the gate is connected to a second word line RWL1. One of the source and drain of FET M42 (fifth FET) is connected to a storage node Q2, the other of the source and drain is connected to a fourth control line CTRL3, and the gate is connected to a third word line RWL2.

[0272] When the memory cells 10 and 10' are 2R1W type ULVR-SRAM memory cells, as shown in Fig. 48, in the inverter circuit 16 (second inverter circuit), the other of the source and drain of FETm4 is connected to the first control line CTRL1, and the gate is connected to the first word line WWL. In the inverter circuit 14, the other of the source and drain of FETm41 is connected to the second control line CTRL2, and the gate is connected to the second word line RWL1. One of the source and drain of FETm42 is connected to the second storage node Q2, the other of the source and the drain is connected to the third control line CTRL3, and the gate is connected to the third word line RWL2.

[0273] The control circuit 28 uses the word line WWL to turn on FETM3 in FIG. 47 or FETm4 of the inverter circuit 16 in FIG. 48, and writes data to the bistable circuit 12 using the control line CTRL1. The control circuit 28 uses the word line RWL1 to turn on FETM41 or FETm41, uses the control line CTRL2 to read data from the bistable circuit 12, uses the word line RWL2 to turn on FETM42 or FETm42, and uses the control line CTRL3 to read data from the bistable circuit 12. This allows data to be written to the bistable circuit 12 using one control line CTRL1 in a 2R1W type NV-SRAM cell and a 2R1W type ULVR-SRAM cell. Also, the control lines CTRL2 and CTRL3 for reading data from the bistable circuit 12 can be selected using the word lines RWL1 and RWL2.

[0274] As shown in Tables 6 and 7, when FETM1, M2, FETm1 and m2 are N-type channels, the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 higher than the voltage of the word line WWL when writing data to the bistable circuit 12, and lower than the higher of the voltages of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12. This can improve the SNM when reading. The voltage of the word line WWL during a read operation is preferably (VDD-VGND) / 10 or more higher than the voltage of the word line WWL during a write operation, and is preferably (VDD-VGND) / 10 or more lower than the higher of the voltages of the word lines RWL1 and RWL2 during a read operation.

[0275] When FETs M1a, M2a, FETs m1a and m2a are P-type channels, the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 lower than the voltage of the word line WWL when writing data to the bistable circuit 12 and higher than the lower voltage of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12. This improves SNM during reading. The voltage of the word line WWL during a read operation is preferably lower than the voltage of the word line WWL during a write operation by (VDD-VGND) / 10 or more, and is preferably higher than the higher voltage of the word lines RWL1 and RWL2 during a read operation by (VDD-VGND) / 10 or more.

[0276] [Modification 4 of Example 3] FIG. 56 is a circuit diagram of an NV-SRAM memory cell according to the fourth modification of the third embodiment. As shown in FIG. 56, cells 78 and 78' include memory cells 10 and 10' of the second embodiment and an XNOR circuit 79. The XNOR circuit 79 includes FETs M7 to M9. In the FET M7, one end of the source and drain is connected to a control line CTRL1, the other end of the source and drain is connected to a node N5, and the gate is connected to a storage node Q2. In the FET M8, one end of the source and drain is connected to a control line CTRL2, the other end of the source and drain is connected to a node N5, and the gate is connected to a storage node Q1. In the FET M9, one end of the source and drain is connected to a ground line 15b, the other end of the source and drain is connected to an output line SAIN, and the gate is connected to a node N5.

[0277] In the hold state of the memory cell 10, the XNOR circuit 79 outputs the XNOR of the memory node Q1 and the control line CTRL1 (which also corresponds to the XNOR of the memory node Q2 and the control line CTRL2) to the output line SAIN. One bit of operation data (for example, H is 1.2V, L is 0V) is input to the control line CTRL1, and the complementary data of the operation data is input to the control line CTRL2. The XNOR of the operation data and the memory node Q1 is output to the output line SAIN.

[0278] 57 is a circuit diagram of a ULVR-SRAM memory cell according to the fourth modification of the third embodiment. As shown in Fig. 57, cells 78 and 78' include memory cells 10 and 10' of the first embodiment and an XNOR circuit 79. The circuit configuration and function of the XNOR circuit 79 are the same as those in Fig. 56.

[0279] FIG. 58 is a block diagram of a BNN device in the fourth modified example of the third embodiment. As shown in FIG. 58, the memory cells in the memories 51 and 61 are the cells 78 and 78' in FIG. 56 or FIG. 57. The processing units 52 and 62 do not include an XNOR circuit. When XNOR is output from the memory 51, the data of the nodes x1 to xn of the input unit 48 and their complementary data are input to the control lines CTRL1 and CTRL2 of the memory 51, respectively. The sense amplifier of the memory 51 reads data from the output line SAIN of each column and outputs it to the counter 54. When XNOR is output from the memory 61, the data of the node yi of the output unit 57 and its complementary data are input to the control lines CTRL1 and CTRL2 of the memory 61. The sense amplifier of the memory 61 reads data from the output line SAIN of each column and outputs it to the accumulator 64.

[0280] As in the fourth modification of the third embodiment, the XNOR circuit 79 may be provided in each of the cells 78 and 78'. In the first to third modifications of the third embodiment, the XNOR circuit 79 may be provided in each of the cells 78.

[0281] 56 and 57, memories 51 and 61 include XNOR circuits 79 (first XNOR circuit and second XNOR circuit) corresponding to memory cells 10 and 10'. This eliminates the need to provide XNOR circuits 53 and 63 in processing units 52 and 62.

[0282] [Modification 5 of Example 3] 59(a) and 59(b) are block diagrams of the power switch and its vicinity in Comparative Example 4 and Modification 5 of Example 3, respectively. As shown in FIG. 59(a), in Comparative Example 4, a plurality of 6T cells 10 are arranged in one row of a memory array. The number of cells 10 in one row is, for example, 512. The power supply lines 15a (virtual power supply lines) of the memory cells 10 in one row are commonly connected. In the power switch 30, one FETPS2 is provided between the power supply 15cL of the voltage VDDL for the sleep state and the power supply line 15a. Note that the power supply 15cH of the voltage VDDH and the power switch FETPS1 are omitted from the illustration. When the FETPS2 is turned on, the virtual power supply voltage VVDD of the power supply line 15a becomes VDDL.

[0283] As shown in Fig. 59(b), in the fifth modification of the third embodiment, the power switch 30 includes a FETPS2 for each memory cell 10, and each FETPS2 is connected between a power supply 15cL of a voltage VDDL for the sleep state and a power supply line 15a. Note that the power supply 15cH of the voltage VDDH and the power switch FETPS1 are not shown. When the FETPS2 is turned on, the virtual power supply voltage VVDD of the power supply line 15a becomes VDDL.

[0284] FIG. 60 is a circuit diagram of a 6T cell in the fifth modification of the third embodiment. As shown in FIG. 60, in the memory cells 10 and 10', the bistable circuit 12 includes an inverter circuit 14 having a PFETM1' and an NFETM1, and an inverter circuit 16 having a PFETM2' and an NFETM2. The inverter circuits 14 and 16 are connected in a loop. NFETs M3 and M4 for pass transistors are provided. The power switch 30 includes a FETPS1 that connects a power supply 15cH that supplies a voltage VDDH to the power supply line 15a, and a FETPS2 that connects a power supply 15cL that supplies a voltage VDDL to the power supply line 15a. The voltage VDDH is a power supply voltage (second power supply voltage) during a read or write operation, and is, for example, 1.2V. The voltage VDDL is a power supply voltage (first power supply voltage) during a sleep state in which the bistable circuit 12 holds data but does not perform a write or read operation, and is, for example, 1 / 3 to 1 / 4 of VDDH. Each of the FETPS1 (second power switch) and the FETPS2 (first power switch) is connected to the virtual power line 15a of one or several (e.g., 10 or less) memory cells 10. The FETPS1 may be connected to more cells than the FETPS2. For example, one FETPS1 may be connected to 64, 128, or 256 memory cells 10.

[0285] SNM and standby power were simulated for a case in which FETPS2 is provided in common to 512 memory cells 10 as Comparative Example 4, and a case in which FETPS2 is provided for each memory cell 10 as Modification 5 of Example 3. Figures 61(a) and 61(b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively.

[0286] As shown in FIG. 61(a), in Comparative Example 4, when VDDL is 1.2V, SNM is 100mV to 180mV. When VDDL is lowered, SNM becomes smaller. The minimum VDDL at which all SNMs are 80mV or more is 0.8V. For this reason, VDDL in the sleep state is set to 0.8V. When VDDL is set to 0.8V, the standby power is approximately 1.6nW.

[0287] As shown in FIG. 61(b), in the fifth modification of the third embodiment, when VDDL is 1.2V, SNM is 300mV or more. Lowering VDDL reduces SNM. The minimum VDDL at which all SNMs are 80mV or more is 0.35V. For this reason, VDDL in the sleep state is set to 0.35V. The standby power when VDDL is 0.35V is approximately 0.5nW. In this way, in the fifth modification of the third embodiment in FIG. 59(b), standby power can be reduced compared to the fourth comparative example in FIG. 59(a).

[0288] In this way, in variant example 5 of embodiment 3, SNM can be increased even if VDDL is lowered. This is because, when multiple memory cells 10 are connected to FETPS2, the virtual power supply voltage VVDD becomes lower than VDDL, resulting in degradation of SNM, but when only one memory cell 10 (or a few) are connected, the virtual power supply voltage VVDD can be maintained at VDDL.

[0289] According to the fifth modification of the third embodiment, even if 6T memory cells are used as the memory cells 10 and 10', the power supply voltage for retention can be reduced. Therefore, the area of ​​the memory cells can be reduced and power consumption can be suppressed. Although the virtual power supply method has been described as an example, the virtual ground method may also be used. The fifth modification of the third embodiment may be applied to the BNN device of the third embodiment and its modifications 1 to 4. The third embodiment and its modifications are also applicable to neural network devices other than the BNN device.

[0290] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0291] 10 Memory Cells 12 Bistable circuit 14, 16 Inverter circuit 22 Memory Array 28 Control Circuit 30 Power Switch 32, 32a, 32b Selection circuit 51, 61 Memory 52, 62 Processing section 79 XNOR circuit

Claims

1. a first FET having a first conductivity type channel, the first FET having a source connected to a power supply line, a drain connected to a first storage node, and a gate connected to a second storage node; a second FET having a channel of the first conductivity type, the second FET having a source connected to the power supply line, a drain connected to the second storage node, and a gate connected to the first storage node; a third FET having a channel of a second conductivity type opposite to the first conductivity type, the third FET having one of a source and a drain connected to the first storage node, the other of the source and the drain connected to a first control line, and a gate connected to a word line; a fourth FET having a channel of the second conductivity type, one of a source and a drain connected to the second storage node, the other of the source and the drain connected to a second control line, and a gate connected to the word line; A bistable circuit comprising: a first switch having one end connected to the first storage node; a second switch having one end connected to the second storage node; a first non-volatile memory element having one end connected to the other end of the first switch and the other end connected to a third control line; a second non-volatile memory element having one end connected to the other end of the second switch and the other end connected to the third control line; a control circuit which turns off the first switch and the second switch during a write operation for volatilely writing data to the bistable circuit and a read operation for reading data from the bistable circuit, and turns on the first switch and the second switch during a store operation for nonvolatilely storing data from the bistable circuit to the first nonvolatile memory element and the second nonvolatile memory element and a restore operation for restoring data from the first nonvolatile memory element and the second nonvolatile memory element to the bistable circuit; Equipped with When executing the store operation, the control circuit executes a first store operation in which the word line is set to a first voltage, the first control line and the second control line are set to a second voltage, and the third control line is set to a third voltage, and a second store operation in which the word line is set to a fourth voltage, the first control line and the second control line are set to a fifth voltage, and the third control line is set to a sixth voltage; when the first conductivity type is N-type, the first voltage is lower than the fourth voltage, the second voltage and the fifth voltage are higher than the voltage of the power supply line, and the third voltage is lower than the sixth voltage; A memory circuit in which, when the first conductivity type is P-type, the first voltage is higher than the fourth voltage, the second voltage and the fifth voltage are lower than the voltage of the power supply line, and the third voltage is higher than the sixth voltage.

2. when the first conductivity type is N-type, the fourth voltage is lower than the fifth voltage; The memory circuit according to claim 1 , wherein when the first conductivity type is P-type, the fourth voltage is higher than the fifth voltage.

3. 3. The memory circuit according to claim 1, wherein the control circuit, when executing the restore operation, sets the voltage of the word line higher than the lower voltage of the first memory node and the second memory node during the write operation and lower than the higher voltage of the first memory node and the second memory node.

4. a first FET having a first conductivity type channel, the first FET having a source connected to a power supply line, a drain connected to a first storage node, and a gate connected to a second storage node; a second FET having a channel of the first conductivity type, the second FET having a source connected to the power supply line, a drain connected to the second storage node, and a gate connected to the first storage node; a third FET having a channel of a second conductivity type opposite to the first conductivity type, the third FET having one of a source and a drain connected to the first storage node, the other of the source and the drain connected to a first control line, and a gate connected to a first word line; a fourth FET having a channel of the second conductivity type, one of a source and a drain connected to the second storage node, the other of the source and the drain connected to a second control line, and a gate connected to a second word line; a fifth FET having a channel of the second conductivity type, one of a source and a drain connected to the second storage node, the other of the source and the drain connected to a fourth control line, and a gate connected to a third word line; A bistable circuit comprising: a first switch having one end connected to the first storage node; a second switch having one end connected to the second storage node; a first non-volatile memory element having one end connected to the other end of the first switch and the other end connected to a third control line; a second non-volatile memory element having one end connected to the other end of the second switch and the other end connected to the third control line; a control circuit which turns off the first switch and the second switch during a write operation for volatilely writing data to the bistable circuit and a read operation for reading data from the bistable circuit, and turns on the first switch and the second switch during a store operation for nonvolatilely storing data from the bistable circuit to the first nonvolatile memory element and the second nonvolatile memory element and a restore operation for restoring data from the first nonvolatile memory element and the second nonvolatile memory element to the bistable circuit; Equipped with The control circuit is a memory circuit that turns on the third FET using the first word line, writes data to the bistable circuit using the first control line, turns on the fourth FET using the second word line, reads data from the bistable circuit using the second control line, turns on the fifth FET using the third word line, and reads data from the bistable circuit using the fourth control line.

5. when the first conductivity type is N-type, the control circuit sets a voltage of the first word line when reading data from the bistable circuit higher than a voltage of the first word line when writing data to the bistable circuit and sets a voltage of the first word line lower than a higher voltage of a voltage of the second word line and a voltage of the third word line when reading data from the bistable circuit; 5. The memory circuit of claim 4, wherein, when the first conductivity type is P-type, the voltage of the first word line when reading data from the bistable circuit is lower than the voltage of the first word line when writing data to the bistable circuit, and higher than the lower of the voltage of the second word line and the voltage of the third word line when reading data from the bistable circuit.

Images