Power Conversion Equipment

Abstract

To restrict the output frequency change rate of a VSG model in a power converter in which virtual synchronous generator control is performed by the VSG model.SOLUTION: A VSG model is provided with a change rate limit processing unit 30 including a subtractor 31 that subtracts output of a governor item from synchronous control output Pm_sync to determine the amount of change in synchronous control output, a limiter 32 that limits the output of the subtractor 31 within a range of a set frequency change rate limit value, and an adder 33 that adds the output of the governor item to the output of the limiter 32. The VSG model adds the output of the adder 33 and a mechanical input command Pm to each other with an adder 21, subtracts an electric output Pe from the added output with a subtractor 22, and adds, with an adder 25, the output of a buffer 26 to an integrated output obtained by integrating the deviation between the output of the subtractor 22 and the output of the governor item with an integrator 24, thereby determining a frequency deviation Δωr. The governor item is obtained by multiplying the previous frequency deviation stored in the buffer 26 by a governor gain Kgov of a multiplier 27.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a control method for a power conversion device equipped with virtual synchronous generator control. [Background technology]

[0002] Conventionally, for example, Patent Document 1 has proposed a synchronization control method in which, when synchronizing a generator with a power system, the phase of the generator is synchronized with the power system by controlling the generator rotation speed by feeding back the frequency and phase of the power system to be synchronized.

[0003] On the other hand, prior art examples of power conversion devices that perform virtual synchronous generator model (VSG (Virtual Synchronous Generators) model) control simulating the oscillation equation of a synchronous generator include Patent Documents 2 and 3. The power conversion device operates like a generator (virtual generator) that is driven at a frequency determined by the oscillation equation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-284246 A [Patent Document 2] JP 2017-127141 A [Patent Document 3] Patent No. 6386718 Summary of the Invention [Problem to be solved by the invention]

[0005] The system configuration assumed in this invention is shown in Fig. 1, and the VSG model inside the power converter is shown in Fig. 2. The system configuration assumes synchronous input to the power system as in Patent Document 1, but there is a power converter that performs virtual synchronous generator control instead of a generator, and distributed power sources are connected to the system.

[0006] In FIG. 1, a distributed power source 3 and a local load 4 are connected to the output side of a power supply system 1 via circuit breakers 2a, 2b, and 2c.

[0007] A power converter 5 includes a semiconductor switching element and converts DC power to AC power by virtual synchronous generator control. The AC output side of the power converter 5 is connected to a common connection point 8 of the circuit breaker 2a and the circuit breakers 2b and 2c via an LC filter unit 6, a transformer 7, and a circuit breaker 2d.

[0008] Reference numeral 9 denotes a synchronous control unit that performs synchronous control by feeding back a signal (Vsys) that is a system voltage of the power supply system 1 detected by an instrument transformer 10.

[0009] Reference numeral 11 denotes an output power calculation unit which detects the output current of LC filter unit 6 using a current transformer 12, and obtains a current value obtained by coordinate conversion of the detected current value using a uvw / dq coordinate converter 13, and which detects the output voltage of LC filter unit 6 using an instrument transformer 14, and obtains a voltage value obtained by coordinate conversion of the detected voltage value using a uvw / dq coordinate converter 15, and calculates the output power of power converter 5 based on the detected current value and outputs the calculated output power as electrical output Pe.

[0010] Reference numeral 16 denotes a voltage controller (AVR) that controls the voltage value output from the coordinate converter 15 to become the output voltage command value |Vac|* of the power converter 5.

[0011] Reference numeral 17 denotes a VSG model which receives as inputs the machine input command Pm, the output Pm_sync of the synchronization control unit 9, and the output Pe of the output power calculation unit 11, and outputs an output frequency ωr using the configuration of FIG. 2 which will be described later.

[0012] An integrator 18 integrates the output frequency ωr output from the VSG model 17 and outputs a phase θr.

[0013] The output voltage of the voltage controller 16 is coordinate-converted by a dq / uvw coordinate converter 19 to obtain a uvw-phase voltage command.

[0014] Reference numeral 20 denotes a PWM modulator that generates a gate signal for controlling a semiconductor switching element of the power converter 5 by comparing the uvw-phase voltage commands with a carrier signal.

[0015] The uvw / dq coordinate converters 13 and 15 and the dq / uvw coordinate converter 19 each perform coordinate conversion using the phase θr output from the integrator 18.

[0016] In FIG. 2 showing the configuration of the VSG model 17, the synchronous control output Pm_sync (output of the synchronous control unit 9 in FIG. 1) and the mechanical input command Pm are added by an adder 21, and the sum output is subtracted by a subtractor 22 from the electrical output Pe (output of the output power calculation unit 11 in FIG. 1).

[0017] A subtractor 23 subtracts an output of a governor term (which will be described later) (an output obtained by multiplying the previous value of the frequency deviation component by a governor gain) from the sum output of the adder 22.

[0018] An integrator 24 integrates the output of the subtractor 23 by the calculation period Ts / the inertia constant M.

[0019] The output of the integrator 24 is added to the output of a buffer 26 (described later) in an adder 25 to obtain a frequency deviation Δωr.

[0020] The buffer 26 delays the frequency deviation Δωr by one calculation and outputs the previous value of the frequency deviation component.

[0021] Numeral 27 denotes a multiplier that multiplies the previous value of the frequency deviation component output from the buffer 26 by a governor gain Kgov, and the output of the multiplier 27 becomes the output of the governor term.

[0022] An adder 28 adds 1, which represents the rated frequency, to the frequency deviation Δωr output from the adder 25 and outputs an output frequency ωr.

[0023] Here, consider a case where the output frequency of the power converter 5 that performs virtual synchronous generator control is controlled by feedback control (synchronization control) of frequency and phase, and synchronization is input to the power supply system 1. The content of the synchronization control may be proportional control or proportional-integral control using the phase difference between the synchronization target and the VSG model as a deviation, or a combination of frequency offset and phase control as in Patent Document 1. The output Pm_sync of the synchronization control is added to the machine input command Pm of the VSG model 17 to control the output frequency.

[0024] At this time, depending on the design of the inertia constant M of the VSG model, the governor gain Kgov, and the synchronization control unit, the output frequency ωr of the VSG model 17 may suddenly change, increasing the rate of change of frequency (RoCoF), which may cause a distributed power source (3) such as a solar PCS connected to the power conversion device to erroneously detect islanding.

[0025] In a virtual synchronous generator, the inertia constant M and governor gain Kgov can be freely changed at any timing, so synchronous control is required that operates while keeping the frequency change rate below a certain level, regardless of the parameters.

[0026] The present invention is intended to solve the above-mentioned problems, and has an object to limit the rate of change of the output frequency of a VSG model in a power conversion device in which virtual synchronous generator control is performed by a VSG model. [Means for solving the problem]

[0027] In order to solve the above problem, the power conversion device according to claim 1 is A power conversion device that is connected to a common connection point between a power supply system and a distributed power supply so as to be interconnected with the distributed power supply and that performs virtual synchronous generator control using a VSG (Virtual Synchronous Generators) model, The VSG model is an adding / subtracting unit that subtracts an electric output obtained by detecting an output power of a power conversion device from an added output of a synchronous control output obtained by performing synchronous control by feeding back a signal that detects a voltage of the power supply system and a machine input command; an integral term that integrates a difference between an output of the adding / subtracting unit and a previous value of a frequency deviation component multiplied by a governor gain, using an inertia constant and a calculation period, to output a frequency deviation component; a governor term that multiplies a previous value of the frequency deviation component output from the integral term by a governor gain; an output frequency generating unit that adds a rated frequency component to the frequency deviation component to generate an output frequency; a change rate limiting processing unit in the adding / subtracting unit that applies a change rate limiting process to the synchronous control output before it is added to the machine input, the change rate limiting processing unit having a subtractor that subtracts the output of the governor term from the synchronous control output to obtain a change amount of the synchronous control output, a limiter that limits the change amount of the synchronous control output obtained by the subtractor to within a set frequency change rate limit value range, and an adder that adds the output of the governor term to the output of the limiter; The present invention is characterized in that it is provided with:

[0028] The power conversion device according to claim 2 comprises: A power conversion device that is connected to a common connection point between a power supply system and a distributed power supply so as to be interconnected with the distributed power supply and that performs virtual synchronous generator control using a VSG (Virtual Synchronous Generators) model, The VSG model is an adder / subtractor that adds a synchronous control output resulting from synchronous control performed by feeding back a signal that detects the voltage of the power supply system and a machine input command, and then subtracts an electrical output that detects the output power of a power conversion device from the added output; an integral term that integrates a difference between an output of the adding / subtracting unit and a previous value of a frequency deviation component multiplied by a governor gain, using an inertia constant and a calculation period, to output a frequency deviation component; a governor term that multiplies a previous value of the frequency deviation component output from the integral term by a governor gain; an output frequency generating unit that adds a rated frequency component to the frequency deviation component to generate an output frequency; a change rate limiting processing unit in the adding / subtracting unit that applies a change rate limiting process to an added output of the synchronous control output and a machine input command, the change rate limiting processing unit having a subtractor that subtracts an output of the governor term from the added output of the synchronous control output and the machine input command, a limiter that limits the output of the subtractor within a set frequency change rate limit value range, and an adder that adds the output of the governor term to the output of the limiter; The present invention is characterized in that it is provided with:

[0029] The power conversion device according to claim 3 is the power conversion device according to claim 1 or 2, The frequency change rate limit value ωratelim of the change rate limiting processor in the VSG model is set so as to satisfy the following formula (4).

[0030]

number

[0031] (Pin is the output of the adder / subtractor, M is the inertia constant of the integral term, Kgov is the governor gain in the governor term, and Δωr(n-1) is the previous value of the frequency deviation component.) Effect of the Invention

[0032] (1) According to the invention described in claims 1 and 3, the rate of change in the output frequency of the VSG model due to changes in the synchronous control output is limited, making it possible to prevent erroneous detection of islanding of a distributed power source connected to a power conversion device under synchronous control. (2) According to the invention described in claims 2 and 3, the rate of change in the output frequency of the VSG model due to changes in the synchronous control output and the mechanical input is limited, thereby making it possible to prevent erroneous detection of islanding operation of a distributed power source connected to a power conversion device under synchronous control. [Brief description of the drawings]

[0033] [Figure 1] 1 is a system configuration diagram of a power conversion device to which the present invention is applied; [Diagram 2] A diagram of the conventional VSG model. [Diagram 3] FIG. 1 is a configuration diagram of a VSG model according to a first embodiment of the present invention. [Figure 4] FIG. 11 is a configuration diagram of a VSG model according to a second embodiment of the present invention. [Diagram 5] A simplified diagram of the VSG model. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiment example. EXAMPLES

[0035] In this embodiment 1, the VSG model 17 in the system configuration of Fig. 1 is configured as shown in Fig. 3. In Fig. 3, the same parts as in Fig. 2 are designated by the same reference numerals. Fig. 3 differs from Fig. 2 in that a change rate limiting processing unit 30 that limits the change rate of the output frequency ωr of the VSG model 17 is provided between the input unit of the synchronous control output Pm_sync and one input end of the adder 21, and the other parts are configured in the same way as in Fig. 2.

[0036] The adder 21 and subtractor 22 constitute an adder / subtractor section of the present invention, the buffer 26 and multiplier 27 constitute a governor term of the present invention, and the adder 28 constitutes an output frequency generating section of the present invention.

[0037] Reference numeral 31 in the change rate limiting processing unit 30 denotes a subtractor that calculates the amount of change in the synchronous control output by subtracting the output of the governor term, i.e., the value (output of multiplier 27) obtained by multiplying the deviation Δωr of the previous output frequency (output of buffer 26) by the governor gain Kgov from the synchronous control output Pm_sync.

[0038] The limiter 32 in the change rate limiting processing unit 30 inputs the amount of change in the synchronous control output output from the subtractor 31 as is if it is within the range of ±M*frequency change rate limit value ωratelim, but limits the amount of change to M*ωratelim if it is outside ±M*ωratelim.

[0039] The output of the limiter 32 is added to the output of the governor term (the output of the multiplier 27) in an adder 33, and the output of the adder 33 is added to the machine input command Pm in an adder 21.

[0040] The configuration and operation of the subtractor 22 and subsequent components, which subtracts the electrical output Pe from the output of the adder 21, are the same as those described with reference to FIG. 2, but the VSG model is simplified as shown in FIG. 5 for analysis purposes.

[0041] 5, the same parts as those in FIG. 3 are designated by the same reference numerals, and the input Pin represents the output of the adder-subtractor unit of the present invention, that is, the output of the subtractor 22.

[0042] In FIG. 5, the rate of change dωr / dt of the frequency deviation Δωr(n) (n is the number of calculations) output from the adder 25 can be calculated from the previous value Δωr(n-1) stored in the buffer 26, the input Pin, and the calculation period Ts as shown in the following equations (1) and (2).

[0043]

number

[0044]

number

[0045] Here, the Pin condition for suppressing the rate of change dωr / dt to be equal to or less than the frequency rate of change limit value ωratelim is found by the following equations (3) and (4).

[0046]

number

[0047]

number

[0048] Therefore, by applying a limiting process to Pin so as to satisfy the formula (4), it is possible to limit the frequency change rate to the frequency change rate limit value ωratelim or less.

[0049] Here, when equation (4) is applied to the VSG model in Figure 2, Pin is given by the following equation (5).

[0050]

number

[0051] In order to suppress the rate of change dωr / dt, the frequency deviation Δωr output from the adder 25 may be directly limited, but since the mechanical input Pm and electrical output Pe of the input respond to fluctuations during command changes and system disturbances, there are cases where it is undesirable to limit the frequency change rate. Therefore, by using the input limit using equation (4), the frequency change rate limit is imposed only on the terms that are to be subject to the rate of change limit.

[0052] As described above, according to the first embodiment, the limiting process of the formula (4) is applied only to the synchronous control output Pm_sync, thereby limiting the frequency change rate of the VSG model due to a change in the synchronous control output. The frequency change rate due to the influence of a change in the mechanical input Pm or the electrical output Pe is not limited. By limiting the frequency change rate due to the input from the synchronous control to less than a certain value, it is possible to prevent erroneous detection of an islanding operation of the distributed power source (3) connected to the power conversion device under synchronous control. EXAMPLES

[0053] In this second embodiment, the VSG model 17 in the system configuration of Fig. 1 is configured as shown in Fig. 4. In Fig. 4, the same parts as in Fig. 2 are designated by the same reference numerals. Fig. 4 differs from Fig. 2 in that a change rate limiting processing unit 40 that limits the change rate of the output frequency ωr of the VSG model 17 is provided between the output side of the adder 21 and the positive input terminal of the subtractor 22, and the other parts are configured in the same way as in Fig. 2.

[0054] The adder 21 and subtractor 22 constitute an adder / subtractor section of the present invention, the buffer 26 and multiplier 27 constitute a governor term of the present invention, and the adder 28 constitutes an output frequency generating section of the present invention.

[0055] Reference numeral 41 in the change rate limiting processing unit 40 denotes a subtractor that calculates the amount of change in Pm' by subtracting the governor term output, i.e., the value (output of multiplier 27) obtained by multiplying the deviation Δωr of the previous output frequency (output of buffer 26) by the governor gain Kgov, from the mechanical input Pm', which is the sum output of adder 21.

[0056] The limiter 42 in the change rate limiting processing unit 40 inputs the output of the subtractor 41 (the change in Pm') as is if it is within the range of ±M*frequency change rate limit value ωratelim, but limits the change to M*ωratelim if it is outside ±M*ωratelim.

[0057] The output of the limiter 42 is added to the output of the governor term (the output of the multiplier 27) in the adder 43, and the output of the adder 43 has the electrical output Pe subtracted from it in the subtractor 22. The configuration and operation of the subtractor 22 and subsequent stages are the same as those described in FIG.

[0058] In this second embodiment, as in the first embodiment, the configuration after the subtractor 22 is considered as a simplified VSG model as shown in FIG. 5, and the rate of change of the output frequency of the VSG model can be limited based on the above equations (1) to (4).

[0059] As described above, according to the second embodiment, by providing the change rate limiting process of the formula (4) after adding the mechanical input command Pm and the synchronous control output Pm_sync (output of the adder 21), the frequency change rate of the VSG model due to changes in the synchronous control output and the mechanical input command is limited. The frequency change rate due to the influence of changes in the electrical output Pe is not limited. By limiting the frequency change rate due to the mechanical input and the input from the synchronous control to less than a certain value, it is possible to prevent erroneous detection of islanding operation of the distributed power source (3) connected to the power conversion device under synchronous control.

[0060] Here, a description will be given of the conditions for selecting between embodiment 1 and embodiment 2. When the fluctuation of the synchronous control output Pm_sync is large, it is preferable to use embodiment 1. When the fluctuation of the machine input command Pm or the machine input Pm' is large, it is preferable to use embodiment 2. [Explanation of symbols]

[0061] 1…Power system 2a~2d…breaker 3…Distributed power supply 4. On-site load 5...Power converter 9...Synchronization control section 11...Output power calculation section 13,15...uvw / dq coordinate converter 16…Voltage controller 17…VSG model 18,24...integrator 19...dq / uvw coordinate converter 20…PWM Modulator 21, 25, 28, 33, 43…Adder 22, 23, 31, 41…Subtractor 26…Buffer 27...Multiplier 30, 40...Change rate limiting processing section

Claims

1. A power conversion device that is connected to a common connection point between a power supply system and a distributed power supply so as to be interconnectable with the distributed power supply, and that performs virtual synchronous generator control using a VSG (Virtual Synchronous Generators) model, The VSG model is an adding / subtracting unit that subtracts an electric output obtained by detecting an output power of a power conversion device from an added output of a synchronous control output obtained by performing synchronous control by feeding back a signal that detects a voltage of the power supply system and a machine input command; an integral term that integrates a difference between an output of the adding / subtracting unit and a previous value of a frequency deviation component multiplied by a governor gain, using an inertia constant and a calculation period, to output a frequency deviation component; a governor term that multiplies a previous value of the frequency deviation component output from the integral term by a governor gain; an output frequency generating unit that adds a rated frequency component to the frequency deviation component to generate an output frequency; a change rate limiting processing unit in the adding / subtracting unit that applies a change rate limiting process to the synchronous control output before it is added to the machine input, the change rate limiting processing unit having a subtractor that subtracts the output of the governor term from the synchronous control output to obtain a change amount of the synchronous control output, a limiter that limits the change amount of the synchronous control output obtained by the subtractor to within a set frequency change rate limit value range, and an adder that adds the output of the governor term to the output of the limiter; A power conversion device comprising:

2. A power conversion device that is connected to a common connection point between a power supply system and a distributed power supply so as to be interconnectable with the distributed power supply, and that performs virtual synchronous generator control using a VSG (Virtual Synchronous Generators) model, The VSG model is an adder / subtractor that adds a synchronous control output resulting from synchronous control performed by feeding back a signal that detects the voltage of the power supply system and a machine input command, and then subtracts an electrical output that detects the output power of a power conversion device from the added output; an integral term that integrates a difference between an output of the adding / subtracting unit and a previous value of a frequency deviation component multiplied by a governor gain, using an inertia constant and a calculation period, to output a frequency deviation component; a governor term that multiplies a previous value of the frequency deviation component output from the integral term by a governor gain; an output frequency generating unit that adds a rated frequency component to the frequency deviation component to generate an output frequency; a change rate limiting processing unit in the adding / subtracting unit that applies a change rate limiting process to an added output of the synchronous control output and a machine input command, the change rate limiting processing unit having a subtractor that subtracts an output of the governor term from the added output of the synchronous control output and the machine input command, a limiter that limits the output of the subtractor within a set frequency change rate limit value range, and an adder that adds the output of the governor term to the output of the limiter; A power conversion device comprising:

3. 3. The power conversion device according to claim 1, wherein a frequency change rate limiting value ωratelim of a change rate limiting processor in the VSG model is set so as to satisfy the following formula (4). [0045] (Pin is the output of the addition and subtraction unit, M is the inertia constant of the integral term, Kgov is the governor gain in the governor term, and Δωr(n-1) is the previous value of the frequency deviation component.)

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