Memory Structure

Abstract

To provide a memory structure which is based on a thyristor operation mechanism, has high expandability, and has high operation speed.SOLUTION: A memory structure 20 is provided, including a substrate 200, a first gate structure 212, a second gate structure 214, a third gate structure 216, and channel bodies 220 separated from each other and passing through the first gate structure to the third gate structure along a first direction X. The first gate structure to the third gate structure are disposed on the substrate, are separated from each other along the first direction, and respectively extend along a second direction Y and the third direction Z. The first gate structure includes a first island structure 2121, a second island structure 2122, and a third island structure 2123 each extending along the third direction and separated from each other along the second direction. The third gate structure includes a fourth island structure 2161, a fifth island structure 2162, and a sixth island structure 2163 each extending along the third direction and separated from each other along the second direction.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] The present invention relates generally to semiconductor structures, and more particularly to memory structures. [Background technology]

[0002] In traditional dynamic random access memory (DRAM), each bit of data requires one transistor (1T) and one capacitor (1C) for processing, i.e., 1T1C DRAM. However, to meet market demand, the size of memory structure needs to be further reduced. And 1T1C DRAM has more challenges, such as leakage current, complex process, and increased cost.

[0003] Therefore, there remains a need to further improve the structure of conventional DRAMs to reduce the size of the memory structure while maintaining the performance of the memory structure. Summary of the Invention

[0004] The present invention relates to a memory structure based on a thyristor operating mechanism, which has the advantages of high scalability and high operating speed.

[0005] According to an embodiment of the present invention, a memory structure is provided. The memory structure includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a plurality of channel bodies. The substrate has a top surface. The first gate structure, the second gate structure, and the third gate structure are disposed on the substrate, and are separated from each other along a first direction and extend along a second direction and a third direction, respectively, and the second gate structure is disposed between the first gate structure and the third gate structure, and the first direction, the second direction, and the third direction intersect with each other. The first direction, the second direction, and the third direction intersect with each other. The second gate structure is disposed between the first gate structure and the third gate structure. The first gate includes a first island structure, a second island structure, and a third island structure. The third gate structure includes a fourth island structure, a fifth island structure, and a sixth island structure. The first island structure, the second island structure, and the third island structure each extend along the third direction and are separated from each other along the second direction. The fourth, fifth and sixth island structures each extend along a third direction and are separated from one another along the second direction. The channel bodies are separated from one another and pass through the first, second and third gate structures along the first direction.

[0006] These and other aspects of the present invention will become more fully understood in connection with the following detailed description of the preferred but non-limiting embodiments, the description being made with reference to the accompanying drawings. [Brief description of the drawings]

[0007] [Figure 1] 1 shows a schematic three-dimensional view of a memory structure according to an embodiment of the present invention;

[0008] [Diagram 2] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Diagram 3] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 4] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Diagram 5] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 6] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 7] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 8] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 9] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 10] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 11] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 12] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 13] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 14] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 15] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 16] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 17] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism. [Figure 18] FIG. 2 shows the result of operating the memory structure shown in FIG. 1 via a thyristor mechanism.

[0009] [Figure 19] 2 is a schematic three-dimensional view of a memory structure according to another embodiment of the present invention;

[0010] [Figure 20] 4 shows an equivalent circuit diagram of a memory structure according to another embodiment of the present invention.

[0011] [Figure 21] FIG. 13 shows a band diagram for operating a memory structure in "PGM" and "ERS" states based on a thyristor operating mechanism.

[0012] [Figure 22] FIG. 1 shows experimental results of operating a memory structure based on a thyristor operating mechanism. [Figure 23] FIG. 1 shows experimental results of operating a memory structure based on a thyristor operating mechanism. [Figure 24] FIG. 1 shows experimental results of operating a memory structure based on a thyristor operating mechanism. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The following are related embodiments that describe in detail the memory structure provided by the present disclosure with accompanying drawings. However, the present disclosure is not limited thereto. The description of the embodiments, such as the detailed structure, the steps of the manufacturing method, and the use of materials, is for illustrative purposes only, and the scope of protection of the present disclosure is not limited to the implementation aspects mentioned.

[0014] At the same time, it should be noted that the present disclosure does not show all possible implementations. Those skilled in the art can make changes and modifications to the structure and manufacturing method of the embodiment to meet the needs of actual applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in the present disclosure may also be applicable. In addition, the drawings are simplified for the purpose of clearly describing the contents of the embodiments, and the dimensions and ratios in the drawings are not drawn according to the scale of the actual deliverables. Therefore, the description and drawings are only used to describe the embodiments, not to limit the protection scope of the present disclosure. The same or similar reference symbols are used to represent the same or similar elements.

[0015] To meet the demand for smaller size, various alternative forms of capacitorless DRAM are being researched in the industry. For example, single-transistor DRAM (1T DRAM) has been proposed. Conventional 1T DRAM consists of a single MOSFET fabricated on a part of an SOI substrate, and uses the floating body effect to generate excess holes by impact ionization and store them in a neutral body, defining this state as logic "1". On the other hand, when the device is forward biased so that holes are swept out of the neutral body, it is in logic "0" state. Later, thyristor RAM (abbreviated as TRAM) has been proposed, which utilizes the biasability of PNPN thyristors without the need to apply a large bias to induce impact ionization as in typical 1T DRAM.

[0016] The memory structure provided in the present invention is an architecture derived from 1T DRAM operation for improved TRAM operation. Compared with a typical 1T DRAM, the semiconductor structure and operating mechanism of the present invention can provide a larger current sensing margin between logic "1" and logic "0" states (e.g., 60 μA); can provide shorter pulse widths (e.g., 50 ns) without reducing the window; can increase the room temperature retention time (e.g., up to 3 seconds) and increase the read disturb free time (e.g., up to 2 seconds). These characteristics make the memory structure and the mechanism for operating the memory structure of the present invention a promising DRAM candidate with high scalability and high operating speed.

[0017] The present invention provides a three dimensional memory structure including three transistors (3T) (as shown in memory structures 10 and 20 in Figures 1 and 19) for 3D DRAM characteristics and thyristor operation.

[0018] 1 shows a schematic three-dimensional view of a memory structure 10 according to an embodiment of the present invention. As shown in FIG. 1, in this embodiment, the Z direction represents a first direction, the Y direction represents a second direction, and the X direction represents a third direction.

[0019] 1, the memory structure 10 includes a substrate 100, a first gate structure 112, a second gate structure 114, a third gate structure 116, a plurality of channel bodies 120, a plurality of insulating films 122, a first plug 132, a second plug 134, a third plug 136, and a first side plug 140. The substrate 100 has a top surface 100a, the top surface 100a is parallel to a second direction (e.g., Y direction) and a third direction (e.g., X direction), and a normal direction of the top surface 100a is parallel to a first direction (e.g., Z direction). A region 100D adjacent to the top surface 100a of the substrate 100 may be doped with a dopant. In one embodiment, the region 100D adjacent to the top surface 100a of the substrate 100 has a first conductivity type, for example, a high concentration of N-type doping (N+). Region 100D of substrate 100 may function as a common source line.

[0020] The first gate structure 112, the second gate structure 114, and the third gate structure 116 are disposed on the substrate 100, are stacked in succession along a first direction (e.g., Z direction) and are separated from each other, and extend along a second direction (e.g., Y direction) and a third direction (e.g., X direction), respectively, and the second gate structure 114 is disposed between the first gate structure 112 and the third gate structure 116, and the first direction, the second direction, and the third direction cross each other, e.g., are orthogonal to each other, i.e., the Z direction, the Y direction, and the X direction may be orthogonal to each other. To make the drawing more concise, some insulating materials are omitted in FIG. 1. For example, insulating materials between the substrate 100, the first gate structure 112, the second gate structure 114, and the third gate structure 116 are omitted. In some embodiments, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may each function as a word line.

[0021] The channel bodies 120 are separated from each other along a second direction (e.g., Y direction) and a third direction (e.g., X direction) and extend along a first direction (e.g., Z direction) through the first gate structure 112, the second gate structure 114, and the third gate structure 116 to the substrate 100. For example, the channel bodies 120 are in electrical contact with the substrate 100 to form a vertical channel structure. At each of the intersections between the channel bodies 120 and each of the gate structures (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116), a transistor is formed. Each of the channel bodies 120 has a first end 120A in electrical contact with the top surface 100a of the substrate 100 and a second end 120B that is farther away from the top surface 100a, the second end 120B being opposite the first end 120A. A region 120D adjacent the second end 120B of the channel body 120 may be doped with a dopant.

[0022] In this embodiment, for example, a thyristor is used in the operating mechanism, and a region 120D of the channel body 120 adjacent the second end 120B has a second conductivity type, such as heavy P-type doping (P+). Region 100D can function as a source and region 120D can function as a drain, although the invention is not limited in this respect.

[0023] The insulating film 122 is disposed between the first gate structure 112 and the channel body 120, between the second gate structure 114 and the channel body 120, and between the third gate structure 116 and the channel body 120. That is, the insulating film 122 extends along a first direction (e.g., the Z direction) and surrounds the side surface of the channel body 120 to separate the first gate structure 112 from the channel body 120, the second gate structure 114 from the channel body 120, and the third gate structure 116 from the channel body 120.

[0024] The first gate structure 112, the second gate structure 114, and the third gate structure 116 surround each of the insulating films 122 and each of the channel bodies 120, which is also called a gate-all-around (GAA) structure. Furthermore, each of the channel bodies 120 can be controlled by three gates (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116).

[0025] The first side plug 140 extends along a first direction (e.g., Z direction) and a third direction (e.g., X direction) and is in electrical contact with the substrate 100. For example, the first side plug 140 is electrically connected to the substrate 100 and the channel body 120.

[0026] The substrate 100 corresponds to a memory array area MA and a staircase area SA. The channel body 120 is disposed in the memory array area MA. The staircase area SA is adjacent to the memory array area MA. The first gate structure 112, the second gate structure 114, and the third gate structure 116 form a step structure in the staircase area SA, exposing the first landing region LR1, the second landing region LR2, and the third landing region LR3, respectively. The first plug 132, the second plug 134, and the third plug 136 are disposed on the first landing region LR1, the second landing region LR2, and the third landing region LR3, respectively, and extend along a first direction (e.g., Z direction) to be in electrical contact with the first gate structure 112, the second gate structure 114, and the third gate structure 116, respectively.

[0027] In some embodiments, the substrate 100 may include a semiconductor substrate such as a bulk silicon substrate. In this embodiment, the channel body 120 may be formed by an epitaxial growth process, and the material of the channel body 120 may include single crystal silicon. During operation (e.g., programming or erasing) of the memory device 10, the channel body 120 may be used to store carriers (e.g., electrons or holes). Since the insulating film 122 does not need to have the function of storing carriers (e.g., electrons or holes), the insulating film 122 does not include a charge storage structure such as an oxide-nitride-oxide (ONO) structure. In one embodiment, the material of the insulating film 122 includes a dielectric material such as an oxide, and the insulating film 122 may be a single layer structure. In one embodiment, the material of the insulating film 122 may include a high dielectric constant material (high-k material). In one embodiment, the materials of the first plug 132, the second plug 134, the third plug 136, the first side plug 140, the first gate structure 112, the second gate structure 114, and the third gate structure 116 may include semiconductor materials or metal materials. In this embodiment, the first gate structure 112 may include polysilicon, and the second gate structure 114 and the third gate structure 116 may each include a metal. It should be understood that the materials of the above-mentioned elements of the present invention are not limited thereto.

[0028] 2-18 show the results of operating the memory structure 10 shown in FIG. 1 through a thyristor mechanism.

[0029] FIG. 2 shows the relationship between bit line bias voltage and bit line current (also representing drain current) in the first to fourth embodiments, where the X-axis is the bit line bias voltage (V BL ) in volts (V), and the Y-axis represents the bit line current (I BL) in amperes (A). The solid curve represents a forward bias voltage FWD (e.g., sweeping from left to right), and the dotted curve represents a reverse bias voltage REV (e.g., sweeping from right to left). In the first to fourth embodiments, 3V is applied to both the second gate structure 114 and the third gate structure 116, and a different voltage is applied to the first gate structure 112. −3V is applied to the first gate structure 112 in the first embodiment, −2.5V is applied to the first gate structure 112 in the second embodiment, −2V is applied to the first gate structure 112 in the third embodiment, and −1.5V is applied to the first gate structure 112 in the fourth embodiment.

[0030] As shown in FIG. 2, first, the forward bias voltage FWD is scanned from 0V to 4V, and then the reverse bias voltage REV is scanned from 4V to 0V. Each of the first to fourth embodiments shows a hysteresis curve. The distance between the solid curve and the dotted curve under the same bit line current represents the size of the hysteresis window. Under the same bit line current, the hysteresis windows of the first to fourth embodiments have different sizes. For example, -8 Under the bit line current adjacent to A, the size of the hysteresis window shown in the first and second embodiments is smaller than the size of the hysteresis window HW shown in the third embodiment, and the size of the hysteresis window shown in the fourth embodiment is larger than the size of the hysteresis window HW shown in the third embodiment. That is, by fixing the voltage of the second gate structure 114 and the third gate structure 116 and changing the voltage of the first gate structure 112, the size of the hysteresis window can be adjusted so that the operation effect of a thyristor can be achieved. By reading the voltage (e.g., 2V) within the range of the hysteresis window, different current magnitudes can be obtained, and thus logical "1" and logical "0" can be distinguished.

[0031] In conventional thyristor operation, since there is only one gate, it is usually necessary to use a complex doping structure such as forming multiple doped regions of different conductivity types (N-type, P-type) (e.g., N / P / N / P structure) to achieve the effect of adjusting the hysteresis window. In contrast, in the thyristor operation of the embodiments of the present application (e.g., embodiments 1 to 4), the hysteresis curve can be adjusted by applying different gate bias voltages, and the size of the hysteresis window can be controlled without the need to form a complex doping structure.

[0032] FIG. 3 shows the simulation results of the band diagram of the first state E1, the second state E2, and the third state E3 of the embodiment 3 shown in FIG. 2. For example, FIG. 3 can be observed by computer simulation using a Technology Computer Aided Design (TCAD) tool. In FIG. 3, the X-axis represents the position between the region 100D and the region 120D (e.g., as shown in the simplified diagram of the region 100D, the region 120D, and other components on the top of FIG. 3) in micrometers (μm), and the Y-axis represents the energy in electron volts (eV). "Ec" represents the conduction band. "Ev" represents the valence band.

[0033] 2 and 3, the bias voltages of the first gate structure 112 in the first state E1 to the third state E3 are all −2 V, the bias voltages of the second gate structure 114 in the first state E1 to the third state E3 are all 3 V, and the bias voltages of the third gate structure 116 in the first state E1 to the third state E3 are all 3 V. The first state E1 is a high resistance state, the bit line bias is 2.3 V, and both the electron energy barrier BR1 and the hole energy barrier BR2 are very high, so that electrons cannot pass through the electron energy barrier BR1 and holes cannot pass through the hole energy barrier BR2.

[0034] The second state E2 is a low resistance state, and the bit line bias voltage is 3.5V. When entering the second state E2 from the first state E1, the bit line bias voltage gradually increases, which will cause the hole energy barrier BR2 to gradually decrease, so that some holes can pass through the energy barrier and flow into the channel body 120. In this way, it also causes the electron energy barrier BR1 to decrease, so that some electrons can also pass through the electron energy barrier BR1 and flow into the channel body 120. Similarly, when some electrons flow into the channel body 120, it can also cause the hole energy barrier BR2 to decrease. Thus, a positive feedback can be formed, so that the electron energy barrier BR1 and the hole energy barrier BR2 gradually decrease in response to each other, so that more electrons and holes can flow into the channel body 120. Accordingly, the electron energy barrier BR1 and the hole energy barrier BR2 in the second state E2 are almost nonexistent, and there may be a large current, which may induce latch-up.

[0035] The third state E3 is also a low resistance state, and the bit line bias voltage is 2.3 V. When entering the third state E3 from the second state E2, the voltages of the first gate structure 112 to the third gate structure 116 do not change, and only the bit line bias voltage changes, so that the electron energy barrier BR1 and the hole energy barrier BR2 are almost nonexistent. Accordingly, the large current is still maintained as in the third state E3, and the latch-up is still maintained.

[0036] Different bias voltages as exemplified in Table 1 below may be applied to the first gate structure 112, the second gate structure 114, the third gate structure 116, the region 120D (equal potential to the bit line BL), and the region 100D (equal potential to the source line SL) shown in FIG. 1 for different operation modes, such as a programming operation mode, an erase operation mode, or a read operation mode. In this embodiment and the accompanying drawings, "PGM" is an abbreviation for a programming operation mode, which indicates an operation mode in which memory cells of the memory structure 10 are programmed to a data state of "1" (i.e., logic "1"); "ERS" is an abbreviation for an erase operation mode, which indicates an operation mode in which memory cells of the memory structure 10 are programmed to a data state of "0" (i.e., logic "0"); and "Read" is an abbreviation for a read operation mode, which indicates an operation mode in which memory cells of the memory structure 10 are read to confirm the voltage data state of each memory cell.

[0037] [Table 1]

[0038] FIG. 4 shows experimental results of program / erase cycles (P / E cycles) and shows waveforms 10 obtained by operating the memory structure with the voltages in Table 1.

[0039] 4, in "PGM", the voltage applied to the first gate structure 112 is lower than 0 (e.g., -2V), the voltage applied to the second gate structure 114 and the third gate structure 116 is higher than 0 (e.g., 3V), and the large bit line bias (e.g., 3V) induces thyristor latch-up, so that the memory structure 10 begins to assume a low resistance state. In "ERS", to suppress latch-up, the gate voltage needs to be reset, so the voltage applied to the first gate structure 112, the second gate structure 114, and the third gate structure 116 (i.e., word line bias) returns to 0V, and a 0V bias of the bit line BL is applied. Thereafter, the voltage applied to the word line (i.e., the first gate structure 112, the second gate structure 114, and the third gate structure 116) can be increased to cause the memory structure 10 to return to a high resistance state. Through the above operations, a cycle of "PGM" → "Read" → "ERS" → "Read" shown in FIG. 4 can be formed. The "PGM" and "ERS" states have pulse widths PW1 and PW2, respectively.

[0040] FIG. 5 shows the measurement results of the source current in different conditions.

[0041] Referring to FIG. 5, the X-axis represents time in microseconds (μs), and the Y-axis represents the source current (I SL ) in microamperes (μA). The read current window RIW between the “PGM” and “ERS” states may be higher than 60 microamperes. This large read current window may be due to a large hysteresis window.

[0042] FIG. 6 is a graph showing the relationship between changes in source current and pulse width.

[0043] Referring to FIG. 6, the X-axis represents the pulse width in nanoseconds (ns) and the Y-axis represents the change in source current (Delta I SL) (i.e., current window) and is measured in microamperes (μA). Even if the pulse width is reduced to 50 nanoseconds (the limit of measurement), the sensing margin of the 60 microampere current window can be maintained.

[0044] Fig. 7 shows the resistance according to embodiment A of the present invention. Fig. 8 shows the band diagram of the "PGM" state and the "ERS" state of embodiment A. Fig. 9 shows the resistance according to comparative example A. Fig. 10 is a schematic diagram of the electron / hole transfer state in the "PGM" state and the "ERS" state of comparative example A.

[0045] The embodiment A can be applied to the memory structure 10 using a thyristor as an operating mechanism, as shown in Fig. 1. The difference between the comparative example A and the embodiment A is that the region 120D' functioning as the drain and the region 100D functioning as the source in the comparative example A have the same first conductivity type, and are, for example, highly doped N-type (N+) using a floating body cell as an operating mechanism.

[0046] Referring to FIG. 7, the X-axis represents the number of P / E cycles, and the Y-axis represents the read current (I read ) in microamperes (μA). During the P / E cycle operation, in the present invention, hot carriers are not used in the operation, so the memory structure of the present invention is not damaged by hot carriers. Compared to the comparative example (e.g., Comparative Example A) in which hot carriers are used in the operation, the memory structure of the present invention has better endurance and can withstand up to 10 10 Until the P / E cycle, there is no difference between the read current in the "PGM" and "ERS" states.

[0047] 8, in the "PGM" operation, for example, 0V is applied to the region 100D and 3V is applied to the region 120D, and the positive feedback described above can be used to lower or eliminate the electron and hole energy barriers, and the operation does not include hot carriers. Since the barriers have been eliminated, the electrons and holes can move toward the center of the channel body 120. In the "ERS" operation, for example, 0V is applied to the region 100D and 0V is applied to the region 120D to restore the electron and hole energy barriers, and the voltages listed in Table 1 are applied from the first gate structure 112 to the third gate structure 116, and neither operation includes hot carriers. Since the energy barriers have been established, the electrons and holes cannot move to the channel body 120.

[0048] Referring to FIG. 9, the X-axis represents the number of P / E cycles, and the Y-axis represents the read current in microamperes (μA). In the P / E cycle operation, Comparative Example A uses a floating body cell as the operating mechanism and uses hot carriers in the operation, so the memory structure is more likely to be damaged by hot carriers. For example, in the "PGM" operation, Comparative Example A uses band-to-band tunneling to generate holes and store the holes in the channel body 120. However, in the "PGM" state, the read current is still 10 3 It can be seen that at lower values, the P / E cycles drop rapidly and the resistance of Comparative Example A is significantly worse than that of Embodiment A.

[0049] 10, in the "PGM" operation, for example, 1V is applied to the third gate structure 116 and 5V is applied to the region 120D' to generate holes (i.e., hot carriers) through a band-to-band tunneling mechanism to generate interface traps Tr. As a result, the electric field is reduced and the read current of Comparative Example A in the "PGM" state is smaller than the read current of Embodiment A in the "PGM" state. In the "ERS" operation, for example, 4V is applied to the third gate structure 116 and -5V is applied to the region 120D' to move the holes stored in the channel body 120 out of the channel body 120.

[0050] 11-13 illustrate the hold state of a memory structure (eg, memory structure 10) according to one embodiment of the present invention, based on a thyristor-based operating mechanism.

[0051] The operating modes of memory structure 10 may further include a hold operation, where "Hold" is an abbreviation for a hold operation and indicates an operating mode for maintaining the voltage data state of the memory cells of memory structure 10.

[0052] Referring to FIG. 11, which shows the relationship between time and the voltage of the bit line BL, the first gate structure 112, the second gate structure 114 and the third gate structure 116 are in different states. "Hold" can be performed after "PGM" or "ERS" is completed, and "Read" can be performed after "Hold" is completed. When "Hold" is operated, different voltages can be applied from the first gate structure 112 to the third gate structure 116 to maintain the state of "PGM" or "ERS". For example, -2.5V can be applied to the first gate structure 112, -1V can be applied to the second gate structure 114, 3V can be applied to the third gate structure 116, and 0V can be applied to the bit line BL.

[0053] Hold time and read current (I read12, which shows the relationship between Hold time and ERS, the X-axis represents Hold time in seconds (sec) and the Y-axis represents read current in microamps (μA). For example, at room temperature, if the Hold time is 3 seconds, the difference between the read currents of "PGM" and "ERS" can still maintain 40 microamps, as shown by the double arrow in FIG. 12.

[0054] See FIG. 13, which shows the relationship between Hold time and read current in “PGM” and “ERS” at 85° C. The X-axis represents Hold time in seconds (sec) and the Y-axis represents read current (I read ) is expressed in microamperes (μA). For example, at 85°C, the Hold time is 10 -1 13. For a period of 100 ms (i.e., 100 ms), the difference between the reading currents of "PGM" and "ERS" can still remain at 60 microamps, as shown by the double arrow in FIG.

[0055] The results of Figures 12 and 13 show that, whether at room temperature or at 85°C, as long as an appropriate hold bias is applied, the memory structure of the present invention can have a moderate hold time (e.g., 3 seconds or 100 ms) that is superior to the DRAM currently used in the industry (hold time is, for example, 64 ms).

[0056] 14-18 show the results of read disturb for a memory structure (e.g., memory structure 10) according to an embodiment of the present invention based on a thyristor-based operating mechanism. Read disturb can be used to detect how long the read time can be sustained during a "Read" process without damaging the data.

[0057] Generally speaking, the 1T1C DRAM currently used in the industry belongs to destructive read, that is, when the "Read" is completed, the state disappears and needs to be rewritten.

[0058] Please refer to FIG. 14, which shows that in the memory structure of the present invention, data can be read repeatedly (e.g., seven consecutive “Reads”) without rewriting, proving that the memory structure of the present invention belongs to non-destructive reading.

[0059] See FIG. 15, which shows the results of continuous reads after “PGM” and “ERS”, for example extending the “Read” time to measure how long the “Read” can continue while data is still present.

[0060] Bit line read voltage (Read V BL 16, which illustrates the relationship between the read time and the read current for "PGM" and "ERS" when the input voltage is 2.5V, where the X-axis represents the read time in seconds (sec) and the Y-axis represents the read current (I read ) in microamperes (μA). The read time is 10 -3 For read times longer than 1 ms (i.e., 1 ms), the difference in read current between "PGM" and "ERS" was maintained at 65 microamps, as shown by the double arrow in Figure 16. For read times longer than 1 ms, due to positive feedback, the current of "ERS" rises rapidly and increases to the same current as that of "PGM".

[0061] Refer to FIG. 17, which shows the relationship between the read time and the read current of “PGM” and “ERS” when the bit line read voltage is 2.1V, where the X-axis represents the read time in seconds (sec) and the Y-axis represents the read current (I read ) in microamperes (μA). When the read time is 2 seconds, the difference in read current between "PGM" and "ERS" is maintained at 33 microamperes, as shown by the double arrow in FIG. 17. When the read time is longer than 2 seconds, the current of "ERS" rises rapidly due to positive feedback and increases to the same current as that of "PGM". Compared with the embodiment of FIG. 16, the difference between the read currents of "PGM" and "ERS" in the embodiment of FIG. 17 is smaller, but the read time can be maintained longer.

[0062] Please refer to FIG. 18, which shows the band diagram of the read voltage of the bit line in the "ERS" state of embodiment B and embodiment C. The structures of embodiment B and embodiment C are the same as that of embodiment A, but the read voltage of the bit line of embodiment B and embodiment C is different. In embodiment B, the read voltage of the bit line is 2.5V. In embodiment C, the read voltage of the bit line is 2.1V. As shown in FIG. 18, a lower read voltage of the bit line (i.e., embodiment C) may increase the hole energy barrier, which may delay the time to generate positive feedback since the holes are less likely to pass through the energy barrier and generate leakage current.

[0063] Therefore, if the time without read disturb is to be extended, the read voltage on the bit line can be lowered, which reduces the probability of inducing positive feedback in the "ERS".

[0064] 19 is a schematic three-dimensional diagram of a memory structure 20 according to another embodiment of the present invention. As shown in FIG. 19, in this embodiment, the Z direction represents the third direction, the Y direction represents the second direction, and the X direction represents the first direction.

[0065] 19, the memory structure 20 includes a substrate 200, a first gate structure 212, a second gate structure 214, a third gate structure 216, a plurality of channel bodies 220, a plurality of insulating films 222, a first side plug 240, a second side plug 250, a plurality of first side pads CP, and a plurality of second side pads BP. The substrate 200 has an upper surface 200a, which is parallel to a first direction (e.g., X direction) and a second direction (e.g., Y direction), and a normal direction of the upper surface 200a is parallel to a third direction (e.g., Z direction).

[0066] The first gate structure 212, the second gate structure 214, and the third gate structure 216 are arranged on the substrate 200 along a first direction (e.g., X direction), are separated from each other along the first direction (e.g., X direction), and extend along a second direction (e.g., Y direction) and a third direction (e.g., Z direction), and the second gate structure 214 is arranged between the first gate structure 212 and the third gate structure 216. The first direction, the second direction, and the third direction intersect with each other, for example, are orthogonal to each other, i.e., the Z direction, the Y direction, and the X direction may be orthogonal to each other. The first gate structure 212 includes a first island structure 2121, a second island structure 2122, and a third island structure 2123, and the first island structure 2121, the second island structure 2122, and the third island structure 2123 each extend along the third direction and are separated from each other along the second direction. The third gate structure 216 includes a fourth island structure 2161, a fifth island structure 2162, and a sixth island structure 2163, and the fourth island structure 2161, the fifth island structure 2162, and the sixth island structure 2163 each extend along the third direction and are separated from each other along the second direction. Also, the first island structure 2121, the second island structure 2122, and the third island structure 2123 are independently controlled. The fourth island structure 2161, the fifth island structure 2162, and the sixth island structure 2163 are independently controlled.

[0067] In one embodiment, the height H1 of the first island structure 2121, the second island structure 2122, or the third island structure 2123 in the third direction is equal to the height H2 of the second gate structure 214 in the third direction. The width WD11, WD12, or WD13 of the first island structure 2121, the second island structure 2122, or the third island structure 2123 in the second direction is smaller than the width WD2 of the second gate structure 214 in the second direction. The height H3 of the fourth island structure 2161, the fifth island structure 2162, or the sixth island structure 2163 in the third direction is equal to the height H2 of the second gate structure 214 in the third direction. The width WD31, WD32, or WD33 of the fourth island structure 2161, the fifth island structure 2162, or the sixth island structure 2163 in the second direction is smaller than the width WD2 of the second gate structure 2162 in the second direction, but the present invention is not limited thereto. 19 , some insulating materials are omitted, for example, insulating materials between the substrate 200, the first gate structure 212, the second gate structure 214, and the third gate structure 216, insulating materials between the first island structure 2121, the second island structure 2122, and the third island structure 2123, and insulating materials between the fourth island structure 2161, the fifth island structure 2162, and the sixth island structure 2163 are omitted. The width WD11, WD12, or WD13 in the second direction of the first island structure 2121, the second island structure 2122, or the third island structure 2123 may be equal to the width WD31, WD32, or WD33 in the second direction of the fourth island structure 2161, the fifth island structure 2162, or the sixth island structure 2163. In some embodiments, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may each function as a word line.

[0068] The channel bodies 220 are separated from each other along a second direction (e.g., Y direction) and a third direction (e.g., Z direction) and pass through the first gate structure 212, the second gate structure 214, and the third gate structure 216 along the first direction (e.g., X direction), i.e., the extending direction of the channel bodies 220 is parallel to the upper surface 200a of the substrate 200, forming a horizontal channel structure. Each of the channel bodies 220 has a first end 220A and a second end 220B, where the first end 220A is adjacent to the first gate structure 212 and is further away from the third gate structure 216, the second end 220B is adjacent to the third gate structure 216 and is further away from the first gate structure 212, and the second end 220B is opposite to the first end 220A.

[0069] The first side pads CP are stacked along a third direction (e.g., Z direction) and separated from one another along the third direction (e.g., Z direction), and each of the first side pads CP is connected to a corresponding first end 220A of the channel body 220. The second side pads BP are stacked along the third direction (e.g., Z direction) and separated from one another along the third direction (e.g., Z direction), and each of the second side pads BP is connected to a corresponding second end 220B of the channel body 220. The first side pads CP and the second side pads BP may be doped with a dopant.

[0070] In this embodiment, where a thyristor is used as the operating mechanism, the first side pad CP has a first conductivity type, e.g., having a high concentration of N-type doping (N+), and the second side pad BP has a second conductivity type, e.g., having a high concentration of P-type doping (P+).

[0071] In one embodiment, the first side pad CP can be used as a source and the second side pad BP can be used as a drain, but the present invention is not limited thereto.

[0072] The insulating film 222 is disposed between the first gate structure 212 and the channel body 220, between the second gate structure 214 and the channel body 220, and between the third gate structure 216 and the channel body 220. That is, the insulating film 222 extends along a first direction (e.g., X-direction) and surrounds the sides of the channel body 220 to separate the first gate structure 212 from the channel body 220, the second gate structure 214 from the channel body 220, and the third gate structure 216 from the channel body 220. In one embodiment, the insulating films 222 surrounding different channel bodies 220 are connected to each other and extend (not shown) along a second direction (e.g., Y-direction) and a third direction (e.g., Z-direction) to cover the first gate structure 212, the second gate structure 214, and the third gate structure 216.

[0073] The first gate structure 212, the second gate structure 214, and the third gate structure 216 surround each of the insulating films 222 and each of the channel bodies 220, and extend along a second direction (e.g., Y direction) and a third direction (e.g., Z direction) in the space between adjacent channel bodies 220. Since the first gate structure 212, the second gate structure 214, and the third gate structure 216 surround the sides of the channel body 220 at corresponding positions (i.e., intersection positions between the first gate structure 212, the second gate structure 214, the third gate structure 216, and the channel body 220), this is also called a gate-all-around (GAA) structure. Furthermore, each of the channel bodies 220 can be controlled by three gates (i.e., the first gate structure 212, the second gate structure 214, and the third gate structure 216). Specifically, the channel body 220 corresponding to the first island structure 2121 can be controlled by the first island structure 2121, the second gate structure 214, and the fourth island structure 2161, the channel body 220 corresponding to the second island structure 2162 can be controlled by the second island structure 2162, the second gate structure 214, and the fifth island structure 2162, and the channel body 220 corresponding to the third island structure 2123 can be controlled by the third island structure 2123, the second gate structure 214, and the sixth island structure 2163. At each of the intersections between the channel body 220 and the gate structures, a transistor is formed.

[0074] The first side plug 240 extends along a second direction (e.g., Y direction) and a third direction (e.g., Z direction) and is in electrical contact with the substrate 200 and the first side pad CP. For example, the first side plug 240 is electrically connected to the substrate 200 and the channel body 220.

[0075] The second side plugs 250 are separated from each other along the second direction (e.g., Y direction) and extend along the third direction (e.g., Z direction) so as to be in electrical contact with the landing regions R1 to R8 on the second side pad BP, respectively. In this embodiment, the height of the second side plugs BP in the third direction (e.g., Z direction) gradually increases along the second direction (e.g., Y direction), and the landing regions R1 to R8 form a stepped structure. However, the present invention is not limited thereto. The upper portions of the second side plugs 250 may be connected to bit lines (not shown), respectively. Different second side plugs 250 are connected to different bit lines (not shown). That is, the channel bodies 220 in the same layer may be electrically connected to the same second side plugs 250 and corresponding bit lines (not shown). The number of second side plugs 250 may be the same as the number of first side pads CP, the number of channel bodies 220, and the number of second side pads BP along the third direction (e.g., Z direction), for example, 4, but the present invention is not limited thereto. For example, in other embodiments, the number of second side plugs 250, the number of first side pads CP along the third direction (e.g., Z direction), the number of channel bodies 220 along the third direction (e.g., Z direction), and the number of second side pads BP along the third direction (e.g., Z direction) may be greater than 4.

[0076] In some embodiments, the substrate 200 may include a semiconductor substrate such as a bulk silicon substrate. In this embodiment, the channel body 220 may be formed by an epitaxial growth process, and the material of the channel body 220 may include single crystal silicon. During operation (e.g., programming or erasing) of the memory device 20, the channel body 220 may be used to store carriers (e.g., electrons or holes). Since the insulating film 222 does not need to have the function of storing carriers (e.g., electrons or holes), the insulating film 222 does not include a charge storage structure such as an oxide-nitride-oxide (ONO) structure. In other words, there is no ONO structure in the space between the channel body 220 and the gate structures (i.e., the first gate structure 212, the second gate structure 214, and the third gate structure 216). In one embodiment, the material of the insulating film 222 includes a dielectric material such as an oxide, and the insulating film 222 may be a single layer structure. In one embodiment, the material of the insulating film 222 may include a high dielectric constant material (high-k material). In one embodiment, the materials of the first side plug 240, the second side plug 250, the first side pad CP, the second side pad BP, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may include semiconductor materials or metal materials. In one embodiment, the materials of the first side pad CP, the second side pad BP, the first gate structure 212, the second gate structure 214, and the third gate structure 216 may include single crystal silicon or polycrystalline silicon or metal. It should be understood that the materials of the above-mentioned elements of the present invention are not limited thereto.

[0077] According to some embodiments, the memory structure 20 can be formed by a stacked gate-all-around nanosheet CMOS process. Compared with the memory structure 10 with a vertical channel, the memory structure 20 with a horizontal channel can have more layers of stacked channel body 220, so that more bits can be formed, and the memory structure 20 with a horizontal channel can have a higher density of memory cells, which is more beneficial for miniaturizing the size of the memory structure.

[0078] In Comparative Example B (not shown), the shape of the first gate structure 212 is the same as that of the second gate structure 214 (i.e., the first gate structure 212 does not include the first island structure 2121, the second island structure 2122, and the third island structure 2123), and other structures of Comparative Example B are the same as those of the memory structure 20 (i.e., the third gate structure 216 also includes the fourth island structure 2161 to the sixth island structure 2163). Compared with Comparative Example B (not shown), the memory structure 20 of the present invention includes separate island structures in the first gate structure 212 and the third gate structure 216, so that the memory structure can have a better control effect and exhibit better electrical characteristics when operating in a thyristor mechanism. For example, in one embodiment of the present invention, the separate island structures in both the first gate structure 212 and the third gate structure 216 can provide more flexibility in the operating design of the write voltage and the erase voltage, which helps to improve the memory window between the "1" state and the "0" state, and also helps to suppress the leakage current from the unselected memory cells.

[0079] FIG. 20 illustrates an equivalent circuit diagram of a memory structure 20 according to another embodiment of the present invention.

[0080] 19 and 20, FIG. 20 exemplarily illustrates, for example, four adjacent channel bodies 220 in FIG. 19, and transistors are formed at the intersections between the channel bodies 220, the first island structure 2121 and the second island structure 2122 in the first gate structure 212, and the fourth island structure 2161 and the fifth island structure 2162 in the second gate structure 214 and the third gate structure 216. As shown in FIG. 20, the transistors TA1, TA2, and TA3 connected by the same channel body 220 together form a memory cell unit CA, the transistors TB1, TB2, and TB3 connected by the same channel body 220 together form a memory cell unit CB, and the transistors TS1, TS2, and TS3 connected by the same channel body 220 together form a memory cell unit CS. The first end 220A of the channel body 220 is connected to the corresponding first side pad CP. The first side pads CP of different layers are electrically connected to the first side plugs 240 and electrically connected to the source lines. Thus, the memory cells CA, CB, and CS are connected to a common source line CSL (i.e., equipotential). The second end 220B of the channel body 220 is connected to a corresponding second side pad BP, and different layers of the second side pad BP are electrically contacted with different second side plugs 250, and the different second side plugs 250 are electrically connected to different bit lines, for example, the memory cells CB and CS in the same layer are electrically connected to the first bit line BL1, and the memory cells CA and CB in the same layer are electrically connected to the second bit line BL2. The memory cells CA, CB, and CS share the second gate structure 214. The memory cells CA and CS share the second island structure 2122 of the first gate structure 212 and the fifth island structure 2162 of the third gate structure 216.

[0081] In this embodiment, the memory cell unit CS is the selected memory cell unit, and the other memory cell units CA, CB are unselected memory cell units (e.g., inhibit memory cell units). In other words, the memory cell CS corresponds to the selected second island structure 2122, the selected second gate structure 214, and the selected fifth island structure 2162, and is electrically connected to the selected first bit line BL1. The unselected memory cell CB may correspond to the unselected first island structure 2121 and the unselected fourth island structure 2161. The second bit line BL2 is an unselected bit line. Furthermore, different bias voltages can be applied to the first island structure 2121, the second island structure 2122, the second gate structure 214, the fourth island structure 2161, the fifth island structure 2162, the first bit line BL1, the second bit line BL2, and the common source line CSL for different operation modes, such as "PGM", "ERS" or "Read" operation modes, similar to their descriptions in the relevant paragraphs of Table 1.

[0082] [Table 2]

[0083] FIG. 21 shows band diagrams in the "PGM" and "ERS" states by operating memory structure 20 based on a thyristor operating mechanism.

[0084] Referring to FIG. 21, in the “PGM” operation, for example, by applying 0V to the first side pad CP and 3V to the second side pad BP, the above-mentioned positive feedback can be used to reduce or eliminate the electron energy barrier and the hole energy barrier, and no hot carrier action is involved. Since the energy barriers have been eliminated, the electrons and holes can move toward the center of the channel body 220. In the “ERS” operation, for example, 0V is applied to the first side pad CP, 0V is applied to the second side pad BP, and the voltages listed in Table 2 are applied to the first gate 212 to the third gate 216 to restore the electron energy barrier and the hole energy barrier, and no hot carrier action is involved. Since the energy barriers have been established, the electrons and holes cannot move to the channel body 220.

[0085] 22 to 24 show the experimental results of operating the memory structure 20 based on the thyristor operation mechanism.

[0086] Referring to FIG. 22, the X-axis represents the programming time (PGM time) in microseconds (μs) and the Y-axis represents the read current (I read ) is expressed in microamperes (μA). During "PGM" operation, a large current flows through the selected memory cell CS, while the unselected memory cells CA and CB are suppressed and no current flows through them.

[0087] Referring to FIG. 23, the X-axis represents the erase time (ERS time) in microseconds (μs), and the Y-axis represents the read current (I read ) and its unit is microamperes (μA). After the "ERS" operation, no current flows through the selected memory cell CS, and the unselected memory cells CA and CB maintain a high current.

[0088] From the above results, it can be seen that, regardless of whether it is "PGM" or "ERS", the memory cell CS can be reliably selected, and the memory cells CA and CB can be suppressed.

[0089] Referring to FIG. 24, the X-axis represents the bias voltage of the third gate structure 216 in volts (V), and the Y-axis represents the read current (I read ) in microamperes (μA). In “Read”, −2V is applied to the first gate structure 212, 3V is applied to the second gate structure 214, and 2.5V is applied to the first bit line BL1. After the “Read” operation, the selected memory cell CS and the unselected memory cell CB are connected to the same bit line (i.e., the first bit line BL1) to ensure that the memory cell CB does not also contribute current. Now, the memory cell CB needs to be turned off, otherwise leakage current will occur and a sneak path will be formed. Therefore, in order to avoid the formation of a sneak path and to correctly read the selected memory cell CS, a sufficiently high bias voltage (e.g., 5V, which is larger than 4.5V indicated by the arrow) needs to be applied to the unselected third gate structure 216 (e.g., the fourth island structure 2161).

[0090] According to an embodiment of the present invention, the first gate structure and the third gate structure of the memory structure both have a three-island structure, and the memory structure of the present invention is operated by a thyristor operating mechanism. The memory structure of the present invention is highly scalable, has a high operating speed, and various electrical characteristics are superior to those of the current industry DRAM.

[0091] While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto, but is intended to cover various modifications and similar arrangements and procedures, and therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. a substrate having a top surface; a first gate structure, a second gate structure, and a third gate structure disposed on the substrate, the first gate structure, the second gate structure, and a third gate structure spaced apart from each other along a first direction and extending along a second direction and a third direction, respectively; a plurality of channel bodies separated from one another along the first direction and passing through the first gate structure, the second gate structure, and the third gate structure; Equipped with the first direction, the second direction, and the third direction intersect with each other, the upper surface is parallel to the first direction and the second direction, and a normal direction of the upper surface is parallel to the third direction, the second gate structure is disposed between the first gate structure and the third gate structure, the first gate structure includes a first island structure, a second island structure, and a third island structure, the third gate structure includes a fourth island structure, a fifth island structure, and a sixth island structure, the first island structure, the second island structure, and the third island structure each extend along the third direction and are separated from one another along the second direction, the fourth island structure, the fifth island structure, and the sixth island structure each extend along the third direction and are separated from one another along the second direction, the second gate structure has a common island structure surrounding each of the plurality of channel bodies; Each of the first gate structure, the second gate structure, and the third gate structure surrounds each of the plurality of channel bodies to form a gate-all-around structure. Memory structures.

2. a plurality of insulating films disposed between the first gate structure and the plurality of channel bodies, between the second gate structure and the plurality of channel bodies, and between the third gate structure and the plurality of channel bodies; a first side plug electrically connected to the substrate and the plurality of channel bodies; The memory structure of claim 1 further comprising:

3. 3. The memory structure of claim 2, wherein each of said plurality of channel bodies has a first end and a second end, said first end adjacent said first gate structure and said second end adjacent said third gate structure, said second end opposite said first end.

4. a plurality of first side pads stacked along the third direction and separated from one another along the third direction, each of the plurality of first side pads connected to the first end of a corresponding one of the plurality of channel bodies; a plurality of second side pads stacked along the third direction and separated from one another along the third direction, each of the plurality of second side pads being connected to the second end of a corresponding one of the plurality of channel bodies; The memory structure of claim 3 further comprising:

5. 5. The memory structure of claim 4, further comprising a plurality of second side plugs separated from one another along the second direction and extending along the third direction to electrically contact a plurality of landing regions on the plurality of second side pads, respectively.

6. 6. The memory structure of claim 5, wherein a height of the second side plugs in the third direction increases along the second direction, and the landing regions form a step structure.

7. The memory structure of claim 5 , wherein each of the plurality of second side plugs is connected to a bit line.

8. The memory structure of claim 4 , wherein said first side plug is in electrical contact with said plurality of first side pads.

9. 5. The memory structure of claim 4, wherein the first side pads have a first conductivity type and the second side pads have a second conductivity type.

10. The memory structure of claim 1 , wherein a material of the plurality of channel bodies comprises single crystal silicon.

11. 10. The memory structure of claim 1 , wherein a height of the first island structure, the second island structure or the third island structure in the third direction is equal to a height of the second gate structure in the third direction, and a width of the first island structure, the second island structure or the third island structure in the second direction is smaller than a width of the second gate structure in the second direction.

12. 12. The memory structure of claim 11, wherein a height of the fourth island structure, the fifth island structure or the sixth island structure in the third direction is equal to a height of the second gate structure in the third direction, and a width of the fourth island structure, the fifth island structure or the sixth island structure in the second direction is smaller than a width of the second gate structure in the second direction.

13. 13. The memory structure of claim 12, wherein a width of the first island structure, the second island structure, or the third island structure in the second direction is equal to a width of the fourth island structure, the fifth island structure, or the sixth island structure in the second direction.

14. The memory structure of claim 2 , wherein the material of the plurality of insulating films comprises a high dielectric constant material.

15. 10. The memory structure of claim 1, wherein the first gate structure, the second gate structure and the third gate structure function as word lines.

16. 10. The memory structure of claim 1, wherein each of the intersections of the first gate structure, the second gate structure and the third gate structure with the plurality of channel bodies forms a transistor.

17. 20. The memory structure of claim 16, wherein three transistors connected by a same channel body in the plurality of channel bodies together form a memory cell unit.

18. 20. The memory structure of claim 17, wherein multiple memory cell units at the same level are electrically connected to the same bit line.

19. The memory structure of claim 1 , wherein the first island structure, the second island structure, and the third island structure are independently controlled.

20. 10. The memory structure of claim 1, wherein the operating mechanism of the memory structure is thyristor-based.

21. The memory structure of claim 2 , wherein said insulating films are free of charge storage structures.

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